From 89177c3d90e19ed10c852d85d668ef8f1095f950 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Mon, 31 Jul 2023 16:43:00 +0200 Subject: [PATCH 01/18] WIP --- riscv/Cargo.toml | 2 + riscv/asm.s | 351 ++++++++++++++++++++++--- riscv/asm.s.old | 40 +++ riscv/disasm.s | 0 riscv/examples/riscv.rs | 170 +++---------- riscv/llvm.riscv | 410 ++++++++++++++++++++++++++++++ riscv/src/components/alu.rs | 2 +- riscv/src/components/decoder.rs | 2 +- riscv/src/components/instr_mem.rs | 4 +- 9 files changed, 804 insertions(+), 177 deletions(-) create mode 100644 riscv/asm.s.old create mode 100644 riscv/disasm.s create mode 100644 riscv/llvm.riscv diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index cbdbecb5..03860a20 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -6,6 +6,7 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] +riscv_asm = {path="/home/pawel/riscv_asm/"} serde = "1.0.167" serde_derive = "1.0.167" typetag = "0.2.9" @@ -16,6 +17,7 @@ log = "0.4.19" num_enum = "0.6.1" fern = "0.6.2" xmas-elf = "0.9.0" +asm_riscv = "0.1.0" [dependencies.syncrim] path = "../" diff --git a/riscv/asm.s b/riscv/asm.s index caa86360..2244c80f 100644 --- a/riscv/asm.s +++ b/riscv/asm.s @@ -1,40 +1,313 @@ .option arch, rv32i -.section .text -.section .init, "ax" -.global _start - -_start: - li x30, 0xffff - sw x30, 0(x0) - lb x8, 0(x0) - addi x1, x0, 0 #x1=0 - jal x2, .+8 - jal x2, .+0 #this is to be jumped over or we will get stuck - jalr x2, x2, 4 - jal x2, .+0 #this is to be jumped over or we will get stuck - addi x2, x0, 16 - addi x1, x0, 0 - addi x1, x1, 4 - bne x1, x2, .-4 - beq x1, x2, .+8 - jal x0, .+0 - addi x1, x0, -8 - addi x2, x0, 0 - addi x1, x1, 4 - blt x1, x2, .-4 - addi x1, x0, -8 - addi x2, x0, 0 - addi x1, x1, 4 - bltu x2, x1, .-4 - addi x1, x0, -8 - addi x2, x0, 0 - addi x1, x1, 4 - bge x2, x1, .-4 - addi x1, x0, -8 - addi x2, x0, 8 - addi x1, x1, 4 - bgeu x1, x2, .-4 - -.section .data -msg: - .string "Hello World\n" +# ---------------------------------------------------------- +# Group 1's "underlag" for Lab 1 +# Pseudo-instructions may be used for Lab 1. +# ---------------------------------------------------------- + + + +# Group 1's Codeword Generator Subroutine (pseudocode) +# (remember: "seed" is a global variable, UNSIGNED INTEGER; +# you may implement local variables in registers or on the stack; +# result returned in v0; preserve all except t regs) +# +# FUNCTION codgen(): UNSIGNED INTEGER; +# LOCAL SIGNED INTEGER n; +# LOCAL UNSIGNED INTEGER x, y; +# BEGIN +# n := [count the number of 0's in word "seed"]; +# x := [rotate "seed" left by 30 bits]; +# y := [shift "seed" right-ARITHMETIC by 6 bits]; +# seed := x XOR y XOR n; +# RETURN( seed XOR 0x464b713e ); +# END; +# +# hint: if "seed" is initialized to 0x3e944b9f, +# the first five calls will generate these values: +# 0x891432f9, 0x4aa1dccc, 0xc54270fa, 0x9885155f, 0xce83d1b8, ... +# your code is to be written farther down (see comment below). + + +# Group 1's Recursive Decoding Subroutine (pseudocode) +# (for "decode", all four local variables must be implemented ON THE +# STACK, and NOT in registers; implement the code literally,. +# no optimizations. We're trying to teach you something. +# remember: result returned in v0; preserve all except t regs) +# +# FUNCTION decode( wordarr, bytearr ): UNSIGNED INTEGER; +# (wordarr, bytearr passed by reference) +# LOCAL UNSIGNED INTEGER m, r, x, y; +# BEGIN +# x := ONE'S-COMPLEMENT of codgen(); +# IF ([contents of word at "wordarr"] = 0) THEN +# [byte pointed to by "bytearr"] := 0; +# r := x; +# ELSE +# y := decode( wordarr+, bytearr+ ); # "k+" means "successor in k" +# m := ( x - y ) - [contents of word at "wordarr"]; +# [byte pointed to by "bytearr"] := [the eight bits at "m"<20:13>]; +# r := TWO'S-COMPLEMENT OF codgen(); +# r := x + y + m + r + 5; +# ENDIF; +# RETURN( r ); +# END; + + +# ---------------------------------------------------------- +# The following are the ONLY lines that may appear in the +# ".data" section of the code. You may add NO other lines. +# NO additional global variables. +# ---------------------------------------------------------- + + + .data +test_word: .word 0xDEADBEEF +some_string: .string "Hi! :)" +.align 4 +abc: .word 0x9fdd9158 # string "abc", encoded + .word 0x85715808 + .word 0xac73323a + .word 0 +plain: .space 132 # room for 132 characters + + .align 4 +seed: .word 0 # 32-bit UNSIGNED INTEGER. + +coded: .word 0x015e7a47 # the real encoded data + .word 0x2ef84ebb + .word 0x177a8db4 + .word 0x1b722ff9 + .word 0x5dc7cff0 + .word 0x5dc9dea6 + .word 0x1da0c15a + .word 0xe4c236a2 + .word 0x3d16b0d0 + .word 0x1f397842 + .word 0xaae0d2ba + .word 0x11246674 + .word 0x0845317f + .word 0xd5512dad + .word 0xb6184977 + .word 0xd293a53e + .word 0x7d9c2716 + .word 0xd917eae6 + .word 0xd8852384 + .word 0x286e46f9 + .word 0xce566029 + .word 0xcefe7daf + .word 0x62d726d4 + .word 0x0dbaeb2d + .word 0x95f57c60 + .word 0xed515141 + .word 0x29b77d0f + .word 0x9f7b8d0c + .word 0x45a8395a + .word 0xfead2b72 + .word 0x883d434c + .word 0xed8ddf60 + .word 0xe51e65e4 + .word 0x19bf6bb1 + .word 0xfeb505ec + .word 0x662aa23c + .word 0xf6827cf8 + .word 0xd1dc7a5c + .word 0x4fa5b066 + .word 0x7ddd25a4 + .word 0xa8ba8e8a + .word 0x72846227 + .word 0xf8f636fb + .word 0x2b389a9c + .word 0xe4038bf6 + .word 0x6e169877 + .word 0xad028132 + .word 0x84dbfe8c + .word 0x243762ff + .word 0x59c8f80c + .word 0xb6e0db4b + .word 0xedb8cab7 + .word 0xcd4b39f6 + .word 0xaf263741 + .word 0x18d9965f + .word 0x1ab1f037 + .word 0x5b458792 + .word 0xc94d960d + .word 0xd45cedea + .word 0x2160aca3 + .word 0x93c77766 + .word 0x2d66e105 + .word 0x9ff74d4f + .word 0x6dc22f21 + .word 0x6b03d689 + .word 0x5fc48de0 + .word 0x1138f000 + .word 0xccb58e57 + .word 0xf9c8e200 + .word 0x7ab26e3c + .word 0xc61dcb3e + .word 0x6aefccb0 + .word 0x7a452f05 + .word 0xa5cf0731 + .word 0xa249383f + .word 0x628fe534 + .word 0xcad81710 + .word 0x7f616276 + .word 0x3ce18308 + .word 0xed4857ff + .word 0xd1e5b1d1 + .word 0xc2e84dc2 + .word 0xaa003742 + .word 0xaf637488 + .word 0x831afc48 + .word 0x287a69a0 + .word 0x6e04546e + .word 0x13dffa07 + .word 0x3232fb10 + .word 0xd69e2e09 + .word 0x355d8dc7 + .word 0xef902301 + .word 0x9a89ac15 + .word 0x967dc900 + .word 0x08dc2b1c + .word 0x6b5be690 + .word 0x894b0e02 + .word 0xe26af9af + .word 0xa6fd3b23 + .word 0xfcf213e5 + .word 0x85217608 + .word 0x7fd3be8b + .word 0xa2e757fb + .word 0x3717a341 + .word 0x85ee426d + .word 0x394bb856 + .word 0x12ac98c3 + .word 0xec7d4ab5 + .word 0x721b6989 + .word 0x30e36360 + .word 0xaa018403 + .word 0x9ee61196 + .word 0xa8697adc + .word 0x51e9d65a + .word 0x11023594 + .word 0xc4c4b36b + .word 0xda80bf7a + .word 0xbd5a645e + .word 0x18cea918 + .word 0xa723dda8 + .word 0x0126c05e + .word 0x2962d48a + .word 0xd5f7d312 + .word 0xb8947041 + .word 0x7c1e2e9a + .word 0x945eeac3 + .word 0x7110fb1c + .word 0xa7bc72cc + .word 0xdf47dfbb + .word 0x09a1c6c8 + .word 0xc2e41061 + .word 0 + + +# ---------------------------------------------------------- +# The following is the main program. You may not change this. +# You may only add your subroutines AFTER the "infinite end loop" instruction here. +# You MUST have two subroutines named "codgen" and "decode". +# BOTH must adhere to our calling conventions; +# both MUST preserve all registers except v-regs and t-regs; +# we are going to TEST for this when we run your code. +# ---------------------------------------------------------- + + + .text +main: + addi t0, t1, 0 + la t0, test_word + li t1, 0xFFFFFFFF + sw t1, 0(t0) + sw t1, 4(t0) + sw t1, 8(t0) + sw t1, 12(t0) + li s0, 0x0e0657c1 # initialize "seed" + la s1, seed # initialize "seed" + sw s0, 0(s1) + la a0, coded # address of start of coded words + la a1, plain # address of start of decoded bytes + jal ra, codgen + jal ra, codgen + jal ra, codgen + jal ra, codgen + jal ra, codgen + jal ra, codgen + jal ra, decode # outer call to recursive "decode" +end: + j end # infinite loop; plaintext now in "plain". + + +# ---------------------------------------------------------- +# Group 1's assembly code for Function CodGen : +# ---------------------------------------------------------- + + # your activation record diagram here. + +# Group 1's Codeword Generator Subroutine (pseudocode) +# (remember: "seed" is a global variable, UNSIGNED INTEGER; +# you may implement local variables in registers or on the stack; +# result returned in v0; preserve all except t regs) +# +# FUNCTION codgen(): UNSIGNED INTEGER; +# LOCAL SIGNED INTEGER n; +# LOCAL UNSIGNED INTEGER x, y; +# BEGIN +# n := [count the number of 0's in word "seed"]; +# x := [rotate "seed" left by 30 bits]; +# y := [shift "seed" right-ARITHMETIC by 6 bits]; +# seed := x XOR y XOR n; +# RETURN( seed XOR 0x464b713e ); +# END; +# +# hint: if "seed" is initialized to 0x3e944b9f, +# the first five calls will generate these values: +# 0x891432f9, 0x4aa1dccc, 0xc54270fa, 0x9885155f, 0xce83d1b8, ... +# your code is to be written farther down (see comment below). + +#t1 = n +#t2 = x +#t3 = y +codgen: + la s1, seed + lw s0, 0(s1) + li t0, 1 + li t1, 0 +loop: + beq t0, x0, continue + and t2, t0, s0 + bne t2, x0, skip + addi t1, t1, 1 +skip: + sll t0, t0, 1 + jal x0, loop +continue: + slli t2, s0, 30 + srli t3, s0, 2 + or t2, t2, t3 #rotate + srai t3, s0, 6 #shift + addi s0, t2, 0 + xor s0, s0, t3 + xor s0, s0, t1 + sw s0, 0(s1) #update seed + jalr x0, ra + + + + + + +# ---------------------------------------------------------- +# Group 1's assembly code for Function DeCode : +# ---------------------------------------------------------- + + # your activation record diagram here. + +decode: # your code here. + + +# end of file. diff --git a/riscv/asm.s.old b/riscv/asm.s.old new file mode 100644 index 00000000..caa86360 --- /dev/null +++ b/riscv/asm.s.old @@ -0,0 +1,40 @@ +.option arch, rv32i +.section .text +.section .init, "ax" +.global _start + +_start: + li x30, 0xffff + sw x30, 0(x0) + lb x8, 0(x0) + addi x1, x0, 0 #x1=0 + jal x2, .+8 + jal x2, .+0 #this is to be jumped over or we will get stuck + jalr x2, x2, 4 + jal x2, .+0 #this is to be jumped over or we will get stuck + addi x2, x0, 16 + addi x1, x0, 0 + addi x1, x1, 4 + bne x1, x2, .-4 + beq x1, x2, .+8 + jal x0, .+0 + addi x1, x0, -8 + addi x2, x0, 0 + addi x1, x1, 4 + blt x1, x2, .-4 + addi x1, x0, -8 + addi x2, x0, 0 + addi x1, x1, 4 + bltu x2, x1, .-4 + addi x1, x0, -8 + addi x2, x0, 0 + addi x1, x1, 4 + bge x2, x1, .-4 + addi x1, x0, -8 + addi x2, x0, 8 + addi x1, x1, 4 + bgeu x1, x2, .-4 + +.section .data +msg: + .string "Hello World\n" diff --git a/riscv/disasm.s b/riscv/disasm.s new file mode 100644 index 00000000..e69de29b diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 93890220..402731d2 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -51,7 +51,7 @@ fn main() { }; println!("{}", memory); let mut instr_mem = BTreeMap::new(); - let mut data_mem = HashMap::new(); + let mut data_mem = BTreeMap::new(); for element in memory.bytes { if element.0 < 0x5000_0000 { instr_mem.insert(element.0, element.1); @@ -138,88 +138,7 @@ fn main() { id: "instr_mem".to_string(), pos: (180.0, 400.0), pc: Input::new("reg", "out"), - // fake instructions just to show the relation between input address and instruction bytes: instr_mem, - //vec![ - //The results are calculated from the reg file start state defined above - //and assuming the blocks are the only code over that reg file. - //OP TEST BLOCK - // 0x003100b3,//add x1, x2, x3 -> x1 = 0x5 - // 0x00308133,//add x2, x1, x3 -> x2 = 0x8 - // 0x40410133,//sub x2, x2, x4 -> x2 = -2 - // 0x004121b3,//slt x3, x2, x4 -> x3 = 0x1 //signed -2<10 - // 0x004131b3,//sltu x3, x2, x4 x3 = 0x0 //unsigned -2>10 - // 0x001151b3,//srl x3, x2, x1 # x3 = 0x07ffffff - // 0x401151b3,//sra x3, x2, x1 # x3 = 0xffffffff - // 0x001111b3,//sll x3, x2, x1 # x3 = 0xffffffc0 - // 0x0020c1b3,//xor x3, x1, x2 # x3 = 0xfffffffb //fel här - // 0x0020f1b3,//and x3, x1, x2 # x3 = 0x00000004 - // 0x0060e1b3,//or x3, x1, x6 # x3 = 0x00000007 - // 0x00000033,//add x0, x0, x0, basically nop before panicking so we can see result. - // 0x00940023,//sb x8, 0(x9) # should panic over opcode for now - //OP_IMM, AUIPC, LUI, STORE, LOAD, OP_IMM TEST BLOCK - // 0x00310093,//addi x1, x2, 3 # x1=0x5 - // 0xffd0a093,//slti x1, x1, -3 # x1=0x0 - // 0x0030a093,//slti x1, x1, 3 # x1=0x1 - // 0xffd0b093,//sltiu x1, x1, -3 #x1=0x1 - // 0x00313093,//sltiu x1, x2, 3 #x1=0x1 - // 0x00324093,//xori x1, x4, 3 #x1 = 0x9 - // 0x00326093,//ori x1, x4, 3 #x1=0xb - // 0x00327093,//andi x1, x4, 3 #x1=0x2 - // 0x00c19093,//slli x1, x3, 12 #x1=0x3000 - // 0x0011d093,//srli x1, x3, 1 #x1=0x1 - // 0xffa00093,//addi x1, x0, -6 #x1=0xfffffffa - // 0x4020d093,//srai x1, x1, 2 #x1=0xfffffffe - // 0x00500093,//addi x1, x0, 5 #x1=0x5 - // 0x4020d093,//srai x1, x1, 2 #x1=0x1 - // 0xfffff0b7,//lui x1, 0xFFFFF #x1=0xFFFFF000 - // 0xfffff097,//auipc x1, 0xFFFFF #x1=0xFFFFF040 - // 0x00000093,//addi, x1, x0, 0 x1 = 0 - // 0x00408093,//addi x1, x1, 4 x1+=4 - // //0xff9ff16f,//jal, x2, -8 should jump to the addi before and keep incrementing x1. - // 0x00000033,//add x0, x0, x0, basically nop before panicking so we can see result. - // //0x00940023,//sb x8, 0(x9) # should panic over opcode for now - // 0x00102023,//sw x1, 0(x0) store x1=4 at 0 - // 0x00002283,//lw x5, 0(x0) x5=4 - // 0x00228213,//addi x4, x5, 2 //x4=6 - // 0x00002303, //lw x6, 0(x0), x6 = 4 - // 0xfff00093,//set x1 to -1 addi x1, x0, -1 - // 0x00102023,//store -1 at 0 - // 0x00000203,//load via lb -1 to x4 - // 0x00004203,//lbu x4 -1 again. - // 0x004002a3,//sb x4, 5(0) - // 0x00000033,//add x0, x0, x0, basically nop before panicking so we can see result. - // 0x00000033,//add x0, x0, x0, basically nop before panicking so we can see result. - //JAL, JALR, BRANCHES TEST BLOCK - // 0x00000093, //addi, x1, x0, 0 x1=0 - // 0x0080016f, //jal x2, 8 - // 0x0000016f, //jal x2, 0 this is to be jumped over or we will get stuck - // 0x00410167, //jalr x2, x2, 4 - // 0x0000016f, //jal x2, 0 this is to be jumped over or we will get stuck - // 0x01000113, //addi x2, x0, 16 - // 0x00000093, //addi x1, x0, 0 - // 0x00408093, //addi x1, x1, 4 - // 0xfe209ee3, //bne x1, x2, -4 - // 0x00208463, //beq, x1, x2, 8 - // 0x0000006f, //jal x0, 0 - // 0xff800093, //addi x1, x0, -8 - // 0x00000113, //addi x2, x0, 0 - // 0x00408093, //addi x1, x1, 4 - // 0xfe20cee3, //blt x1, x2, -4 - // 0xff800093, //addi x1, x0, -8 - // 0x00000113, //addi x2, x0, 0 - // 0x00408093, //addi x1, x1, 4 - // 0xfe116ee3, //bltu, x2, x1, -4 - // 0xff800093, //addi x1, x0, -8 - // 0x00000113, //addi x2, x0, 0 - // 0x00408093, //addi x1, x1, 4 - // 0xfe115ee3, //bge x2, x1, -4 - // 0xff800093, //addi x1, x0, -8 - // 0x00800113, //addi x2, x0, 8 - // 0x00408093, //addi x1, x1, 4 - // 0xfe20fee3, //bgeu x1, x2, -4 - // 0x00408093, 0x00408093, 0x00408093, 0x00408093, 4, 5, 6, 7, 8, 9, - // ], }), Rc::new(Decoder { id: "decoder".to_string(), @@ -252,58 +171,35 @@ fn main() { write_data: Input::new("wb_mux", "out"), write_addr: Input::new("regfile_rd_reg", "out"), write_enable: Input::new("regfile_we_reg", "out"), - registers: RegStore::new(Rc::new(RefCell::new([ - 0, 1, 2, 3, 10, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, - ]))), - // registers: vec![Cell::new(0), - // RefCell::new(1), - // Cell::new(2), - // Cell::new(3), - // Cell::new(10), - // Cell::new(5), - // Cell::new(6), - // Cell::new(7), - // Cell::new(8), - // Cell::new(9), - // Cell::new(10), - // Cell::new(11), - // Cell::new(12), - // Cell::new(13), - // Cell::new(14), - // Cell::new(15), - // Cell::new(16), - // Cell::new(17), - // Cell::new(18), - // Cell::new(19), - // Cell::new(20), - // Cell::new(21), - // Cell::new(22), - // Cell::new(23), - // Cell::new(24), - // Cell::new(25), - // Cell::new(26), - // Cell::new(27), - // Cell::new(28), - // Cell::new(29), - // Cell::new(30), - // Cell::new(31), - // ], + registers: RegStore::new(Rc::new(RefCell::new([0; 32]))), history: RegHistory::new(), }), - Mem::rc_new_from_bytes( - "data_memory", - (700.0, 600.0), - 100.0, - 100.0, - false, - Input::new("reg_file", "reg_b"), - Input::new("alu", "result_o"), - Input::new("decoder", "data_mem_ctrl"), - Input::new("decoder", "data_se"), - Input::new("decoder", "data_mem_size"), - data_mem, - ), + Rc::new(Mem { + id: "data_memory".to_string(), + pos: (700.0, 600.0), + width: 100.0, + height: 100.0, + big_endian: false, + data: Input::new("reg_file", "reg_b"), + addr: Input::new("alu", "result_o"), + ctrl: Input::new("decoder", "data_mem_ctrl"), + sext: Input::new("decoder", "data_se"), + size: Input::new("decoder", "data_mem_size"), + memory: Memory::new(Rc::new(RefCell::new(data_mem))), + }), + // Mem::rc_new_from_bytes( + // "data_memory", + // (700.0, 600.0), + // 100.0, + // 100.0, + // false, + // Input::new("reg_file", "reg_b"), + // Input::new("alu", "result_o"), + // Input::new("decoder", "data_mem_ctrl"), + // Input::new("decoder", "data_se"), + // Input::new("decoder", "data_mem_size"), + // data_mem, + // ), Constant::rc_new("zero_c", (680.0, 150.0), 0), Mux::rc_new( "alu_operand_a_mux", @@ -323,6 +219,7 @@ fn main() { Input::new("reg_file", "reg_b"), Input::new("imm_szext", "out"), Input::new("pc_adder", "out"), + Input::new("reg", "out"), ], ), Rc::new(ALU { @@ -373,9 +270,12 @@ fn fern_setup_riscv() { // - and per-module overrides #[cfg(feature = "gui-vizia")] let f = f - .level_for("syncrim::components::mem", LevelFilter::Trace) - .level_for("riscv::components::instr_mem", LevelFilter::Trace); - //.level_for("riscv", LevelFilter::Trace); + //.level_for("syncrim::components::mem", LevelFilter::Trace) + //.level_for("riscv::components::instr_mem", LevelFilter::Trace) + .level_for("syncrim::gui_vizia::components::mem", LevelFilter::Trace) + .level_for("riscv::gui_vizia::components::reg_file", LevelFilter::Trace) + //.level_for("riscv::components::alu", LevelFilter::Trace); + .level_for("syncrim::components::mem", LevelFilter::Trace); f // Output to stdout, files, and other Dispatch configurations diff --git a/riscv/llvm.riscv b/riscv/llvm.riscv new file mode 100644 index 00000000..4f721001 --- /dev/null +++ b/riscv/llvm.riscv @@ -0,0 +1,410 @@ + +llvm.o: file format elf32-littleriscv + +Disassembly of section .strtab: + +00000000 <.strtab>: + 0: 00 2e + 2: 72 65 + 4: 6c 61 + 6: 2e 74 + 8: 65 78 + a: 74 00 + c: 6d 61 + e: 69 6e + 10: 00 70 + 12: 6c 61 + 14: 69 6e + 16: 00 63 + 18: 6f 64 67 65 jal s0, 0x7666e <.strtab+0x7666e> + 1c: 6e 00 + 1e: 64 65 + 20: 63 6f 64 65 bltu s0, s6, 0x67e <.strtab+0x67e> + 24: 00 65 + 26: 6e 64 + 28: 00 73 + 2a: 65 65 + 2c: 64 00 + 2e: 63 6f 64 65 bltu s0, s6, 0x68c <.strtab+0x68c> + 32: 64 00 + 34: 61 62 + 36: 63 00 2e 73 beq t3, s2, 0x756 <.strtab+0x756> + 3a: 74 72 + 3c: 74 61 + 3e: 62 00 + 40: 2e 73 + 42: 79 6d + 44: 74 61 + 46: 62 00 + 48: 2e 64 + 4a: 61 74 + 4c: 61 00 + 4e: 2e 4c + 50: 70 63 + 52: 72 65 + 54: 6c 5f + 56: 68 69 + 58: 32 00 + 5a: 2e 4c + 5c: 70 63 + 5e: 72 65 + 60: 6c 5f + 62: 68 69 + 64: 31 00 + 66: 2e 4c + 68: 70 63 + 6a: 72 65 + 6c: 6c 5f + 6e: 68 69 + 70: 30 00 + +Disassembly of section .text: + +00000000
: + 0: 37 54 06 0e lui s0, 57445 + 4: 13 04 14 7c addi s0, s0, 1985 + +00000008 <.Lpcrel_hi0>: + 8: 97 04 00 00 auipc s1, 0 + c: 93 84 04 00 mv s1, s1 + 10: 23 a0 84 00 sw s0, 0(s1) + +00000014 <.Lpcrel_hi1>: + 14: 17 05 00 00 auipc a0, 0 + 18: 13 05 05 00 mv a0, a0 + +0000001c <.Lpcrel_hi2>: + 1c: 97 05 00 00 auipc a1, 0 + 20: 93 85 05 00 mv a1, a1 + 24: ef 00 80 00 jal 0x2c + +00000028 : + 28: 6f 00 00 00 j 0x28 + +Disassembly of section .rela.text: + +00000000 <.rela.text>: + 0: 08 00 + 2: 00 00 + 4: 17 02 00 00 auipc tp, 0 + 8: 00 00 + a: 00 00 + c: 0c 00 + e: 00 00 + 10: 18 06 + 12: 00 00 + 14: 00 00 + 16: 00 00 + 18: 14 00 + 1a: 00 00 + 1c: 17 04 00 00 auipc s0, 0 + 20: 00 00 + 22: 00 00 + 24: 18 00 + 26: 00 00 + 28: 18 07 + 2a: 00 00 + 2c: 00 00 + 2e: 00 00 + 30: 1c 00 + 32: 00 00 + 34: 17 01 00 00 auipc sp, 0 + 38: 00 00 + 3a: 00 00 + 3c: 20 00 + 3e: 00 00 + 40: 18 08 + 42: 00 00 + 44: 00 00 + 46: 00 00 + +Disassembly of section .data: + +00000000 : + ... + +00000090 : + 90: 00 00 + 92: 00 00 + +00000094 : + 94: 58 91 + 96: dd 9f + 98: 08 58 + 9a: 71 85 + 9c: 3a 32 + 9e: 73 ac 00 00 csrrs s8, ustatus, ra + a2: 00 00 + +000000a4 : + a4: 47 7a 5e 01 + a8: bb 4e f8 2e + ac: b4 8d + ae: 7a 17 + b0: f9 2f + b2: 72 1b + b4: f0 cf + b6: c7 5d a6 de + ba: c9 5d + bc: 5a c1 + be: a0 1d + c0: a2 36 + c2: c2 e4 + c4: d0 b0 + c6: 16 3d + c8: 42 78 + ca: 39 1f + cc: ba d2 + ce: e0 aa + d0: 74 66 + d2: 24 11 + d4: 7f 31 45 08 + d8: ad 2d + da: 51 d5 + dc: 77 49 18 b6 + e0: 3e a5 + e2: 93 d2 16 27 + e6: 9c 7d + e8: e6 ea + ea: 17 d9 84 23 auipc s2, 145485 + ee: 85 d8 + f0: f9 46 + f2: 6e 28 + f4: 29 60 + f6: 56 ce + f8: af 7d fe ce + fc: d4 26 + fe: d7 62 2d eb + 102: ba 0d + 104: 60 7c + 106: f5 95 + 108: 41 51 + 10a: 51 ed + 10c: 0f 7d b7 29 + 110: 0c 8d + 112: 7b 9f 5a 39 + 116: a8 45 + 118: 72 2b + 11a: ad fe + 11c: 4c 43 + 11e: 3d 88 + 120: 60 df + 122: 8d ed + 124: e4 65 + 126: 1e e5 + 128: b1 6b + 12a: bf 19 ec 05 + 12e: b5 fe + 130: 3c a2 + 132: 2a 66 + 134: f8 7c + 136: 82 f6 + 138: 5c 7a + 13a: dc d1 + 13c: 66 b0 + 13e: a5 4f + 140: a4 25 + 142: dd 7d + 144: 8a 8e + 146: ba a8 + 148: 27 62 84 72 + 14c: fb 36 f6 f8 + 150: 9c 9a + 152: 38 2b + 154: f6 8b + 156: 03 e4 77 98 + 15a: 16 6e + 15c: 32 81 + 15e: 02 ad + 160: 8c fe + 162: db 84 ff 62 + 166: 37 24 0c f8 lui s0, 1016002 + 16a: c8 59 + 16c: 4b db e0 b6 + 170: b7 ca b8 ed lui s5, 973708 + 174: f6 39 + 176: 4b cd 41 37 + 17a: 26 af + 17c: 5f 96 d9 18 + 180: 37 f0 b1 1a lui zero, 109343 + 184: 92 87 + 186: 45 5b + 188: 0d 96 + 18a: 4d c9 + 18c: ea ed + 18e: 5c d4 + 190: a3 ac 60 21 sw s6, 537(ra) + 194: 66 77 + 196: c7 93 05 e1 + 19a: 66 2d + 19c: 4f 4d f7 9f + 1a0: 21 2f + 1a2: c2 6d + 1a4: 89 d6 + 1a6: 03 6b e0 8d + 1aa: c4 5f + 1ac: 00 f0 + 1ae: 38 11 + 1b0: 57 8e b5 cc + 1b4: 00 e2 + 1b6: c8 f9 + 1b8: 3c 6e + 1ba: b2 7a + 1bc: 3e cb + 1be: 1d c6 + 1c0: b0 cc + 1c2: ef 6a 05 2f jal s5, 0x564b2 + 1c6: 45 7a + 1c8: 31 07 + 1ca: cf a5 3f 38 + 1ce: 49 a2 + 1d0: 34 e5 + 1d2: 8f 62 10 17 + 1d6: d8 ca + 1d8: 76 62 + 1da: 61 7f + 1dc: 08 83 + 1de: e1 3c + 1e0: ff 57 48 ed + 1e4: d1 b1 + 1e6: e5 d1 + 1e8: c2 4d + 1ea: e8 c2 + 1ec: 42 37 + 1ee: 00 aa + 1f0: 88 74 + 1f2: 63 af 48 fc + 1f6: 1a 83 + 1f8: a0 69 + 1fa: 7a 28 + 1fc: 6e 54 + 1fe: 04 6e + 200: 07 fa df 13 + 204: 10 fb + 206: 32 32 + 208: 09 2e + 20a: 9e d6 + 20c: c7 8d 5d 35 + 210: 01 23 + 212: 90 ef + 214: 15 ac + 216: 89 9a + 218: 00 c9 + 21a: 7d 96 + 21c: 1c 2b + 21e: dc 08 + 220: 90 e6 + 222: 5b 6b 02 0e + 226: 4b 89 af f9 + 22a: 6a e2 + 22c: 23 3b fd a6 + 230: e5 13 + 232: f2 fc + 234: 08 76 + 236: 21 85 + 238: 8b be d3 7f + 23c: fb 57 e7 a2 + 240: 41 a3 + 242: 17 37 6d 42 auipc a4, 272083 + 246: ee 85 + 248: 56 b8 + 24a: 4b 39 c3 98 + 24e: ac 12 + 250: b5 4a + 252: 7d ec + 254: 89 69 + 256: 1b 72 60 63 + 25a: e3 30 03 84 + 25e: 01 aa + 260: 96 11 + 262: e6 9e + 264: dc 7a + 266: 69 a8 + 268: 5a d6 + 26a: e9 51 + 26c: 94 35 + 26e: 02 11 + 270: 6b b3 c4 c4 + 274: 7a bf + 276: 80 da + 278: 5e 64 + 27a: 5a bd + 27c: 18 a9 + 27e: ce 18 + 280: a8 dd + 282: 23 a7 5e c0 sw t0, -1010(t4) + 286: 26 01 + 288: 8a d4 + 28a: 62 29 + 28c: 12 d3 + 28e: f7 d5 41 70 + 292: 94 b8 + 294: 9a 2e + 296: 1e 7c + 298: c3 ea 5e 94 + 29c: 1c fb + 29e: 10 71 + 2a0: cc 72 + 2a2: bc a7 + 2a4: bb df 47 df + 2a8: c8 c6 + 2aa: a1 09 + 2ac: 61 10 + 2ae: e4 c2 + 2b0: 00 00 + 2b2: 00 00 + +Disassembly of section .symtab: + +00000000 <.symtab>: + ... + 10: 11 00 + ... + 1e: 04 00 + 20: 29 00 + 22: 00 00 + 24: 90 00 + ... + 2e: 04 00 + 30: 34 00 + 32: 00 00 + 34: 94 00 + ... + 3e: 04 00 + 40: 2e 00 + 42: 00 00 + 44: a4 00 + ... + 4e: 04 00 + 50: 0c 00 + ... + 5e: 02 00 + 60: 66 00 + 62: 00 00 + 64: 08 00 + ... + 6e: 02 00 + 70: 5a 00 + 72: 00 00 + 74: 14 00 + ... + 7e: 02 00 + 80: 4e 00 + 82: 00 00 + 84: 1c 00 + ... + 8e: 02 00 + 90: 1e 00 + 92: 00 00 + 94: 2c 00 + ... + 9e: 02 00 + a0: 25 00 + a2: 00 00 + a4: 28 00 + ... + ae: 02 00 + b0: 17 00 00 00 auipc zero, 0 + b4: 2c 00 + ... + be: 02 00 diff --git a/riscv/src/components/alu.rs b/riscv/src/components/alu.rs index 31d6069e..0684aa43 100644 --- a/riscv/src/components/alu.rs +++ b/riscv/src/components/alu.rs @@ -128,7 +128,7 @@ impl Component for ALU { } //BGEU _ => {} } - trace!("ALU result_o:{}", result_o); + trace!("ALU result_o:{:08x}", result_o); simulator.set_out_value(&self.id, "result_o", result_o); } } diff --git a/riscv/src/components/decoder.rs b/riscv/src/components/decoder.rs index ccf2262a..bd271238 100644 --- a/riscv/src/components/decoder.rs +++ b/riscv/src/components/decoder.rs @@ -277,7 +277,7 @@ impl Component for Decoder { //AUIPC trace!("opcode=AUIPC"); alu_operand_a_sel = SignalValue::from(1); //big-imm - alu_operand_b_sel = SignalValue::from(2); //PC + alu_operand_b_sel = SignalValue::from(3); //PC regfile_rd = SignalValue::from((instruction & (0b11111 << 7)) >> 7); //regfile_rs1 = SignalValue::from(0); //x0 dont care regfile_we = SignalValue::from(1); //enable write diff --git a/riscv/src/components/instr_mem.rs b/riscv/src/components/instr_mem.rs index c5228a5d..dd1fdaba 100644 --- a/riscv/src/components/instr_mem.rs +++ b/riscv/src/components/instr_mem.rs @@ -1,4 +1,5 @@ use std::collections::BTreeMap; +use asm_riscv; use log::trace; use serde::{Deserialize, Serialize}; @@ -36,7 +37,8 @@ impl Component for InstrMem { | (*self.bytes.get(&((pc + 1) as usize)).unwrap() as u32) << 16 | (*self.bytes.get(&((pc + 2) as usize)).unwrap() as u32) << 8 | (*self.bytes.get(&((pc + 3) as usize)).unwrap() as u32); - trace!("instruction: 0x{:08x}", instr); + let instruction = asm_riscv::I::try_from(instr).unwrap(); + trace!("instruction: {:?}", instruction); trace!("pc:0x{:08x}", pc); // set output simulator.set_out_value(&self.id, "instruction", instr); From 0f6723f4b1eaff5a6830d4babf19282966b80746 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Mon, 31 Jul 2023 17:43:40 +0200 Subject: [PATCH 02/18] Left view is functional, needs formatting --- riscv/examples/riscv.rs | 26 ++++++------- src/components/mem.rs | 68 ++++++++++++++++++++------------- src/gui_vizia/components/mem.rs | 55 +++++++++++++++++++++++++- 3 files changed, 109 insertions(+), 40 deletions(-) diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 402731d2..5af2ae21 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -174,19 +174,19 @@ fn main() { registers: RegStore::new(Rc::new(RefCell::new([0; 32]))), history: RegHistory::new(), }), - Rc::new(Mem { - id: "data_memory".to_string(), - pos: (700.0, 600.0), - width: 100.0, - height: 100.0, - big_endian: false, - data: Input::new("reg_file", "reg_b"), - addr: Input::new("alu", "result_o"), - ctrl: Input::new("decoder", "data_mem_ctrl"), - sext: Input::new("decoder", "data_se"), - size: Input::new("decoder", "data_mem_size"), - memory: Memory::new(Rc::new(RefCell::new(data_mem))), - }), + Mem::rc_new_from_bytes( + "data_memory", + (700.0, 600.0), + 100.0, + 100.0, + false, + Input::new("reg_file", "reg_b"), + Input::new("alu", "result_o"), + Input::new("decoder", "data_mem_ctrl"), + Input::new("decoder", "data_se"), + Input::new("decoder", "data_mem_size"), + data_mem, + ), // Mem::rc_new_from_bytes( // "data_memory", // (700.0, 600.0), diff --git a/src/components/mem.rs b/src/components/mem.rs index 4bf52ce5..8b922f58 100644 --- a/src/components/mem.rs +++ b/src/components/mem.rs @@ -5,7 +5,7 @@ use log::*; use num_enum::IntoPrimitive; use num_enum::TryFromPrimitive; use serde::{Deserialize, Serialize}; -use std::{cell::RefCell, collections::HashMap, convert::TryFrom, rc::Rc}; +use std::{cell::RefCell, collections::BTreeMap, convert::TryFrom, rc::Rc}; #[derive(Serialize, Deserialize)] pub struct Mem { @@ -42,7 +42,7 @@ impl Mem { ctrl: Input, sext: Input, size: Input, - memory: HashMap, + memory: BTreeMap, ) -> Self { Mem { id: id.to_string(), @@ -83,7 +83,7 @@ impl Mem { ctrl, sext, size, - HashMap::new(), + BTreeMap::new(), )) } @@ -98,7 +98,7 @@ impl Mem { ctrl: Input, sext: Input, size: Input, - memory: HashMap, + memory: BTreeMap, ) -> Rc { Rc::new(Mem::new( id, pos, width, height, big_endian, data, addr, ctrl, sext, size, memory, @@ -106,22 +106,18 @@ impl Mem { } } -#[derive(Serialize, Deserialize, Debug)] -pub struct Memory { - bytes: RefCell>, -} +#[derive(Serialize, Deserialize, Debug, Clone)] +pub struct Memory(pub Rc>>); impl Default for Memory { fn default() -> Self { - Self::new(HashMap::new()) + Self::new(BTreeMap::new()) } } impl Memory { - pub fn new(data: HashMap) -> Self { - Memory { - bytes: RefCell::new(data), - } + pub fn new(data: BTreeMap) -> Self { + Memory(Rc::new(RefCell::new(data))) } fn align(&self, addr: usize, size: usize) -> SignalValue { @@ -130,7 +126,7 @@ impl Memory { fn read(&self, addr: usize, size: usize, sign: bool, big_endian: bool) -> SignalValue { let data: Vec = (0..size) - .map(|i| *self.bytes.borrow().get(&(addr + i)).unwrap_or(&0)) + .map(|i| *self.0.borrow().get(&(addr + i)).unwrap_or(&0)) .collect(); let data = data.as_slice(); @@ -201,7 +197,7 @@ impl Memory { match size { 1 => { trace!("write byte"); - self.bytes.borrow_mut().insert(addr, data as u8); + self.0.borrow_mut().insert(addr, data as u8); } 2 => { if big_endian { @@ -211,7 +207,7 @@ impl Memory { .iter() .enumerate() .for_each(|(i, bytes)| { - self.bytes.borrow_mut().insert(addr + i, *bytes); + self.0.borrow_mut().insert(addr + i, *bytes); }) } else { trace!("write half word le"); @@ -220,7 +216,7 @@ impl Memory { .iter() .enumerate() .for_each(|(i, bytes)| { - self.bytes.borrow_mut().insert(addr + i, *bytes); + self.0.borrow_mut().insert(addr + i, *bytes); }) } } @@ -232,7 +228,7 @@ impl Memory { .iter() .enumerate() .for_each(|(i, bytes)| { - self.bytes.borrow_mut().insert(addr + i, *bytes); + self.0.borrow_mut().insert(addr + i, *bytes); }) } else { trace!("write word le"); @@ -240,7 +236,7 @@ impl Memory { .iter() .enumerate() .for_each(|(i, bytes)| { - self.bytes.borrow_mut().insert(addr + i, *bytes); + self.0.borrow_mut().insert(addr + i, *bytes); }) } } @@ -328,7 +324,31 @@ impl Component for Mem { } } - trace!("memory {:?}", self.memory); + for (idx, i) in self.memory.0.borrow().iter().enumerate() { + if i.0 % 4 == 0 && idx < 40 { + //only print 40 bytes so the trace isn't busy + trace!( + "0x{:08x} : 0x{:02x}{:02x}{:02x}{:02x}", + i.0, + self.memory.0.borrow().get(&(i.0)).unwrap_or_else(|| &0u8), + self.memory + .0 + .borrow() + .get(&(i.0 + 1)) + .unwrap_or_else(|| &0u8), + self.memory + .0 + .borrow() + .get(&(i.0 + 2)) + .unwrap_or_else(|| &0u8), + self.memory + .0 + .borrow() + .get(&(i.0 + 3)) + .unwrap_or_else(|| &0u8), + ) + } + } } } @@ -365,9 +385,7 @@ mod test { sext: Input::new("sign", "out"), // memory - memory: Memory { - bytes: RefCell::new(HashMap::new()), - }, + memory: Memory(Rc::new(RefCell::new(BTreeMap::new()))), }), ], }; @@ -545,9 +563,7 @@ mod test { sext: Input::new("sign", "out"), // memory - memory: Memory { - bytes: RefCell::new(HashMap::new()), - }, + memory: Memory(Rc::new(RefCell::new(BTreeMap::new()))), // later history... tbd }), ], diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index eeb8a52f..df65bba7 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -1,10 +1,30 @@ +use std::ops::Range; + use crate::{ - components::Mem, + components::{Mem, Memory}, gui_vizia::{ViziaComponent, V}, }; use log::*; use vizia::prelude::*; +fn range_view(cx: &mut Context) { + let range = Range { + start: 0x8000_0000u32, + end: 0x8000_0020u32, + }; + for i in range { + let item = DataMemView::data + .map(move |mem: &Memory| mem.0.borrow().get(&(i as usize)).copied().unwrap()); + + HStack::new(cx, |cx| { + Label::new(cx, item).width(Pixels(50.0)).left(Pixels(10.0)); + Label::new(cx, item); + }) + .font_size(12.0) + .size(Auto); + } +} + #[typetag::serde] impl ViziaComponent for Mem { // create view @@ -23,4 +43,37 @@ impl ViziaComponent for Mem { .height(Pixels(self.height)) .background_color(Color::lightgrey()) } + + fn left_view(&self, cx: &mut Context) { + trace!("---- Create Left Mem View"); + + View::build( + DataMemView { + data: self.memory.clone(), + }, + cx, + |cx| { + Label::new(cx, "Register File") + .left(Pixels(10.0)) + .top(Pixels(10.0)); + + ScrollView::new(cx, 0.0, 0.0, false, true, |cx| { + range_view(cx); + }) + // .size(Units::Pixels(300.0)) + .class("bg-default"); + }, + ); + } +} + +#[derive(Lens, Clone)] +pub struct DataMemView { + data: Memory, +} + +impl View for DataMemView { + fn element(&self) -> Option<&'static str> { + Some("MemView") + } } From 5d341eed1a9c72d62757766a165888193cac13e9 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Mon, 31 Jul 2023 17:52:53 +0200 Subject: [PATCH 03/18] Data Memory left side view functional and formatted, view range is TBD --- src/gui_vizia/components/mem.rs | 47 +++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index df65bba7..eec38e04 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -13,15 +13,46 @@ fn range_view(cx: &mut Context) { end: 0x8000_0020u32, }; for i in range { - let item = DataMemView::data - .map(move |mem: &Memory| mem.0.borrow().get(&(i as usize)).copied().unwrap()); + if i % 4 == 0 { + let item = ( + DataMemView::data.map(move |mem: &Memory| { + format!( + "0x{:02x}", + mem.0.borrow().get(&(i as usize)).copied().unwrap() + ) + }), + DataMemView::data.map(move |mem: &Memory| { + format!( + "{:02x}", + mem.0.borrow().get(&((i + 1) as usize)).copied().unwrap() + ) + }), + DataMemView::data.map(move |mem: &Memory| { + format!( + "{:02x}", + mem.0.borrow().get(&((i + 2) as usize)).copied().unwrap() + ) + }), + DataMemView::data.map(move |mem: &Memory| { + format!( + "{:02x}", + mem.0.borrow().get(&((i + 3) as usize)).copied().unwrap() + ) + }), + ); - HStack::new(cx, |cx| { - Label::new(cx, item).width(Pixels(50.0)).left(Pixels(10.0)); - Label::new(cx, item); - }) - .font_size(12.0) - .size(Auto); + HStack::new(cx, |cx| { + Label::new(cx, &format!("0x{:08x}", i)) + .width(Pixels(100.0)) + .left(Pixels(10.0)); + Label::new(cx, item.0); + Label::new(cx, item.1); + Label::new(cx, item.2); + Label::new(cx, item.3); + }) + .font_size(12.0) + .size(Auto); + } } } From f59b70e6475a75a45432d1b5aca435a48619eabe Mon Sep 17 00:00:00 2001 From: onsdagens Date: Fri, 4 Aug 2023 20:55:42 +0200 Subject: [PATCH 04/18] Add data memory view, slight data memory rework --- examples/data_mem.rs | 6 +- riscv/examples/riscv.rs | 19 +++--- riscv/src/components/decoder.rs | 2 +- riscv/src/components/instr_mem.rs | 11 ++-- src/components/mem.rs | 33 +++++++---- src/gui_vizia/components/mem.rs | 97 +++++++++++++------------------ 6 files changed, 85 insertions(+), 83 deletions(-) diff --git a/examples/data_mem.rs b/examples/data_mem.rs index 73181852..21a25078 100644 --- a/examples/data_mem.rs +++ b/examples/data_mem.rs @@ -1,4 +1,4 @@ -use std::path::PathBuf; +use std::{ops::Range, path::PathBuf}; use syncrim::{ common::{ComponentStore, Input, SignalUnsigned}, components::*, @@ -22,6 +22,10 @@ fn main() { Input::new("ctrl", "out"), Input::new("sext", "out"), Input::new("size", "out"), + Range { + start: 0, + end: 0x20, + }, // later history... tbd ), Constant::rc_new("data", (100.0, 100.0), 3), diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 5af2ae21..03647890 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -3,13 +3,7 @@ use clap::Parser; use fern; use riscv::components::*; use riscv_elf_parse; -use std::{ - cell::RefCell, - collections::{BTreeMap, HashMap}, - fs, - path::PathBuf, - rc::Rc, -}; +use std::{cell::RefCell, collections::BTreeMap, fs, ops::Range, path::PathBuf, rc::Rc}; use syncrim::{ common::{ComponentStore, Input}, components::*, @@ -52,6 +46,15 @@ fn main() { println!("{}", memory); let mut instr_mem = BTreeMap::new(); let mut data_mem = BTreeMap::new(); + + //init data memory with 0's + let range = Range { + start: 0x8000_0000u32, + end: 0x8000_1000u32, + }; + for address in range.clone() { + data_mem.insert(address as usize, 0); + } for element in memory.bytes { if element.0 < 0x5000_0000 { instr_mem.insert(element.0, element.1); @@ -59,6 +62,7 @@ fn main() { data_mem.insert(element.0, element.1); } } + let cs = ComponentStore { store: vec![ Add::rc_new( @@ -186,6 +190,7 @@ fn main() { Input::new("decoder", "data_se"), Input::new("decoder", "data_mem_size"), data_mem, + range, ), // Mem::rc_new_from_bytes( // "data_memory", diff --git a/riscv/src/components/decoder.rs b/riscv/src/components/decoder.rs index bd271238..61516055 100644 --- a/riscv/src/components/decoder.rs +++ b/riscv/src/components/decoder.rs @@ -1660,7 +1660,7 @@ mod test { simulator.clock(); assert_eq!(simulator.get_input_value(wb_mux), 0.into()); assert_eq!(simulator.get_input_value(alu_operand_a_sel), 1.into()); - assert_eq!(simulator.get_input_value(alu_operand_b_sel), 2.into()); + assert_eq!(simulator.get_input_value(alu_operand_b_sel), 3.into()); assert_eq!( simulator.get_input_value(regfile_rs1), SignalValue::Uninitialized diff --git a/riscv/src/components/instr_mem.rs b/riscv/src/components/instr_mem.rs index dd1fdaba..f4ea9615 100644 --- a/riscv/src/components/instr_mem.rs +++ b/riscv/src/components/instr_mem.rs @@ -1,5 +1,5 @@ -use std::collections::BTreeMap; -use asm_riscv; +use asm_riscv::{self}; +use std::{collections::BTreeMap, panic}; use log::trace; use serde::{Deserialize, Serialize}; @@ -37,8 +37,11 @@ impl Component for InstrMem { | (*self.bytes.get(&((pc + 1) as usize)).unwrap() as u32) << 16 | (*self.bytes.get(&((pc + 2) as usize)).unwrap() as u32) << 8 | (*self.bytes.get(&((pc + 3) as usize)).unwrap() as u32); - let instruction = asm_riscv::I::try_from(instr).unwrap(); - trace!("instruction: {:?}", instruction); + //the asm_riscv crate incorrectly panics when trying from instead of + //returning Err, catch it and handle instead + let instruction_fmt = panic::catch_unwind(|| format!("{:?}", asm_riscv::I::from(instr))) + .unwrap_or_else(|_| format!("Unknown instruction")); + trace!("instruction: {}", instruction_fmt); trace!("pc:0x{:08x}", pc); // set output simulator.set_out_value(&self.id, "instruction", instr); diff --git a/src/components/mem.rs b/src/components/mem.rs index 8b922f58..5dd21003 100644 --- a/src/components/mem.rs +++ b/src/components/mem.rs @@ -5,6 +5,7 @@ use log::*; use num_enum::IntoPrimitive; use num_enum::TryFromPrimitive; use serde::{Deserialize, Serialize}; +use std::ops::Range; use std::{cell::RefCell, collections::BTreeMap, convert::TryFrom, rc::Rc}; #[derive(Serialize, Deserialize)] @@ -26,6 +27,7 @@ pub struct Mem { // memory pub(crate) memory: Memory, + pub(crate) range: Range, // later history... tbd } @@ -43,6 +45,7 @@ impl Mem { sext: Input, size: Input, memory: BTreeMap, + range: Range, ) -> Self { Mem { id: id.to_string(), @@ -56,6 +59,7 @@ impl Mem { sext, size, memory: Memory::new(memory), + range, } } @@ -71,19 +75,15 @@ impl Mem { ctrl: Input, sext: Input, size: Input, + range: Range, ) -> Rc { + let mut mem = BTreeMap::new(); + //fill the defined memory range with zeroes + for i in range.clone() { + mem.insert(i as usize, 0u8); + } Rc::new(Mem::new( - id, - pos, - width, - height, - big_endian, - data, - addr, - ctrl, - sext, - size, - BTreeMap::new(), + id, pos, width, height, big_endian, data, addr, ctrl, sext, size, mem, range, )) } @@ -99,9 +99,10 @@ impl Mem { sext: Input, size: Input, memory: BTreeMap, + range: Range, ) -> Rc { Rc::new(Mem::new( - id, pos, width, height, big_endian, data, addr, ctrl, sext, size, memory, + id, pos, width, height, big_endian, data, addr, ctrl, sext, size, memory, range, )) } } @@ -386,6 +387,10 @@ mod test { // memory memory: Memory(Rc::new(RefCell::new(BTreeMap::new()))), + range: Range { + start: 0u32, + end: 1u32, + }, }), ], }; @@ -565,6 +570,10 @@ mod test { // memory memory: Memory(Rc::new(RefCell::new(BTreeMap::new()))), // later history... tbd + range: Range { + start: 0u32, + end: 1u32, + }, }), ], }; diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index eec38e04..1c6e5e7d 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -1,5 +1,3 @@ -use std::ops::Range; - use crate::{ components::{Mem, Memory}, gui_vizia::{ViziaComponent, V}, @@ -7,55 +5,6 @@ use crate::{ use log::*; use vizia::prelude::*; -fn range_view(cx: &mut Context) { - let range = Range { - start: 0x8000_0000u32, - end: 0x8000_0020u32, - }; - for i in range { - if i % 4 == 0 { - let item = ( - DataMemView::data.map(move |mem: &Memory| { - format!( - "0x{:02x}", - mem.0.borrow().get(&(i as usize)).copied().unwrap() - ) - }), - DataMemView::data.map(move |mem: &Memory| { - format!( - "{:02x}", - mem.0.borrow().get(&((i + 1) as usize)).copied().unwrap() - ) - }), - DataMemView::data.map(move |mem: &Memory| { - format!( - "{:02x}", - mem.0.borrow().get(&((i + 2) as usize)).copied().unwrap() - ) - }), - DataMemView::data.map(move |mem: &Memory| { - format!( - "{:02x}", - mem.0.borrow().get(&((i + 3) as usize)).copied().unwrap() - ) - }), - ); - - HStack::new(cx, |cx| { - Label::new(cx, &format!("0x{:08x}", i)) - .width(Pixels(100.0)) - .left(Pixels(10.0)); - Label::new(cx, item.0); - Label::new(cx, item.1); - Label::new(cx, item.2); - Label::new(cx, item.3); - }) - .font_size(12.0) - .size(Auto); - } - } -} - #[typetag::serde] impl ViziaComponent for Mem { // create view @@ -77,22 +26,54 @@ impl ViziaComponent for Mem { fn left_view(&self, cx: &mut Context) { trace!("---- Create Left Mem View"); - View::build( DataMemView { data: self.memory.clone(), }, cx, |cx| { - Label::new(cx, "Register File") + Label::new(cx, "Data Memory") .left(Pixels(10.0)) .top(Pixels(10.0)); - ScrollView::new(cx, 0.0, 0.0, false, true, |cx| { - range_view(cx); - }) - // .size(Units::Pixels(300.0)) - .class("bg-default"); + VirtualList::new( + cx, + DataMemView::data.map(|mem| { + let mut vec = vec![]; + for i in mem.0.borrow().iter() { + if i.0 % 4 == 0 { + vec.push(format!( + "0x{:08x}: 0x{:02x}{:02x}{:02x}{:02x}", + i.0, + i.1, + mem.0 + .borrow() + .get(&((i.0 + 1) as usize)) + .copied() + .unwrap_or_else(|| 0u8), + mem.0 + .borrow() + .get(&((i.0 + 2) as usize)) + .copied() + .unwrap_or_else(|| 0u8), + mem.0 + .borrow() + .get(&((i.0 + 3) as usize)) + .copied() + .unwrap_or_else(|| 0u8) + )); + } + } + vec + }), + 20.0, + |cx, _, item| { + HStack::new(cx, |cx| { + Label::new(cx, item); + }) + .child_left(Pixels(10.0)) + }, + ); }, ); } From c41b18e6d97d4112aa9abab77740f117b920621f Mon Sep 17 00:00:00 2001 From: onsdagens Date: Fri, 4 Aug 2023 20:56:59 +0200 Subject: [PATCH 05/18] Remove unused deps --- riscv/Cargo.toml | 1 - 1 file changed, 1 deletion(-) diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index 03860a20..c43f1db2 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -6,7 +6,6 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -riscv_asm = {path="/home/pawel/riscv_asm/"} serde = "1.0.167" serde_derive = "1.0.167" typetag = "0.2.9" From 8991af08ac85b91261f42b07aaa4ee2a1d05149b Mon Sep 17 00:00:00 2001 From: onsdagens Date: Fri, 4 Aug 2023 20:58:20 +0200 Subject: [PATCH 06/18] Remove loose files --- riscv/disasm.s | 0 riscv/llvm.riscv | 410 ----------------------------------------------- 2 files changed, 410 deletions(-) delete mode 100644 riscv/disasm.s delete mode 100644 riscv/llvm.riscv diff --git a/riscv/disasm.s b/riscv/disasm.s deleted file mode 100644 index e69de29b..00000000 diff --git a/riscv/llvm.riscv b/riscv/llvm.riscv deleted file mode 100644 index 4f721001..00000000 --- a/riscv/llvm.riscv +++ /dev/null @@ -1,410 +0,0 @@ - -llvm.o: file format elf32-littleriscv - -Disassembly of section .strtab: - -00000000 <.strtab>: - 0: 00 2e - 2: 72 65 - 4: 6c 61 - 6: 2e 74 - 8: 65 78 - a: 74 00 - c: 6d 61 - e: 69 6e - 10: 00 70 - 12: 6c 61 - 14: 69 6e - 16: 00 63 - 18: 6f 64 67 65 jal s0, 0x7666e <.strtab+0x7666e> - 1c: 6e 00 - 1e: 64 65 - 20: 63 6f 64 65 bltu s0, s6, 0x67e <.strtab+0x67e> - 24: 00 65 - 26: 6e 64 - 28: 00 73 - 2a: 65 65 - 2c: 64 00 - 2e: 63 6f 64 65 bltu s0, s6, 0x68c <.strtab+0x68c> - 32: 64 00 - 34: 61 62 - 36: 63 00 2e 73 beq t3, s2, 0x756 <.strtab+0x756> - 3a: 74 72 - 3c: 74 61 - 3e: 62 00 - 40: 2e 73 - 42: 79 6d - 44: 74 61 - 46: 62 00 - 48: 2e 64 - 4a: 61 74 - 4c: 61 00 - 4e: 2e 4c - 50: 70 63 - 52: 72 65 - 54: 6c 5f - 56: 68 69 - 58: 32 00 - 5a: 2e 4c - 5c: 70 63 - 5e: 72 65 - 60: 6c 5f - 62: 68 69 - 64: 31 00 - 66: 2e 4c - 68: 70 63 - 6a: 72 65 - 6c: 6c 5f - 6e: 68 69 - 70: 30 00 - -Disassembly of section .text: - -00000000
: - 0: 37 54 06 0e lui s0, 57445 - 4: 13 04 14 7c addi s0, s0, 1985 - -00000008 <.Lpcrel_hi0>: - 8: 97 04 00 00 auipc s1, 0 - c: 93 84 04 00 mv s1, s1 - 10: 23 a0 84 00 sw s0, 0(s1) - -00000014 <.Lpcrel_hi1>: - 14: 17 05 00 00 auipc a0, 0 - 18: 13 05 05 00 mv a0, a0 - -0000001c <.Lpcrel_hi2>: - 1c: 97 05 00 00 auipc a1, 0 - 20: 93 85 05 00 mv a1, a1 - 24: ef 00 80 00 jal 0x2c - -00000028 : - 28: 6f 00 00 00 j 0x28 - -Disassembly of section .rela.text: - -00000000 <.rela.text>: - 0: 08 00 - 2: 00 00 - 4: 17 02 00 00 auipc tp, 0 - 8: 00 00 - a: 00 00 - c: 0c 00 - e: 00 00 - 10: 18 06 - 12: 00 00 - 14: 00 00 - 16: 00 00 - 18: 14 00 - 1a: 00 00 - 1c: 17 04 00 00 auipc s0, 0 - 20: 00 00 - 22: 00 00 - 24: 18 00 - 26: 00 00 - 28: 18 07 - 2a: 00 00 - 2c: 00 00 - 2e: 00 00 - 30: 1c 00 - 32: 00 00 - 34: 17 01 00 00 auipc sp, 0 - 38: 00 00 - 3a: 00 00 - 3c: 20 00 - 3e: 00 00 - 40: 18 08 - 42: 00 00 - 44: 00 00 - 46: 00 00 - -Disassembly of section .data: - -00000000 : - ... - -00000090 : - 90: 00 00 - 92: 00 00 - -00000094 : - 94: 58 91 - 96: dd 9f - 98: 08 58 - 9a: 71 85 - 9c: 3a 32 - 9e: 73 ac 00 00 csrrs s8, ustatus, ra - a2: 00 00 - -000000a4 : - a4: 47 7a 5e 01 - a8: bb 4e f8 2e - ac: b4 8d - ae: 7a 17 - b0: f9 2f - b2: 72 1b - b4: f0 cf - b6: c7 5d a6 de - ba: c9 5d - bc: 5a c1 - be: a0 1d - c0: a2 36 - c2: c2 e4 - c4: d0 b0 - c6: 16 3d - c8: 42 78 - ca: 39 1f - cc: ba d2 - ce: e0 aa - d0: 74 66 - d2: 24 11 - d4: 7f 31 45 08 - d8: ad 2d - da: 51 d5 - dc: 77 49 18 b6 - e0: 3e a5 - e2: 93 d2 16 27 - e6: 9c 7d - e8: e6 ea - ea: 17 d9 84 23 auipc s2, 145485 - ee: 85 d8 - f0: f9 46 - f2: 6e 28 - f4: 29 60 - f6: 56 ce - f8: af 7d fe ce - fc: d4 26 - fe: d7 62 2d eb - 102: ba 0d - 104: 60 7c - 106: f5 95 - 108: 41 51 - 10a: 51 ed - 10c: 0f 7d b7 29 - 110: 0c 8d - 112: 7b 9f 5a 39 - 116: a8 45 - 118: 72 2b - 11a: ad fe - 11c: 4c 43 - 11e: 3d 88 - 120: 60 df - 122: 8d ed - 124: e4 65 - 126: 1e e5 - 128: b1 6b - 12a: bf 19 ec 05 - 12e: b5 fe - 130: 3c a2 - 132: 2a 66 - 134: f8 7c - 136: 82 f6 - 138: 5c 7a - 13a: dc d1 - 13c: 66 b0 - 13e: a5 4f - 140: a4 25 - 142: dd 7d - 144: 8a 8e - 146: ba a8 - 148: 27 62 84 72 - 14c: fb 36 f6 f8 - 150: 9c 9a - 152: 38 2b - 154: f6 8b - 156: 03 e4 77 98 - 15a: 16 6e - 15c: 32 81 - 15e: 02 ad - 160: 8c fe - 162: db 84 ff 62 - 166: 37 24 0c f8 lui s0, 1016002 - 16a: c8 59 - 16c: 4b db e0 b6 - 170: b7 ca b8 ed lui s5, 973708 - 174: f6 39 - 176: 4b cd 41 37 - 17a: 26 af - 17c: 5f 96 d9 18 - 180: 37 f0 b1 1a lui zero, 109343 - 184: 92 87 - 186: 45 5b - 188: 0d 96 - 18a: 4d c9 - 18c: ea ed - 18e: 5c d4 - 190: a3 ac 60 21 sw s6, 537(ra) - 194: 66 77 - 196: c7 93 05 e1 - 19a: 66 2d - 19c: 4f 4d f7 9f - 1a0: 21 2f - 1a2: c2 6d - 1a4: 89 d6 - 1a6: 03 6b e0 8d - 1aa: c4 5f - 1ac: 00 f0 - 1ae: 38 11 - 1b0: 57 8e b5 cc - 1b4: 00 e2 - 1b6: c8 f9 - 1b8: 3c 6e - 1ba: b2 7a - 1bc: 3e cb - 1be: 1d c6 - 1c0: b0 cc - 1c2: ef 6a 05 2f jal s5, 0x564b2 - 1c6: 45 7a - 1c8: 31 07 - 1ca: cf a5 3f 38 - 1ce: 49 a2 - 1d0: 34 e5 - 1d2: 8f 62 10 17 - 1d6: d8 ca - 1d8: 76 62 - 1da: 61 7f - 1dc: 08 83 - 1de: e1 3c - 1e0: ff 57 48 ed - 1e4: d1 b1 - 1e6: e5 d1 - 1e8: c2 4d - 1ea: e8 c2 - 1ec: 42 37 - 1ee: 00 aa - 1f0: 88 74 - 1f2: 63 af 48 fc - 1f6: 1a 83 - 1f8: a0 69 - 1fa: 7a 28 - 1fc: 6e 54 - 1fe: 04 6e - 200: 07 fa df 13 - 204: 10 fb - 206: 32 32 - 208: 09 2e - 20a: 9e d6 - 20c: c7 8d 5d 35 - 210: 01 23 - 212: 90 ef - 214: 15 ac - 216: 89 9a - 218: 00 c9 - 21a: 7d 96 - 21c: 1c 2b - 21e: dc 08 - 220: 90 e6 - 222: 5b 6b 02 0e - 226: 4b 89 af f9 - 22a: 6a e2 - 22c: 23 3b fd a6 - 230: e5 13 - 232: f2 fc - 234: 08 76 - 236: 21 85 - 238: 8b be d3 7f - 23c: fb 57 e7 a2 - 240: 41 a3 - 242: 17 37 6d 42 auipc a4, 272083 - 246: ee 85 - 248: 56 b8 - 24a: 4b 39 c3 98 - 24e: ac 12 - 250: b5 4a - 252: 7d ec - 254: 89 69 - 256: 1b 72 60 63 - 25a: e3 30 03 84 - 25e: 01 aa - 260: 96 11 - 262: e6 9e - 264: dc 7a - 266: 69 a8 - 268: 5a d6 - 26a: e9 51 - 26c: 94 35 - 26e: 02 11 - 270: 6b b3 c4 c4 - 274: 7a bf - 276: 80 da - 278: 5e 64 - 27a: 5a bd - 27c: 18 a9 - 27e: ce 18 - 280: a8 dd - 282: 23 a7 5e c0 sw t0, -1010(t4) - 286: 26 01 - 288: 8a d4 - 28a: 62 29 - 28c: 12 d3 - 28e: f7 d5 41 70 - 292: 94 b8 - 294: 9a 2e - 296: 1e 7c - 298: c3 ea 5e 94 - 29c: 1c fb - 29e: 10 71 - 2a0: cc 72 - 2a2: bc a7 - 2a4: bb df 47 df - 2a8: c8 c6 - 2aa: a1 09 - 2ac: 61 10 - 2ae: e4 c2 - 2b0: 00 00 - 2b2: 00 00 - -Disassembly of section .symtab: - -00000000 <.symtab>: - ... - 10: 11 00 - ... - 1e: 04 00 - 20: 29 00 - 22: 00 00 - 24: 90 00 - ... - 2e: 04 00 - 30: 34 00 - 32: 00 00 - 34: 94 00 - ... - 3e: 04 00 - 40: 2e 00 - 42: 00 00 - 44: a4 00 - ... - 4e: 04 00 - 50: 0c 00 - ... - 5e: 02 00 - 60: 66 00 - 62: 00 00 - 64: 08 00 - ... - 6e: 02 00 - 70: 5a 00 - 72: 00 00 - 74: 14 00 - ... - 7e: 02 00 - 80: 4e 00 - 82: 00 00 - 84: 1c 00 - ... - 8e: 02 00 - 90: 1e 00 - 92: 00 00 - 94: 2c 00 - ... - 9e: 02 00 - a0: 25 00 - a2: 00 00 - a4: 28 00 - ... - ae: 02 00 - b0: 17 00 00 00 auipc zero, 0 - b4: 2c 00 - ... - be: 02 00 From 00b63378287371a1471e95497a9ae3160b131f19 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Fri, 4 Aug 2023 21:58:46 +0200 Subject: [PATCH 07/18] merge --- riscv/examples/riscv.rs | 4 +++- src/components/mem.rs | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index fbbd0bd4..7e7580ea 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -3,7 +3,9 @@ use clap::Parser; use fern; use riscv::components::*; use riscv_elf_parse; -use std::{cell::RefCell, collections::BTreeMap, fs, ops::Range, path::PathBuf, rc::Rc}; +use std::{ + cell::RefCell, collections::BTreeMap, fs, ops::Range, path::PathBuf, process::Command, rc::Rc, +}; use syncrim::{ common::{ComponentStore, Input}, components::*, diff --git a/src/components/mem.rs b/src/components/mem.rs index 378c0beb..f3e82b14 100644 --- a/src/components/mem.rs +++ b/src/components/mem.rs @@ -352,6 +352,8 @@ impl Component for Mem { ) } } + + Ok(()) } } From 5fb624c3bcce3fd462bcc6a0bb782966b343800e Mon Sep 17 00:00:00 2001 From: onsdagens Date: Fri, 4 Aug 2023 22:01:44 +0200 Subject: [PATCH 08/18] Move memory init range to the actual address space --- riscv/examples/riscv.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 7e7580ea..64890382 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -49,8 +49,8 @@ fn main() { //init data memory with 0's let range = Range { - start: 0x8000_0000u32, - end: 0x8000_1000u32, + start: 0x5000_0000u32, + end: 0x5000_1000u32, }; for address in range.clone() { data_mem.insert(address as usize, 0); From 25bdf2bc35476910c912fb102c93082ef82f4e28 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Fri, 4 Aug 2023 22:04:58 +0200 Subject: [PATCH 09/18] Remove random comments, adjust trace to something reasonable --- riscv/examples/riscv.rs | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 64890382..996777ea 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -192,19 +192,6 @@ fn main() { data_mem, range, ), - // Mem::rc_new_from_bytes( - // "data_memory", - // (700.0, 600.0), - // 100.0, - // 100.0, - // false, - // Input::new("reg_file", "reg_b"), - // Input::new("alu", "result_o"), - // Input::new("decoder", "data_mem_ctrl"), - // Input::new("decoder", "data_se"), - // Input::new("decoder", "data_mem_size"), - // data_mem, - // ), Constant::rc_new("zero_c", (680.0, 150.0), 0), Mux::rc_new( "alu_operand_a_mux", @@ -274,13 +261,7 @@ fn fern_setup_riscv() { // - and per-module overrides #[cfg(feature = "gui-vizia")] - let f = f - //.level_for("syncrim::components::mem", LevelFilter::Trace) - //.level_for("riscv::components::instr_mem", LevelFilter::Trace) - .level_for("syncrim::gui_vizia::components::mem", LevelFilter::Trace) - .level_for("riscv::gui_vizia::components::reg_file", LevelFilter::Trace) - //.level_for("riscv::components::alu", LevelFilter::Trace); - .level_for("syncrim::components::mem", LevelFilter::Trace); + let f = f.level_for("riscv::components::instr_mem", LevelFilter::Trace); f // Output to stdout, files, and other Dispatch configurations From d02fbef52922ee24d2db38653bcb5a89f727d286 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Mon, 7 Aug 2023 02:08:06 +0200 Subject: [PATCH 10/18] Performance improvements --- riscv/examples/riscv.rs | 2 +- riscv/src/components/instr_mem.rs | 5 +- src/components/mem.rs | 9 +++ src/gui_vizia/components/mem.rs | 130 +++++++++++++++++++++--------- src/gui_vizia/components/mux.rs | 2 +- 5 files changed, 105 insertions(+), 43 deletions(-) diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 996777ea..6ba028e8 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -50,7 +50,7 @@ fn main() { //init data memory with 0's let range = Range { start: 0x5000_0000u32, - end: 0x5000_1000u32, + end: 0x5000_0500u32, }; for address in range.clone() { data_mem.insert(address as usize, 0); diff --git a/riscv/src/components/instr_mem.rs b/riscv/src/components/instr_mem.rs index 07986e81..eb5d74a6 100644 --- a/riscv/src/components/instr_mem.rs +++ b/riscv/src/components/instr_mem.rs @@ -39,8 +39,9 @@ impl Component for InstrMem { | (*self.bytes.get(&((pc + 3) as usize)).unwrap() as u32); //the asm_riscv crate incorrectly panics when trying from instead of //returning Err, catch it and handle instead - let instruction_fmt = panic::catch_unwind(|| format!("{:?}", asm_riscv::I::from(instr))) - .unwrap_or_else(|_| format!("Unknown instruction")); + let instruction_fmt = + panic::catch_unwind(|| format!("{:?}", asm_riscv::I::try_from(instr))) + .unwrap_or_else(|_| format!("Unknown instruction")); trace!("instruction: {}", instruction_fmt); trace!("pc:0x{:08x}", pc); // set output diff --git a/src/components/mem.rs b/src/components/mem.rs index f3e82b14..6f66e42b 100644 --- a/src/components/mem.rs +++ b/src/components/mem.rs @@ -6,6 +6,7 @@ use log::*; use num_enum::IntoPrimitive; use num_enum::TryFromPrimitive; use serde::{Deserialize, Serialize}; +use std::ops::Deref; use std::ops::Range; use std::{cell::RefCell, collections::BTreeMap, convert::TryFrom, rc::Rc}; @@ -357,6 +358,14 @@ impl Component for Mem { } } +impl Deref for Memory { + type Target = RefCell>; + + fn deref(&self) -> &Self::Target { + &self.0 + } +} + #[cfg(test)] mod test { use super::*; diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index 1c6e5e7d..f152178a 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -1,6 +1,7 @@ use crate::{ + common::Simulator, components::{Mem, Memory}, - gui_vizia::{ViziaComponent, V}, + gui_vizia::{GuiData, ViziaComponent, V}, }; use log::*; use vizia::prelude::*; @@ -26,9 +27,42 @@ impl ViziaComponent for Mem { fn left_view(&self, cx: &mut Context) { trace!("---- Create Left Mem View"); + //We initialize data_slice with the initial state of the memory. + //from now on, data_slice only gets updated over + //the relevant (visible) data interval, and when needed (so only on clock) + //so as to not trigger unneccessary redraws. + let data_slice = { + let mut data_slice = vec![]; + let mem = self.memory.clone(); + for idx in self.range.start as usize..self.range.end as usize { + data_slice.push(format!( + "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", + idx, + mem.0.borrow().get(&idx).copied().unwrap_or_else(|| 0u8), + mem.0 + .borrow() + .get(&(idx + 1)) + .copied() + .unwrap_or_else(|| 0u8), + mem.0 + .borrow() + .get(&(idx + 2)) + .copied() + .unwrap_or_else(|| 0u8), + mem.0 + .borrow() + .get(&(idx + 3)) + .copied() + .unwrap_or_else(|| 0u8) + )); + } + data_slice + }; View::build( DataMemView { data: self.memory.clone(), + start: self.range.start as usize, + data_slice: data_slice, }, cx, |cx| { @@ -36,44 +70,22 @@ impl ViziaComponent for Mem { .left(Pixels(10.0)) .top(Pixels(10.0)); - VirtualList::new( - cx, - DataMemView::data.map(|mem| { - let mut vec = vec![]; - for i in mem.0.borrow().iter() { - if i.0 % 4 == 0 { - vec.push(format!( - "0x{:08x}: 0x{:02x}{:02x}{:02x}{:02x}", - i.0, - i.1, - mem.0 - .borrow() - .get(&((i.0 + 1) as usize)) - .copied() - .unwrap_or_else(|| 0u8), - mem.0 - .borrow() - .get(&((i.0 + 2) as usize)) - .copied() - .unwrap_or_else(|| 0u8), - mem.0 - .borrow() - .get(&((i.0 + 3) as usize)) - .copied() - .unwrap_or_else(|| 0u8) - )); - } - } - vec - }), - 20.0, - |cx, _, item| { - HStack::new(cx, |cx| { - Label::new(cx, item); - }) - .child_left(Pixels(10.0)) - }, - ); + VirtualList::new(cx, DataMemView::data_slice, 20.0, |cx, idx, item| { + HStack::new(cx, |cx| { + //if a value comes into view, update it with fresh data from memory + cx.emit(DataEvent::UpdateVal(idx)); + Label::new(cx, item); + }) + .child_left(Pixels(10.0)) + .bind( + GuiData::simulator.then(Simulator::cycle), + move |mut view, _| { + trace!("Emitting idx {}", idx); + //on clock, update all values in view. + view.context().emit(DataEvent::UpdateVal(idx)); + }, + ) + }); }, ); } @@ -82,10 +94,50 @@ impl ViziaComponent for Mem { #[derive(Lens, Clone)] pub struct DataMemView { data: Memory, + start: usize, + data_slice: Vec, +} + +pub enum DataEvent { + UpdateVal(usize), } impl View for DataMemView { fn element(&self) -> Option<&'static str> { Some("MemView") } + fn event(&mut self, _cx: &mut EventContext, event: &mut Event) { + event.map(|event, _| match event { + DataEvent::UpdateVal(idx) => { + self.data_slice[*idx] = format!( + "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", + idx, + self.data + .0 + .borrow() + .get(&(self.start + idx * 4)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 1)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 2)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 3)) + .copied() + .unwrap_or_else(|| 0u8) + ); + } + }) + } } diff --git a/src/gui_vizia/components/mux.rs b/src/gui_vizia/components/mux.rs index d5f169ce..c92fde74 100644 --- a/src/gui_vizia/components/mux.rs +++ b/src/gui_vizia/components/mux.rs @@ -41,7 +41,7 @@ impl View for MuxView { fn draw(&self, cx: &mut DrawContext<'_>, canvas: &mut Canvas) { let bounds = cx.bounds(); let scale = cx.scale_factor(); - // trace!("Mux draw {:?}", bounds); + //println!("Mux draw {:?}", bounds); let mut path = Path::new(); let mut paint = Paint::color(vizia::vg::Color::rgbf(0.0, 0.0, 0.0)); From acf7a042addc20c033f63f3749a2d90f4d83341e Mon Sep 17 00:00:00 2001 From: Per Lindgren Date: Mon, 7 Aug 2023 11:01:03 +0200 Subject: [PATCH 11/18] mem bugfix --- riscv/examples/riscv.rs | 6 ++- src/gui_vizia/components/mem.rs | 74 ++++++++++++++++++--------------- 2 files changed, 46 insertions(+), 34 deletions(-) diff --git a/riscv/examples/riscv.rs b/riscv/examples/riscv.rs index 6ba028e8..d3c1effe 100644 --- a/riscv/examples/riscv.rs +++ b/riscv/examples/riscv.rs @@ -257,7 +257,11 @@ fn fern_setup_riscv() { }) // Add blanket level filter - // .level(log::LevelFilter::Debug); - .level(log::LevelFilter::Warn); + .level_for( + "syncrim::gui_vizia::components::mem", + log::LevelFilter::Trace, + ) + .level(log::LevelFilter::Error); // - and per-module overrides #[cfg(feature = "gui-vizia")] diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index f152178a..8c254daf 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -13,7 +13,6 @@ impl ViziaComponent for Mem { V::new(cx, self, |cx| { trace!("---- Create Mem View "); Label::new(cx, "DataMemory") - .hoverable(false) .left(Pixels(10.0)) .top(Pixels(10.0)) .hoverable(false) @@ -30,14 +29,17 @@ impl ViziaComponent for Mem { //We initialize data_slice with the initial state of the memory. //from now on, data_slice only gets updated over //the relevant (visible) data interval, and when needed (so only on clock) - //so as to not trigger unneccessary redraws. + //so as to not trigger unnecessary redraws. let data_slice = { let mut data_slice = vec![]; let mem = self.memory.clone(); - for idx in self.range.start as usize..self.range.end as usize { + trace!("range {:x?}", self.range); + for idx in (self.range.start as usize..self.range.end as usize).step_by(4) { + trace!("idx {:x?}", idx); + data_slice.push(format!( "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", - idx, + idx * 4, mem.0.borrow().get(&idx).copied().unwrap_or_else(|| 0u8), mem.0 .borrow() @@ -73,7 +75,7 @@ impl ViziaComponent for Mem { VirtualList::new(cx, DataMemView::data_slice, 20.0, |cx, idx, item| { HStack::new(cx, |cx| { //if a value comes into view, update it with fresh data from memory - cx.emit(DataEvent::UpdateVal(idx)); + // cx.emit(DataEvent::UpdateVal(idx)); Label::new(cx, item); }) .child_left(Pixels(10.0)) @@ -109,34 +111,40 @@ impl View for DataMemView { fn event(&mut self, _cx: &mut EventContext, event: &mut Event) { event.map(|event, _| match event { DataEvent::UpdateVal(idx) => { - self.data_slice[*idx] = format!( - "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", - idx, - self.data - .0 - .borrow() - .get(&(self.start + idx * 4)) - .copied() - .unwrap_or_else(|| 0u8), - self.data - .0 - .borrow() - .get(&(self.start + idx * 4 + 1)) - .copied() - .unwrap_or_else(|| 0u8), - self.data - .0 - .borrow() - .get(&(self.start + idx * 4 + 2)) - .copied() - .unwrap_or_else(|| 0u8), - self.data - .0 - .borrow() - .get(&(self.start + idx * 4 + 3)) - .copied() - .unwrap_or_else(|| 0u8) - ); + trace!("idx {:x}", idx); + if let Some(data_fmt) = self.data_slice.get_mut(*idx) { + *data_fmt = format!( + "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", + idx * 4 + self.start, + self.data + .0 + .borrow() + .get(&(self.start + idx * 4)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 1)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 2)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 3)) + .copied() + .unwrap_or_else(|| 0u8) + ); + } else { + // Why do we end up here, seems wrong + // panic!("Internal error, lookup should always succeed.") + } } }) } From 62b80d84ed259f4b5b89aa3d475a3d431a1a6dcf Mon Sep 17 00:00:00 2001 From: onsdagens Date: Mon, 7 Aug 2023 11:56:43 +0200 Subject: [PATCH 12/18] Fix view address mapping --- src/gui_vizia/components/mem.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index 8c254daf..ddef2f51 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -39,7 +39,7 @@ impl ViziaComponent for Mem { data_slice.push(format!( "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", - idx * 4, + self.range.start as usize + idx * 4, mem.0.borrow().get(&idx).copied().unwrap_or_else(|| 0u8), mem.0 .borrow() @@ -143,7 +143,8 @@ impl View for DataMemView { ); } else { // Why do we end up here, seems wrong - // panic!("Internal error, lookup should always succeed.") + println!("{}", idx); + panic!("Internal error, lookup should always succeed.") } } }) From 04defd9c392fb09c86645fb524d94322916b02e6 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Mon, 7 Aug 2023 17:41:04 +0200 Subject: [PATCH 13/18] Refactor left view using new vizia feature --- Cargo.toml | 1 + src/gui_vizia/components/mem.rs | 105 ++++++++++++++++++-------------- 2 files changed, 60 insertions(+), 46 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index cf3989bd..dcb34bdb 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -24,6 +24,7 @@ typetag = "0.2.10" [dependencies.vizia] git = "https://github.com/vizia/vizia.git" +branch = "virtual-list-update" # path = "../vizia" optional = true diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index ddef2f51..e73f8d15 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -1,3 +1,5 @@ +use std::ops::Range; + use crate::{ common::Simulator, components::{Mem, Memory}, @@ -60,11 +62,13 @@ impl ViziaComponent for Mem { } data_slice }; - View::build( + let view = View::build( DataMemView { data: self.memory.clone(), start: self.range.start as usize, data_slice: data_slice, + //we may init to 0 range, once view opens this will be updated. + slice_range: Range { start: 0, end: 0 }, }, cx, |cx| { @@ -79,16 +83,17 @@ impl ViziaComponent for Mem { Label::new(cx, item); }) .child_left(Pixels(10.0)) - .bind( - GuiData::simulator.then(Simulator::cycle), - move |mut view, _| { - trace!("Emitting idx {}", idx); - //on clock, update all values in view. - view.context().emit(DataEvent::UpdateVal(idx)); - }, - ) + }) + .on_change(|cx, range| { + cx.emit(DataEvent::UpdateSlice(range)); }); }, + ) + .entity(); + Binding::new( + cx, + GuiData::simulator.then(Simulator::cycle), + move |cx, _| cx.emit_to(view, DataEvent::UpdateData), ); } } @@ -98,55 +103,63 @@ pub struct DataMemView { data: Memory, start: usize, data_slice: Vec, + slice_range: Range, } pub enum DataEvent { - UpdateVal(usize), + UpdateData, + UpdateSlice(Range), } impl View for DataMemView { fn element(&self) -> Option<&'static str> { Some("MemView") } - fn event(&mut self, _cx: &mut EventContext, event: &mut Event) { + fn event(&mut self, cx: &mut EventContext, event: &mut Event) { event.map(|event, _| match event { - DataEvent::UpdateVal(idx) => { - trace!("idx {:x}", idx); - if let Some(data_fmt) = self.data_slice.get_mut(*idx) { - *data_fmt = format!( - "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", - idx * 4 + self.start, - self.data - .0 - .borrow() - .get(&(self.start + idx * 4)) - .copied() - .unwrap_or_else(|| 0u8), - self.data - .0 - .borrow() - .get(&(self.start + idx * 4 + 1)) - .copied() - .unwrap_or_else(|| 0u8), - self.data - .0 - .borrow() - .get(&(self.start + idx * 4 + 2)) - .copied() - .unwrap_or_else(|| 0u8), - self.data - .0 - .borrow() - .get(&(self.start + idx * 4 + 3)) - .copied() - .unwrap_or_else(|| 0u8) - ); - } else { - // Why do we end up here, seems wrong - println!("{}", idx); - panic!("Internal error, lookup should always succeed.") + DataEvent::UpdateData => { + for idx in self.slice_range.clone().into_iter() { + if let Some(data_fmt) = self.data_slice.get_mut(idx) { + *data_fmt = format!( + "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", + idx * 4 + self.start, + self.data + .0 + .borrow() + .get(&(self.start + idx * 4)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 1)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 2)) + .copied() + .unwrap_or_else(|| 0u8), + self.data + .0 + .borrow() + .get(&(self.start + idx * 4 + 3)) + .copied() + .unwrap_or_else(|| 0u8) + ); + } else { + // Why do we end up here, seems wrong + println!("{:x}", idx); + panic!("Internal error, lookup should always succeed.") + } } } + DataEvent::UpdateSlice(range) => { + println!("{:?}", range); + self.slice_range = range.clone(); + cx.emit(DataEvent::UpdateData); + } }) } } From 523ad6600259d3301d9603c80778e7fbd5136fbd Mon Sep 17 00:00:00 2001 From: onsdagens Date: Wed, 9 Aug 2023 22:24:45 +0200 Subject: [PATCH 14/18] Improve memory view performance on scroll by only drawing the delta --- riscv/asm.s | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/riscv/asm.s b/riscv/asm.s index 2244c80f..440c89b2 100644 --- a/riscv/asm.s +++ b/riscv/asm.s @@ -226,6 +226,11 @@ main: sw t1, 4(t0) sw t1, 8(t0) sw t1, 12(t0) + li t0, 0x500000F4 # address should be outide of memview range + sw t1, 0(t0) + sw t1, 4(t0) + sw t1, 8(t0) + sw t1, 12(t0) li s0, 0x0e0657c1 # initialize "seed" la s1, seed # initialize "seed" sw s0, 0(s1) From 9662cd7bc047da79664df0b1c9ebd8c942e97562 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Wed, 9 Aug 2023 23:38:37 +0200 Subject: [PATCH 15/18] some improvements --- src/gui_vizia/components/mem.rs | 45 ++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index e73f8d15..e5a9a2e0 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -85,7 +85,7 @@ impl ViziaComponent for Mem { .child_left(Pixels(10.0)) }) .on_change(|cx, range| { - cx.emit(DataEvent::UpdateSlice(range)); + cx.emit(DataEvent::UpdateScroll(range)); }); }, ) @@ -93,7 +93,7 @@ impl ViziaComponent for Mem { Binding::new( cx, GuiData::simulator.then(Simulator::cycle), - move |cx, _| cx.emit_to(view, DataEvent::UpdateData), + move |cx, _| cx.emit_to(view, DataEvent::UpdateClock), ); } } @@ -107,8 +107,9 @@ pub struct DataMemView { } pub enum DataEvent { - UpdateData, - UpdateSlice(Range), + UpdateClock, + UpdateScroll(Range), + UpdateView(Range), } impl View for DataMemView { @@ -117,11 +118,11 @@ impl View for DataMemView { } fn event(&mut self, cx: &mut EventContext, event: &mut Event) { event.map(|event, _| match event { - DataEvent::UpdateData => { - for idx in self.slice_range.clone().into_iter() { + DataEvent::UpdateView(range) => { + for idx in range.clone().into_iter() { if let Some(data_fmt) = self.data_slice.get_mut(idx) { *data_fmt = format!( - "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", + "0x{:08x}: 0x{:02x}{:02x}{:02x}{:02x}", idx * 4 + self.start, self.data .0 @@ -150,15 +151,35 @@ impl View for DataMemView { ); } else { // Why do we end up here, seems wrong - println!("{:x}", idx); panic!("Internal error, lookup should always succeed.") } } } - DataEvent::UpdateSlice(range) => { - println!("{:?}", range); - self.slice_range = range.clone(); - cx.emit(DataEvent::UpdateData); + DataEvent::UpdateClock => cx.emit(DataEvent::UpdateView(self.slice_range.clone())), //update the entire view on clock. + DataEvent::UpdateScroll(new_range) => { + //calculate the "delta" between the view before and after scroll, update that. + let old_range = self.slice_range.clone(); + self.slice_range = new_range.clone(); + let dirty_range_start = if new_range.start < old_range.start { + new_range.start + } else if new_range.start < old_range.end { + old_range.end + } else { + new_range.start + }; + let dirty_range_end = if new_range.end < old_range.start { + new_range.end + } else if new_range.end < old_range.end { + old_range.start + } else { + new_range.end + }; + let dirty_range = Range { + start: dirty_range_start, + end: dirty_range_end, + }; + + cx.emit(DataEvent::UpdateView(dirty_range)) } }) } From 0d57f870feb96eacac9486f7639f10c26625f302 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Wed, 9 Aug 2023 23:43:21 +0200 Subject: [PATCH 16/18] main branch vizia --- Cargo.toml | 1 - 1 file changed, 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index dcb34bdb..cf3989bd 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -24,7 +24,6 @@ typetag = "0.2.10" [dependencies.vizia] git = "https://github.com/vizia/vizia.git" -branch = "virtual-list-update" # path = "../vizia" optional = true From 13b5cb6b61098180bcb9b878df53ef3b70cfa1e4 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Wed, 9 Aug 2023 23:55:15 +0200 Subject: [PATCH 17/18] remove residual file, fix assembly formatting --- riscv/asm.s | 48 ++++++++++++++++++++++++------------------------ riscv/asm.s.old | 40 ---------------------------------------- 2 files changed, 24 insertions(+), 64 deletions(-) delete mode 100644 riscv/asm.s.old diff --git a/riscv/asm.s b/riscv/asm.s index 440c89b2..be51b34f 100644 --- a/riscv/asm.s +++ b/riscv/asm.s @@ -231,11 +231,11 @@ main: sw t1, 4(t0) sw t1, 8(t0) sw t1, 12(t0) - li s0, 0x0e0657c1 # initialize "seed" - la s1, seed # initialize "seed" - sw s0, 0(s1) - la a0, coded # address of start of coded words - la a1, plain # address of start of decoded bytes + li s0, 0x0e0657c1 # initialize "seed" + la s1, seed # initialize "seed" + sw s0, 0(s1) + la a0, coded # address of start of coded words + la a1, plain # address of start of decoded bytes jal ra, codgen jal ra, codgen jal ra, codgen @@ -278,28 +278,28 @@ end: #t2 = x #t3 = y codgen: - la s1, seed - lw s0, 0(s1) - li t0, 1 - li t1, 0 + la s1, seed + lw s0, 0(s1) + li t0, 1 + li t1, 0 loop: - beq t0, x0, continue - and t2, t0, s0 - bne t2, x0, skip - addi t1, t1, 1 + beq t0, x0, continue + and t2, t0, s0 + bne t2, x0, skip + addi t1, t1, 1 skip: - sll t0, t0, 1 - jal x0, loop + sll t0, t0, 1 + jal x0, loop continue: - slli t2, s0, 30 - srli t3, s0, 2 - or t2, t2, t3 #rotate - srai t3, s0, 6 #shift - addi s0, t2, 0 - xor s0, s0, t3 - xor s0, s0, t1 - sw s0, 0(s1) #update seed - jalr x0, ra + slli t2, s0, 30 + srli t3, s0, 2 + or t2, t2, t3 #rotate + srai t3, s0, 6 #shift + addi s0, t2, 0 + xor s0, s0, t3 + xor s0, s0, t1 + sw s0, 0(s1) #update seed + jalr x0, ra diff --git a/riscv/asm.s.old b/riscv/asm.s.old deleted file mode 100644 index caa86360..00000000 --- a/riscv/asm.s.old +++ /dev/null @@ -1,40 +0,0 @@ -.option arch, rv32i -.section .text -.section .init, "ax" -.global _start - -_start: - li x30, 0xffff - sw x30, 0(x0) - lb x8, 0(x0) - addi x1, x0, 0 #x1=0 - jal x2, .+8 - jal x2, .+0 #this is to be jumped over or we will get stuck - jalr x2, x2, 4 - jal x2, .+0 #this is to be jumped over or we will get stuck - addi x2, x0, 16 - addi x1, x0, 0 - addi x1, x1, 4 - bne x1, x2, .-4 - beq x1, x2, .+8 - jal x0, .+0 - addi x1, x0, -8 - addi x2, x0, 0 - addi x1, x1, 4 - blt x1, x2, .-4 - addi x1, x0, -8 - addi x2, x0, 0 - addi x1, x1, 4 - bltu x2, x1, .-4 - addi x1, x0, -8 - addi x2, x0, 0 - addi x1, x1, 4 - bge x2, x1, .-4 - addi x1, x0, -8 - addi x2, x0, 8 - addi x1, x1, 4 - bgeu x1, x2, .-4 - -.section .data -msg: - .string "Hello World\n" From 3d97133b7cd18645785e2027b88604af2d3ce9e9 Mon Sep 17 00:00:00 2001 From: onsdagens Date: Thu, 10 Aug 2023 00:58:06 +0200 Subject: [PATCH 18/18] clippy fixes --- riscv/asm.s | 1 + src/components/mem.rs | 20 ++++-------------- src/gui_vizia/components/mem.rs | 36 ++++++++++----------------------- src/gui_vizia/components/mux.rs | 2 +- 4 files changed, 17 insertions(+), 42 deletions(-) diff --git a/riscv/asm.s b/riscv/asm.s index be51b34f..03f5000d 100644 --- a/riscv/asm.s +++ b/riscv/asm.s @@ -306,6 +306,7 @@ continue: + # ---------------------------------------------------------- # Group 1's assembly code for Function DeCode : # ---------------------------------------------------------- diff --git a/src/components/mem.rs b/src/components/mem.rs index 6f66e42b..96419d36 100644 --- a/src/components/mem.rs +++ b/src/components/mem.rs @@ -334,22 +334,10 @@ impl Component for Mem { trace!( "0x{:08x} : 0x{:02x}{:02x}{:02x}{:02x}", i.0, - self.memory.0.borrow().get(&(i.0)).unwrap_or_else(|| &0u8), - self.memory - .0 - .borrow() - .get(&(i.0 + 1)) - .unwrap_or_else(|| &0u8), - self.memory - .0 - .borrow() - .get(&(i.0 + 2)) - .unwrap_or_else(|| &0u8), - self.memory - .0 - .borrow() - .get(&(i.0 + 3)) - .unwrap_or_else(|| &0u8), + self.memory.0.borrow().get(i.0).unwrap_or(&0u8), + self.memory.0.borrow().get(&(i.0 + 1)).unwrap_or(&0u8), + self.memory.0.borrow().get(&(i.0 + 2)).unwrap_or(&0u8), + self.memory.0.borrow().get(&(i.0 + 3)).unwrap_or(&0u8), ) } } diff --git a/src/gui_vizia/components/mem.rs b/src/gui_vizia/components/mem.rs index e5a9a2e0..1d443380 100644 --- a/src/gui_vizia/components/mem.rs +++ b/src/gui_vizia/components/mem.rs @@ -42,22 +42,10 @@ impl ViziaComponent for Mem { data_slice.push(format!( "0x{:08x}: {:02x}{:02x}{:02x}{:02x}", self.range.start as usize + idx * 4, - mem.0.borrow().get(&idx).copied().unwrap_or_else(|| 0u8), - mem.0 - .borrow() - .get(&(idx + 1)) - .copied() - .unwrap_or_else(|| 0u8), - mem.0 - .borrow() - .get(&(idx + 2)) - .copied() - .unwrap_or_else(|| 0u8), - mem.0 - .borrow() - .get(&(idx + 3)) - .copied() - .unwrap_or_else(|| 0u8) + mem.0.borrow().get(&idx).copied().unwrap_or(0u8), + mem.0.borrow().get(&(idx + 1)).copied().unwrap_or(0u8), + mem.0.borrow().get(&(idx + 2)).copied().unwrap_or(0u8), + mem.0.borrow().get(&(idx + 3)).copied().unwrap_or(0u8), )); } data_slice @@ -66,7 +54,7 @@ impl ViziaComponent for Mem { DataMemView { data: self.memory.clone(), start: self.range.start as usize, - data_slice: data_slice, + data_slice, //we may init to 0 range, once view opens this will be updated. slice_range: Range { start: 0, end: 0 }, }, @@ -76,10 +64,8 @@ impl ViziaComponent for Mem { .left(Pixels(10.0)) .top(Pixels(10.0)); - VirtualList::new(cx, DataMemView::data_slice, 20.0, |cx, idx, item| { + VirtualList::new(cx, DataMemView::data_slice, 20.0, |cx, _, item| { HStack::new(cx, |cx| { - //if a value comes into view, update it with fresh data from memory - // cx.emit(DataEvent::UpdateVal(idx)); Label::new(cx, item); }) .child_left(Pixels(10.0)) @@ -119,7 +105,7 @@ impl View for DataMemView { fn event(&mut self, cx: &mut EventContext, event: &mut Event) { event.map(|event, _| match event { DataEvent::UpdateView(range) => { - for idx in range.clone().into_iter() { + for idx in range.clone() { if let Some(data_fmt) = self.data_slice.get_mut(idx) { *data_fmt = format!( "0x{:08x}: 0x{:02x}{:02x}{:02x}{:02x}", @@ -129,25 +115,25 @@ impl View for DataMemView { .borrow() .get(&(self.start + idx * 4)) .copied() - .unwrap_or_else(|| 0u8), + .unwrap_or(0u8), self.data .0 .borrow() .get(&(self.start + idx * 4 + 1)) .copied() - .unwrap_or_else(|| 0u8), + .unwrap_or(0u8), self.data .0 .borrow() .get(&(self.start + idx * 4 + 2)) .copied() - .unwrap_or_else(|| 0u8), + .unwrap_or(0u8), self.data .0 .borrow() .get(&(self.start + idx * 4 + 3)) .copied() - .unwrap_or_else(|| 0u8) + .unwrap_or(0u8), ); } else { // Why do we end up here, seems wrong diff --git a/src/gui_vizia/components/mux.rs b/src/gui_vizia/components/mux.rs index c92fde74..4821c6e6 100644 --- a/src/gui_vizia/components/mux.rs +++ b/src/gui_vizia/components/mux.rs @@ -41,7 +41,7 @@ impl View for MuxView { fn draw(&self, cx: &mut DrawContext<'_>, canvas: &mut Canvas) { let bounds = cx.bounds(); let scale = cx.scale_factor(); - //println!("Mux draw {:?}", bounds); + trace!("Mux draw {:?}", bounds); let mut path = Path::new(); let mut paint = Paint::color(vizia::vg::Color::rgbf(0.0, 0.0, 0.0));