diff --git a/Counter/Counter.cr.mti b/Counter/Counter.cr.mti new file mode 100644 index 0000000..964e41b --- /dev/null +++ b/Counter/Counter.cr.mti @@ -0,0 +1,15 @@ +C:/Rearch/SIM/Counter/tb_Counter.v {1 {vlog -work work C:/Rearch/SIM/Counter/tb_Counter.v +Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 +-- Compiling module tb_Cnt + +Top level modules: + tb_Cnt + +} {} {}} C:/Rearch/SIM/Counter/Counter.v {1 {vlog -work work C:/Rearch/SIM/Counter/Counter.v +Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 +-- Compiling module Counter + +Top level modules: + Counter + +} {} {}} diff --git a/Counter/Counter.mpf b/Counter/Counter.mpf new file mode 100644 index 0000000..02b7806 --- /dev/null +++ b/Counter/Counter.mpf @@ -0,0 +1,503 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +max = $MODEL_TECH/../altera/vhdl/max +maxii = $MODEL_TECH/../altera/vhdl/maxii +maxv = $MODEL_TECH/../altera/vhdl/maxv +stratix = $MODEL_TECH/../altera/vhdl/stratix +stratixii = $MODEL_TECH/../altera/vhdl/stratixii +stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx +hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii +hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii +hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv +cyclone = $MODEL_TECH/../altera/vhdl/cyclone +cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii +cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii +cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils +sgate = $MODEL_TECH/../altera/vhdl/sgate +stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx +altgxb = $MODEL_TECH/../altera/vhdl/altgxb +stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb +stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi +arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz +arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi +arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip +arriagx = $MODEL_TECH/../altera/vhdl/arriagx +altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive +hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi +hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip +stratixv = $MODEL_TECH/../altera/vhdl/stratixv +stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi +stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip +arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz +arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi +arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip +arriav = $MODEL_TECH/../altera/vhdl/arriav +cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev +twentynm = $MODEL_TECH/../altera/vhdl/twentynm +twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi +twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +max_ver = $MODEL_TECH/../altera/verilog/max +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +maxv_ver = $MODEL_TECH/../altera/verilog/maxv +stratix_ver = $MODEL_TECH/../altera/verilog/stratix +stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii +stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx +arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx +hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii +hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii +hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv +cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone +cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii +cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii +cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx +altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb +stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb +stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi +arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz +arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi +arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip +stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii +stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv +stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi +stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip +arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz +arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi +arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip +arriav_ver = $MODEL_TECH/../altera/verilog/arriav +arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi +arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip +cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev +cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi +cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive +hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi +hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip +twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm +twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi +twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 1 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 3 +Project_File_0 = C:/Rearch/SIM/Counter/tb_Counter.v +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1727783254 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_1 = C:/Rearch/SIM/Counter/Counter.v +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1728460283 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = C:/Rearch/SIM/Counter/FND.v +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1728460288 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 1 diff --git a/Counter/Counter.v b/Counter/Counter.v new file mode 100644 index 0000000..417d859 --- /dev/null +++ b/Counter/Counter.v @@ -0,0 +1,36 @@ +module Counter(i_Clk, i_Rst, i_Push, o_LED, o_FNDA, o_FNDB);//?? ??? ??? ??? ?? + input i_Clk; // 50MHz + input i_Rst; + input [1:0] i_Push; + output wire [3:0] o_LED; + output wire [6:0] o_FNDA; + output wire [6:0] o_FNDB; + + reg [3:0] c_Cnt, n_Cnt; + reg [1:0] c_UpDn, n_UpDn; + + wire fUp; + wire fDn; + + FND FND0(c_Cnt, o_FNDA, o_FNDB); + + always@(posedge i_Clk, posedge i_Rst) + if(i_Rst) begin + c_Cnt = 0; + c_UpDn = 2'b11; + end else begin + c_Cnt = n_Cnt; + c_UpDn = n_UpDn; + end + + assign {fUp, fDn} = ~i_Push & c_UpDn; + assign o_LED = c_Cnt; + + always@* + begin + n_UpDn = i_Push; + n_Cnt = fUp ? c_Cnt + 1 : + fDn ? c_Cnt - 1 : c_Cnt; + end + +endmodule diff --git a/Counter/Counter.v.bak b/Counter/Counter.v.bak new file mode 100644 index 0000000..43f3b2c --- /dev/null +++ b/Counter/Counter.v.bak @@ -0,0 +1,36 @@ +module Counter(i_Clk, i_Rst, i_Push, o_LED, o_FNDA, o_FNDB);//?? ??? ??? ??? ?? + input i_Clk; // 50MHz + input i_Rst; + input [1:0] i_Push; + output wire [3:0] o_LED; + output wire [6:0] o_FNDA; + output wire [15:7] o_FNDB; + + reg [3:0] c_Cnt, n_Cnt; + reg [1:0] c_UpDn, n_UpDn; + + wire fUp; + wire fDn; + + FND FND0(c_Cnt, o_FNDA, o_FNDB); + + always@(posedge i_Clk, posedge i_Rst) + if(i_Rst) begin + c_Cnt = 0; + c_UpDn = 2'b11; + end else begin + c_Cnt = n_Cnt; + c_UpDn = n_UpDn; + end + + assign {fUp, fDn} = ~i_Push & c_UpDn; + assign o_LED = c_Cnt; + + always@* + begin + n_UpDn = i_Push; + n_Cnt = fUp ? c_Cnt + 1 : + fDn ? c_Cnt - 1 : c_Cnt; + end + +endmodule diff --git a/Counter/FND.v b/Counter/FND.v new file mode 100644 index 0000000..6796bcc --- /dev/null +++ b/Counter/FND.v @@ -0,0 +1,37 @@ +module FND(i_NumA, i_NumB, o_FNDA, o_FNDB); + input [3:0] i_NumA; + input [3:0] i_NumB; + output reg [6:0] o_FNDA; + output reg [6:0] o_FNDB; + + always@* + case(i_NumA) + 4'h0: o_FNDA = 7'b1000000; + 4'h1: o_FNDA = 7'b1111001; + 4'h2: o_FNDA = 7'b0100100; + 4'h3: o_FNDA = 7'b0110000; + 4'h4: o_FNDA = 7'b0011001; + 4'h5: o_FNDA = 7'b0010010; + 4'h6: o_FNDA = 7'b0000010; + 4'h7: o_FNDA = 7'b1111000; + 4'h8: o_FNDA = 7'b0000000; + 4'h9: o_FNDA = 7'b0010000; + default: o_FNDA = 7'b1111111; + endcase + + always@* + case(i_NumB) + 4'h0: o_FNDB = 7'b1000000; + 4'h1: o_FNDB = 7'b1111001; + 4'h2: o_FNDB = 7'b0100100; + 4'h3: o_FNDB = 7'b0110000; + 4'h4: o_FNDB = 7'b0011001; + 4'h5: o_FNDB = 7'b0010010; + 4'h6: o_FNDB = 7'b0000010; + 4'h7: o_FNDB = 7'b1111000; + 4'h8: o_FNDB = 7'b0000000; + 4'h9: o_FNDB = 7'b0010000; + default: o_FNDB = 7'b1111111; + endcase + +endmodule \ No newline at end of file diff --git a/Counter/FND.v.bak b/Counter/FND.v.bak new file mode 100644 index 0000000..1fd1aa9 --- /dev/null +++ b/Counter/FND.v.bak @@ -0,0 +1,37 @@ +module FND(i_NumA, i_NumB, o_FNDA, o_FNDB); + input [3:0] i_NumA; + input [3:0] i_NumB; + output reg [6:0] o_FNDA; + output reg [15:0] o_FNDB; + + always@* + case(i_NumA) + 4'h0: o_FNDA = 7'b1000000; + 4'h1: o_FNDA = 7'b1111001; + 4'h2: o_FNDA = 7'b0100100; + 4'h3: o_FNDA = 7'b0110000; + 4'h4: o_FNDA = 7'b0011001; + 4'h5: o_FNDA = 7'b0010010; + 4'h6: o_FNDA = 7'b0000010; + 4'h7: o_FNDA = 7'b1111000; + 4'h8: o_FNDA = 7'b0000000; + 4'h9: o_FNDA = 7'b0010000; + default: o_FNDA = 7'b1111111; + endcase + + always@* + case(i_NumB) + 4'h0: o_FNDB = 7'b1000000; + 4'h1: o_FNDB = 7'b1111001; + 4'h2: o_FNDB = 7'b0100100; + 4'h3: o_FNDB = 7'b0110000; + 4'h4: o_FNDB = 7'b0011001; + 4'h5: o_FNDB = 7'b0010010; + 4'h6: o_FNDB = 7'b0000010; + 4'h7: o_FNDB = 7'b1111000; + 4'h8: o_FNDB = 7'b0000000; + 4'h9: o_FNDB = 7'b0010000; + default: o_FNDB = 7'b1111111; + endcase + +endmodule \ No newline at end of file diff --git a/Counter/qsf_setting.txt b/Counter/qsf_setting.txt new file mode 100644 index 0000000..bacd857 --- /dev/null +++ b/Counter/qsf_setting.txt @@ -0,0 +1,11 @@ +set_location_assignment PIN_AE26 -to o_FND[0] +set_location_assignment PIN_AE27 -to o_FND[1] +set_location_assignment PIN_AE28 -to o_FND[2] +set_location_assignment PIN_AG27 -to o_FND[3] +set_location_assignment PIN_AF28 -to o_FND[4] +set_location_assignment PIN_AG28 -to o_FND[5] +set_location_assignment PIN_AH28 -to o_FND[6] +set_location_assignment PIN_V16 -to o_LED[0] +set_location_assignment PIN_W16 -to o_LED[1] +set_location_assignment PIN_V17 -to o_LED[2] +set_location_assignment PIN_V18 -to o_LED[3] diff --git a/Counter/tb_Counter.v b/Counter/tb_Counter.v new file mode 100644 index 0000000..a2db7ce --- /dev/null +++ b/Counter/tb_Counter.v @@ -0,0 +1,43 @@ +`timescale 1 ns / 1ns +module tb_Cnt(); + reg Clk; + reg Rst; + reg [1:0] Push; + wire[3:0] Cnt_o_LED; + + Counter U0(Clk, Rst, Push, Cnt_o_LED,); + + always + #10 Clk = ~Clk; + + initial + begin + // initialize + Clk = 1; + Rst = 1; + Push = 2'b11; + + // reset + @(posedge Clk) Rst = 1; + @(negedge Clk) Rst = 0; + + // action + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + end +endmodule \ No newline at end of file diff --git a/Counter/tb_Counter.v.bak b/Counter/tb_Counter.v.bak new file mode 100644 index 0000000..a2db7ce --- /dev/null +++ b/Counter/tb_Counter.v.bak @@ -0,0 +1,43 @@ +`timescale 1 ns / 1ns +module tb_Cnt(); + reg Clk; + reg Rst; + reg [1:0] Push; + wire[3:0] Cnt_o_LED; + + Counter U0(Clk, Rst, Push, Cnt_o_LED,); + + always + #10 Clk = ~Clk; + + initial + begin + // initialize + Clk = 1; + Rst = 1; + Push = 2'b11; + + // reset + @(posedge Clk) Rst = 1; + @(negedge Clk) Rst = 0; + + // action + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b01; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + #200 Push = 2'b10; #200 Push = 2'b11; + end +endmodule \ No newline at end of file diff --git a/Counter/vsim.wlf b/Counter/vsim.wlf new file mode 100644 index 0000000..e730a89 Binary files /dev/null and b/Counter/vsim.wlf differ diff --git a/Counter/work/@counter/_primary.dat b/Counter/work/@counter/_primary.dat new file mode 100644 index 0000000..9a978de Binary files /dev/null and b/Counter/work/@counter/_primary.dat differ diff --git a/Counter/work/@counter/_primary.dbs b/Counter/work/@counter/_primary.dbs new file mode 100644 index 0000000..949bffb Binary files /dev/null and b/Counter/work/@counter/_primary.dbs differ diff --git a/Counter/work/@counter/_primary.vhd b/Counter/work/@counter/_primary.vhd new file mode 100644 index 0000000..ca22c1e --- /dev/null +++ b/Counter/work/@counter/_primary.vhd @@ -0,0 +1,12 @@ +library verilog; +use verilog.vl_types.all; +entity Counter is + port( + i_Clk : in vl_logic; + i_Rst : in vl_logic; + i_Push : in vl_logic_vector(1 downto 0); + o_LED : out vl_logic_vector(3 downto 0); + o_FNDA : out vl_logic_vector(6 downto 0); + o_FNDB : out vl_logic_vector(6 downto 0) + ); +end Counter; diff --git a/Counter/work/@counter/verilog.prw b/Counter/work/@counter/verilog.prw new file mode 100644 index 0000000..edf9202 Binary files /dev/null and b/Counter/work/@counter/verilog.prw differ diff --git a/Counter/work/@counter/verilog.psm b/Counter/work/@counter/verilog.psm new file mode 100644 index 0000000..76729d1 Binary files /dev/null and b/Counter/work/@counter/verilog.psm differ diff --git a/Counter/work/@f@n@d/_primary.dat b/Counter/work/@f@n@d/_primary.dat new file mode 100644 index 0000000..bf994a2 Binary files /dev/null and b/Counter/work/@f@n@d/_primary.dat differ diff --git a/Counter/work/@f@n@d/_primary.dbs b/Counter/work/@f@n@d/_primary.dbs new file mode 100644 index 0000000..a1ddd01 Binary files /dev/null and b/Counter/work/@f@n@d/_primary.dbs differ diff --git a/Counter/work/@f@n@d/_primary.vhd b/Counter/work/@f@n@d/_primary.vhd new file mode 100644 index 0000000..2174993 --- /dev/null +++ b/Counter/work/@f@n@d/_primary.vhd @@ -0,0 +1,10 @@ +library verilog; +use verilog.vl_types.all; +entity FND is + port( + i_NumA : in vl_logic_vector(3 downto 0); + i_NumB : in vl_logic_vector(3 downto 0); + o_FNDA : out vl_logic_vector(6 downto 0); + o_FNDB : out vl_logic_vector(6 downto 0) + ); +end FND; diff --git a/Counter/work/@f@n@d/verilog.prw b/Counter/work/@f@n@d/verilog.prw new file mode 100644 index 0000000..f53040b Binary files /dev/null and b/Counter/work/@f@n@d/verilog.prw differ diff --git a/Counter/work/@f@n@d/verilog.psm b/Counter/work/@f@n@d/verilog.psm new file mode 100644 index 0000000..83ed2e6 Binary files /dev/null and b/Counter/work/@f@n@d/verilog.psm differ diff --git a/Counter/work/_info b/Counter/work/_info new file mode 100644 index 0000000..84f3c32 --- /dev/null +++ b/Counter/work/_info @@ -0,0 +1,65 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\Rearch\SIM\verilo_g +vCounter +Z1 !s100 LZkM[DdOj>;[^^6NWG[j<1 +Z2 ISaYFId4mO?a>7bPk@a:RZ0 +Z3 Vh1EIeUXX?F`BoShnFQiDD3 +Z4 dC:\Rearch\SIM\Counter +Z5 w1728460283 +Z6 8C:/Rearch/SIM/Counter/Counter.v +Z7 FC:/Rearch/SIM/Counter/Counter.v +L0 1 +Z8 OV;L;10.1d;51 +r1 +31 +Z9 !s90 -reportprogress|300|-work|work|C:/Rearch/SIM/Counter/Counter.v| +Z10 o-work work -O0 +Z11 n@counter +Z12 !s108 1728460294.164000 +Z13 !s107 C:/Rearch/SIM/Counter/Counter.v| +!i10b 1 +!s85 0 +!s101 -O0 +vFND +Z14 IA@ 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 4 +Project_File_0 = C:/Rearch/SIM/verilo_g/FA.v +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1727702261 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_1 = C:/Rearch/SIM/verilo_g/Add4b.v +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1727702945 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = C:/Rearch/SIM/verilo_g/tb_Add4b.v +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1727707433 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_3 = C:/Rearch/SIM/verilo_g/HA.v +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1727701785 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 1 diff --git a/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.dat b/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.dat new file mode 100644 index 0000000..07eb08d Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.dat differ diff --git a/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.dbs b/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.dbs new file mode 100644 index 0000000..a9d90b3 Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.dbs differ diff --git a/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.vhd b/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.vhd new file mode 100644 index 0000000..95427de --- /dev/null +++ b/Rearch_PH/SIM/verilo_g/work/@add4b/_primary.vhd @@ -0,0 +1,10 @@ +library verilog; +use verilog.vl_types.all; +entity Add4b is + port( + i_A : in vl_logic_vector(3 downto 0); + i_B : in vl_logic_vector(3 downto 0); + o_S : out vl_logic_vector(3 downto 0); + o_C : out vl_logic + ); +end Add4b; diff --git a/Rearch_PH/SIM/verilo_g/work/@add4b/verilog.prw b/Rearch_PH/SIM/verilo_g/work/@add4b/verilog.prw new file mode 100644 index 0000000..1b90741 Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@add4b/verilog.prw differ diff --git a/Rearch_PH/SIM/verilo_g/work/@add4b/verilog.psm b/Rearch_PH/SIM/verilo_g/work/@add4b/verilog.psm new file mode 100644 index 0000000..27d2a23 Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@add4b/verilog.psm differ diff --git a/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.dat b/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.dat new file mode 100644 index 0000000..28990a0 Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.dat differ diff --git a/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.dbs b/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.dbs new file mode 100644 index 0000000..1c25c9b Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.dbs differ diff --git a/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.vhd b/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.vhd new file mode 100644 index 0000000..04bdabc --- /dev/null +++ b/Rearch_PH/SIM/verilo_g/work/@h@a/_primary.vhd @@ -0,0 +1,11 @@ +library verilog; +use verilog.vl_types.all; +entity HA is + port( + i_A : in vl_logic; + i_B : in vl_logic; + i_C : in vl_logic; + o_S : out vl_logic; + o_C : out vl_logic + ); +end HA; diff --git a/Rearch_PH/SIM/verilo_g/work/@h@a/verilog.prw b/Rearch_PH/SIM/verilo_g/work/@h@a/verilog.prw new file mode 100644 index 0000000..b50b693 Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@h@a/verilog.prw differ diff --git a/Rearch_PH/SIM/verilo_g/work/@h@a/verilog.psm b/Rearch_PH/SIM/verilo_g/work/@h@a/verilog.psm new file mode 100644 index 0000000..d82f474 Binary files /dev/null and b/Rearch_PH/SIM/verilo_g/work/@h@a/verilog.psm differ diff --git a/Rearch_PH/SIM/verilo_g/work/_info b/Rearch_PH/SIM/verilo_g/work/_info new file mode 100644 index 0000000..743dbb5 --- /dev/null +++ b/Rearch_PH/SIM/verilo_g/work/_info @@ -0,0 +1,65 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\altera\13.1 +vAdd4b +Z1 !s100 VcaHzB9:Q6dU=ha01Vgko0 +Z2 Iddc6Ce1;mnmO@iIoR[c;[1 +Z3 V`:kDQcn0j02>T^3HmbcgG3 +Z4 dC:\Rearch\SIM\verilo_g +Z5 w1727702945 +Z6 8C:/Rearch/SIM/verilo_g/Add4b.v +Z7 FC:/Rearch/SIM/verilo_g/Add4b.v +L0 1 +Z8 OV;L;10.1d;51 +r1 +31 +Z9 !s90 -reportprogress|300|-work|work|C:/Rearch/SIM/verilo_g/Add4b.v| +Z10 o-work work -O0 +Z11 n@add4b +!i10b 1 +!s85 0 +Z12 !s108 1727707484.583000 +Z13 !s107 C:/Rearch/SIM/verilo_g/Add4b.v| +!s101 -O0 +vHA +Z14 I`?`650LJT5OzdC@`hQjM@3 +Z15 V[@P1>@Z;hIFZ^VP^BenW91 +R4 +Z16 w1727702261 +Z17 8C:/Rearch/SIM/verilo_g/FA.v +Z18 FC:/Rearch/SIM/verilo_g/FA.v +L0 1 +R8 +r1 +31 +R10 +n@h@a +Z19 !s100 zcPOfVX>:Z^a 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 4 +Project_File_0 = C:/Rearch/SIM/verilo_g/FA.v +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1727702261 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_1 = C:/Rearch/SIM/verilo_g/Add4b.v +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1727702945 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_2 = C:/Rearch/SIM/verilo_g/tb_Add4b.v +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1727777056 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_3 = C:/Rearch/SIM/verilo_g/HA.v +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1727701785 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +VRM_DoubleClick = Edit +VRM_CustomDoubleClick = +DEBUGDATABASE_DoubleClick = Edit +DEBUGDATABASE_CustomDoubleClick = +DEBUGARCHIVE_DoubleClick = Edit +DEBUGARCHIVE_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 1 diff --git a/verilo_g/work/@add4b/_primary.dat b/verilo_g/work/@add4b/_primary.dat new file mode 100644 index 0000000..62e3626 Binary files /dev/null and b/verilo_g/work/@add4b/_primary.dat differ diff --git a/verilo_g/work/@add4b/_primary.dbs b/verilo_g/work/@add4b/_primary.dbs new file mode 100644 index 0000000..9a6b5fc Binary files /dev/null and b/verilo_g/work/@add4b/_primary.dbs differ diff --git a/verilo_g/work/@add4b/_primary.vhd b/verilo_g/work/@add4b/_primary.vhd new file mode 100644 index 0000000..95427de --- /dev/null +++ b/verilo_g/work/@add4b/_primary.vhd @@ -0,0 +1,10 @@ +library verilog; +use verilog.vl_types.all; +entity Add4b is + port( + i_A : in vl_logic_vector(3 downto 0); + i_B : in vl_logic_vector(3 downto 0); + o_S : out vl_logic_vector(3 downto 0); + o_C : out vl_logic + ); +end Add4b; diff --git a/verilo_g/work/@add4b/verilog.prw b/verilo_g/work/@add4b/verilog.prw new file mode 100644 index 0000000..1b90741 Binary files /dev/null and b/verilo_g/work/@add4b/verilog.prw differ diff --git a/verilo_g/work/@add4b/verilog.psm b/verilo_g/work/@add4b/verilog.psm new file mode 100644 index 0000000..27d2a23 Binary files /dev/null and b/verilo_g/work/@add4b/verilog.psm differ diff --git a/verilo_g/work/@h@a/_primary.dat b/verilo_g/work/@h@a/_primary.dat new file mode 100644 index 0000000..6ed00f0 Binary files /dev/null and b/verilo_g/work/@h@a/_primary.dat differ diff --git a/verilo_g/work/@h@a/_primary.dbs b/verilo_g/work/@h@a/_primary.dbs new file mode 100644 index 0000000..54941a8 Binary files /dev/null and b/verilo_g/work/@h@a/_primary.dbs differ diff --git a/verilo_g/work/@h@a/_primary.vhd b/verilo_g/work/@h@a/_primary.vhd new file mode 100644 index 0000000..04bdabc --- /dev/null +++ b/verilo_g/work/@h@a/_primary.vhd @@ -0,0 +1,11 @@ +library verilog; +use verilog.vl_types.all; +entity HA is + port( + i_A : in vl_logic; + i_B : in vl_logic; + i_C : in vl_logic; + o_S : out vl_logic; + o_C : out vl_logic + ); +end HA; diff --git a/verilo_g/work/@h@a/verilog.prw b/verilo_g/work/@h@a/verilog.prw new file mode 100644 index 0000000..b50b693 Binary files /dev/null and b/verilo_g/work/@h@a/verilog.prw differ diff --git a/verilo_g/work/@h@a/verilog.psm b/verilo_g/work/@h@a/verilog.psm new file mode 100644 index 0000000..d82f474 Binary files /dev/null and b/verilo_g/work/@h@a/verilog.psm differ diff --git a/verilo_g/work/_info b/verilo_g/work/_info new file mode 100644 index 0000000..24558dd --- /dev/null +++ b/verilo_g/work/_info @@ -0,0 +1,65 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\altera\13.1 +vAdd4b +Z1 !s100 VcaHzB9:Q6dU=ha01Vgko0 +Z2 Iddc6Ce1;mnmO@iIoR[c;[1 +Z3 V`:kDQcn0j02>T^3HmbcgG3 +Z4 dC:\Rearch\SIM\verilo_g +Z5 w1727702945 +Z6 8C:/Rearch/SIM/verilo_g/Add4b.v +Z7 FC:/Rearch/SIM/verilo_g/Add4b.v +L0 1 +Z8 OV;L;10.1d;51 +r1 +31 +Z9 !s90 -reportprogress|300|-work|work|C:/Rearch/SIM/verilo_g/Add4b.v| +Z10 o-work work -O0 +Z11 n@add4b +Z12 !s108 1727710036.993000 +Z13 !s107 C:/Rearch/SIM/verilo_g/Add4b.v| +!i10b 1 +!s85 0 +!s101 -O0 +vHA +Z14 I`?`650LJT5OzdC@`hQjM@3 +Z15 V[@P1>@Z;hIFZ^VP^BenW91 +R4 +Z16 w1727702261 +Z17 8C:/Rearch/SIM/verilo_g/FA.v +Z18 FC:/Rearch/SIM/verilo_g/FA.v +L0 1 +R8 +r1 +31 +R10 +n@h@a +Z19 !s100 zcPOfVX>:Z^a