diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.c index 2b6e3c67..455c5c64 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -7,9 +7,9 @@ * implementation. * */ -#include -#include #include "mpfs_hal/mss_hal.h" +#include "mss_uart_regs.h" +#include "mss_uart.h" #ifdef __cplusplus extern "C" { @@ -62,6 +62,7 @@ static uint32_t g_uart_axi_pos = 0x0u; #define FCR_TRIG_LEVEL_MASK 0xC0u #define IIRF_MASK 0x0Fu +#define IER_MASK 0x0Du #define INVALID_INTERRUPT 0u #define INVALID_IRQ_HANDLER ((mss_uart_irq_handler_t) 0) @@ -439,7 +440,7 @@ MSS_UART_enable_irq { ASSERT(MSS_UART_INVALID_IRQ > irq_mask); - enable_irq(this_uart); + if (MSS_UART_INVALID_IRQ > irq_mask) { @@ -448,10 +449,13 @@ MSS_UART_enable_irq * bit 1 - Transmitter Holding Register Empty Interrupt * bit 2 - Receiver Line Status Interrupt * bit 3 - Modem Status Interrupt + * + * The use of the IER_MASK macro is to prevent the THRE to be + * set at this point of the design flow and to lead to a break + * later on. */ this_uart->hw_reg->IER |= ((uint8_t)(((uint32_t)irq_mask & - (uint32_t)IIRF_MASK))); - + (uint32_t)IER_MASK))); /* * bit 4 - Receiver time-out interrupt @@ -1650,7 +1654,7 @@ uart_isr } /* NACK interrupt */ - if (this_uart->hw_reg->IIM &ENACKI) + if (this_uart->hw_reg->IIM & ENACKI_MASK) { ASSERT(NULL_HANDLER != this_uart->nack_handler); @@ -1661,7 +1665,7 @@ uart_isr } /* PID parity error interrupt */ - if (this_uart->hw_reg->IIM & EPID_PEI) + if (this_uart->hw_reg->IIM & EPID_PEI_MASK) { ASSERT(NULL_HANDLER != this_uart->pid_pei_handler); @@ -1672,7 +1676,7 @@ uart_isr } /* LIN break detection interrupt */ - if (this_uart->hw_reg->IIM & ELINBI) + if (this_uart->hw_reg->IIM & ELINBI_MASK) { ASSERT(NULL_HANDLER != this_uart->break_handler); @@ -1683,7 +1687,7 @@ uart_isr } /* LIN Sync detection interrupt */ - if (this_uart->hw_reg->IIM & ELINSI) + if (this_uart->hw_reg->IIM & ELINSI_MASK) { ASSERT(NULL_HANDLER != this_uart->sync_handler); diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.h index 49e18448..5858c31c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -1573,6 +1573,10 @@ MSS_UART_get_rx Note: You can disable the RDA interrupt when required by calling the MSS_UART_disable_irq() function. This is your choice and is dependent upon your application. + + Note: The trigger level is actually applied only if the this_uart is set + to ready mode 1. See the MSS_UART_set_ready_mode() function for more + information. @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -1685,17 +1689,17 @@ MSS_UART_set_loopback /***************************************************************************//** The MSS_UART_enable_irq() function enables the MSS UART interrupts specified - by the irq_mask parameter. The irq_mask parameter identifies the MSS UART - interrupts by bit position, as defined in the interrupt enable register (IER) - of MSS UART. The MSS UART interrupts and their identifying irq_mask bit - positions are as follows: - When an irq_mask bit position is set to 1, this function enables the - corresponding MSS UART interrupt in the IER register. When an irq_mask bit - position is set to 0, the state of the corresponding interrupt remains - unchanged in the IER register. - - Note: The MSS_UART_enable_irq() function also enables the MSS UART instance - interrupt in the PolarFire SoC Core Complex PLIC. + by the irq_mask parameter. The irq_mask parameter identifies the MSS UART + interrupts by bit position, as defined in the interrupt enable register (IER) + of MSS UART. The MSS UART interrupts and their identifying irq_mask bit + positions are as follows: When an irq_mask bit position is set to 1, this + function enables the corresponding MSS UART interrupt in the IER register. + + Note: the Transmit Buffer Empty interrupt is not enabled in this API. Indeed, + enabling it here leads to an interrupt occuring before any data is passed to + the UART, causing a crash. The TBE bit in the IER register is set + in the MSS_UART_irq_tx() function, that actually starts the transmission. + @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -1732,12 +1736,17 @@ MSS_UART_set_loopback int main(void) { uint8_t tx_buff[10] = "abcdefghi"; + uint32_t interrupt_priority = 4; + enable_interrupts(); + (void) mss_config_clk_rst(MSS_PERIPH_MMUART0, (uint8_t) 1, PERIPHERAL_ON); MSS_UART_init(&g_mss_uart0_lo, - MSS_UART_57600_BAUD, - MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); - - MSS_UART_enable_irq(&g_mss_uart0_lo,(MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + PLIC_init(); + MSS_UART_enable_irq(&g_mss_uart0_lo, (MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + PLIC_SetPriority(MMUART0_PLIC_77, interrupt_priority); + PLIC_SetPriority_Threshold(0); return(0); } @@ -3188,7 +3197,8 @@ MSS_UART_set_address /***************************************************************************//** The MSS_UART_set_ready_mode() function is used to configure the MODE0 or MODE1 to the TXRDY and RXRDY signals of the MSS UART referenced by this_uart - parameter. The mode parameter is used to provide the mode to be configured. + parameter. The mode parameter is used to provide the mode to be configured. + See below for MODE0 and MODE1 description. @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -3204,6 +3214,12 @@ MSS_UART_set_address @param mode The mode parameter is the mss_uart_ready_mode_t type which is used to configure the TXRDY and RXRDY signal modes. + MODE0: RXRDY will go high active when there is at least one character + in the RX FIFO (i.e. the RDA is triggered when there is at least one + character in the RX FIFO). TXRDY will go inactive after the first + character is loaded in the TX FIFO. + MODE1: RXRDY will go active high when the trigger level or the timeout is + reached. TXRDY will go inactive when the TX FIFO is completely full. @return This function does not return a value. diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h index d550810a..bb1561ac 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.c index f3866c46..6e452edc 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.c @@ -1,5 +1,5 @@ /***************************************************************************//** - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -133,7 +133,8 @@ void MSS_SPI_init { uint16_t slave; - ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi1_lo)); +ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi) + || (this_spi == &g_mss_spi1_lo) || (this_spi == &g_mss_spi1_hi)); /* Initialize SPI driver instance data. Relies on the majority * of data requiring 0 for initial state so we just need to fill diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.h index bd264414..e208244b 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/drivers/mss/mss_spi/mss_spi.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/bits.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/bits.h index b347d3d8..9e89d7e9 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/bits.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/bits.h @@ -39,11 +39,11 @@ extern "C" { #define unlikely(x) __builtin_expect((x), 0) #ifndef ROUNDUP -#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +# define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) #endif #ifndef ROUNDDOWN -#define ROUNDDOWN(a, b) ((a)/(b)*(b)) +# define ROUNDDOWN(a, b) ((a)/(b)*(b)) #endif #define MAX(a, b) ((a) > (b) ? (a) : (b)) diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu.c new file mode 100644 index 00000000..c1606bcb --- /dev/null +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu.c @@ -0,0 +1,87 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ +/******************************************************************************* + * @file mss_beu.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolarFire SoC MSS MPU driver for configuring the Bus Error Unit + * + */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#include +#include +#include "mpfs_hal/mss_hal.h" + +/** + * \brief BEU user configuration for BEU enables + * + */ +const uint64_t beu_enable[] = { + LIBERO_SETTING_BEU_ENABLE_HART0, + LIBERO_SETTING_BEU_ENABLE_HART1, + LIBERO_SETTING_BEU_ENABLE_HART2, + LIBERO_SETTING_BEU_ENABLE_HART3, + LIBERO_SETTING_BEU_ENABLE_HART4 +}; + +/** + * \brief BEU user configuration for BEU PLIC enables + * + */ +const uint64_t beu_plic_enable[] = { + LIBERO_SETTING_BEU_PLIC_ENABLE_HART0, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART1, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART2, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART3, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 +}; + +/** + * \brief BEU user configuration for BEU local interrupt enables + * + */ +const uint64_t beu_local_enable[] = { + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 +}; + + +/** + * This function is configured by editing parameters in + * mss_sw_config.h as required. + * @return + */ +__attribute__((weak)) uint8_t init_bus_error_unit(void) +{ + uint8_t hart_id; + /* Init BEU in all harts - enable local interrupt */ + for(hart_id = MPFS_HAL_FIRST_HART; hart_id <= MPFS_HAL_LAST_HART; hart_id++) + { + BEU->regs[hart_id].ENABLE = beu_enable[hart_id]; + BEU->regs[hart_id].PLIC_INT = beu_plic_enable[hart_id]; + BEU->regs[hart_id].LOCAL_INT = beu_local_enable[hart_id]; + BEU->regs[hart_id].CAUSE = 0ULL; + BEU->regs[hart_id].ACCRUED = 0ULL; + BEU->regs[hart_id].VALUE = 0ULL; + } + return (0U); +} + +/** + * This interrupt is called if BEU->regs[hart_id].LOCAL_INT's is enabled. + * If using, instantiate in your code, and add handling of errors as required. + */ +__attribute__((weak)) void handle_local_beu_interrupt(void) +{ +} + diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu.h new file mode 100644 index 00000000..193af6ff --- /dev/null +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu.h @@ -0,0 +1,119 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * + * @file mss_beu.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Bus Error Unit (BEU) user defines and function prototypes + * + */ + +#ifndef MSS_BEU_H +#define MSS_BEU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Default user values. Define these in mss_sw_config.h if you want to change + * from the default. + */ +#ifndef LIBERO_SETTING_BEU_ENABLE_HART0 +#define LIBERO_SETTING_BEU_ENABLE_HART0 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART1 +#define LIBERO_SETTING_BEU_ENABLE_HART1 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART2 +#define LIBERO_SETTING_BEU_ENABLE_HART2 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART3 +#define LIBERO_SETTING_BEU_ENABLE_HART3 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART4 +#define LIBERO_SETTING_BEU_ENABLE_HART4 BEU_ENABLE +#endif + +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 BEU_PLIC_INT +#endif + +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 BEU_LOCAL_INT +#endif + +/***************************************************************************//** + The handle_local_beu_interrupt() function is used to handle local interrupts + generated by the Bus Error Unit (BEU) + + Example: + @code + void handle_local_beu_interrupt(void) + { + uint32_t hart_id = read_csr(mhartid); + + if(BEU->regs[hart_id].CAUSE == ECC2BIT) + { + while(1U); wait for watchdog, or orderly reboot ... + } + // Clear ECC interrupt + BEU->regs[hart_id].CAUSE = 0ULL; + BEU->regs[hart_id].ACCRUED = 0ULL; + BEU->regs[hart_id].VALUE = 0ULL; + } + @endcode + */ +void handle_local_beu_interrupt(void); + +/***************************************************************************//** + The init_bus_error_unit() function is used to setup the Bus Error Unit (BEU) + for all the harts used in the system. Define the defines + (LIBERO_SETTING_BEU_ENABLE_HART0 etc) in mss_sw_config.h if you want to use + non default values. + Example: + @code + when all mem init, call the setup function + init_bus_error_unit(); + @endcode + */ +uint8_t init_bus_error_unit(void); + +#ifdef __cplusplus +} +#endif + +#endif /*MSS_SEG_H*/ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu_def.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu_def.h new file mode 100644 index 00000000..f0d04ec3 --- /dev/null +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_beu_def.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * + * @file mss_beu_def.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Bus Error Unit (BEU) fixed defines + * + */ + +#ifndef MSS_BEU_DEF_H +#define MSS_BEU_DEF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum BEU_event_cause { + BEU_EVENT_NO_ERROR = 0, + BEU_EVENT_RESEVERD1 = 1, + BEU_EVENT_ITIM_CORRECTABLE = 2, + BEU_EVENT_ITIM_UNCORRECTABLE = 3, + BEU_EVENT_RESERVED2 = 4, + BEU_EVENT_TILELINK_BUS_ERROR = 5, + BEU_EVENT_DATA_CACHE_CORRECTABLE = 6, + BEU_EVENT_DATA_CACHE_UNCORRECTABLE = 7, + MAX_BEU_CAUSES = BEU_EVENT_DATA_CACHE_UNCORRECTABLE + 1 +}; + +typedef struct BEU_Type_ +{ + volatile uint64_t CAUSE; /*!< Cause of event, BEU_event_cause{} */ + volatile uint64_t VALUE; /*!< Value of address where issue occurred */ + volatile uint64_t ENABLE; /*!< Enable mask */ + volatile uint64_t PLIC_INT; /*!< PLIC bit enables */ + volatile uint64_t ACCRUED; /*!< events since this was last cleared */ + volatile uint64_t LOCAL_INT; /*!< Local int enables */ + volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)]; +} BEU_Type; + +typedef struct BEU_Types_ +{ + volatile BEU_Type regs[5]; +} BEU_Types; + +#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL +#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL +#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL +#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL +#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL + +#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) + +#ifdef __cplusplus +} +#endif + +#endif /*MSS_SEG_H*/ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_clint.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_clint.c index 63a0413d..43d5baa0 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_clint.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_clint.c @@ -127,7 +127,6 @@ void handle_m_timer_interrupt(void) } - /** * */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_hart_ints.h index ba26cc65..1939c829 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_hart_ints.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_hart_ints.h @@ -25,30 +25,6 @@ extern "C" { #endif -typedef struct BEU_Type_ -{ - volatile uint64_t CAUSE; - volatile uint64_t VALUE; - volatile uint64_t ENABLE; - volatile uint64_t PLIC_INT; - volatile uint64_t ACCRUED; - volatile uint64_t LOCAL_INT; - volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)]; -} BEU_Type; - -typedef struct BEU_Types_ -{ - volatile BEU_Type regs[5]; -} BEU_Types; - -#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL -#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL -#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL -#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL -#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL - -#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) - /* * Local Interrupt offsets for the E51 */ @@ -381,4 +357,3 @@ void U54_f2m_31_local_IRQHandler(void); #endif #endif /* MSS_HART_INTS_H */ - diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_l2_cache.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_l2_cache.c index 3400e751..af4b00ec 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_l2_cache.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_l2_cache.c @@ -20,6 +20,7 @@ #include #include +#include #include "mpfs_hal/mss_hal.h" #include "mss_l2_cache.h" @@ -46,10 +47,9 @@ static void check_config_l2_scratchpad(void); */ __attribute__((weak)) void config_l2_cache(void) { - ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U); - - /* - * confirm the amount of l2lim used in the Linker script has been allocated + static_assert(LIBERO_SETTING_WAY_ENABLE < 16U, "Too many ways"); + /* + * confirm the amount of l2lim used in the Linker script has been allocated * in the MSS Configurator */ ASSERT(((const uint64_t)&__l2lim_end - (const uint64_t)&__l2lim_start)\ @@ -70,12 +70,10 @@ __attribute__((weak)) void config_l2_cache(void) /* If you are not using scratchpad, no need to include the following code */ - ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS); - - + static_assert(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS, "Scratchpad Missing"); /* - * Compute the mask used to specify ways that will be used by the + * Compute the mask (In HSS CONFIG_SERVICE_SCRUB=y) used to specify ways that will be used by the * scratchpad. */ @@ -198,107 +196,3 @@ static void check_config_l2_scratchpad(void) ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways); } - -#if 0 // todo - remove, no longer used - - -/*============================================================================== - * Reserve a number of cache ways to be used as scratchpad memory. - * - * @param nways - * Number of ways to be used as scratchpad. One way is 128Kbytes. - * - * @param scratchpad_start - * Start address within the Zero Device memory range in which the scratchpad - * will be located. - */ -static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) -{ - uint8_t way_enable; - uint64_t available_ways = 1; - uint64_t scratchpad_ways = 0; - uint64_t non_scratchpad_ways; - uint32_t inc; - - ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM); - ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP); - - /* - * Ensure at least one way remains available as cache. - */ - way_enable = CACHE_CTRL->WAY_ENABLE; - ASSERT(nways <= way_enable); - if(nways <= way_enable) - { - /* - * Compute the mask used to specify ways that will be used by the - * scratchpad. - */ - - for(inc = 0; inc < way_enable; ++inc) - { - available_ways = (available_ways << 1) | (uint64_t)0x01; - if(inc < nways) - { - scratchpad_ways = (scratchpad_ways << 1) | (uint64_t)0x01; - } - } - - /* - * Prevent other masters from evicting cache lines from scratchpad ways. - * Only allow E51 to evict from scratchpad ways. - */ - non_scratchpad_ways = available_ways & ~scratchpad_ways; - - CACHE_CTRL->WAY_MASK_DMA = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_E51_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_1_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_1_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_2_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_2_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_3_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_3_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_4_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_4_ICACHE = non_scratchpad_ways; - - /* - * Assign ways to Zero Device - */ - uint64_t * p_scratchpad = scratchpad_start; - int ways_inc; - uint64_t current_way = 1; - for(ways_inc = 0; ways_inc < nways; ++ways_inc) - { - /* - * Populate the scratchpad memory one way at a time. - */ - CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way; - /* - * Write to the first 64-bit location of each cache block. - */ - for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc) - { - *p_scratchpad = g_init_marker + inc; - p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH; - } - current_way = current_way << 1U; - mb(); - } - - /* - * Prevent E51 from evicting from scratchpad ways. - */ - CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways; - } -} -#endif diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.c index e1b8dfa9..27a04ac3 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.c @@ -7,7 +7,7 @@ * */ -/*************************************************************************** +/******************************************************************************* * * @file mss_mtrap.c * @author Microchip-FPGA Embedded Systems Solutions @@ -20,8 +20,6 @@ extern "C" { #endif - - void handle_local_interrupt(uint8_t interrupt_no); void handle_m_soft_interrupt(void); void handle_m_timer_interrupt(void); @@ -32,7 +30,6 @@ void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc); - void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc) { (void)regs; @@ -631,7 +628,7 @@ void handle_m_ext_interrupt(void) } uint8_t disable = EXT_IRQ_KEEP_ENABLED; - disable = ext_irq_handler_table[int_num /* + OFFSET_TO_MSS_GLOBAL_INTS Think this was required in early bitfile */](); + disable = ext_irq_handler_table[int_num](); PLIC_CompleteIRQ(int_num); @@ -662,29 +659,38 @@ void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc) { volatile uintptr_t mcause = read_csr(mcause); - if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) + if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) >=\ + IRQ_M_LOCAL_MIN)&& ((mcause & MCAUSE_CAUSE) <= IRQ_M_LOCAL_MAX)) { handle_local_interrupt((uint8_t)(mcause & MCAUSE_CAUSE)); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_EXT)) { handle_m_ext_interrupt(); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_SOFT)) { handle_m_soft_interrupt(); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_TIMER)) { handle_m_timer_interrupt(); } + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_BEU )) + { + handle_local_beu_interrupt(); + } else { uint32_t i = 0U; - while(1) + while(1U) { /* wait for watchdog */ - i++; /* added some code as SC debugger hangs if in loop doing nothing */ + i++; if(i == 0x1000U) { i = (uint32_t)mcause; /* so mcause is not optimised out */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.h index 3d68eb12..4d201b6b 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_mtrap.h @@ -45,6 +45,10 @@ extern "C" { #define IPI_FENCE_I 0x02 #define IPI_SFENCE_VMA 0x04 +#define IRQ_M_BEU 0x80 +#define IRQ_M_LOCAL_MIN 16 +#define IRQ_M_LOCAL_MAX 63 + #define MACHINE_STACK_SIZE (RISCV_PGSIZE) /* this is 4k for HLS and 4k for the stack*/ #define MENTRY_HLS_OFFSET (INTEGER_CONTEXT_SIZE + SOFT_FLOAT_CONTEXT_SIZE) #define MENTRY_FRAME_SIZE (MENTRY_HLS_OFFSET + HLS_SIZE) diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_plic.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_plic.h index 4e1b31f9..b0083d9d 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_plic.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_plic.h @@ -24,7 +24,6 @@ #include "encoding.h" #endif -#include "mss_legacy_defines.h" #include "mss_assert.h" #ifdef __cplusplus @@ -628,7 +627,7 @@ static inline void PLIC_init(void) break; } - /* Enable PLIC_MMUARTine external interrupts. */ + /* Enable machine external interrupts. */ set_csr(mie, MIP_MEIP); } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_util.c index 938667d2..5e5d503f 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_util.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/mss_util.c @@ -225,4 +225,3 @@ void enable_branch_prediction(void) #ifdef __cplusplus } #endif - diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.c index 381ff41c..c67539a2 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.c @@ -32,8 +32,10 @@ * Local Defines */ /* This string is updated if any change to ddr driver */ -#define DDR_DRIVER_VERSION_STRING "0.4.018" +#define DDR_DRIVER_VERSION_STRING "0.4.019" +const char DDR_DRIVER_VERSION[] = DDR_DRIVER_VERSION_STRING; /* Version | Comment */ +/* 0.4.019 | Added full memory initalization function */ /* 0.4.018 | Corrected error introduced for DDR3 in 0.4.14 */ /* 0.4.017 | made SW_TRAING_BCLK_SCLK_OFFSET seperate for each mem type */ /* 0.4.016 | DDR3-Added support for DDR3L removed in v0.3.027 */ @@ -311,6 +313,7 @@ static uint32_t ddr_setup(void) DDR_TYPE ddr_type; uint32_t ret_status = 0U; uint8_t number_of_lanes_to_calibrate; + uint64_t mem_size; ddr_type = LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_MASK; @@ -837,7 +840,6 @@ static uint32_t ddr_setup(void) /* * We have chosen to use software bclk sclk sweep instead of IP */ - { uint32_t bclk_phase, bclk90_phase,refclk_phase; bclk_answer = 0U; @@ -1106,7 +1108,6 @@ static uint32_t ddr_setup(void) } else { - vref_answer = vref_answer; dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12) | (0x1<<18U); } @@ -1136,7 +1137,7 @@ static uint32_t ddr_setup(void) MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); delay(DELAY_CYCLES_500_NS); } - + #ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, "\n\r Returning FPGA CA VREF & CA drive to user setting.\n\r ", 0x0); #endif @@ -1168,7 +1169,7 @@ static uint32_t ddr_setup(void) /* RX_MD_CLKN */ CFG_DDR_SGMII_PHY->rpc168.rpc168 = 0x0U; } - + #ifdef DDR_TRAINING_IP_SM_START_DELAY delay(DELAY_CYCLES_5_MICRO); #endif @@ -1301,7 +1302,7 @@ static uint32_t ddr_setup(void) } break; case DDR_TRAINING_IP_SM_RDGATE: - /* vrgen, revert temp change during write leveling for lpddr4, + /* vrgen, revert temp change during write leveling for lpddr4, turn back on ODT */ CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS = dpc_bits ; CFG_DDR_SGMII_PHY->rpc3_ODT.rpc3_ODT = LIBERO_SETTING_RPC_ODT_DQ; @@ -1448,7 +1449,7 @@ static uint32_t ddr_setup(void) } #define DCT_EXTRA_CHECKS -#ifdef DCT_EXTRA_CHECKS +#ifdef DCT_EXTRA_CHECKS uint32_t temp = 0U, gt_clk_sel = (CFG_DDR_SGMII_PHY->gt_clk_sel.gt_clk_sel & 3U); if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly)&0xFFU) == 0U) // Gate training tx_dly check: AL { @@ -1870,7 +1871,9 @@ static uint32_t ddr_setup(void) } break; case DDR_LOAD_PATTERN_TO_CACHE: - load_ddr_pattern(LIBERO_SETTING_DDR_32_CACHE, SIZE_OF_PATTERN_TEST*2, SIZE_OF_PATTERN_OFFSET); + load_ddr_pattern(LIBERO_SETTING_DDR_32_CACHE,\ + SIZE_OF_PATTERN_TEST*2, DDR_TEST_FILL,\ + SIZE_OF_PATTERN_OFFSET); if(error == 0U) { ddr_training_state = DDR_VERIFY_PATTERN_IN_CACHE; @@ -1927,7 +1930,7 @@ static uint32_t ddr_setup(void) ddr_training_state = DDR_TRAINING_FAIL; } CFG_DDR_SGMII_PHY->rpc166.rpc166 = rpc_166_fifo_offset; - + /* PAUSE to reset fifo (loads new RXPTR value).*/ //CFG_DDR_SGMII_PHY->expert_dfi_status_override_to_shim.expert_dfi_status_override_to_shim = 0x07U; CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x1U; @@ -2028,6 +2031,33 @@ static uint32_t ddr_setup(void) { ddr_error_count++; } +#endif + ddr_training_state = DDR_TRAINING_INIT_ALL_MEMORY; + break; + + case DDR_TRAINING_INIT_ALL_MEMORY: +#ifdef DEBUG_DDR_INIT + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + (void)uprint64(g_debug_uart, " Init memory, size = , 0x",\ + (uint64_t)mem_size); +#endif + +#ifndef ENABLE_MEM_INIT_NON_ECC + /* Check if using ECC, if so, init all memory */ + if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_ECC_MASK) ==\ + DDRPHY_MODE_ECC_ON) + { + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + load_ddr_pattern(LIBERO_SETTING_DDR_64_NON_CACHE, mem_size,\ + DDR_INIT_FILL, 0U); + } +#else + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + load_ddr_pattern(LIBERO_SETTING_DDR_64_NON_CACHE, mem_size,\ + DDR_INIT_FILL, 0U); #endif ddr_training_state = DDR_TRAINING_FINISH_CHECK; break; @@ -2036,10 +2066,13 @@ static uint32_t ddr_setup(void) /* * return status */ - ddr_diag.train_time = (uint64_t)(rdcycle() - training_start_cycle) / (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK/1000); + ddr_diag.train_time = (uint64_t)(rdcycle() - training_start_cycle)\ + / (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK/1000); #ifdef DEBUG_DDR_INIT - (void)uprint32(g_debug_uart, "\n\r ddr train time (ms): ", (uint32_t)ddr_diag.train_time); - (void)uprint32(g_debug_uart, "\n\r Number of retrains: ", ddr_diag.num_retrains); + (void)uprint32(g_debug_uart, "\n\r ddr train time (ms): ",\ + (uint32_t)ddr_diag.train_time); + (void)uprint32(g_debug_uart, "\n\r Number of retrains: ",\ + ddr_diag.num_retrains); { tip_register_status (g_debug_uart); uprint(g_debug_uart, "\n\r\n\r DDR_TRAINING_PASS: "); @@ -2391,7 +2424,7 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type) */ CFG_DDR_SGMII_PHY->rpc226.rpc226 = 0x14U; CFG_DDR_SGMII_PHY->UNUSED_SPACE0[0] = 0xA000U; - /* for Skew debug at 125C MIN TTHH18->Changing the common mode of the Receiver + /* for Skew debug at 125C MIN TTHH18->Changing the common mode of the Receiver to low common mode to improve IO Performance of LPDDR4 */ CFG_DDR_SGMII_PHY->SPARE0.SPARE0 = 0xA000U; @@ -2612,7 +2645,7 @@ static uint8_t memory_tests(void) mult by (4 lanes) */ { SIM_FEEDBACK1(shift_walking_one); - start_address = (uint64_t)(0xC0000000U + (0x1U< 1G { SIM_FEEDBACK1(shift_walking_one); - start_address = (uint64_t)(0x1400000000U + (0x1U<= 4U) { - start_address = (uint64_t)(0x1400000000U + \ + start_address = (uint64_t)(BASE_ADDRESS_NON_CACHED_64_DDR + \ (((0x1U<<(shift_walking_one +1)) - 1U) -0x0F) ); error = rw_sanity_chk((uint64_t *)start_address , (uint32_t)0x5U); @@ -3591,10 +3624,10 @@ static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC if (mask & 0x1U) { DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFFFFFF00U; - DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; } if (mask & 0x2U) { @@ -4658,6 +4691,7 @@ MSS_DDR_user_commands return error; } #endif + #ifdef DEBUG_DDR_INIT void debug_read_ddrcfg(void) { @@ -4710,6 +4744,7 @@ void debug_read_ddrcfg(void) } #endif + const uint8_t REFCLK_OFFSETS[][5U] = { {LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS, LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0, @@ -5180,7 +5215,6 @@ static void lpddr4_manual_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_ind } else { - vref_answer = vref_answer; dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12) | (0x1<<18U); } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.h index d6c806e6..f75bf85b 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr.h @@ -968,6 +968,7 @@ typedef enum DDR_TRAINING_SM_ DDR_TRAINING_VREFDQ_CALIB, DDR_TRAINING_FPGA_VREFDQ_CALIB, DDR_TRAINING_FINISH_CHECK, + DDR_TRAINING_INIT_ALL_MEMORY, DDR_TRAINING_FINISHED, DDR_TRAINING_FAIL_SM2_VERIFY, DDR_TRAINING_FAIL_SM_VERIFY, diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c index a4710a80..5c8589b0 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c @@ -40,6 +40,7 @@ static uint32_t g_test_buffer_not_cached[765]; * External Defines */ extern const uint32_t ddr_test_pattern[768]; +extern const uint32_t ddr_init_pattern[64U]; /******************************************************************************* * External function declarations @@ -667,18 +668,33 @@ uint32_t tip_register_status (mss_uart_instance_t *g_mss_uart_debug_pt) /** * Load a pattern to DDR */ -void load_ddr_pattern(uint64_t base, uint32_t size, uint8_t pattern_offset) +void load_ddr_pattern(uint64_t base, uint64_t size, uint32_t pattern_type, \ + volatile uint8_t pattern_offset) { int alive = 0; - + uint32_t *pattern; + volatile uint32_t pattern_size; uint8_t *p_ddr = (uint8_t *)base; - uint32_t pattern_length = (uint32_t)(sizeof(ddr_test_pattern) - pattern_offset) ; + + if (pattern_type == DDR_TEST_FILL) + { + pattern = (uint32_t *)ddr_test_pattern; + pattern_size = sizeof(ddr_test_pattern); + } + else + { + pattern = (uint32_t *)ddr_init_pattern; + pattern_size = sizeof(ddr_init_pattern); + } + + uint32_t pattern_length = (uint32_t)(pattern_size - pattern_offset) ; #ifdef DEBUG_DDR_INIT uprint(g_debug_uart, (const char*)(const uint8_t*)"\r\nLoading test pattern\r\n"); + uprint32(g_debug_uart, (const char*)(const uint8_t*)"\r\npattern_length = \r\n",pattern_length); #endif - while(((uint64_t)p_ddr + pattern_length) < (base + size)) + while(((uint64_t)p_ddr + pattern_length) <= (base + size)) { switch ( ((uint64_t)p_ddr)%8U ) @@ -686,22 +702,22 @@ void load_ddr_pattern(uint64_t base, uint32_t size, uint8_t pattern_offset) case 0: case 4: pdma_transfer_complete(PDMA_CHANNEL0_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL0_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL0_BASE_ADDRESS); break; case 1: case 5: pdma_transfer_complete(PDMA_CHANNEL1_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL1_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL1_BASE_ADDRESS); break; case 2: case 6: pdma_transfer_complete(PDMA_CHANNEL2_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL2_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL2_BASE_ADDRESS); break; case 3: case 7: pdma_transfer_complete(PDMA_CHANNEL3_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL3_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL3_BASE_ADDRESS); break; } @@ -763,8 +779,8 @@ static void load_test_buffers(uint32_t * p_cached_ddr, uint32_t * p_not_cached_d uint32_t test_ddr(uint32_t no_of_iterations, uint32_t size) { uint32_t pattern_length = sizeof(ddr_test_pattern) - (3 * sizeof(uint32_t)); - uint32_t * p_ddr_cached = (uint32_t *)0x80000000; - uint32_t * p_ddr_noncached = (uint32_t *)0x1400000000; + uint32_t * p_ddr_cached = (uint32_t *)BASE_ADDRESS_CACHED_32_DDR; + uint32_t * p_ddr_noncached = (uint32_t *)BASE_ADDRESS_NON_CACHED_64_DDR; uint32_t word_offset; uint32_t alive = 0; uint32_t alive_idx = 0U; @@ -812,8 +828,8 @@ uint32_t test_ddr(uint32_t no_of_iterations, uint32_t size) } else { - p_ddr_cached = (uint32_t *)0x80000000; - p_ddr_noncached = (uint32_t *)0x1400000000; + p_ddr_cached = (uint32_t *)BASE_ADDRESS_CACHED_32_DDR; + p_ddr_noncached = (uint32_t *)BASE_ADDRESS_NON_CACHED_64_DDR; iteration++; #ifdef DEBUG_DDR_INIT uprint32(g_debug_uart, " Iteration ", (uint64_t)(unsigned int)iteration); diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h index ea98ea17..3bb0af8a 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h @@ -63,6 +63,12 @@ typedef enum DDR_ACCESS_SIZE_ DDR_64_BIT } DDR_ACCESS_SIZE; +typedef enum DDR_FILL_TYPE_ +{ + DDR_TEST_FILL, + DDR_INIT_FILL +} DDR_FILL_TYPE; + /***************************************************************************//** The ddr_read_write_fn function is used to write/read test patterns to the DDR @@ -230,8 +236,9 @@ void load_ddr_pattern ( uint64_t base, -uint32_t size, -uint8_t pattern_offset +uint64_t size, +uint32_t pattern_type, +volatile uint8_t pattern_offset ); /***************************************************************************//** diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h index 3677ee34..1263bc79 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h @@ -56,4 +56,9 @@ #define DDR_ADD_CMD_A5_OFFSET_FAIL 0x01 #define DDR_ADD_CMD_A5_OFFSET_FAIL_LOW_FREQ 0x04 +#define BASE_ADDRESS_CACHED_32_DDR 0x80000000UL +#define BASE_ADDRESS_NON_CACHED_32_DDR 0xC0000000UL +#define BASE_ADDRESS_CACHED_64_DDR 0x1000000000ULL +#define BASE_ADDRESS_NON_CACHED_64_DDR 0x1400000000ULL + #endif /* SRC_PLATFORM_MPFS_HAL_NWC_MSS_DDR_DEFS_H_ */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c index 2bda43d8..7300c144 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c @@ -205,3 +205,44 @@ const uint32_t ddr_test_pattern[768] = 0x842a8082, 0x651785a6, 0x05130003, 0xa0efa325 }; +#ifdef INIT_PATTERN_ZERO +const uint32_t ddr_init_pattern[64U] = +{ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; +#else +const uint32_t ddr_init_pattern[64U] = +{ + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF +}; +#endif diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io.c index 2e454264..5470aae9 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io.c @@ -272,7 +272,6 @@ static uint8_t io_mux_and_bank_config(void) set_bank2_and_bank4_volts(DEFAULT_MSSIO_CONFIGURATION); - return(0L); } @@ -510,12 +509,12 @@ uint8_t switch_mssio_config(MSS_IO_OPTIONS option) if (mss_is_alternate_io_setting_sd() == true) { io_mux_and_bank_config_alt(); - } else { io_mux_and_bank_config(); } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); break; case EMMC_MSSIO_CONFIGURATION: @@ -527,6 +526,7 @@ uint8_t switch_mssio_config(MSS_IO_OPTIONS option) { io_mux_and_bank_config(); } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); break; case NO_SUPPORT_MSSIO_CONFIGURATION: @@ -545,40 +545,64 @@ uint8_t switch_mssio_config(MSS_IO_OPTIONS option) } /** - * switch_external_mux() - * Requires fpga switch hdl. This comes with reference icicle kit design. + * Is there a mux present, define is true by default + * @return true/false + */ +__attribute__((weak)) uint8_t fabric_sd_emmc_demux_present(void) +{ + return (uint8_t) FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT; +} + +/** + * Returns the fabric mux address + * @return address of the mux in fabric + */ +__attribute__((weak)) uint32_t * fabric_sd_emmc_demux_address(void) +{ + return (uint32_t *)FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS; +} + +/** + * switch_demux_using_fabric_ip() + * Requires fpga switch hdl. This comes with the reference icicle kit design. * You will need to create your own or copy when creating your own fpga design * along with an external mux in your board design if you wish to use SD/eMMC * muxing in your hardware design. * Please note this function will cause a hang if you do not have support - * for switching in your fpga design, nlu use if you have this support if your + * for switching in your fpga design. Only use if you have this support if your * fabric design. * @param option SD_MSSIO_CONFIGURATION/EMMC_MSSIO_CONFIGURATION * @return */ -__attribute__((weak)) uint8_t switch_external_mux(MSS_IO_OPTIONS option) +__attribute__((weak)) uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option) { uint8_t result = false; - volatile uint32_t *reg_pt = (uint32_t *)ICICLE_KIT_REF_DESIGN_FPGS_SWITCH_ADDRESS; - switch(option) + if (fabric_sd_emmc_demux_present() == true) { - case SD_MSSIO_CONFIGURATION: - *reg_pt = 1UL; - break; + volatile uint32_t *reg_pt = fabric_sd_emmc_demux_address(); + switch(option) + { + case SD_MSSIO_CONFIGURATION: + *reg_pt = CMD_SD_EMMC_DEMUX_SD_ON; + break; - case EMMC_MSSIO_CONFIGURATION: - *reg_pt = 0UL; - break; + case EMMC_MSSIO_CONFIGURATION: + *reg_pt = CMD_SD_EMMC_DEMUX_EMMC_ON; + break; - case NO_SUPPORT_MSSIO_CONFIGURATION: - break; + case NO_SUPPORT_MSSIO_CONFIGURATION: + break; - case NOT_SETUP_MSSIO_CONFIGURATION: - break; + case NOT_SETUP_MSSIO_CONFIGURATION: + break; + } + result = true; + } + else + { + result = false; } - result = true; - return result; } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io_config.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io_config.h index bafe18ef..79a60e05 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io_config.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_io_config.h @@ -22,14 +22,28 @@ extern "C" { #endif +#define CMD_SD_EMMC_DEMUX_EMMC_ON 0U +#define CMD_SD_EMMC_DEMUX_SD_ON 1U + /* * fields of LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS * */ -#define EMMC_CONFIGURED_MASK (0x01U<<0U) /*!< set => eMMC is configured */ -#define SD_CONFIGURED_MASK (0x01U<<1U) /*!< set => SD is configured */ -#define DEFAULT_ON_START_MASK (0x01U<<2U) /*!< set => default is SD config, not set default is eMMC config */ - -#define ICICLE_KIT_REF_DESIGN_FPGS_SWITCH_ADDRESS 0x4f000000 +#define EMMC_CONFIGURED_MASK (0x01U<<0U) /*!< set => eMMC is configured */ +#define SD_CONFIGURED_MASK (0x01U<<1U) /*!< set => SD is configured */ +#define DEFAULT_ON_START_MASK (0x01U<<2U) /*!< set => default is SD config, + not set default is eMMC config */ +/* + * Please note in Icicle kit reference design pre 2022.09, the address below + * was 0x4F000000UL + */ +#ifndef FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS +#define FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS 0x4FFFFF00UL /*!< This is design + dependent */ +#endif +#ifndef FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT +#define FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT true /*!< true/false This is design + dependent */ +#endif #if !defined (LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR) /*To limit the number of interrupts fed to the PLINT, the seventy GPIO @@ -315,9 +329,9 @@ set_bank2_and_bank4_volts if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) { - while(1u); + // print warning message + return; } - switch_external_mux(EMMC_MSSIO_CONFIGURATION); g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; @@ -358,9 +372,22 @@ uint8_t mss_does_xml_ver_support_switch(void); @code + // e.g. first try SD, and fail, then try alt config + if ( mss_is_alternate_io_configured() == true ) { - ... + if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) + { + // print warning message + return + } + g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; + g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; + g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; + g_mmc.data_bus_width = MSS_MMC_DATA_WIDTH_4BIT; + g_mmc.bus_voltage = MSS_MMC_1_8V_BUS_VOLTAGE; + + // ... } @endcode @@ -407,10 +434,11 @@ uint8_t mss_is_alternate_io_setting_emmc(void); uint8_t mss_is_alternate_io_setting_sd(void); /***************************************************************************//** - switch_external_mux() + switch_demux_using_fabric_ip() This is a function used to switch external mux. - Requires fpga switch hdl. This comes with reference icicle kit design. - Will need to create your own or copy when creating your own fpga design + It requires fpga switch IP in the fabric. This comes with reference icicle + kit design. + You will need to create your own or copy when creating your own fpga design along with an external mux in your board design if you wish to use SD/eMMC muxing in your hardware design. @@ -418,12 +446,35 @@ uint8_t mss_is_alternate_io_setting_sd(void); @code - switch_external_mux(SD_MSSIO_CONFIGURATION); + case SD_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_sd() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); + break; + + case EMMC_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_emmc() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); + break; + @endcode */ -uint8_t switch_external_mux(MSS_IO_OPTIONS option); +uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option); /***************************************************************************//** mss_io_default_setting() @@ -444,6 +495,51 @@ uint8_t switch_external_mux(MSS_IO_OPTIONS option); */ uint8_t mss_io_default_setting(void); +/***************************************************************************//** + fabric_sd_emmc_demux_present() + + Is there sd_emmc_demux IP present in the fabric. + + @return true/false + + Example: + + @code + + if ( fabric_sd_emmc_demux_present() == true ) + { + // ... + } + + @endcode + + */ +uint8_t fabric_sd_emmc_demux_present(void); + +/***************************************************************************//** + fabric_sd_emmc_demux_address() + + This function is used by the routine switch_demux_using_fabric_ip() + The address returned is a default address, used by the Icicle kit design + post v2022.09. + If another address is used in your Libero design, instantiate this function + in your application, and return the address that matches your Libero design. + + @return returns the address of the sd_emmc_demux in fabric + + Example: + + @code + + volatile uint32_t *reg_pt = fabric_sd_emmc_demux_address(); + + *reg_pt = CMD_SD_EMMC_DEMUX_SD_ON; + + @endcode + + */ +uint32_t * fabric_sd_emmc_demux_address(void); + /***************************************************************************//** This function is used to set the apb_bus_cr register value diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c index 261d929b..27bde361 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c @@ -336,7 +336,7 @@ uint8_t mss_nwc_init_ddr(void) uint32_t ddr_status; ddr_status = ddr_state_machine(DDR_SS__INIT); - next_time = 0U; + next_time = rdcycle() + DELAY_CYCLES_100MS; while((ddr_status & DDR_SETUP_DONE) != DDR_SETUP_DONE) { ddr_status = ddr_state_machine(DDR_SS_MONITOR); @@ -358,7 +358,7 @@ uint8_t mss_nwc_init_ddr(void) */ static uint64_t report_status_functions(MSS_REPORT_STATUS report_status, uint64_t next_time) { - if (next_time >= rdcycle()) + if (next_time <= rdcycle()) { switch(report_status) { diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_pll.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_pll.c index 20401b53..761ef34c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_pll.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/common/nwc/mss_pll.c @@ -195,9 +195,9 @@ static void mss_mux_pre_mss_pll_config(void) * */ volatile uint32_t i; - for(i = 0U; i < 400U; i++) + for(i = 0U; i < 200U; i++) { - i++; + ; //i++; } } @@ -399,7 +399,6 @@ void sgmii_mux_config(uint8_t option) ******************************************************************************/ void mss_pll_config(void) { - copy_switch_code(); /* copy switch code to RAM */ MSS_SCB_DDR_PLL->SOFT_RESET = PLL_INIT_AND_OUT_OF_RESET; @@ -731,6 +730,3 @@ __attribute__((weak)) void copy_switch_code(void) } #endif /* MPFS_HAL_HW_CONFIG */ - - - diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mpfs_hal_version.h index 078fab91..2f4376fb 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mpfs_hal_version.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mpfs_hal_version.h @@ -2,7 +2,7 @@ #define MPFS_HAL_VERSION_H /******************************************************************************* - * Copyright 2019-2022 Microchip Corporation. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -40,8 +40,8 @@ extern "C" { #endif #define MPFS_HAL_VERSION_MAJOR 2 -#define MPFS_HAL_VERSION_MINOR 0 -#define MPFS_HAL_VERSION_PATCH 102 +#define MPFS_HAL_VERSION_MINOR 1 +#define MPFS_HAL_VERSION_PATCH 103 #ifdef __cplusplus } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mss_hal.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mss_hal.h index a493a8e9..7f4fc3a7 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mss_hal.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/mss_hal.h @@ -29,6 +29,7 @@ typedef long ssize_t; #include "common/mss_assert.h" #include "common/mss_legacy_defines.h" +#include "common/mss_beu_def.h" #include "common/nwc/mss_ddr_defs.h" #include "common/nwc/mss_ddr_sgmii_regs.h" #include "common/nwc/mss_io_config.h" @@ -40,19 +41,21 @@ typedef long ssize_t; * mpfs_hal folder */ #include "mpfs_hal_config/mss_sw_config.h" + +#include "common/atomic.h" +#include "common/bits.h" +#include "common/encoding.h" /* - * The hw_platform.h is included here only. It must be included after + * The fpga_design_config.h is included here only. It must be included after * mss_sw_config.h. This allows defines in hw_platform.h be overload from * mss_sw_config.h if necessary. * */ -#include "common/atomic.h" -#include "common/bits.h" -#include "common/encoding.h" #include "fpga_design_config/fpga_design_config.h" #include "common/nwc/mss_ddr.h" #include "common/mss_clint.h" #include "common/mss_h2f.h" #include "common/mss_hart_ints.h" +#include "common/mss_beu.h" #include "common/mss_mpu.h" #include "common/mss_pmp.h" #include "common/mss_plic.h" diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_entry.S index 2fad16b7..b530e05c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_entry.S +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_entry.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2022 Microchip Corporation. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_utils.S b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_utils.S index 482d4b61..4ec8701c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_utils.S +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/mss_utils.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2021 Microchip Corporation. + * Copyright 2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.c b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.c index c95ae5c6..d96cb67a 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.c @@ -601,27 +601,7 @@ __attribute__((weak)) void u54_4(void) } } - /** - * This function is configured by editing parameters in - * mss_sw_config.h as required. - * @return - */ -__attribute__((weak)) uint8_t init_bus_error_unit(void) -{ - uint8_t hart_id; - /* Init BEU in all harts - enable local interrupt */ - for(hart_id = MPFS_HAL_FIRST_HART; hart_id <= MPFS_HAL_LAST_HART; hart_id++) - { - BEU->regs[hart_id].ENABLE = (uint64_t)BEU_ENABLE; - BEU->regs[hart_id].PLIC_INT = (uint64_t)BEU_PLIC_INT; - BEU->regs[hart_id].LOCAL_INT = (uint64_t)BEU_LOCAL_INT; - BEU->regs[hart_id].CAUSE = 0ULL; - BEU->regs[hart_id].ACCRUED = 0ULL; - BEU->regs[hart_id].VALUE = 0ULL; - } - return (0U); -} /** * init_mem_protection_unit(void) diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.h index 7abdaaa7..376b1acd 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup.h @@ -128,7 +128,7 @@ void init_memory( void); void init_ddr( void); uint8_t init_mem_protection_unit(void); uint8_t init_pmp(uint8_t hart_id); -uint8_t init_bus_error_unit( void); + char * memfill(void *dest, const void * src, size_t len); char * config_copy(void *dest, const void * src, size_t len); char * config_16_copy(void *dest, const void * src, size_t len); diff --git a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h index 27e82ae3..6d230661 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-flash/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h @@ -14,7 +14,7 @@ */ #ifndef SYSTEM_STARTUP_DEFS_H -#define SYSTEM_STARTUP_DESF_H +#define SYSTEM_STARTUP_DEFS_H #ifdef __cplusplus extern "C" { @@ -43,4 +43,4 @@ extern "C" { } #endif -#endif /* SYSTEM_STARTUP_DESF_H */ +#endif /* SYSTEM_STARTUP_DEFS_H */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/boards/icicle-kit-es/fpga_design/design_description/MPFS_Icicle_MSS_Linux_SPI_Loopback_cfg.xml b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/boards/icicle-kit-es/fpga_design/design_description/MPFS_Icicle_MSS_Baremetal_SPI_Loopback.xml similarity index 99% rename from driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/boards/icicle-kit-es/fpga_design/design_description/MPFS_Icicle_MSS_Linux_SPI_Loopback_cfg.xml rename to driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/boards/icicle-kit-es/fpga_design/design_description/MPFS_Icicle_MSS_Baremetal_SPI_Loopback.xml index deb0514e..232049fd 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/boards/icicle-kit-es/fpga_design/design_description/MPFS_Icicle_MSS_Linux_SPI_Loopback_cfg.xml +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/boards/icicle-kit-es/fpga_design/design_description/MPFS_Icicle_MSS_Baremetal_SPI_Loopback.xml @@ -4,7 +4,7 @@ ICICLE_MSS MPFS250T_ES FCVG484 - 08-08-2022_14:13:38 + 08-08-2022_14:48:56 0.6.5 @@ -2358,7 +2358,7 @@ 0x1 - 0x7002 + 0x7030 0x0 0x1 @@ -2403,7 +2403,7 @@ 0x0 - 0x7FB8 + 0x7FB0 0x0 0x1 @@ -2413,7 +2413,7 @@ 0x1 - 0x7FA8 + 0x7FA0 0x0 0x1 diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.c index 2b6e3c67..4cfe5d5c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -7,9 +7,10 @@ * implementation. * */ -#include -#include + #include "mpfs_hal/mss_hal.h" +#include "mss_uart_regs.h" +#include "mss_uart.h" #ifdef __cplusplus extern "C" { @@ -62,6 +63,7 @@ static uint32_t g_uart_axi_pos = 0x0u; #define FCR_TRIG_LEVEL_MASK 0xC0u #define IIRF_MASK 0x0Fu +#define IER_MASK 0x0Du #define INVALID_INTERRUPT 0u #define INVALID_IRQ_HANDLER ((mss_uart_irq_handler_t) 0) @@ -439,7 +441,7 @@ MSS_UART_enable_irq { ASSERT(MSS_UART_INVALID_IRQ > irq_mask); - enable_irq(this_uart); + if (MSS_UART_INVALID_IRQ > irq_mask) { @@ -448,10 +450,13 @@ MSS_UART_enable_irq * bit 1 - Transmitter Holding Register Empty Interrupt * bit 2 - Receiver Line Status Interrupt * bit 3 - Modem Status Interrupt + * + * The use of the IER_MASK macro is to prevent the THRE to be + * set at this point of the design flow and to lead to a break + * later on. */ this_uart->hw_reg->IER |= ((uint8_t)(((uint32_t)irq_mask & - (uint32_t)IIRF_MASK))); - + (uint32_t)IER_MASK))); /* * bit 4 - Receiver time-out interrupt @@ -1650,7 +1655,7 @@ uart_isr } /* NACK interrupt */ - if (this_uart->hw_reg->IIM &ENACKI) + if (this_uart->hw_reg->IIM & ENACKI_MASK) { ASSERT(NULL_HANDLER != this_uart->nack_handler); @@ -1661,7 +1666,7 @@ uart_isr } /* PID parity error interrupt */ - if (this_uart->hw_reg->IIM & EPID_PEI) + if (this_uart->hw_reg->IIM & EPID_PEI_MASK) { ASSERT(NULL_HANDLER != this_uart->pid_pei_handler); @@ -1672,7 +1677,7 @@ uart_isr } /* LIN break detection interrupt */ - if (this_uart->hw_reg->IIM & ELINBI) + if (this_uart->hw_reg->IIM & ELINBI_MASK) { ASSERT(NULL_HANDLER != this_uart->break_handler); @@ -1683,7 +1688,7 @@ uart_isr } /* LIN Sync detection interrupt */ - if (this_uart->hw_reg->IIM & ELINSI) + if (this_uart->hw_reg->IIM & ELINSI_MASK) { ASSERT(NULL_HANDLER != this_uart->sync_handler); diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.h index 49e18448..5858c31c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -1573,6 +1573,10 @@ MSS_UART_get_rx Note: You can disable the RDA interrupt when required by calling the MSS_UART_disable_irq() function. This is your choice and is dependent upon your application. + + Note: The trigger level is actually applied only if the this_uart is set + to ready mode 1. See the MSS_UART_set_ready_mode() function for more + information. @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -1685,17 +1689,17 @@ MSS_UART_set_loopback /***************************************************************************//** The MSS_UART_enable_irq() function enables the MSS UART interrupts specified - by the irq_mask parameter. The irq_mask parameter identifies the MSS UART - interrupts by bit position, as defined in the interrupt enable register (IER) - of MSS UART. The MSS UART interrupts and their identifying irq_mask bit - positions are as follows: - When an irq_mask bit position is set to 1, this function enables the - corresponding MSS UART interrupt in the IER register. When an irq_mask bit - position is set to 0, the state of the corresponding interrupt remains - unchanged in the IER register. - - Note: The MSS_UART_enable_irq() function also enables the MSS UART instance - interrupt in the PolarFire SoC Core Complex PLIC. + by the irq_mask parameter. The irq_mask parameter identifies the MSS UART + interrupts by bit position, as defined in the interrupt enable register (IER) + of MSS UART. The MSS UART interrupts and their identifying irq_mask bit + positions are as follows: When an irq_mask bit position is set to 1, this + function enables the corresponding MSS UART interrupt in the IER register. + + Note: the Transmit Buffer Empty interrupt is not enabled in this API. Indeed, + enabling it here leads to an interrupt occuring before any data is passed to + the UART, causing a crash. The TBE bit in the IER register is set + in the MSS_UART_irq_tx() function, that actually starts the transmission. + @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -1732,12 +1736,17 @@ MSS_UART_set_loopback int main(void) { uint8_t tx_buff[10] = "abcdefghi"; + uint32_t interrupt_priority = 4; + enable_interrupts(); + (void) mss_config_clk_rst(MSS_PERIPH_MMUART0, (uint8_t) 1, PERIPHERAL_ON); MSS_UART_init(&g_mss_uart0_lo, - MSS_UART_57600_BAUD, - MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); - - MSS_UART_enable_irq(&g_mss_uart0_lo,(MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + PLIC_init(); + MSS_UART_enable_irq(&g_mss_uart0_lo, (MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + PLIC_SetPriority(MMUART0_PLIC_77, interrupt_priority); + PLIC_SetPriority_Threshold(0); return(0); } @@ -3188,7 +3197,8 @@ MSS_UART_set_address /***************************************************************************//** The MSS_UART_set_ready_mode() function is used to configure the MODE0 or MODE1 to the TXRDY and RXRDY signals of the MSS UART referenced by this_uart - parameter. The mode parameter is used to provide the mode to be configured. + parameter. The mode parameter is used to provide the mode to be configured. + See below for MODE0 and MODE1 description. @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -3204,6 +3214,12 @@ MSS_UART_set_address @param mode The mode parameter is the mss_uart_ready_mode_t type which is used to configure the TXRDY and RXRDY signal modes. + MODE0: RXRDY will go high active when there is at least one character + in the RX FIFO (i.e. the RDA is triggered when there is at least one + character in the RX FIFO). TXRDY will go inactive after the first + character is loaded in the TX FIFO. + MODE1: RXRDY will go active high when the trigger level or the timeout is + reached. TXRDY will go inactive when the TX FIFO is completely full. @return This function does not return a value. diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h index d550810a..6ffe10c6 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.c index f3866c46..6e452edc 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.c @@ -1,5 +1,5 @@ /***************************************************************************//** - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -133,7 +133,8 @@ void MSS_SPI_init { uint16_t slave; - ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi1_lo)); +ASSERT((this_spi == &g_mss_spi0_lo) || (this_spi == &g_mss_spi0_hi) + || (this_spi == &g_mss_spi1_lo) || (this_spi == &g_mss_spi1_hi)); /* Initialize SPI driver instance data. Relies on the majority * of data requiring 0 for initial state so we just need to fill diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.h index bd264414..e208244b 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/drivers/mss/mss_spi/mss_spi.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/bits.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/bits.h index b347d3d8..9e89d7e9 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/bits.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/bits.h @@ -39,11 +39,11 @@ extern "C" { #define unlikely(x) __builtin_expect((x), 0) #ifndef ROUNDUP -#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +# define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) #endif #ifndef ROUNDDOWN -#define ROUNDDOWN(a, b) ((a)/(b)*(b)) +# define ROUNDDOWN(a, b) ((a)/(b)*(b)) #endif #define MAX(a, b) ((a) > (b) ? (a) : (b)) diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu.c new file mode 100644 index 00000000..c1606bcb --- /dev/null +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu.c @@ -0,0 +1,87 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ +/******************************************************************************* + * @file mss_beu.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolarFire SoC MSS MPU driver for configuring the Bus Error Unit + * + */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#include +#include +#include "mpfs_hal/mss_hal.h" + +/** + * \brief BEU user configuration for BEU enables + * + */ +const uint64_t beu_enable[] = { + LIBERO_SETTING_BEU_ENABLE_HART0, + LIBERO_SETTING_BEU_ENABLE_HART1, + LIBERO_SETTING_BEU_ENABLE_HART2, + LIBERO_SETTING_BEU_ENABLE_HART3, + LIBERO_SETTING_BEU_ENABLE_HART4 +}; + +/** + * \brief BEU user configuration for BEU PLIC enables + * + */ +const uint64_t beu_plic_enable[] = { + LIBERO_SETTING_BEU_PLIC_ENABLE_HART0, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART1, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART2, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART3, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 +}; + +/** + * \brief BEU user configuration for BEU local interrupt enables + * + */ +const uint64_t beu_local_enable[] = { + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 +}; + + +/** + * This function is configured by editing parameters in + * mss_sw_config.h as required. + * @return + */ +__attribute__((weak)) uint8_t init_bus_error_unit(void) +{ + uint8_t hart_id; + /* Init BEU in all harts - enable local interrupt */ + for(hart_id = MPFS_HAL_FIRST_HART; hart_id <= MPFS_HAL_LAST_HART; hart_id++) + { + BEU->regs[hart_id].ENABLE = beu_enable[hart_id]; + BEU->regs[hart_id].PLIC_INT = beu_plic_enable[hart_id]; + BEU->regs[hart_id].LOCAL_INT = beu_local_enable[hart_id]; + BEU->regs[hart_id].CAUSE = 0ULL; + BEU->regs[hart_id].ACCRUED = 0ULL; + BEU->regs[hart_id].VALUE = 0ULL; + } + return (0U); +} + +/** + * This interrupt is called if BEU->regs[hart_id].LOCAL_INT's is enabled. + * If using, instantiate in your code, and add handling of errors as required. + */ +__attribute__((weak)) void handle_local_beu_interrupt(void) +{ +} + diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu.h new file mode 100644 index 00000000..193af6ff --- /dev/null +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu.h @@ -0,0 +1,119 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * + * @file mss_beu.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Bus Error Unit (BEU) user defines and function prototypes + * + */ + +#ifndef MSS_BEU_H +#define MSS_BEU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Default user values. Define these in mss_sw_config.h if you want to change + * from the default. + */ +#ifndef LIBERO_SETTING_BEU_ENABLE_HART0 +#define LIBERO_SETTING_BEU_ENABLE_HART0 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART1 +#define LIBERO_SETTING_BEU_ENABLE_HART1 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART2 +#define LIBERO_SETTING_BEU_ENABLE_HART2 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART3 +#define LIBERO_SETTING_BEU_ENABLE_HART3 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART4 +#define LIBERO_SETTING_BEU_ENABLE_HART4 BEU_ENABLE +#endif + +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 BEU_PLIC_INT +#endif + +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 BEU_LOCAL_INT +#endif + +/***************************************************************************//** + The handle_local_beu_interrupt() function is used to handle local interrupts + generated by the Bus Error Unit (BEU) + + Example: + @code + void handle_local_beu_interrupt(void) + { + uint32_t hart_id = read_csr(mhartid); + + if(BEU->regs[hart_id].CAUSE == ECC2BIT) + { + while(1U); wait for watchdog, or orderly reboot ... + } + // Clear ECC interrupt + BEU->regs[hart_id].CAUSE = 0ULL; + BEU->regs[hart_id].ACCRUED = 0ULL; + BEU->regs[hart_id].VALUE = 0ULL; + } + @endcode + */ +void handle_local_beu_interrupt(void); + +/***************************************************************************//** + The init_bus_error_unit() function is used to setup the Bus Error Unit (BEU) + for all the harts used in the system. Define the defines + (LIBERO_SETTING_BEU_ENABLE_HART0 etc) in mss_sw_config.h if you want to use + non default values. + Example: + @code + when all mem init, call the setup function + init_bus_error_unit(); + @endcode + */ +uint8_t init_bus_error_unit(void); + +#ifdef __cplusplus +} +#endif + +#endif /*MSS_SEG_H*/ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu_def.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu_def.h new file mode 100644 index 00000000..f0d04ec3 --- /dev/null +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_beu_def.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * + * @file mss_beu_def.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Bus Error Unit (BEU) fixed defines + * + */ + +#ifndef MSS_BEU_DEF_H +#define MSS_BEU_DEF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum BEU_event_cause { + BEU_EVENT_NO_ERROR = 0, + BEU_EVENT_RESEVERD1 = 1, + BEU_EVENT_ITIM_CORRECTABLE = 2, + BEU_EVENT_ITIM_UNCORRECTABLE = 3, + BEU_EVENT_RESERVED2 = 4, + BEU_EVENT_TILELINK_BUS_ERROR = 5, + BEU_EVENT_DATA_CACHE_CORRECTABLE = 6, + BEU_EVENT_DATA_CACHE_UNCORRECTABLE = 7, + MAX_BEU_CAUSES = BEU_EVENT_DATA_CACHE_UNCORRECTABLE + 1 +}; + +typedef struct BEU_Type_ +{ + volatile uint64_t CAUSE; /*!< Cause of event, BEU_event_cause{} */ + volatile uint64_t VALUE; /*!< Value of address where issue occurred */ + volatile uint64_t ENABLE; /*!< Enable mask */ + volatile uint64_t PLIC_INT; /*!< PLIC bit enables */ + volatile uint64_t ACCRUED; /*!< events since this was last cleared */ + volatile uint64_t LOCAL_INT; /*!< Local int enables */ + volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)]; +} BEU_Type; + +typedef struct BEU_Types_ +{ + volatile BEU_Type regs[5]; +} BEU_Types; + +#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL +#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL +#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL +#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL +#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL + +#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) + +#ifdef __cplusplus +} +#endif + +#endif /*MSS_SEG_H*/ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_clint.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_clint.c index 63a0413d..43d5baa0 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_clint.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_clint.c @@ -127,7 +127,6 @@ void handle_m_timer_interrupt(void) } - /** * */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_hart_ints.h index ba26cc65..1939c829 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_hart_ints.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_hart_ints.h @@ -25,30 +25,6 @@ extern "C" { #endif -typedef struct BEU_Type_ -{ - volatile uint64_t CAUSE; - volatile uint64_t VALUE; - volatile uint64_t ENABLE; - volatile uint64_t PLIC_INT; - volatile uint64_t ACCRUED; - volatile uint64_t LOCAL_INT; - volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)]; -} BEU_Type; - -typedef struct BEU_Types_ -{ - volatile BEU_Type regs[5]; -} BEU_Types; - -#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL -#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL -#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL -#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL -#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL - -#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) - /* * Local Interrupt offsets for the E51 */ @@ -381,4 +357,3 @@ void U54_f2m_31_local_IRQHandler(void); #endif #endif /* MSS_HART_INTS_H */ - diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_l2_cache.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_l2_cache.c index 3400e751..af4b00ec 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_l2_cache.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_l2_cache.c @@ -20,6 +20,7 @@ #include #include +#include #include "mpfs_hal/mss_hal.h" #include "mss_l2_cache.h" @@ -46,10 +47,9 @@ static void check_config_l2_scratchpad(void); */ __attribute__((weak)) void config_l2_cache(void) { - ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U); - - /* - * confirm the amount of l2lim used in the Linker script has been allocated + static_assert(LIBERO_SETTING_WAY_ENABLE < 16U, "Too many ways"); + /* + * confirm the amount of l2lim used in the Linker script has been allocated * in the MSS Configurator */ ASSERT(((const uint64_t)&__l2lim_end - (const uint64_t)&__l2lim_start)\ @@ -70,12 +70,10 @@ __attribute__((weak)) void config_l2_cache(void) /* If you are not using scratchpad, no need to include the following code */ - ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS); - - + static_assert(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS, "Scratchpad Missing"); /* - * Compute the mask used to specify ways that will be used by the + * Compute the mask (In HSS CONFIG_SERVICE_SCRUB=y) used to specify ways that will be used by the * scratchpad. */ @@ -198,107 +196,3 @@ static void check_config_l2_scratchpad(void) ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways); } - -#if 0 // todo - remove, no longer used - - -/*============================================================================== - * Reserve a number of cache ways to be used as scratchpad memory. - * - * @param nways - * Number of ways to be used as scratchpad. One way is 128Kbytes. - * - * @param scratchpad_start - * Start address within the Zero Device memory range in which the scratchpad - * will be located. - */ -static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) -{ - uint8_t way_enable; - uint64_t available_ways = 1; - uint64_t scratchpad_ways = 0; - uint64_t non_scratchpad_ways; - uint32_t inc; - - ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM); - ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP); - - /* - * Ensure at least one way remains available as cache. - */ - way_enable = CACHE_CTRL->WAY_ENABLE; - ASSERT(nways <= way_enable); - if(nways <= way_enable) - { - /* - * Compute the mask used to specify ways that will be used by the - * scratchpad. - */ - - for(inc = 0; inc < way_enable; ++inc) - { - available_ways = (available_ways << 1) | (uint64_t)0x01; - if(inc < nways) - { - scratchpad_ways = (scratchpad_ways << 1) | (uint64_t)0x01; - } - } - - /* - * Prevent other masters from evicting cache lines from scratchpad ways. - * Only allow E51 to evict from scratchpad ways. - */ - non_scratchpad_ways = available_ways & ~scratchpad_ways; - - CACHE_CTRL->WAY_MASK_DMA = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_E51_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_1_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_1_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_2_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_2_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_3_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_3_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_4_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_4_ICACHE = non_scratchpad_ways; - - /* - * Assign ways to Zero Device - */ - uint64_t * p_scratchpad = scratchpad_start; - int ways_inc; - uint64_t current_way = 1; - for(ways_inc = 0; ways_inc < nways; ++ways_inc) - { - /* - * Populate the scratchpad memory one way at a time. - */ - CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way; - /* - * Write to the first 64-bit location of each cache block. - */ - for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc) - { - *p_scratchpad = g_init_marker + inc; - p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH; - } - current_way = current_way << 1U; - mb(); - } - - /* - * Prevent E51 from evicting from scratchpad ways. - */ - CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways; - } -} -#endif diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.c index e1b8dfa9..27a04ac3 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.c @@ -7,7 +7,7 @@ * */ -/*************************************************************************** +/******************************************************************************* * * @file mss_mtrap.c * @author Microchip-FPGA Embedded Systems Solutions @@ -20,8 +20,6 @@ extern "C" { #endif - - void handle_local_interrupt(uint8_t interrupt_no); void handle_m_soft_interrupt(void); void handle_m_timer_interrupt(void); @@ -32,7 +30,6 @@ void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc); - void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc) { (void)regs; @@ -631,7 +628,7 @@ void handle_m_ext_interrupt(void) } uint8_t disable = EXT_IRQ_KEEP_ENABLED; - disable = ext_irq_handler_table[int_num /* + OFFSET_TO_MSS_GLOBAL_INTS Think this was required in early bitfile */](); + disable = ext_irq_handler_table[int_num](); PLIC_CompleteIRQ(int_num); @@ -662,29 +659,38 @@ void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc) { volatile uintptr_t mcause = read_csr(mcause); - if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) + if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) >=\ + IRQ_M_LOCAL_MIN)&& ((mcause & MCAUSE_CAUSE) <= IRQ_M_LOCAL_MAX)) { handle_local_interrupt((uint8_t)(mcause & MCAUSE_CAUSE)); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_EXT)) { handle_m_ext_interrupt(); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_SOFT)) { handle_m_soft_interrupt(); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_TIMER)) { handle_m_timer_interrupt(); } + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_BEU )) + { + handle_local_beu_interrupt(); + } else { uint32_t i = 0U; - while(1) + while(1U) { /* wait for watchdog */ - i++; /* added some code as SC debugger hangs if in loop doing nothing */ + i++; if(i == 0x1000U) { i = (uint32_t)mcause; /* so mcause is not optimised out */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.h index 3d68eb12..4d201b6b 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_mtrap.h @@ -45,6 +45,10 @@ extern "C" { #define IPI_FENCE_I 0x02 #define IPI_SFENCE_VMA 0x04 +#define IRQ_M_BEU 0x80 +#define IRQ_M_LOCAL_MIN 16 +#define IRQ_M_LOCAL_MAX 63 + #define MACHINE_STACK_SIZE (RISCV_PGSIZE) /* this is 4k for HLS and 4k for the stack*/ #define MENTRY_HLS_OFFSET (INTEGER_CONTEXT_SIZE + SOFT_FLOAT_CONTEXT_SIZE) #define MENTRY_FRAME_SIZE (MENTRY_HLS_OFFSET + HLS_SIZE) diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_plic.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_plic.h index 4e1b31f9..b0083d9d 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_plic.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_plic.h @@ -24,7 +24,6 @@ #include "encoding.h" #endif -#include "mss_legacy_defines.h" #include "mss_assert.h" #ifdef __cplusplus @@ -628,7 +627,7 @@ static inline void PLIC_init(void) break; } - /* Enable PLIC_MMUARTine external interrupts. */ + /* Enable machine external interrupts. */ set_csr(mie, MIP_MEIP); } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_util.c index 938667d2..5e5d503f 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_util.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/mss_util.c @@ -225,4 +225,3 @@ void enable_branch_prediction(void) #ifdef __cplusplus } #endif - diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.c index 381ff41c..c67539a2 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.c @@ -32,8 +32,10 @@ * Local Defines */ /* This string is updated if any change to ddr driver */ -#define DDR_DRIVER_VERSION_STRING "0.4.018" +#define DDR_DRIVER_VERSION_STRING "0.4.019" +const char DDR_DRIVER_VERSION[] = DDR_DRIVER_VERSION_STRING; /* Version | Comment */ +/* 0.4.019 | Added full memory initalization function */ /* 0.4.018 | Corrected error introduced for DDR3 in 0.4.14 */ /* 0.4.017 | made SW_TRAING_BCLK_SCLK_OFFSET seperate for each mem type */ /* 0.4.016 | DDR3-Added support for DDR3L removed in v0.3.027 */ @@ -311,6 +313,7 @@ static uint32_t ddr_setup(void) DDR_TYPE ddr_type; uint32_t ret_status = 0U; uint8_t number_of_lanes_to_calibrate; + uint64_t mem_size; ddr_type = LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_MASK; @@ -837,7 +840,6 @@ static uint32_t ddr_setup(void) /* * We have chosen to use software bclk sclk sweep instead of IP */ - { uint32_t bclk_phase, bclk90_phase,refclk_phase; bclk_answer = 0U; @@ -1106,7 +1108,6 @@ static uint32_t ddr_setup(void) } else { - vref_answer = vref_answer; dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12) | (0x1<<18U); } @@ -1136,7 +1137,7 @@ static uint32_t ddr_setup(void) MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); delay(DELAY_CYCLES_500_NS); } - + #ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, "\n\r Returning FPGA CA VREF & CA drive to user setting.\n\r ", 0x0); #endif @@ -1168,7 +1169,7 @@ static uint32_t ddr_setup(void) /* RX_MD_CLKN */ CFG_DDR_SGMII_PHY->rpc168.rpc168 = 0x0U; } - + #ifdef DDR_TRAINING_IP_SM_START_DELAY delay(DELAY_CYCLES_5_MICRO); #endif @@ -1301,7 +1302,7 @@ static uint32_t ddr_setup(void) } break; case DDR_TRAINING_IP_SM_RDGATE: - /* vrgen, revert temp change during write leveling for lpddr4, + /* vrgen, revert temp change during write leveling for lpddr4, turn back on ODT */ CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS = dpc_bits ; CFG_DDR_SGMII_PHY->rpc3_ODT.rpc3_ODT = LIBERO_SETTING_RPC_ODT_DQ; @@ -1448,7 +1449,7 @@ static uint32_t ddr_setup(void) } #define DCT_EXTRA_CHECKS -#ifdef DCT_EXTRA_CHECKS +#ifdef DCT_EXTRA_CHECKS uint32_t temp = 0U, gt_clk_sel = (CFG_DDR_SGMII_PHY->gt_clk_sel.gt_clk_sel & 3U); if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly)&0xFFU) == 0U) // Gate training tx_dly check: AL { @@ -1870,7 +1871,9 @@ static uint32_t ddr_setup(void) } break; case DDR_LOAD_PATTERN_TO_CACHE: - load_ddr_pattern(LIBERO_SETTING_DDR_32_CACHE, SIZE_OF_PATTERN_TEST*2, SIZE_OF_PATTERN_OFFSET); + load_ddr_pattern(LIBERO_SETTING_DDR_32_CACHE,\ + SIZE_OF_PATTERN_TEST*2, DDR_TEST_FILL,\ + SIZE_OF_PATTERN_OFFSET); if(error == 0U) { ddr_training_state = DDR_VERIFY_PATTERN_IN_CACHE; @@ -1927,7 +1930,7 @@ static uint32_t ddr_setup(void) ddr_training_state = DDR_TRAINING_FAIL; } CFG_DDR_SGMII_PHY->rpc166.rpc166 = rpc_166_fifo_offset; - + /* PAUSE to reset fifo (loads new RXPTR value).*/ //CFG_DDR_SGMII_PHY->expert_dfi_status_override_to_shim.expert_dfi_status_override_to_shim = 0x07U; CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x1U; @@ -2028,6 +2031,33 @@ static uint32_t ddr_setup(void) { ddr_error_count++; } +#endif + ddr_training_state = DDR_TRAINING_INIT_ALL_MEMORY; + break; + + case DDR_TRAINING_INIT_ALL_MEMORY: +#ifdef DEBUG_DDR_INIT + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + (void)uprint64(g_debug_uart, " Init memory, size = , 0x",\ + (uint64_t)mem_size); +#endif + +#ifndef ENABLE_MEM_INIT_NON_ECC + /* Check if using ECC, if so, init all memory */ + if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_ECC_MASK) ==\ + DDRPHY_MODE_ECC_ON) + { + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + load_ddr_pattern(LIBERO_SETTING_DDR_64_NON_CACHE, mem_size,\ + DDR_INIT_FILL, 0U); + } +#else + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + load_ddr_pattern(LIBERO_SETTING_DDR_64_NON_CACHE, mem_size,\ + DDR_INIT_FILL, 0U); #endif ddr_training_state = DDR_TRAINING_FINISH_CHECK; break; @@ -2036,10 +2066,13 @@ static uint32_t ddr_setup(void) /* * return status */ - ddr_diag.train_time = (uint64_t)(rdcycle() - training_start_cycle) / (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK/1000); + ddr_diag.train_time = (uint64_t)(rdcycle() - training_start_cycle)\ + / (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK/1000); #ifdef DEBUG_DDR_INIT - (void)uprint32(g_debug_uart, "\n\r ddr train time (ms): ", (uint32_t)ddr_diag.train_time); - (void)uprint32(g_debug_uart, "\n\r Number of retrains: ", ddr_diag.num_retrains); + (void)uprint32(g_debug_uart, "\n\r ddr train time (ms): ",\ + (uint32_t)ddr_diag.train_time); + (void)uprint32(g_debug_uart, "\n\r Number of retrains: ",\ + ddr_diag.num_retrains); { tip_register_status (g_debug_uart); uprint(g_debug_uart, "\n\r\n\r DDR_TRAINING_PASS: "); @@ -2391,7 +2424,7 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type) */ CFG_DDR_SGMII_PHY->rpc226.rpc226 = 0x14U; CFG_DDR_SGMII_PHY->UNUSED_SPACE0[0] = 0xA000U; - /* for Skew debug at 125C MIN TTHH18->Changing the common mode of the Receiver + /* for Skew debug at 125C MIN TTHH18->Changing the common mode of the Receiver to low common mode to improve IO Performance of LPDDR4 */ CFG_DDR_SGMII_PHY->SPARE0.SPARE0 = 0xA000U; @@ -2612,7 +2645,7 @@ static uint8_t memory_tests(void) mult by (4 lanes) */ { SIM_FEEDBACK1(shift_walking_one); - start_address = (uint64_t)(0xC0000000U + (0x1U< 1G { SIM_FEEDBACK1(shift_walking_one); - start_address = (uint64_t)(0x1400000000U + (0x1U<= 4U) { - start_address = (uint64_t)(0x1400000000U + \ + start_address = (uint64_t)(BASE_ADDRESS_NON_CACHED_64_DDR + \ (((0x1U<<(shift_walking_one +1)) - 1U) -0x0F) ); error = rw_sanity_chk((uint64_t *)start_address , (uint32_t)0x5U); @@ -3591,10 +3624,10 @@ static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC if (mask & 0x1U) { DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFFFFFF00U; - DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; } if (mask & 0x2U) { @@ -4658,6 +4691,7 @@ MSS_DDR_user_commands return error; } #endif + #ifdef DEBUG_DDR_INIT void debug_read_ddrcfg(void) { @@ -4710,6 +4744,7 @@ void debug_read_ddrcfg(void) } #endif + const uint8_t REFCLK_OFFSETS[][5U] = { {LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS, LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0, @@ -5180,7 +5215,6 @@ static void lpddr4_manual_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_ind } else { - vref_answer = vref_answer; dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12) | (0x1<<18U); } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.h index d6c806e6..f75bf85b 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr.h @@ -968,6 +968,7 @@ typedef enum DDR_TRAINING_SM_ DDR_TRAINING_VREFDQ_CALIB, DDR_TRAINING_FPGA_VREFDQ_CALIB, DDR_TRAINING_FINISH_CHECK, + DDR_TRAINING_INIT_ALL_MEMORY, DDR_TRAINING_FINISHED, DDR_TRAINING_FAIL_SM2_VERIFY, DDR_TRAINING_FAIL_SM_VERIFY, diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c index a4710a80..5c8589b0 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c @@ -40,6 +40,7 @@ static uint32_t g_test_buffer_not_cached[765]; * External Defines */ extern const uint32_t ddr_test_pattern[768]; +extern const uint32_t ddr_init_pattern[64U]; /******************************************************************************* * External function declarations @@ -667,18 +668,33 @@ uint32_t tip_register_status (mss_uart_instance_t *g_mss_uart_debug_pt) /** * Load a pattern to DDR */ -void load_ddr_pattern(uint64_t base, uint32_t size, uint8_t pattern_offset) +void load_ddr_pattern(uint64_t base, uint64_t size, uint32_t pattern_type, \ + volatile uint8_t pattern_offset) { int alive = 0; - + uint32_t *pattern; + volatile uint32_t pattern_size; uint8_t *p_ddr = (uint8_t *)base; - uint32_t pattern_length = (uint32_t)(sizeof(ddr_test_pattern) - pattern_offset) ; + + if (pattern_type == DDR_TEST_FILL) + { + pattern = (uint32_t *)ddr_test_pattern; + pattern_size = sizeof(ddr_test_pattern); + } + else + { + pattern = (uint32_t *)ddr_init_pattern; + pattern_size = sizeof(ddr_init_pattern); + } + + uint32_t pattern_length = (uint32_t)(pattern_size - pattern_offset) ; #ifdef DEBUG_DDR_INIT uprint(g_debug_uart, (const char*)(const uint8_t*)"\r\nLoading test pattern\r\n"); + uprint32(g_debug_uart, (const char*)(const uint8_t*)"\r\npattern_length = \r\n",pattern_length); #endif - while(((uint64_t)p_ddr + pattern_length) < (base + size)) + while(((uint64_t)p_ddr + pattern_length) <= (base + size)) { switch ( ((uint64_t)p_ddr)%8U ) @@ -686,22 +702,22 @@ void load_ddr_pattern(uint64_t base, uint32_t size, uint8_t pattern_offset) case 0: case 4: pdma_transfer_complete(PDMA_CHANNEL0_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL0_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL0_BASE_ADDRESS); break; case 1: case 5: pdma_transfer_complete(PDMA_CHANNEL1_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL1_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL1_BASE_ADDRESS); break; case 2: case 6: pdma_transfer_complete(PDMA_CHANNEL2_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL2_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL2_BASE_ADDRESS); break; case 3: case 7: pdma_transfer_complete(PDMA_CHANNEL3_BASE_ADDRESS); - pdma_transfer((uint64_t)p_ddr, (uint64_t)ddr_test_pattern, pattern_length, PDMA_CHANNEL3_BASE_ADDRESS); + pdma_transfer((uint64_t)p_ddr, (uint64_t)pattern, pattern_length, PDMA_CHANNEL3_BASE_ADDRESS); break; } @@ -763,8 +779,8 @@ static void load_test_buffers(uint32_t * p_cached_ddr, uint32_t * p_not_cached_d uint32_t test_ddr(uint32_t no_of_iterations, uint32_t size) { uint32_t pattern_length = sizeof(ddr_test_pattern) - (3 * sizeof(uint32_t)); - uint32_t * p_ddr_cached = (uint32_t *)0x80000000; - uint32_t * p_ddr_noncached = (uint32_t *)0x1400000000; + uint32_t * p_ddr_cached = (uint32_t *)BASE_ADDRESS_CACHED_32_DDR; + uint32_t * p_ddr_noncached = (uint32_t *)BASE_ADDRESS_NON_CACHED_64_DDR; uint32_t word_offset; uint32_t alive = 0; uint32_t alive_idx = 0U; @@ -812,8 +828,8 @@ uint32_t test_ddr(uint32_t no_of_iterations, uint32_t size) } else { - p_ddr_cached = (uint32_t *)0x80000000; - p_ddr_noncached = (uint32_t *)0x1400000000; + p_ddr_cached = (uint32_t *)BASE_ADDRESS_CACHED_32_DDR; + p_ddr_noncached = (uint32_t *)BASE_ADDRESS_NON_CACHED_64_DDR; iteration++; #ifdef DEBUG_DDR_INIT uprint32(g_debug_uart, " Iteration ", (uint64_t)(unsigned int)iteration); diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h index ea98ea17..3bb0af8a 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h @@ -63,6 +63,12 @@ typedef enum DDR_ACCESS_SIZE_ DDR_64_BIT } DDR_ACCESS_SIZE; +typedef enum DDR_FILL_TYPE_ +{ + DDR_TEST_FILL, + DDR_INIT_FILL +} DDR_FILL_TYPE; + /***************************************************************************//** The ddr_read_write_fn function is used to write/read test patterns to the DDR @@ -230,8 +236,9 @@ void load_ddr_pattern ( uint64_t base, -uint32_t size, -uint8_t pattern_offset +uint64_t size, +uint32_t pattern_type, +volatile uint8_t pattern_offset ); /***************************************************************************//** diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h index 3677ee34..1263bc79 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h @@ -56,4 +56,9 @@ #define DDR_ADD_CMD_A5_OFFSET_FAIL 0x01 #define DDR_ADD_CMD_A5_OFFSET_FAIL_LOW_FREQ 0x04 +#define BASE_ADDRESS_CACHED_32_DDR 0x80000000UL +#define BASE_ADDRESS_NON_CACHED_32_DDR 0xC0000000UL +#define BASE_ADDRESS_CACHED_64_DDR 0x1000000000ULL +#define BASE_ADDRESS_NON_CACHED_64_DDR 0x1400000000ULL + #endif /* SRC_PLATFORM_MPFS_HAL_NWC_MSS_DDR_DEFS_H_ */ diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c index 2bda43d8..7300c144 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_ddr_test_pattern.c @@ -205,3 +205,44 @@ const uint32_t ddr_test_pattern[768] = 0x842a8082, 0x651785a6, 0x05130003, 0xa0efa325 }; +#ifdef INIT_PATTERN_ZERO +const uint32_t ddr_init_pattern[64U] = +{ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; +#else +const uint32_t ddr_init_pattern[64U] = +{ + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, + 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF +}; +#endif diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io.c index 2e454264..5470aae9 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io.c @@ -272,7 +272,6 @@ static uint8_t io_mux_and_bank_config(void) set_bank2_and_bank4_volts(DEFAULT_MSSIO_CONFIGURATION); - return(0L); } @@ -510,12 +509,12 @@ uint8_t switch_mssio_config(MSS_IO_OPTIONS option) if (mss_is_alternate_io_setting_sd() == true) { io_mux_and_bank_config_alt(); - } else { io_mux_and_bank_config(); } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); break; case EMMC_MSSIO_CONFIGURATION: @@ -527,6 +526,7 @@ uint8_t switch_mssio_config(MSS_IO_OPTIONS option) { io_mux_and_bank_config(); } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); break; case NO_SUPPORT_MSSIO_CONFIGURATION: @@ -545,40 +545,64 @@ uint8_t switch_mssio_config(MSS_IO_OPTIONS option) } /** - * switch_external_mux() - * Requires fpga switch hdl. This comes with reference icicle kit design. + * Is there a mux present, define is true by default + * @return true/false + */ +__attribute__((weak)) uint8_t fabric_sd_emmc_demux_present(void) +{ + return (uint8_t) FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT; +} + +/** + * Returns the fabric mux address + * @return address of the mux in fabric + */ +__attribute__((weak)) uint32_t * fabric_sd_emmc_demux_address(void) +{ + return (uint32_t *)FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS; +} + +/** + * switch_demux_using_fabric_ip() + * Requires fpga switch hdl. This comes with the reference icicle kit design. * You will need to create your own or copy when creating your own fpga design * along with an external mux in your board design if you wish to use SD/eMMC * muxing in your hardware design. * Please note this function will cause a hang if you do not have support - * for switching in your fpga design, nlu use if you have this support if your + * for switching in your fpga design. Only use if you have this support if your * fabric design. * @param option SD_MSSIO_CONFIGURATION/EMMC_MSSIO_CONFIGURATION * @return */ -__attribute__((weak)) uint8_t switch_external_mux(MSS_IO_OPTIONS option) +__attribute__((weak)) uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option) { uint8_t result = false; - volatile uint32_t *reg_pt = (uint32_t *)ICICLE_KIT_REF_DESIGN_FPGS_SWITCH_ADDRESS; - switch(option) + if (fabric_sd_emmc_demux_present() == true) { - case SD_MSSIO_CONFIGURATION: - *reg_pt = 1UL; - break; + volatile uint32_t *reg_pt = fabric_sd_emmc_demux_address(); + switch(option) + { + case SD_MSSIO_CONFIGURATION: + *reg_pt = CMD_SD_EMMC_DEMUX_SD_ON; + break; - case EMMC_MSSIO_CONFIGURATION: - *reg_pt = 0UL; - break; + case EMMC_MSSIO_CONFIGURATION: + *reg_pt = CMD_SD_EMMC_DEMUX_EMMC_ON; + break; - case NO_SUPPORT_MSSIO_CONFIGURATION: - break; + case NO_SUPPORT_MSSIO_CONFIGURATION: + break; - case NOT_SETUP_MSSIO_CONFIGURATION: - break; + case NOT_SETUP_MSSIO_CONFIGURATION: + break; + } + result = true; + } + else + { + result = false; } - result = true; - return result; } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io_config.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io_config.h index bafe18ef..79a60e05 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io_config.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_io_config.h @@ -22,14 +22,28 @@ extern "C" { #endif +#define CMD_SD_EMMC_DEMUX_EMMC_ON 0U +#define CMD_SD_EMMC_DEMUX_SD_ON 1U + /* * fields of LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS * */ -#define EMMC_CONFIGURED_MASK (0x01U<<0U) /*!< set => eMMC is configured */ -#define SD_CONFIGURED_MASK (0x01U<<1U) /*!< set => SD is configured */ -#define DEFAULT_ON_START_MASK (0x01U<<2U) /*!< set => default is SD config, not set default is eMMC config */ - -#define ICICLE_KIT_REF_DESIGN_FPGS_SWITCH_ADDRESS 0x4f000000 +#define EMMC_CONFIGURED_MASK (0x01U<<0U) /*!< set => eMMC is configured */ +#define SD_CONFIGURED_MASK (0x01U<<1U) /*!< set => SD is configured */ +#define DEFAULT_ON_START_MASK (0x01U<<2U) /*!< set => default is SD config, + not set default is eMMC config */ +/* + * Please note in Icicle kit reference design pre 2022.09, the address below + * was 0x4F000000UL + */ +#ifndef FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS +#define FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS 0x4FFFFF00UL /*!< This is design + dependent */ +#endif +#ifndef FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT +#define FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT true /*!< true/false This is design + dependent */ +#endif #if !defined (LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR) /*To limit the number of interrupts fed to the PLINT, the seventy GPIO @@ -315,9 +329,9 @@ set_bank2_and_bank4_volts if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) { - while(1u); + // print warning message + return; } - switch_external_mux(EMMC_MSSIO_CONFIGURATION); g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; @@ -358,9 +372,22 @@ uint8_t mss_does_xml_ver_support_switch(void); @code + // e.g. first try SD, and fail, then try alt config + if ( mss_is_alternate_io_configured() == true ) { - ... + if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) + { + // print warning message + return + } + g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; + g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; + g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; + g_mmc.data_bus_width = MSS_MMC_DATA_WIDTH_4BIT; + g_mmc.bus_voltage = MSS_MMC_1_8V_BUS_VOLTAGE; + + // ... } @endcode @@ -407,10 +434,11 @@ uint8_t mss_is_alternate_io_setting_emmc(void); uint8_t mss_is_alternate_io_setting_sd(void); /***************************************************************************//** - switch_external_mux() + switch_demux_using_fabric_ip() This is a function used to switch external mux. - Requires fpga switch hdl. This comes with reference icicle kit design. - Will need to create your own or copy when creating your own fpga design + It requires fpga switch IP in the fabric. This comes with reference icicle + kit design. + You will need to create your own or copy when creating your own fpga design along with an external mux in your board design if you wish to use SD/eMMC muxing in your hardware design. @@ -418,12 +446,35 @@ uint8_t mss_is_alternate_io_setting_sd(void); @code - switch_external_mux(SD_MSSIO_CONFIGURATION); + case SD_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_sd() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); + break; + + case EMMC_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_emmc() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); + break; + @endcode */ -uint8_t switch_external_mux(MSS_IO_OPTIONS option); +uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option); /***************************************************************************//** mss_io_default_setting() @@ -444,6 +495,51 @@ uint8_t switch_external_mux(MSS_IO_OPTIONS option); */ uint8_t mss_io_default_setting(void); +/***************************************************************************//** + fabric_sd_emmc_demux_present() + + Is there sd_emmc_demux IP present in the fabric. + + @return true/false + + Example: + + @code + + if ( fabric_sd_emmc_demux_present() == true ) + { + // ... + } + + @endcode + + */ +uint8_t fabric_sd_emmc_demux_present(void); + +/***************************************************************************//** + fabric_sd_emmc_demux_address() + + This function is used by the routine switch_demux_using_fabric_ip() + The address returned is a default address, used by the Icicle kit design + post v2022.09. + If another address is used in your Libero design, instantiate this function + in your application, and return the address that matches your Libero design. + + @return returns the address of the sd_emmc_demux in fabric + + Example: + + @code + + volatile uint32_t *reg_pt = fabric_sd_emmc_demux_address(); + + *reg_pt = CMD_SD_EMMC_DEMUX_SD_ON; + + @endcode + + */ +uint32_t * fabric_sd_emmc_demux_address(void); + /***************************************************************************//** This function is used to set the apb_bus_cr register value diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c index 261d929b..27bde361 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c @@ -336,7 +336,7 @@ uint8_t mss_nwc_init_ddr(void) uint32_t ddr_status; ddr_status = ddr_state_machine(DDR_SS__INIT); - next_time = 0U; + next_time = rdcycle() + DELAY_CYCLES_100MS; while((ddr_status & DDR_SETUP_DONE) != DDR_SETUP_DONE) { ddr_status = ddr_state_machine(DDR_SS_MONITOR); @@ -358,7 +358,7 @@ uint8_t mss_nwc_init_ddr(void) */ static uint64_t report_status_functions(MSS_REPORT_STATUS report_status, uint64_t next_time) { - if (next_time >= rdcycle()) + if (next_time <= rdcycle()) { switch(report_status) { diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_pll.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_pll.c index 20401b53..761ef34c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_pll.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/common/nwc/mss_pll.c @@ -195,9 +195,9 @@ static void mss_mux_pre_mss_pll_config(void) * */ volatile uint32_t i; - for(i = 0U; i < 400U; i++) + for(i = 0U; i < 200U; i++) { - i++; + ; //i++; } } @@ -399,7 +399,6 @@ void sgmii_mux_config(uint8_t option) ******************************************************************************/ void mss_pll_config(void) { - copy_switch_code(); /* copy switch code to RAM */ MSS_SCB_DDR_PLL->SOFT_RESET = PLL_INIT_AND_OUT_OF_RESET; @@ -731,6 +730,3 @@ __attribute__((weak)) void copy_switch_code(void) } #endif /* MPFS_HAL_HW_CONFIG */ - - - diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mpfs_hal_version.h index 078fab91..72208576 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mpfs_hal_version.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mpfs_hal_version.h @@ -2,7 +2,7 @@ #define MPFS_HAL_VERSION_H /******************************************************************************* - * Copyright 2019-2022 Microchip Corporation. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -40,8 +40,8 @@ extern "C" { #endif #define MPFS_HAL_VERSION_MAJOR 2 -#define MPFS_HAL_VERSION_MINOR 0 -#define MPFS_HAL_VERSION_PATCH 102 +#define MPFS_HAL_VERSION_MINOR 1 +#define MPFS_HAL_VERSION_PATCH 103 #ifdef __cplusplus } diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mss_hal.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mss_hal.h index a493a8e9..3261f105 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mss_hal.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/mss_hal.h @@ -29,6 +29,7 @@ typedef long ssize_t; #include "common/mss_assert.h" #include "common/mss_legacy_defines.h" +#include "common/mss_beu_def.h" #include "common/nwc/mss_ddr_defs.h" #include "common/nwc/mss_ddr_sgmii_regs.h" #include "common/nwc/mss_io_config.h" @@ -40,19 +41,20 @@ typedef long ssize_t; * mpfs_hal folder */ #include "mpfs_hal_config/mss_sw_config.h" +#include "common/atomic.h" +#include "common/bits.h" +#include "common/encoding.h" /* - * The hw_platform.h is included here only. It must be included after + * The fpga_design_config.h is included here only. It must be included after * mss_sw_config.h. This allows defines in hw_platform.h be overload from * mss_sw_config.h if necessary. * */ -#include "common/atomic.h" -#include "common/bits.h" -#include "common/encoding.h" #include "fpga_design_config/fpga_design_config.h" #include "common/nwc/mss_ddr.h" #include "common/mss_clint.h" #include "common/mss_h2f.h" #include "common/mss_hart_ints.h" +#include "common/mss_beu.h" #include "common/mss_mpu.h" #include "common/mss_pmp.h" #include "common/mss_plic.h" diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_entry.S index 2fad16b7..b530e05c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_entry.S +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_entry.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2022 Microchip Corporation. + * Copyright 2019-2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_utils.S b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_utils.S index 482d4b61..4ec8701c 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_utils.S +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/mss_utils.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2021 Microchip Corporation. + * Copyright 2023 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.c b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.c index c95ae5c6..fb37a270 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.c +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.c @@ -601,27 +601,6 @@ __attribute__((weak)) void u54_4(void) } } - /** - * This function is configured by editing parameters in - * mss_sw_config.h as required. - * @return - */ - -__attribute__((weak)) uint8_t init_bus_error_unit(void) -{ - uint8_t hart_id; - /* Init BEU in all harts - enable local interrupt */ - for(hart_id = MPFS_HAL_FIRST_HART; hart_id <= MPFS_HAL_LAST_HART; hart_id++) - { - BEU->regs[hart_id].ENABLE = (uint64_t)BEU_ENABLE; - BEU->regs[hart_id].PLIC_INT = (uint64_t)BEU_PLIC_INT; - BEU->regs[hart_id].LOCAL_INT = (uint64_t)BEU_LOCAL_INT; - BEU->regs[hart_id].CAUSE = 0ULL; - BEU->regs[hart_id].ACCRUED = 0ULL; - BEU->regs[hart_id].VALUE = 0ULL; - } - return (0U); -} /** * init_mem_protection_unit(void) diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.h index 7abdaaa7..376b1acd 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup.h @@ -128,7 +128,7 @@ void init_memory( void); void init_ddr( void); uint8_t init_mem_protection_unit(void); uint8_t init_pmp(uint8_t hart_id); -uint8_t init_bus_error_unit( void); + char * memfill(void *dest, const void * src, size_t len); char * config_copy(void *dest, const void * src, size_t len); char * config_16_copy(void *dest, const void * src, size_t len); diff --git a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h index 27e82ae3..6d230661 100644 --- a/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h +++ b/driver-examples/mss/mss-spi/mpfs-spi-master-slave/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h @@ -14,7 +14,7 @@ */ #ifndef SYSTEM_STARTUP_DEFS_H -#define SYSTEM_STARTUP_DESF_H +#define SYSTEM_STARTUP_DEFS_H #ifdef __cplusplus extern "C" { @@ -43,4 +43,4 @@ extern "C" { } #endif -#endif /* SYSTEM_STARTUP_DESF_H */ +#endif /* SYSTEM_STARTUP_DEFS_H */