From c5f21e1e9f469c488aaa795088e14fe43ea437a9 Mon Sep 17 00:00:00 2001 From: Lavakrishna Date: Thu, 5 Jan 2023 11:39:51 +0000 Subject: [PATCH] Squashed 'driver-examples/mss/mss-watchdog/' changes from d7f9aa2..1e8482d 1e8482d updated mpfs-hal to version 2.1.103 8c60ca3 Updated mpfs-hal to version 2.1.101 52cc40b Libero Design: Used the reference design 2022.08 8151ebe Updated latest mss_mmuart and mss_watchdog driver source code 9e8ded9 Updated latest platform-config-reference folder 6a62385 Updated mpfs-hal folder to version 2.0.102 git-subtree-dir: driver-examples/mss/mss-watchdog git-subtree-split: 1e8482d4c25bbca9ee4a1b6085cb9e8deb054392 --- mpfs-watchdog-interrupt/README.md | 2 +- .../ICICLE_MSS_eMMC_cfg_05.xml | 4024 ----------------- ...g_04.xml => MPFS_Icicle_MSS_Baremetal.xml} | 465 +- .../linker/mpfs-ddr-loaded-by-boot-loader.ld | 226 - .../linker/mpfs-envm-lma-scratchpad-vma.ld | 387 -- .../platform_config/linker/mpfs-envm.ld | 344 -- .../linker/mpfs-lim-lma-scratchpad-vma.ld | 375 -- .../platform_config/linker/mpfs-lim.ld | 309 -- .../mpfs_hal_config/mss_sw_config.h | 11 +- .../drivers/mss/mss_mmuart/mss_uart.c | 30 +- .../drivers/mss/mss_mmuart/mss_uart.h | 42 +- .../drivers/mss/mss_mmuart/mss_uart_regs.h | 2 +- .../drivers/mss/mss_watchdog/mss_watchdog.h | 2 +- .../src/platform/mpfs_hal/common/bits.h | 9 +- .../src/platform/mpfs_hal/common/mss_assert.h | 2 +- .../platform/mpfs_hal/common/mss_axiswitch.c | 2 +- .../platform/mpfs_hal/common/mss_axiswitch.h | 2 +- .../src/platform/mpfs_hal/common/mss_beu.c | 87 + .../src/platform/mpfs_hal/common/mss_beu.h | 119 + .../platform/mpfs_hal/common/mss_beu_def.h | 67 + .../src/platform/mpfs_hal/common/mss_clint.c | 23 +- .../src/platform/mpfs_hal/common/mss_clint.h | 2 +- .../src/platform/mpfs_hal/common/mss_h2f.c | 245 +- .../src/platform/mpfs_hal/common/mss_h2f.h | 34 +- .../platform/mpfs_hal/common/mss_hart_ints.h | 602 ++- .../mpfs_hal/common/mss_irq_handler_stubs.c | 886 ++-- .../platform/mpfs_hal/common/mss_l2_cache.c | 123 +- .../platform/mpfs_hal/common/mss_l2_cache.h | 2 +- .../mpfs_hal/common/mss_legacy_defines.h | 710 +++ .../src/platform/mpfs_hal/common/mss_mpu.c | 5 +- .../src/platform/mpfs_hal/common/mss_mpu.h | 5 +- .../src/platform/mpfs_hal/common/mss_mtrap.c | 1056 ++--- .../src/platform/mpfs_hal/common/mss_mtrap.h | 4 + .../mpfs_hal/common/mss_peripherals.c | 42 +- .../mpfs_hal/common/mss_peripherals.h | 52 +- .../src/platform/mpfs_hal/common/mss_plic.c | 2 +- .../src/platform/mpfs_hal/common/mss_plic.h | 983 ++-- .../src/platform/mpfs_hal/common/mss_pmp.c | 8 +- .../src/platform/mpfs_hal/common/mss_pmp.h | 4 +- .../src/platform/mpfs_hal/common/mss_seg.h | 2 +- .../src/platform/mpfs_hal/common/mss_sysreg.h | 64 +- .../src/platform/mpfs_hal/common/mss_util.c | 101 +- .../src/platform/mpfs_hal/common/mss_util.h | 26 +- .../platform/mpfs_hal/common/nwc/mss_cfm.c | 2 +- .../platform/mpfs_hal/common/nwc/mss_cfm.h | 2 +- .../platform/mpfs_hal/common/nwc/mss_ddr.c | 2654 ++++++++--- .../platform/mpfs_hal/common/nwc/mss_ddr.h | 270 +- .../mpfs_hal/common/nwc/mss_ddr_debug.c | 297 +- .../mpfs_hal/common/nwc/mss_ddr_debug.h | 38 +- .../mpfs_hal/common/nwc/mss_ddr_defs.h | 21 +- .../common/nwc/mss_ddr_sgmii_phy_defs.h | 2 +- .../mpfs_hal/common/nwc/mss_ddr_sgmii_regs.h | 2 +- .../common/nwc/mss_ddr_test_pattern.c | 43 +- .../src/platform/mpfs_hal/common/nwc/mss_io.c | 421 +- .../mpfs_hal/common/nwc/mss_io_config.h | 337 +- .../mpfs_hal/common/nwc/mss_nwc_init.c | 132 +- .../mpfs_hal/common/nwc/mss_nwc_init.h | 92 +- .../platform/mpfs_hal/common/nwc/mss_pll.c | 26 +- .../platform/mpfs_hal/common/nwc/mss_pll.h | 28 +- .../mpfs_hal/common/nwc/mss_scb_nwc_regs.h | 2 +- .../platform/mpfs_hal/common/nwc/mss_sgmii.c | 8 +- .../platform/mpfs_hal/common/nwc/mss_sgmii.h | 2 +- .../platform/mpfs_hal/common/nwc/simulation.h | 2 +- .../src/platform/mpfs_hal/mpfs_hal_version.h | 8 +- .../src/platform/mpfs_hal/mss_hal.h | 13 +- .../platform/mpfs_hal/startup_gcc/mss_entry.S | 245 +- .../platform/mpfs_hal/startup_gcc/mss_utils.S | 2 +- .../mpfs_hal/startup_gcc/newlib_stubs.c | 57 +- .../mpfs_hal/startup_gcc/system_startup.c | 229 +- .../mpfs_hal/startup_gcc/system_startup.h | 8 +- .../startup_gcc/system_startup_defs.h | 6 +- .../linker/mpfs-ddr-loaded-by-boot-loader.ld | 91 +- .../linker/mpfs-envm-lma-scratchpad-vma.ld | 47 +- .../linker/mpfs-envm.ld | 29 +- .../linker/mpfs-lim-lma-scratchpad-vma.ld | 39 +- .../linker/mpfs-lim.ld | 32 +- .../mpfs_hal_config/mss_sw_config.h | 11 +- 77 files changed, 7074 insertions(+), 9612 deletions(-) delete mode 100644 mpfs-watchdog-interrupt/src/boards/icicle-kit-es/fpga_design/design_description/ICICLE_MSS_eMMC_cfg_05.xml rename mpfs-watchdog-interrupt/src/boards/icicle-kit-es/fpga_design/design_description/{ICICLE_MSS_eMMC_cfg_04.xml => MPFS_Icicle_MSS_Baremetal.xml} (97%) delete mode 100644 mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader.ld delete mode 100644 mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm-lma-scratchpad-vma.ld delete mode 100644 mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm.ld delete mode 100644 mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim-lma-scratchpad-vma.ld delete mode 100644 mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim.ld create mode 100644 mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.c create mode 100644 mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.h create mode 100644 mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu_def.h create mode 100644 mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_legacy_defines.h diff --git a/mpfs-watchdog-interrupt/README.md b/mpfs-watchdog-interrupt/README.md index 3431cff2..a3916a56 100644 --- a/mpfs-watchdog-interrupt/README.md +++ b/mpfs-watchdog-interrupt/README.md @@ -28,6 +28,6 @@ build configurations will not allow the functioality to complete. This project needs to use the E51 monitor core to configure the watchdog0. Hence this project can not be run when a Hart System Services (HSS) or similar bootloader which are executing on E51 and keep running even after the U54 applications are launched. Note that the HSS provides watchdog services and the applications launched by HSS bootloader -can avail them. For more information refer [HSS watchdog services](https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/hart-software-services/watchdog-service/watchdog-service.md). +can avail them. For more information refer [HSS watchdog services]( https://mi-v-ecosystem.github.io/redirects/watchdog-service_watchdog-service). For latest version of the HSS refer [HSS release page](https://github.com/polarfire-soc/hart-software-services/releases/tag/2021.04). \ No newline at end of file diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/fpga_design/design_description/ICICLE_MSS_eMMC_cfg_05.xml b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/fpga_design/design_description/ICICLE_MSS_eMMC_cfg_05.xml deleted file mode 100644 index 310f2916..00000000 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/fpga_design/design_description/ICICLE_MSS_eMMC_cfg_05.xml +++ /dev/null @@ -1,4024 +0,0 @@ - - - 2021.1 - ICICLE_MSS - MPFS250T_ES - FCVG484 - 04-11-2021_22:30:25 - 0.5.3 - - - - - 0x20220000 - 0x20220000 - 0x20220000 - 0x20220000 - 0x20220000 - 0x80000000 - 0xC0000000 - 0x1000000000 - 0x1400000000 - 0xD0000000 - 0x1800000000 - 0x00000000 - 0x00000000 - - - - - - 0x1 - - - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 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2021.1 + 2022.1 ICICLE_MSS MPFS250T_ES FCVG484 - 04-11-2021_22:30:25 - 0.5.31 + 07-27-2022_14:07:49 + 0.5.9 @@ -34,7 +34,7 @@ 0x0 0x0 - + 0x0 0x0 0x0 @@ -160,12 +160,12 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 - + 0x1 0x1 0x1 @@ -178,12 +178,12 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 - + 0x1 0x1 0x1 @@ -196,10 +196,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -214,12 +214,12 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 - + 0x1 0x1 0x1 @@ -232,12 +232,12 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 - + 0x1 0x1 0x1 @@ -250,12 +250,12 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 - + 0x1 0x1 0x1 @@ -268,10 +268,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -286,10 +286,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -304,10 +304,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -322,10 +322,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -340,12 +340,12 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 - + 0x1 0x1 0x1 @@ -358,10 +358,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -376,10 +376,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -394,10 +394,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x1 @@ -412,10 +412,10 @@ 0x0 0x0 0x0 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 0x4 @@ -1239,7 +1239,7 @@ 0x1 0x1 0x0 - 0x0 + 0x1 0x1 0x1 0x1 @@ -1249,22 +1249,22 @@ 0x0 - 0x1 - 0x1 - 0x1 - 0x1 - 0x1 - 0x1 - 0x1 - 0x1 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 - 0x1 - 0x1 - 0x1 - 0x1 - 0xF - 0xF + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 0x4 @@ -1287,21 +1287,21 @@ 0x8 - 0x2 - 0x2 - 0x2 - 0x2 + 0x3 + 0x3 + 0x3 + 0x3 0x7 0x7 0x7 0xF - 0x0 + 0x1 0x0 - 0x0 - 0x0 - 0x0 + 0x1 + 0x1 + 0x1 0x0 0x0 0x0 @@ -1316,32 +1316,32 @@ 0x0 - 0x0928 - 0x0928 + 0x0938 + 0x0938 - 0x0928 - 0x0928 + 0x0938 + 0x0938 - 0x0928 - 0x0928 + 0x0938 + 0x0938 0x0928 0x0928 - 0x0928 - 0x0928 + 0x0938 + 0x0938 - 0x0928 - 0x0928 + 0x0938 + 0x0938 - 0x0928 - 0x0928 + 0x0938 + 0x0938 0x7 @@ -1436,77 +1436,77 @@ 0x0 - 0x0 - 0x0 - 0x0 + 0x1 + 0x1 + 0x1 - 0x0 + 0x1 0x0 - 0x0 - 0x0 - 0x0 + 0x1 + 0x1 + 0x1 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 0x0 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + 0xF + 0xF - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + 0x4 + 0x4 + 0x4 + 0x4 + 0x4 + 0x4 + 0x4 + 0x4 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + 0x4 + 0x4 + 0x4 + 0x4 + 0xC + 0xC + 0x8 + 0x8 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + 0x3 + 0x3 + 0x3 + 0x3 + 0x7 + 0x7 + 0x7 + 0xF 0x0 @@ -1520,96 +1520,96 @@ 0x0 - 0x3F + 0xD 0x00 - 0x3F + 0xA 0x0 - 0x0 + 0x4 0x0 - 0x0 - 0x0 + 0x0938 + 0x0938 - 0x0 - 0x0 + 0x0938 + 0x0938 - 0x0 - 0x0 + 0x0938 + 0x0938 - 0x0 - 0x0 + 0x0928 + 0x0938 - 0x0 - 0x0 + 0x0938 + 0x0938 - 0x0 - 0x0 + 0x0938 + 0x0938 - 0x0 - 0x0 + 0x0928 + 0x0928 - 0x3F + 0x7 0x00 - 0x3F + 0x9 0x0 - 0x0 + 0x8 0x0 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 - 0x0 - 0x0 + 0x0829 + 0x0829 0x0 @@ -1682,7 +1682,7 @@ 0x9 0x1 0x1 - 0x00 + 0x0 0x1 0x1 0x8 @@ -1846,11 +1846,11 @@ 0x0 - 0x2 + 0x7 0x5 0x0 - 0x7F - 0x1F + 0x7F + 0x1F 0x02 @@ -2229,7 +2229,7 @@ 0x0 0x0 0x1 - 0x1 + 0x0 0x1 0x1 0x2 @@ -2528,13 +2528,13 @@ 0x00000006 - 0x00000000 + 0x1 - 0x00000000 + 0x1 - 0x00000000 + 0x17 0x00000004 @@ -2783,7 +2783,7 @@ 0x1F - 0x1 + 0xF 0x0 @@ -3248,10 +3248,10 @@ 0x00000000 - 0x1 + 0x0 - 0x0 + 0x1 0x0 @@ -3478,37 +3478,52 @@ - + + 0x1 + + 125000000 - + 600000000 - + 600000000 - + 1000000 - + 300000000 - + 150000000 + + 1600000000 + - + + 0x1 + + 0x0 0x1 0x2 - - + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + 0x7D - + 0x6 0x0 0x0 @@ -3564,7 +3579,7 @@ 0x0 0x0 0x0 - 0x2 + 0x1 0x0 0x0 0x0 @@ -3576,12 +3591,12 @@ 0x0 0x0 0x0 - 0x6 + 0x3 0x0 0x0 0x0 0x0 - 0xF + 0x4B 0x0 @@ -3628,7 +3643,7 @@ 0x0 - 0xC0 + 0x60 0x0 0x0 diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader.ld b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader.ld deleted file mode 100644 index 45c143ed..00000000 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader.ld +++ /dev/null @@ -1,226 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ -/******************************************************************************* - * - * file name : mpfs-ddr-loaded-by-boot-loader.ld - * Use this linker script when the program is fully located in DDR. The - * assumption is DDR has already been initialized by another program. - * - * This linker script can be used with a debugger or when compiled and loaded - * by a boot-loader. - * The loading program passes two parameters in a0 and a1 - * a0 - The hartid is passed here - * a1 - A pointer to Hart Local Storage (HLS) is passed here - * The HLS is a small amount of memory dedicated to each hart. - * The HLS also contains a pointer to shared memory. - * The shared memory is accessible by all harts if used. It is - * allocated by the boot-loader if the MPFS_HAL_SHARED_MEM_ENABLED - * is defined in the mss_sw_config.h file project configuration file. - * Please see the project mpfs-hal-run-from-ddr-u54-1 located in the Bare Metal - * library under examples/mpfs-hal for an example of it use. - * - * https://github.com/polarfire-soc/polarfire-soc-bare-metal-library - * - * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md - * which can be found under the link below: - * https://github.com/polarfire-soc/polarfire-soc-documentation - * - */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------------- - --- MSS hart Reset vector - -The MSS reset vector for each hart is stored securely in the MPFS. -The most common usage will be where the reset vector for each hart will be set -to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous -non-volatile storage. Normally this is where the initial boot-loader will -reside. (Note: The first 256B page of envm is used for metadata associated with -secure boot. When not using secure boot (mode 0,1), this area is still reserved -by convention. It allows easier transition from non-secure to secure boot flow -during the development process. - -------------------------------------------------------------------------------*/ - -MEMORY -{ - /* In this example, our reset vector is set to point to the */ - /* start at page 1 of the envm */ - envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 - dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k - u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k - u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k - u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k - u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k - l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k - scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1K of DTIM is used to run code when switching the envm clock */ - switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k - /* DDR sections example */ - ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M - ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M - ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M - ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M - ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k - ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k -} -HEAP_SIZE = 0k; /* needs to be calculated for your application if using */ - -/* - * Stack size for our single hart U54 application. - */ -STACK_SIZE_U54_APPLICATION = 8k; - -/* - * A small amount of unitialised memory used to store information - * obtained from the boot-loader on start-up - */ -UNITITALISED_MEM = 16B; - -/* reset address 0xC0000000 */ -SECTION_START_ADDRESS = 0x80000000; - - -SECTIONS -{ - - /* text: test code section */ - . = SECTION_START_ADDRESS; - .text : ALIGN(0x10) - { - __text_load = LOADADDR(.text); - __text_start = .; - *(.text.init) - . = ALIGN(0x10); - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - . = ALIGN(0x10); - - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - - . = ALIGN(0x10); - __text_end = .; - } > ddr_cached_32bit - - /* short/global data section */ - .sdata : ALIGN(0x10) - { - __sdata_load = LOADADDR(.sdata); - __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ - __global_pointer$ = . + 0x800; - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(0x10); - __sdata_end = .; - } > ddr_cached_32bit - - /* data section */ - .data : ALIGN(0x10) - { - __data_load = LOADADDR(.data); - __data_start = .; - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN(0x10); - __data_end = .; - } > ddr_cached_32bit - - /* sbss section */ - .sbss : ALIGN(0x10) - { - __sbss_start = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - . = ALIGN(0x10); - __sbss_end = .; - } > ddr_cached_32bit - - /* sbss section */ - .bss : ALIGN(0x10) - { - __bss_start = .; - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(0x10); - __bss_end = .; - } > ddr_cached_32bit - - /* End of uninitialized data segment */ - _end = .; - - .heap : ALIGN(0x10) - { - __heap_start = .; - . += HEAP_SIZE; - __heap_end = .; - . = ALIGN(0x10); - _heap_end = __heap_end; - } > ddr_cached_32bit - - /* must be on 4k boundary- corresponds to page size */ - .stack : ALIGN(0x1000) - { - PROVIDE(__app_stack_bottom = .); - . += STACK_SIZE_U54_APPLICATION; - PROVIDE(__app_stack_top = .); - } > ddr_cached_32bit - - /* - * used by a program loaded by a bootloader to store information passed - * from boot-loader - * a0 holds the hart ID - * a1 hold pointer to device data, which includes pointer to shared memory - * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the - * mss_sw_config.h - */ - .no_init : ALIGN(0x10) - { - PROVIDE(__uninit_bottom$ = .); - . += UNITITALISED_MEM; - PROVIDE(__uninit_top_h$ = .); - } > ddr_cached_32bit -} diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm-lma-scratchpad-vma.ld b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm-lma-scratchpad-vma.ld deleted file mode 100644 index b98f7342..00000000 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm-lma-scratchpad-vma.ld +++ /dev/null @@ -1,387 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ -/******************************************************************************* - * - * file name : mpfs-envm-lma-scratchpad-vma.ld - * Code starts from eNVM and relocates itself to an L2 cache scratchpad mapped in - * the Zero Device address range. - * - * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md - * which can be found under the link below: - * https://github.com/polarfire-soc/polarfire-soc-documentation - * - */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------------- - --- MSS hart Reset vector - -The MSS reset vector for each hart is stored securely in the MPFS. -The most common usage will be where the reset vector for each hart will be set -to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous -non-volatile storage. Normally this is where the initial boot-loader will -reside. (Note: The first 256B page of envm is used for metadata associated with -secure boot. When not using secure boot (mode 0,1), this area is still reserved -by convention. It allows easier transition from non-secure to secure boot flow -during the development process. -When debugging a bare metal program that is run out of reset from envm, a linker -script will be used whereby the program will run from LIM instead of envm. -In this case, the reset vector in the linker script is normally set to the -start of LIM, 0x0800_0000. -This means you are not continually programming the envm each time you load a -program and there is no limitation with break points when debugging. -See the mpfs-lim.ld example linker script when runing from LIM. - -------------------------------------------------------------------------------*/ - -MEMORY -{ - /* In this example, our reset vector is set to point to the */ - /* start at page 1 of the envm */ - envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 - dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k - u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k - u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k - u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k - u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k - l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k - scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1k of DTIM is used to run code when switching the envm clock */ - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k - /* DDR sections example */ - ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M - ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M - ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M - ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M - ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k - ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k -} - -HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ - -/* - * There is common area for shared variables, accessed from a pointer in a harts HLS - */ -SIZE_OF_COMMON_HART_MEM = 4k; - -/* - * The stack size needs to be calculated for your - * application. It must be Must be aligned - * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack - * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 - * stack hart1 - * TLS hart 1 - * etc - * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h - */ - -/* - * STACK_SIZE_xxx_STARTUP - * Stack size for each hart's startup code. - * Before copying itself to the scratchpad memory area and executing the code from there, the - * startup code is executing from LIM. The scratchpad area is not configured yet. This per-hart - * startup stack area is located in LIM and used during this phase of the startup code. - * STACK_SIZE_xxx_APPLICATION - * After the startup code executing from LIM configures the scratchpad memory, it configures - * the each hart's SP with this stack area for the respective hart's application function, - * (namely e51(), u54_1(), u54_2(), u54_3(), u54_4() ) to use it. - * This per-hart application stack area is located in scratchpad and used by application when - * it is executing from scratchpad. - * - */ -STACK_SIZE_E51_STARTUP = 4k; -STACK_SIZE_U54_1_STARTUP = 4k; -STACK_SIZE_U54_2_STARTUP = 4k; -STACK_SIZE_U54_3_STARTUP = 4k; -STACK_SIZE_U54_4_STARTUP = 4k; - -STACK_SIZE_E51_APPLICATION = 8k; -STACK_SIZE_U54_1_APPLICATION = 8k; -STACK_SIZE_U54_2_APPLICATION = 8k; -STACK_SIZE_U54_3_APPLICATION = 8k; -STACK_SIZE_U54_4_APPLICATION = 8k; - - -SECTIONS -{ - PROVIDE(__envm_start = ORIGIN(envm)); - PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); - PROVIDE(__l2lim_start = ORIGIN(l2lim)); - PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); - PROVIDE(__ddr_cached_32bit_start = ORIGIN(ddr_cached_32bit)); - PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_start = ORIGIN(ddr_non_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit)); - PROVIDE(__ddr_wcb_32bit_start = ORIGIN(ddr_wcb_32bit)); - PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit)); - PROVIDE(__ddr_cached_38bit_start = ORIGIN(ddr_cached_38bit)); - PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_start = ORIGIN(ddr_non_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit)); - PROVIDE(__ddr_wcb_38bit_start = ORIGIN(ddr_wcb_38bit)); - PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit)); - PROVIDE(__dtim_start = ORIGIN(dtim)); - PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); - PROVIDE(__e51itim_start = ORIGIN(e51_itim)); - PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); - PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); - PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); - PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); - PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); - PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); - PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); - PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); - PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); - - . = __envm_start; - .text_init : ALIGN(0x10) - { - *(.text.init) - *system_startup.o (.text .text* .rodata .rodata* .srodata*) - *mtrap.o (.text .text* .rodata .rodata* .srodata*) - *mss_h2f.o (.text .text* .rodata .rodata* .srodata*) - *mss_l2_cache.o (.text .text* .rodata .rodata* .srodata*) - . = ALIGN(0x10); - } >envm - - .text : ALIGN(0x10) - { - __text_load = LOADADDR(.text); - . = ALIGN(0x10); - __text_start = .; - /* placed at the start of used scratchpad, used as check to verify enough available in code */ - __l2_scratchpad_vma_start = .; - - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - . = ALIGN(0x10); - - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - - . = ALIGN(0x10); - __text_end = .; - } >scratchpad AT> envm - - /* short/global data section */ - .sdata : ALIGN(0x10) - { - __sdata_load = LOADADDR(.sdata); - __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ - __global_pointer$ = . + 0x800; - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(0x10); - __sdata_end = .; - } >scratchpad AT> envm - - /* data section */ - .data : ALIGN(0x10) - { - __data_load = LOADADDR(.data); - __data_start = .; - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN(0x10); - __data_end = .; - } > scratchpad AT> envm - - /* sbss section */ - .sbss : ALIGN(0x10) - { - __sbss_start = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - . = ALIGN(0x10); - __sbss_end = .; - } > scratchpad - - /* sbss section */ - .bss : ALIGN(0x10) - { - __bss_start = .; - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(0x10); - __bss_end = .; - } > scratchpad - - /* End of uninitialized data segment */ - _end = .; - - .heap : ALIGN(0x10) - { - __heap_start = .; - . += HEAP_SIZE; - __heap_end = .; - . = ALIGN(0x10); - _heap_end = __heap_end; - __l2_scratchpad_vma_end = .; - } > scratchpad - - - /* must be on 4k boundary- corresponds to page size */ - .stack_e51 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h0$ = .); - . += STACK_SIZE_E51_STARTUP; - PROVIDE(__stack_top_h0$ = .); - } > l2lim - - /* must be on 4k boundary- corresponds to page size */ - .stack_u54_1 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h1$ = .); - . += STACK_SIZE_U54_1_STARTUP; - PROVIDE(__stack_top_h1$ = .); - } > l2lim - - /* must be on 4k boundary- corresponds to page size */ - .stack_u54_2 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h2$ = .); - . += STACK_SIZE_U54_2_STARTUP; - PROVIDE(__stack_top_h2$ = .); - } > l2lim - - /* */ - .stack_u54_3 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h3$ = .); - . += STACK_SIZE_U54_3_STARTUP; - PROVIDE(__stack_top_h3$ = .); - } > l2lim - - /* */ - .stack_u54_4 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h4$ = .); - . += STACK_SIZE_U54_4_STARTUP; - PROVIDE(__stack_top_h4$ = .); - } > l2lim - /* application stacks defined below here */ - - /* must be on 4k boundary- corresponds to page size */ - .app_stack_e51 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h0 = .); - . += STACK_SIZE_E51_APPLICATION; - PROVIDE(__app_stack_top_h0 = .); - } > scratchpad - - /* must be on 4k boundary- corresponds to page size */ - .app_stack_u54_1 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h1$ = .); - . += STACK_SIZE_U54_1_APPLICATION; - PROVIDE(__app_stack_top_h1 = .); - } > scratchpad - - /* */ - .app_stack_u54_2 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h2 = .); - . += STACK_SIZE_U54_2_APPLICATION; - PROVIDE(__app_stack_top_h2 = .); - } > scratchpad - - /* */ - .app_stack_u54_3 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h3 = .); - . += STACK_SIZE_U54_3_APPLICATION; - PROVIDE(__app_stack_top_h3 = .); - } > scratchpad - - /* */ - .app_stack_u54_4 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h4 = .); - . += STACK_SIZE_U54_4_APPLICATION; - PROVIDE(__app_stack_top_h4 = .); - } > scratchpad - - /* - * memory shared accross harts. - * The boot Hart Local Storage holds a pointer to this area for each hart if - * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the - * mss_sw_config.h - */ - .app_hart_common : /* ALIGN(0x1000) */ - { - PROVIDE(__app_hart_common_start = .); - . += SIZE_OF_COMMON_HART_MEM; - PROVIDE(__app_hart_common_end = .); - /* place at the end of used scratchpad, used as check to verify enough available in code */ - __l2_scratchpad_vma_end = .; - } > scratchpad - - /* - * The .ram_code section will contain the code That is run from RAM. - * We are using this code to switch the clocks including envm clock. - * This can not be done when running from envm - * This will need to be copied to ram, before any of this code is run. - */ - .ram_code : - { - . = ALIGN (4); - __sc_load = LOADADDR (.ram_code); - __sc_start = .; - *(.ram_codetext) /* .ram_codetext sections (code) */ - *(.ram_codetext*) /* .ram_codetext* sections (code) */ - *(.ram_coderodata) /* read-only data (constants) */ - *(.ram_coderodata*) - . = ALIGN (4); - __sc_end = .; - /* place __start_of_free_lim$ after last allocation of l2lim */ - PROVIDE(__start_of_free_lim$ = .); - } >switch_code AT> envm /* On the MPFS for startup code use, >switch_code AT>envm */ -} - - diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm.ld b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm.ld deleted file mode 100644 index 29817bd0..00000000 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-envm.ld +++ /dev/null @@ -1,344 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ -/******************************************************************************* - * - * file name : mpfs_envm.ld - * Use with Bare metal startup code. - * Startup code runs from envm on MSS reset - * - * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md - * which can be found under the link below: - * https://github.com/polarfire-soc/polarfire-soc-documentation - * - */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------------- - --- MSS hart Reset vector - -The MSS reset vector for each hart is stored securely in the MPFS. -The most common usage will be where the reset vector for each hart will be set -to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous -non-volatile storage. Normally this is where the initial boot-loader will -reside. (Note: The first 256B page of envm is used for metadata associated with -secure boot. When not using secure boot (mode 0,1), this area is still reserved -by convention. It allows easier transition from non-secure to secure boot flow -during the development process. -When debugging a bare metal program that is run out of reset from envm, a linker -script will be used whereby the program will run from LIM instead of envm. -In this case, the reset vector in the linker script is normally set to the -start of LIM, 0x0800_0000. -This means you are not continually programming the envm each time you load a -program and there is no limitation with break points when debugging. -See the mpfs-lim.ld example linker script when runing from LIM. - -------------------------------------------------------------------------------*/ - - -MEMORY -{ - /* In this example, our reset vector is set to point to the */ - /* start at page 1 of the envm */ - envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 - dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k - u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k - u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k - u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k - u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k - l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k - scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1K of DTIM is used to run code when switching the envm clock */ - switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k - /* DDR sections example */ - ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M - ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M - ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M - ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M - ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k - ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k -} - -HEAP_SIZE = 8k; /* needs to be calculated for your application */ - -/* - * There is common area for shared variables, accessed from a pointer in a harts HLS - */ -SIZE_OF_COMMON_HART_MEM = 4k; - -/* - * The stack size needs to be calculated for your - * application. It must be Must be aligned - * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack - * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 - * stack hart1 - * TLS hart 1 - * etc - * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h - */ - -/* - * Stack size for each hart's application. - * These are the stack sizes that will be allocated to each hart before starting - * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). - */ -STACK_SIZE_E51_APPLICATION = 8k; -STACK_SIZE_U54_1_APPLICATION = 8k; -STACK_SIZE_U54_2_APPLICATION = 8k; -STACK_SIZE_U54_3_APPLICATION = 8k; -STACK_SIZE_U54_4_APPLICATION = 8k; - -SECTIONS -{ - PROVIDE(__envm_start = ORIGIN(envm)); - PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); - PROVIDE(__l2lim_start = ORIGIN(l2lim)); - PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); - PROVIDE(__ddr_cached_32bit_start = ORIGIN(ddr_cached_32bit)); - PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_start = ORIGIN(ddr_non_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit)); - PROVIDE(__ddr_wcb_32bit_start = ORIGIN(ddr_wcb_32bit)); - PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit)); - PROVIDE(__ddr_cached_38bit_start = ORIGIN(ddr_cached_38bit)); - PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_start = ORIGIN(ddr_non_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit)); - PROVIDE(__ddr_wcb_38bit_start = ORIGIN(ddr_wcb_38bit)); - PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit)); - PROVIDE(__dtim_start = ORIGIN(dtim)); - PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); - PROVIDE(__e51itim_start = ORIGIN(e51_itim)); - PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); - PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); - PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); - PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); - PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); - PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); - PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); - PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); - PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); - - . = __envm_start; - .text : ALIGN(0x10) - { - __text_load = LOADADDR(.text); - __text_start = .; - *(.text.init) - /* *entry.o(.text); */ - . = ALIGN(0x10); - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - . = ALIGN(0x10); - - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - - . = ALIGN(0x10); - __text_end = .; - } > envm - - .l2_scratchpad : ALIGN(0x10) - { - __l2_scratchpad_load = LOADADDR(.l2_scratchpad); - __l2_scratchpad_start = .; - __l2_scratchpad_vma_start = .; - *(.l2_scratchpad) - . = ALIGN(0x10); - __l2_scratchpad_end = .; - __l2_scratchpad_vma_end = .; - } >scratchpad AT> envm - - /* - * The .ram_code section will contain the code that is run from RAM. - * We are using this code to switch the clocks including envm clock. - * This can not be done when running from envm - * This will need to be copied to ram, before any of this code is run. - */ - .ram_code : - { - . = ALIGN (4); - __sc_load = LOADADDR (.ram_code); - __sc_start = .; - *(.ram_codetext) /* .ram_codetext sections (code) */ - *(.ram_codetext*) /* .ram_codetext* sections (code) */ - *(.ram_coderodata) /* read-only data (constants) */ - *(.ram_coderodata*) - . = ALIGN (4); - __sc_end = .; - } >switch_code_dtim AT>envm - - /* - * The .ddr_code section will contain the code that is run from DDR. - * This is to verify DDR working as expeted - */ - .ddr_code : - { - . = ALIGN (4); - __ddr_load = LOADADDR (.ram_code); - __ddr_start = .; - *(.ddr_codetext) /* .ram_codetext sections (code) */ - *(.ddr_codetext*) /* .ram_codetext* sections (code) */ - *(.ddr_coderodata) /* read-only data (constants) */ - *(.ddr_coderodata*) - . = ALIGN (4); - __ddr_end = .; - } >ddr_cached_32bit AT>envm - - /* short/global data section */ - .sdata : ALIGN(0x10) - { - __sdata_load = LOADADDR(.sdata); - __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set - point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. - Perhaps we should add check/warning to linker script if sdata is > 4k */ - __global_pointer$ = . + 0x800; - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(0x10); - __sdata_end = .; - } > l2lim AT > envm - - /* data section */ - .data : ALIGN(0x10) - { - __data_load = LOADADDR(.data); - __data_start = .; - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN(0x10); - __data_end = .; - } > l2lim AT > envm - - /* sbss section */ - .sbss : ALIGN(0x10) - { - __sbss_start = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - . = ALIGN(0x10); - __sbss_end = .; - } > l2lim - - /* sbss section */ - .bss : ALIGN(0x10) - { - __bss_start = .; - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(0x10); - __bss_end = .; - } > l2lim - - /* End of uninitialized data segment */ - _end = .; - - .heap : ALIGN(0x10) - { - __heap_start = .; - . += HEAP_SIZE; - __heap_end = .; - . = ALIGN(0x10); - _heap_end = __heap_end; - } > l2lim - - /* must be on 4k boundary (0x1000) - corresponds to page size, when using - memory mem */ - /* protection */ - /* .stack : ALIGN(0x1000) */ - .stack : ALIGN(0x10) - { - PROVIDE(__stack_bottom_h0$ = .); - PROVIDE(__app_stack_bottom_h0 = .); - . += STACK_SIZE_E51_APPLICATION; - PROVIDE(__app_stack_top_h0 = .); - PROVIDE(__stack_top_h0$ = .); - - PROVIDE(__stack_bottom_h1$ = .); - PROVIDE(__app_stack_bottom_h1$ = .); - . += STACK_SIZE_U54_1_APPLICATION; - PROVIDE(__app_stack_top_h1 = .); - PROVIDE(__stack_top_h1$ = .); - - PROVIDE(__stack_bottom_h2$ = .); - PROVIDE(__app_stack_bottom_h2 = .); - . += STACK_SIZE_U54_2_APPLICATION; - PROVIDE(__app_stack_top_h2 = .); - PROVIDE(__stack_top_h2$ = .); - - PROVIDE(__stack_bottom_h3$ = .); - PROVIDE(__app_stack_bottom_h3 = .); - . += STACK_SIZE_U54_3_APPLICATION; - PROVIDE(__app_stack_top_h3 = .); - PROVIDE(__stack_top_h3$ = .); - - PROVIDE(__stack_bottom_h4$ = .); - PROVIDE(__app_stack_bottom_h4 = .); - . += STACK_SIZE_U54_4_APPLICATION; - PROVIDE(__app_stack_top_h4 = .); - PROVIDE(__stack_top_h4$ = .); - - /* place __start_of_free_lim$ after last allocation of l2_lim */ - . = ALIGN(0x10); - PROVIDE(__start_of_free_lim$ = .); - } > l2lim - - /* - * memory shared accross harts. - * The boot Hart Local Storage holds a pointer to this area for each hart if - * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the - * mss_sw_config.h - */ - .app_hart_common : /* ALIGN(0x1000) */ - { - PROVIDE(__app_hart_common_start = .); - . += SIZE_OF_COMMON_HART_MEM; - PROVIDE(__app_hart_common_end = .); - } > l2lim -} - diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim-lma-scratchpad-vma.ld b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim-lma-scratchpad-vma.ld deleted file mode 100644 index 391c47bf..00000000 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim-lma-scratchpad-vma.ld +++ /dev/null @@ -1,375 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ -/******************************************************************************* - * - * file name : mpfs-lim-lma-scratchpad-vma.ld - * Used when debugging code. The debugger loads the code to LIM. - * Code starts from LIM and relocates itself to an L2 cache scratchpad mapped in - * the Zero Device address range. - * - * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md - * which can be found under the link below: - * https://github.com/polarfire-soc/polarfire-soc-documentation - * - */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------------- - --- MSS hart Reset vector - -The MSS reset vector for each hart is stored securely in the MPFS. -The most common usage will be where the reset vector for each hart will be set -to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous -non-volatile storage. Normally this is where the initial boot-loader will -reside. (Note: The first 256B page of envm is used for metadata associated with -secure boot. When not using secure boot (mode 0,1), this area is still reserved -by convention. It allows easier transition from non-secure to secure boot flow -during the development process. - -------------------------------------------------------------------------------*/ - -MEMORY -{ - envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 - dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k - u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k - u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k - u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k - u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k - l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k - scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1k of DTIM is used to run code when switching the envm clock */ - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k - /* DDR sections example */ - ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M - ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M - ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M - ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M - ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k - ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k -} - -HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ - -/* - * There is common area for shared variables, accessed from a pointer in a harts HLS - */ -SIZE_OF_COMMON_HART_MEM = 4k; - -/* - * The stack size needs to be calculated for your - * application. It must be Must be aligned - * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack - * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 - * stack hart1 - * TLS hart 1 - * etc - * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h - */ - -/* - * STACK_SIZE_xxx_STARTUP - * Stack size for each hart's startup code. - * Before copying itself to the scratchpad memory area and executing the code from there, the - * startup code is executing from LIM. The scratchpad area is not configured yet. This per-hart - * startup stack area is located in LIM and used during this phase of the startup code. - * STACK_SIZE_xxx_APPLICATION - * After the startup code executing from LIM configures the scratchpad memory, it configures - * the each hart's SP with this stack area for the respective hart's application function, - * (namely e51(), u54_1(), u54_2(), u54_3(), u54_4() ) to use it. - * This per-hart application stack area is located in scratchpad and used by application when - * it is executing from scratchpad. - * - */ -STACK_SIZE_E51_STARTUP = 4k; -STACK_SIZE_U54_1_STARTUP = 4k; -STACK_SIZE_U54_2_STARTUP = 4k; -STACK_SIZE_U54_3_STARTUP = 4k; -STACK_SIZE_U54_4_STARTUP = 4k; - -STACK_SIZE_E51_APPLICATION = 8k; -STACK_SIZE_U54_1_APPLICATION = 8k; -STACK_SIZE_U54_2_APPLICATION = 8k; -STACK_SIZE_U54_3_APPLICATION = 8k; -STACK_SIZE_U54_4_APPLICATION = 8k; - -SECTIONS -{ - PROVIDE(__envm_start = ORIGIN(envm)); - PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); - PROVIDE(__l2lim_start = ORIGIN(l2lim)); - PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); - PROVIDE(__ddr_cached_32bit_start = ORIGIN(ddr_cached_32bit)); - PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_start = ORIGIN(ddr_non_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit)); - PROVIDE(__ddr_wcb_32bit_start = ORIGIN(ddr_wcb_32bit)); - PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit)); - PROVIDE(__ddr_cached_38bit_start = ORIGIN(ddr_cached_38bit)); - PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_start = ORIGIN(ddr_non_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit)); - PROVIDE(__ddr_wcb_38bit_start = ORIGIN(ddr_wcb_38bit)); - PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit)); - PROVIDE(__dtim_start = ORIGIN(dtim)); - PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); - PROVIDE(__e51itim_start = ORIGIN(e51_itim)); - PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); - PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); - PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); - PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); - PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); - PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); - PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); - PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); - PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); - - . = __l2lim_start; - .text_init : ALIGN(0x10) - { - *(.text.init) - *system_startup.o (.text .text* .rodata .rodata* .srodata*) - *mtrap.o (.text .text* .rodata .rodata* .srodata*) - *mss_h2f.o (.text .text* .rodata .rodata* .srodata*) - *mss_l2_cache.o (.text .text* .rodata .rodata* .srodata*) - . = ALIGN(0x10); - } >l2lim - - .text : ALIGN(0x10) - { - __text_load = LOADADDR(.text); - . = ALIGN(0x10); - __text_start = .; - /* placed at the start of used scratchpad, used as check to verify enough available in code */ - __l2_scratchpad_vma_start = .; - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - . = ALIGN(0x10); - - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - - . = ALIGN(0x10); - __text_end = .; - } >scratchpad AT> l2lim - - /* short/global data section */ - .sdata : ALIGN(0x10) - { - __sdata_load = LOADADDR(.sdata); - __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ - __global_pointer$ = . + 0x800; - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(0x10); - __sdata_end = .; - } >scratchpad AT> l2lim - - /* data section */ - .data : ALIGN(0x10) - { - __data_load = LOADADDR(.data); - __data_start = .; - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN(0x10); - __data_end = .; - } > scratchpad AT> l2lim - - /* sbss section */ - .sbss : ALIGN(0x10) - { - __sbss_start = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - . = ALIGN(0x10); - __sbss_end = .; - } > scratchpad - - /* sbss section */ - .bss : ALIGN(0x10) - { - __bss_start = .; - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(0x10); - __bss_end = .; - } > scratchpad - - /* End of uninitialized data segment */ - _end = .; - - .heap : ALIGN(0x10) - { - __heap_start = .; - . += HEAP_SIZE; - __heap_end = .; - . = ALIGN(0x10); - _heap_end = __heap_end; - } > scratchpad - - /* must be on 4k boundary- corresponds to page size */ - .stack_e51 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h0$ = .); - . += STACK_SIZE_E51_STARTUP; - PROVIDE(__stack_top_h0$ = .); - } > l2lim - - /* must be on 4k boundary- corresponds to page size */ - .stack_u54_1 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h1$ = .); - . += STACK_SIZE_U54_1_STARTUP; - PROVIDE(__stack_top_h1$ = .); - } > l2lim - - /* must be on 4k boundary- corresponds to page size */ - .stack_u54_2 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h2$ = .); - . += STACK_SIZE_U54_2_STARTUP; - PROVIDE(__stack_top_h2$ = .); - } > l2lim - - /* */ - .stack_u54_3 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h3$ = .); - . += STACK_SIZE_U54_3_STARTUP; - PROVIDE(__stack_top_h3$ = .); - } > l2lim - - /* */ - .stack_u54_4 : /* ALIGN(0x1000) */ - { - PROVIDE(__stack_bottom_h4$ = .); - . += STACK_SIZE_U54_4_STARTUP; - PROVIDE(__stack_top_h4$ = .); - } > l2lim - /* application stacks defined below here */ - - /* must be on 4k boundary- corresponds to page size */ - .app_stack_e51 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h0 = .); - . += STACK_SIZE_E51_APPLICATION; - PROVIDE(__app_stack_top_h0 = .); - } > scratchpad - - /* must be on 4k boundary- corresponds to page size */ - .app_stack_u54_1 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h1$ = .); - . += STACK_SIZE_U54_1_APPLICATION; - PROVIDE(__app_stack_top_h1 = .); - } > scratchpad - - /* */ - .app_stack_u54_2 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h2 = .); - . += STACK_SIZE_U54_2_APPLICATION; - PROVIDE(__app_stack_top_h2 = .); - } > scratchpad - - /* */ - .app_stack_u54_3 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h3 = .); - . += STACK_SIZE_U54_3_APPLICATION; - PROVIDE(__app_stack_top_h3 = .); - } > scratchpad - - /* */ - .app_stack_u54_4 : /* ALIGN(0x1000) */ - { - PROVIDE(__app_stack_bottom_h4 = .); - . += STACK_SIZE_U54_4_APPLICATION; - PROVIDE(__app_stack_top_h4 = .); - } > scratchpad - - - /* - * memory shared accross harts. - * The boot Hart Local Storage holds a pointer to this area for each hart if - * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the - * mss_sw_config.h - */ - .app_hart_common : /* ALIGN(0x1000) */ - { - PROVIDE(__app_hart_common_start = .); - . += SIZE_OF_COMMON_HART_MEM; - PROVIDE(__app_hart_common_end = .); - /* place at the end of used scratchpad, used as check to verify enough available in code */ - __l2_scratchpad_vma_end = .; - } > scratchpad - - /* - * The .ram_code section will contain the code That is run from RAM. - * We are using this code to switch the clocks including envm clock. - * This can not be done when running from envm - * This will need to be copied to ram, before any of this code is run. - */ - .ram_code : - { - . = ALIGN (4); - __sc_load = LOADADDR (.ram_code); - __sc_start = .; - *(.ram_codetext) /* .ram_codetext sections (code) */ - *(.ram_codetext*) /* .ram_codetext* sections (code) */ - *(.ram_coderodata) /* read-only data (constants) */ - *(.ram_coderodata*) - . = ALIGN (4); - __sc_end = .; - /* place __start_of_free_lim$ after last allocation of l2lim */ - PROVIDE(__start_of_free_lim$ = .); - } >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>envm */ - -} diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim.ld b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim.ld deleted file mode 100644 index 908cf23e..00000000 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/linker/mpfs-lim.ld +++ /dev/null @@ -1,309 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ -/******************************************************************************* - * - * file name : mpfs_lim.ld - * Used when debugging code. The debugger loads the code to LIM. - * - * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md - * which can be found under the link below: - * https://github.com/polarfire-soc/polarfire-soc-documentation - * - */ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -/*----------------------------------------------------------------------------- - --- MSS hart Reset vector - -The MSS reset vector for each hart is stored securely in the MPFS. -The most common usage will be where the reset vector for each hart will be set -to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous -non-volatile storage. Normally this is where the initial boot-loader will -reside. (Note: The first 256B page of envm is used for metadata associated with -secure boot. When not using secure boot (mode 0,1), this area is still reserved -by convention. It allows easier transition from non-secure to secure boot flow -during the development process. - -------------------------------------------------------------------------------*/ - -MEMORY -{ - envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 - dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k - e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k - u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k - u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k - u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k - u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k - l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k - scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* DDR sections example */ - ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M - ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M - ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M - ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M - ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k - ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k -} - -HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ - -/* - * There is common area for shared variables, accessed from a pointer in a harts HLS - */ -SIZE_OF_COMMON_HART_MEM = 4k; - -/* - * The stack size needs to be calculated for your - * application. It must be Must be aligned - * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack - * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 - * stack hart1 - * TLS hart 1 - * etc - * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h - */ - -/* - * Stack size for each hart's application. - * These are the stack sizes that will be allocated to each hart before starting - * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). - */ -STACK_SIZE_E51_APPLICATION = 8k; -STACK_SIZE_U54_1_APPLICATION = 8k; -STACK_SIZE_U54_2_APPLICATION = 8k; -STACK_SIZE_U54_3_APPLICATION = 8k; -STACK_SIZE_U54_4_APPLICATION = 8k; - - -SECTIONS -{ - PROVIDE(__envm_start = ORIGIN(envm)); - PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); - PROVIDE(__l2lim_start = ORIGIN(l2lim)); - PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); - PROVIDE(__ddr_cached_32bit_start = ORIGIN(ddr_cached_32bit)); - PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_start = ORIGIN(ddr_non_cached_32bit)); - PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit)); - PROVIDE(__ddr_wcb_32bit_start = ORIGIN(ddr_wcb_32bit)); - PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit)); - PROVIDE(__ddr_cached_38bit_start = ORIGIN(ddr_cached_38bit)); - PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_start = ORIGIN(ddr_non_cached_38bit)); - PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit)); - PROVIDE(__ddr_wcb_38bit_start = ORIGIN(ddr_wcb_38bit)); - PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit)); - PROVIDE(__dtim_start = ORIGIN(dtim)); - PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); - PROVIDE(__e51itim_start = ORIGIN(e51_itim)); - PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); - PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); - PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); - PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); - PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); - PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); - PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); - PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); - PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); - /* text: text code section */ - . = __l2lim_start; - .text : ALIGN(0x10) - { - __text_load = LOADADDR(.text); - __text_start = .; - *(.text.init) - . = ALIGN(0x10); - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - . = ALIGN(0x10); - - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - - . = ALIGN(0x10); - __text_end = .; - . = ALIGN(0x10); - } > l2lim - - .l2_scratchpad : ALIGN(0x10) - { - . = ALIGN (0x10); - __l2_scratchpad_load = LOADADDR(.l2_scratchpad); - __l2_scratchpad_start = .; - __l2_scratchpad_vma_start = .; - *(.l2_scratchpad) - . = ALIGN(0x10); - __l2_scratchpad_end = .; - __l2_scratchpad_vma_end = .; - } >scratchpad AT> l2lim - - /* - * The .ram_code section will contain the code That is run from RAM. - * We are using this code to switch the clocks including eNVM clock. - * This can not be done when running from eNVM - * This will need to be copied to ram, before any of this code is run. - */ - .ram_code : - { - . = ALIGN (4); - __sc_load = LOADADDR (.ram_code); - __sc_start = .; - *(.ram_codetext) /* .ram_codetext sections (code) */ - *(.ram_codetext*) /* .ram_codetext* sections (code) */ - *(.ram_coderodata) /* read-only data (constants) */ - *(.ram_coderodata*) - . = ALIGN (4); - __sc_end = .; - } >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>eNVM */ - - /* short/global data section */ - .sdata : ALIGN(0x10) - { - __sdata_load = LOADADDR(.sdata); - __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ - __global_pointer$ = . + 0x800; - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(0x10); - __sdata_end = .; - } > l2lim - - /* data section */ - .data : ALIGN(0x10) - { - __data_load = LOADADDR(.data); - __data_start = .; - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN(0x10); - __data_end = .; - } > l2lim - - /* sbss section */ - .sbss : ALIGN(0x10) - { - __sbss_start = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - . = ALIGN(0x10); - __sbss_end = .; - } > l2lim - - /* sbss section */ - .bss : ALIGN(0x10) - { - __bss_start = .; - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(0x10); - __bss_end = .; - } > l2lim - - /* End of uninitialized data segment */ - _end = .; - - .heap : ALIGN(0x10) - { - __heap_start = .; - . += HEAP_SIZE; - __heap_end = .; - . = ALIGN(0x10); - _heap_end = __heap_end; - } > l2lim - - /* must be on 4k boundary- corresponds to page size */ - .stack : ALIGN(0x1000) - { - PROVIDE(__stack_bottom_h0$ = .); - PROVIDE(__app_stack_bottom_h0 = .); - . += STACK_SIZE_E51_APPLICATION; - PROVIDE(__app_stack_top_h0 = .); - PROVIDE(__stack_top_h0$ = .); - - PROVIDE(__stack_bottom_h1$ = .); - PROVIDE(__app_stack_bottom_h1$ = .); - . += STACK_SIZE_U54_1_APPLICATION; - PROVIDE(__app_stack_top_h1 = .); - PROVIDE(__stack_top_h1$ = .); - - PROVIDE(__stack_bottom_h2$ = .); - PROVIDE(__app_stack_bottom_h2 = .); - . += STACK_SIZE_U54_2_APPLICATION; - PROVIDE(__app_stack_top_h2 = .); - PROVIDE(__stack_top_h2$ = .); - - PROVIDE(__stack_bottom_h3$ = .); - PROVIDE(__app_stack_bottom_h3 = .); - . += STACK_SIZE_U54_3_APPLICATION; - PROVIDE(__app_stack_top_h3 = .); - PROVIDE(__stack_top_h3$ = .); - - PROVIDE(__stack_bottom_h4$ = .); - PROVIDE(__app_stack_bottom_h4 = .); - . += STACK_SIZE_U54_4_APPLICATION; - PROVIDE(__app_stack_top_h4 = .); - PROVIDE(__stack_top_h4$ = .); - - } > l2lim - - /* - * memory shared accross harts. - * The boot Hart Local Storage holds a pointer to this area for each hart if - * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the - * mss_sw_config.h - */ - .app_hart_common : /* ALIGN(0x1000) */ - { - PROVIDE(__app_hart_common_start = .); - . += SIZE_OF_COMMON_HART_MEM; - PROVIDE(__app_hart_common_end = .); - } > l2lim -} - diff --git a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h index 77c7d9ad..5a6c0c92 100644 --- a/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h +++ b/mpfs-watchdog-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -161,9 +161,16 @@ * The reason you may want to use below is to save code space. */ #define SGMII_SUPPORT -#define DDR_SUPPORT +//#define DDR_SUPPORT #define MSSIO_SUPPORT +/* + * Uncomment MICROCHIP_STDIO_THRU_MMUARTx to enable stdio port + * Note: you must have mss_mmuart driver source code included in the project. + */ +//#define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart0_lo +//#define MICROCHIP_STDIO_BAUD_RATE MSS_UART_115200_BAUD + /* * DDR software options */ diff --git a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.c b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.c index fa78be99..2ead827b 100644 --- a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.c +++ b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -62,6 +62,7 @@ static uint32_t g_uart_axi_pos = 0x0u; #define FCR_TRIG_LEVEL_MASK 0xC0u #define IIRF_MASK 0x0Fu +#define IER_MASK 0x0Du #define INVALID_INTERRUPT 0u #define INVALID_IRQ_HANDLER ((mss_uart_irq_handler_t) 0) @@ -439,7 +440,7 @@ MSS_UART_enable_irq { ASSERT(MSS_UART_INVALID_IRQ > irq_mask); - enable_irq(this_uart); + if (MSS_UART_INVALID_IRQ > irq_mask) { @@ -448,10 +449,13 @@ MSS_UART_enable_irq * bit 1 - Transmitter Holding Register Empty Interrupt * bit 2 - Receiver Line Status Interrupt * bit 3 - Modem Status Interrupt + * + * The use of the IER_MASK macro is to prevent the THRE to be + * set at this point of the design flow and to lead to a break + * later on. */ this_uart->hw_reg->IER |= ((uint8_t)(((uint32_t)irq_mask & - (uint32_t)IIRF_MASK))); - + (uint32_t)IER_MASK))); /* * bit 4 - Receiver time-out interrupt @@ -1317,12 +1321,12 @@ MSS_UART_enable_local_irq mss_uart_instance_t * this_uart ) { - /* Make sure to disable interrupt on PLIC as it might have been enabled - * when application registered an interrupt handler function or - * used MSS_UART_enable_irq() to enable PLIC interrupt */ - disable_irq(this_uart); + /* Make sure to disable interrupt on PLIC as it might have been enabled + * when application registered an interrupt handler function or + * used MSS_UART_enable_irq() to enable PLIC interrupt */ + disable_irq(this_uart); - this_uart->local_irq_enabled = 1u; + this_uart->local_irq_enabled = 1u; /* Enable local interrupt UART instance. * Local interrupt will be enabled on the HART on which the application @@ -1650,7 +1654,7 @@ uart_isr } /* NACK interrupt */ - if (this_uart->hw_reg->IIM &ENACKI) + if (this_uart->hw_reg->IIM & ENACKI_MASK) { ASSERT(NULL_HANDLER != this_uart->nack_handler); @@ -1661,7 +1665,7 @@ uart_isr } /* PID parity error interrupt */ - if (this_uart->hw_reg->IIM & EPID_PEI) + if (this_uart->hw_reg->IIM & EPID_PEI_MASK) { ASSERT(NULL_HANDLER != this_uart->pid_pei_handler); @@ -1672,7 +1676,7 @@ uart_isr } /* LIN break detection interrupt */ - if (this_uart->hw_reg->IIM & ELINBI) + if (this_uart->hw_reg->IIM & ELINBI_MASK) { ASSERT(NULL_HANDLER != this_uart->break_handler); @@ -1683,7 +1687,7 @@ uart_isr } /* LIN Sync detection interrupt */ - if (this_uart->hw_reg->IIM & ELINSI) + if (this_uart->hw_reg->IIM & ELINSI_MASK) { ASSERT(NULL_HANDLER != this_uart->sync_handler); diff --git a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.h b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.h index b2ff63d0..01994bb4 100644 --- a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.h +++ b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -777,8 +777,7 @@ struct mss_uart_instance{ uint32_t baudrate; /*!< Operating baud rate. */ uint8_t lineconfig; /*!< Line configuration parameters. */ uint8_t status; /*!< Sticky line status. */ - uint16_t padding; /*!< Padding for alignment */ - + /* transmit related info (used with interrupt driven transmit): */ const uint8_t * tx_buffer; /*!< Pointer to transmit buffer. */ uint32_t tx_buff_size; /*!< Transmit buffer size. */ @@ -803,7 +802,7 @@ struct mss_uart_instance{ /* LIN sync detection interrupt handler */ mss_uart_irq_handler_t sync_handler; /*!< Pointer to user registered LIN sync detection handler. */ uint8_t local_irq_enabled; /*!< check if local interrupt were enabled on this instance*/ - uint8_t padding1[7]; /*!< padding for alignment */ + void* user_data; /*!< Pointer to user provided pointer for user specific use. */ }; @@ -1687,17 +1686,17 @@ MSS_UART_set_loopback /***************************************************************************//** The MSS_UART_enable_irq() function enables the MSS UART interrupts specified - by the irq_mask parameter. The irq_mask parameter identifies the MSS UART - interrupts by bit position, as defined in the interrupt enable register (IER) - of MSS UART. The MSS UART interrupts and their identifying irq_mask bit - positions are as follows: - When an irq_mask bit position is set to 1, this function enables the - corresponding MSS UART interrupt in the IER register. When an irq_mask bit - position is set to 0, the state of the corresponding interrupt remains - unchanged in the IER register. - - Note: The MSS_UART_enable_irq() function also enables the MSS UART instance - interrupt in the PolarFire SoC Core Complex PLIC. + by the irq_mask parameter. The irq_mask parameter identifies the MSS UART + interrupts by bit position, as defined in the interrupt enable register (IER) + of MSS UART. The MSS UART interrupts and their identifying irq_mask bit + positions are as follows: When an irq_mask bit position is set to 1, this + function enables the corresponding MSS UART interrupt in the IER register. + + Note: the Transmit Buffer Empty interrupt is not enabled in this API. Indeed, + enabling it here leads to an interrupt occuring before any data is passed to + the UART, causing a crash. The TBE bit in the IER register is set + in the MSS_UART_irq_tx() function, that actually starts the transmission. + @param this_uart The this_uart parameter is a pointer to an mss_uart_instance_t @@ -1734,12 +1733,17 @@ MSS_UART_set_loopback int main(void) { uint8_t tx_buff[10] = "abcdefghi"; + uint32_t interrupt_priority = 4; + enable_interrupts(); + (void) mss_config_clk_rst(MSS_PERIPH_MMUART0, (uint8_t) 1, PERIPHERAL_ON); MSS_UART_init(&g_mss_uart0_lo, - MSS_UART_57600_BAUD, - MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); - - MSS_UART_enable_irq(&g_mss_uart0_lo,(MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + PLIC_init(); + MSS_UART_enable_irq(&g_mss_uart0_lo, (MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + PLIC_SetPriority(MMUART0_PLIC_77, interrupt_priority); + PLIC_SetPriority_Threshold(0); return(0); } diff --git a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h index d550810a..bb1561ac 100644 --- a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h +++ b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_mmuart/mss_uart_regs.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_watchdog/mss_watchdog.h b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_watchdog/mss_watchdog.h index 27643332..34118da3 100644 --- a/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_watchdog/mss_watchdog.h +++ b/mpfs-watchdog-interrupt/src/platform/drivers/mss/mss_watchdog/mss_watchdog.h @@ -551,7 +551,7 @@ MSS_WD_enable_mvrp_irq mss_watchdog_num_t wd_num ) { - wdog_hw_base[wd_num]->STATUS |= 0x03; + if ((WATCHDOG_TypeDef*)0 != wdog_hw_base[wd_num]) { wdog_hw_base[wd_num]->CONTROL |= MSS_WDOG_INTEN_MVRP_MASK; diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/bits.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/bits.h index b2df5f55..9e89d7e9 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/bits.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/bits.h @@ -38,8 +38,13 @@ extern "C" { #define likely(x) __builtin_expect((x), 1) #define unlikely(x) __builtin_expect((x), 0) -#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) -#define ROUNDDOWN(a, b) ((a)/(b)*(b)) +#ifndef ROUNDUP +# define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#endif + +#ifndef ROUNDDOWN +# define ROUNDDOWN(a, b) ((a)/(b)*(b)) +#endif #define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MIN(a, b) ((a) < (b) ? (a) : (b)) diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_assert.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_assert.h index ebd70632..c307fb66 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_assert.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_assert.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.c index c324cdbd..680ed0ae 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.h index 437ea9bd..2a74b782 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.c new file mode 100644 index 00000000..c1606bcb --- /dev/null +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.c @@ -0,0 +1,87 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ +/******************************************************************************* + * @file mss_beu.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolarFire SoC MSS MPU driver for configuring the Bus Error Unit + * + */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#include +#include +#include "mpfs_hal/mss_hal.h" + +/** + * \brief BEU user configuration for BEU enables + * + */ +const uint64_t beu_enable[] = { + LIBERO_SETTING_BEU_ENABLE_HART0, + LIBERO_SETTING_BEU_ENABLE_HART1, + LIBERO_SETTING_BEU_ENABLE_HART2, + LIBERO_SETTING_BEU_ENABLE_HART3, + LIBERO_SETTING_BEU_ENABLE_HART4 +}; + +/** + * \brief BEU user configuration for BEU PLIC enables + * + */ +const uint64_t beu_plic_enable[] = { + LIBERO_SETTING_BEU_PLIC_ENABLE_HART0, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART1, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART2, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART3, + LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 +}; + +/** + * \brief BEU user configuration for BEU local interrupt enables + * + */ +const uint64_t beu_local_enable[] = { + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3, + LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 +}; + + +/** + * This function is configured by editing parameters in + * mss_sw_config.h as required. + * @return + */ +__attribute__((weak)) uint8_t init_bus_error_unit(void) +{ + uint8_t hart_id; + /* Init BEU in all harts - enable local interrupt */ + for(hart_id = MPFS_HAL_FIRST_HART; hart_id <= MPFS_HAL_LAST_HART; hart_id++) + { + BEU->regs[hart_id].ENABLE = beu_enable[hart_id]; + BEU->regs[hart_id].PLIC_INT = beu_plic_enable[hart_id]; + BEU->regs[hart_id].LOCAL_INT = beu_local_enable[hart_id]; + BEU->regs[hart_id].CAUSE = 0ULL; + BEU->regs[hart_id].ACCRUED = 0ULL; + BEU->regs[hart_id].VALUE = 0ULL; + } + return (0U); +} + +/** + * This interrupt is called if BEU->regs[hart_id].LOCAL_INT's is enabled. + * If using, instantiate in your code, and add handling of errors as required. + */ +__attribute__((weak)) void handle_local_beu_interrupt(void) +{ +} + diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.h new file mode 100644 index 00000000..193af6ff --- /dev/null +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu.h @@ -0,0 +1,119 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * + * @file mss_beu.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Bus Error Unit (BEU) user defines and function prototypes + * + */ + +#ifndef MSS_BEU_H +#define MSS_BEU_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Default user values. Define these in mss_sw_config.h if you want to change + * from the default. + */ +#ifndef LIBERO_SETTING_BEU_ENABLE_HART0 +#define LIBERO_SETTING_BEU_ENABLE_HART0 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART1 +#define LIBERO_SETTING_BEU_ENABLE_HART1 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART2 +#define LIBERO_SETTING_BEU_ENABLE_HART2 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART3 +#define LIBERO_SETTING_BEU_ENABLE_HART3 BEU_ENABLE +#endif +#ifndef LIBERO_SETTING_BEU_ENABLE_HART4 +#define LIBERO_SETTING_BEU_ENABLE_HART4 BEU_ENABLE +#endif + +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 BEU_PLIC_INT +#endif +#ifndef LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 +#define LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 BEU_PLIC_INT +#endif + +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 BEU_LOCAL_INT +#endif +#ifndef LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 +#define LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 BEU_LOCAL_INT +#endif + +/***************************************************************************//** + The handle_local_beu_interrupt() function is used to handle local interrupts + generated by the Bus Error Unit (BEU) + + Example: + @code + void handle_local_beu_interrupt(void) + { + uint32_t hart_id = read_csr(mhartid); + + if(BEU->regs[hart_id].CAUSE == ECC2BIT) + { + while(1U); wait for watchdog, or orderly reboot ... + } + // Clear ECC interrupt + BEU->regs[hart_id].CAUSE = 0ULL; + BEU->regs[hart_id].ACCRUED = 0ULL; + BEU->regs[hart_id].VALUE = 0ULL; + } + @endcode + */ +void handle_local_beu_interrupt(void); + +/***************************************************************************//** + The init_bus_error_unit() function is used to setup the Bus Error Unit (BEU) + for all the harts used in the system. Define the defines + (LIBERO_SETTING_BEU_ENABLE_HART0 etc) in mss_sw_config.h if you want to use + non default values. + Example: + @code + when all mem init, call the setup function + init_bus_error_unit(); + @endcode + */ +uint8_t init_bus_error_unit(void); + +#ifdef __cplusplus +} +#endif + +#endif /*MSS_SEG_H*/ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu_def.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu_def.h new file mode 100644 index 00000000..f0d04ec3 --- /dev/null +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_beu_def.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * + * @file mss_beu_def.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Bus Error Unit (BEU) fixed defines + * + */ + +#ifndef MSS_BEU_DEF_H +#define MSS_BEU_DEF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum BEU_event_cause { + BEU_EVENT_NO_ERROR = 0, + BEU_EVENT_RESEVERD1 = 1, + BEU_EVENT_ITIM_CORRECTABLE = 2, + BEU_EVENT_ITIM_UNCORRECTABLE = 3, + BEU_EVENT_RESERVED2 = 4, + BEU_EVENT_TILELINK_BUS_ERROR = 5, + BEU_EVENT_DATA_CACHE_CORRECTABLE = 6, + BEU_EVENT_DATA_CACHE_UNCORRECTABLE = 7, + MAX_BEU_CAUSES = BEU_EVENT_DATA_CACHE_UNCORRECTABLE + 1 +}; + +typedef struct BEU_Type_ +{ + volatile uint64_t CAUSE; /*!< Cause of event, BEU_event_cause{} */ + volatile uint64_t VALUE; /*!< Value of address where issue occurred */ + volatile uint64_t ENABLE; /*!< Enable mask */ + volatile uint64_t PLIC_INT; /*!< PLIC bit enables */ + volatile uint64_t ACCRUED; /*!< events since this was last cleared */ + volatile uint64_t LOCAL_INT; /*!< Local int enables */ + volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)]; +} BEU_Type; + +typedef struct BEU_Types_ +{ + volatile BEU_Type regs[5]; +} BEU_Types; + +#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL +#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL +#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL +#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL +#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL + +#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) + +#ifdef __cplusplus +} +#endif + +#endif /*MSS_SEG_H*/ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.c index cd1558ac..43d5baa0 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -99,19 +99,19 @@ void handle_m_timer_interrupt(void) switch(hart_id) { case 0U: - SysTick_Handler_h0_IRQHandler(); + E51_sysTick_IRQHandler(); break; case 1U: - SysTick_Handler_h1_IRQHandler(); + U54_1_sysTick_IRQHandler(); break; case 2U: - SysTick_Handler_h2_IRQHandler(); + U54_2_sysTick_IRQHandler(); break; case 3U: - SysTick_Handler_h3_IRQHandler(); + U54_3_sysTick_IRQHandler(); break; case 4U: - SysTick_Handler_h4_IRQHandler(); + U54_4_sysTick_IRQHandler(); break; default: while (hart_id != 0U) @@ -127,7 +127,6 @@ void handle_m_timer_interrupt(void) } - /** * */ @@ -139,19 +138,19 @@ void handle_m_soft_interrupt(void) switch(hart_id) { case 0U: - Software_h0_IRQHandler(); + E51_software_IRQHandler(); break; case 1U: - Software_h1_IRQHandler(); + U54_1_software_IRQHandler(); break; case 2U: - Software_h2_IRQHandler(); + U54_2_software_IRQHandler(); break; case 3U: - Software_h3_IRQHandler(); + U54_3_software_IRQHandler(); break; case 4U: - Software_h4_IRQHandler(); + U54_4_software_IRQHandler(); break; default: while (hart_id != 0U) diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.h index 86b4a1cd..56c6734f 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_clint.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.c index 2a1c10b5..ff746ecb 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -9,9 +9,9 @@ /******************************************************************************* * - * @file mss_h2f.c + * @file mss_m2f.c * @author Microchip-FPGA Embedded Systems Solutions - * @brief H2F access data structures and functions. + * @brief M2F access data structures and functions. * */ #include "mss_plic.h" @@ -21,31 +21,29 @@ extern "C" { #endif -#ifndef SIFIVE_HIFIVE_UNLEASHED - -#define H2F_MAPPING_INVALID 255U +#define M2F_MAPPING_INVALID 255U /*============================================================================== - * H2F_int_mapping, source to H2F output lines + * M2F_int_mapping, source to M2F output lines * The internal interrupt are multiplexed to fabric I/O lines. * That is, each line will contain several interrupts. */ -const uint8_t H2F_int_mapping[BUS_ERROR_UNIT_HART_4]= { \ - - H2F_MAPPING_INVALID /*INVALID_IRQn = 0*/, \ - H2F_MAPPING_INVALID /*L2_METADATA_CORR_IRQn = 1*/, \ - H2F_MAPPING_INVALID /*L2_METADAT_UNCORR_IRQn = 2*/, \ - H2F_MAPPING_INVALID /*L2_DATA_CORR_IRQn = 3*/, \ - H2F_MAPPING_INVALID /*L2_DATA_UNCORR_IRQn = 4*/, \ - H2F_MAPPING_INVALID /*DMA_CH0_DONE_IRQn = 5*/, \ - H2F_MAPPING_INVALID /*DMA_CH0_ERR_IRQn = 6*/, \ - H2F_MAPPING_INVALID /*DMA_CH1_DONE_IRQn = 7*/, \ - H2F_MAPPING_INVALID /*DMA_CH1_ERR_IRQn = 8*/, \ - H2F_MAPPING_INVALID /*DMA_CH2_DONE_IRQn = 9*/, \ - H2F_MAPPING_INVALID /*DMA_CH2_ERR_IRQn = 10*/, \ - H2F_MAPPING_INVALID /*DMA_CH3_DONE_IRQn = 11*/, \ - H2F_MAPPING_INVALID /*DMA_CH3_ERR_IRQn = 12*/, \ +const uint8_t M2F_int_mapping[PLIC_U54_4_BUS_ERROR_UNIT_OFFSET]= { \ + + M2F_MAPPING_INVALID /*INVALID_IRQn = 0*/, \ + M2F_MAPPING_INVALID /*L2_METADATA_CORR_IRQn = 1*/, \ + M2F_MAPPING_INVALID /*L2_METADAT_UNCORR_IRQn = 2*/, \ + M2F_MAPPING_INVALID /*L2_DATA_CORR_IRQn = 3*/, \ + M2F_MAPPING_INVALID /*L2_DATA_UNCORR_IRQn = 4*/, \ + M2F_MAPPING_INVALID /*DMA_CH0_DONE_IRQn = 5*/, \ + M2F_MAPPING_INVALID /*DMA_CH0_ERR_IRQn = 6*/, \ + M2F_MAPPING_INVALID /*DMA_CH1_DONE_IRQn = 7*/, \ + M2F_MAPPING_INVALID /*DMA_CH1_ERR_IRQn = 8*/, \ + M2F_MAPPING_INVALID /*DMA_CH2_DONE_IRQn = 9*/, \ + M2F_MAPPING_INVALID /*DMA_CH2_ERR_IRQn = 10*/, \ + M2F_MAPPING_INVALID /*DMA_CH3_DONE_IRQn = 11*/, \ + M2F_MAPPING_INVALID /*DMA_CH3_ERR_IRQn = 12*/, \ 0x00U /*GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 = 0 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ 0x00U /*GPIO0_BIT1_or_GPIO2_BIT1_PLIC_1 = 1 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ @@ -150,90 +148,90 @@ const uint8_t H2F_int_mapping[BUS_ERROR_UNIT_HART_4]= { \ 0x05U /*WDOG3_TOUT_PLIC =95 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ 0x05U /*WDOG4_TOUT_PLIC =96 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ 0x0DU /*G5C_MSS_SPI_PLIC =97 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*VOLT_TEMP_ALARM_PLIC =98 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*ATHENA_COMPLETE_PLIC =99 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*ATHENA_ALARM_PLIC =100 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*ATHENA_BUS_ERROR_PLIC =101 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*VOLT_TEMP_ALARM_PLIC =98 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*ATHENA_COMPLETE_PLIC =99 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*ATHENA_ALARM_PLIC =100 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*ATHENA_BUS_ERROR_PLIC =101 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ 0x0BU /*USOC_AXIC_US_PLIC =102 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ 0x0BU /*USOC_AXIC_DS_PLIC =103 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_0_PLIC = 105 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_1_PLIC = 106 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_2_PLIC = 107 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_3_PLIC = 108 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_4_PLIC = 109 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_5_PLIC = 110 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_6_PLIC = 111 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_7_PLIC = 112 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_8_PLIC = 113 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_9_PLIC = 114 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_10_PLIC = 115 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_11_PLIC = 116 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_12_PLIC = 117 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_13_PLIC = 118 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_14_PLIC = 119 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_15_PLIC = 120 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_16_PLIC = 121 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_17_PLIC = 122 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_18_PLIC = 123 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_19_PLIC = 124 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_20_PLIC = 125 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_21_PLIC = 126 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_22_PLIC = 127 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_23_PLIC = 128 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_24_PLIC = 129 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_25_PLIC = 130 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_26_PLIC = 131 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_27_PLIC = 132 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_28_PLIC = 133 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_29_PLIC = 134 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_30_PLIC = 135 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_31_PLIC = 136 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_32_PLIC = 137 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_33_PLIC = 138 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_34_PLIC = 139 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_35_PLIC = 140 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_36_PLIC = 141 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_37_PLIC = 142 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_38_PLIC = 143 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_39_PLIC = 144 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_40_PLIC = 145 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_41_PLIC = 146 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_42_PLIC = 147 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_43_PLIC = 148 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_44_PLIC = 149 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_45_PLIC = 150 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_46_PLIC = 151 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_47_PLIC = 152 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_48_PLIC = 153 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_49_PLIC = 154 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_50_PLIC = 155 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_51_PLIC = 156 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_52_PLIC = 157 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_53_PLIC = 158 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_54_PLIC = 159 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_55_PLIC = 160 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_56_PLIC = 161 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_57_PLIC = 162 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_58_PLIC = 163 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_59_PLIC = 164 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_60_PLIC = 165 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_61_PLIC = 166 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*FABRIC_F2H_62_PLIC = 167 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - H2F_MAPPING_INVALID /*FABRIC_F2H_63_PLIC = 168 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ - - H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_0 = 182*/, \ - H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_1 = 183*/, \ - H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_2 = 184*/, \ - H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_3 = 185*/, \ - H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_4 = 186 */ + M2F_MAPPING_INVALID /*MSS_INT_F2M_0_PLIC = 105 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_1_PLIC = 106 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_2_PLIC = 107 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_3_PLIC = 108 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_4_PLIC = 109 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_5_PLIC = 110 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_6_PLIC = 111 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_7_PLIC = 112 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_8_PLIC = 113 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_9_PLIC = 114 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_10_PLIC = 115 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_11_PLIC = 116 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_12_PLIC = 117 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_13_PLIC = 118 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_14_PLIC = 119 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_15_PLIC = 120 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_16_PLIC = 121 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_17_PLIC = 122 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_18_PLIC = 123 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_19_PLIC = 124 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_20_PLIC = 125 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_21_PLIC = 126 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_22_PLIC = 127 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_23_PLIC = 128 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_24_PLIC = 129 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_25_PLIC = 130 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_26_PLIC = 131 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_27_PLIC = 132 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_28_PLIC = 133 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_29_PLIC = 134 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_30_PLIC = 135 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_31_PLIC = 136 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_32_PLIC = 137 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_33_PLIC = 138 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_34_PLIC = 139 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_35_PLIC = 140 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_36_PLIC = 141 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_37_PLIC = 142 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_38_PLIC = 143 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_39_PLIC = 144 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_40_PLIC = 145 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_41_PLIC = 146 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_42_PLIC = 147 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_43_PLIC = 148 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_44_PLIC = 149 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_45_PLIC = 150 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_46_PLIC = 151 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_47_PLIC = 152 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_48_PLIC = 153 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_49_PLIC = 154 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_50_PLIC = 155 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_51_PLIC = 156 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_52_PLIC = 157 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_53_PLIC = 158 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_54_PLIC = 159 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_55_PLIC = 160 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_56_PLIC = 161 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_57_PLIC = 162 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_58_PLIC = 163 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_59_PLIC = 164 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_60_PLIC = 165 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_61_PLIC = 166 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*MSS_INT_F2M_62_PLIC = 167 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + M2F_MAPPING_INVALID /*MSS_INT_F2M_63_PLIC = 168 + OFFSET_TO_MSS_GLOBAL_INTS*/, \ + + M2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_0 = 182*/, \ + M2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_1 = 183*/, \ + M2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_2 = 184*/, \ + M2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_3 = 185*/, \ + M2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_4 = 186 */ }; @@ -243,29 +241,29 @@ const uint8_t H2F_int_mapping[BUS_ERROR_UNIT_HART_4]= { \ * @param source_int * @return */ -static uint32_t get_corresponding_h2f_output(uint32_t source_int) +static uint32_t get_corresponding_m2f_output(uint32_t source_int) { - uint32_t h2f_line = H2F_int_mapping[source_int]; + uint32_t m2f_line = M2F_int_mapping[source_int]; - if(h2f_line < H2F_MAPPING_INVALID) /* if no error */ + if(m2f_line < M2F_MAPPING_INVALID) /* if no error */ { - return(0x01U << h2f_line); + return(0x01U << m2f_line); } - return(h2f_line); + return(m2f_line); } /** - * set H2F controller to reset to defaults- disabled + * set M2F controller to reset to defaults- disabled */ -void reset_h2f(void) +void reset_m2f(void) { uint8_t index = 0U; - H2F_CONTROLLER->ENABLE = 0U; + M2F_CONTROLLER->ENABLE = 0U; while(index < 4U) { - H2F_CONTROLLER->PLENABLE[index] = 0U; + M2F_CONTROLLER->PLENABLE[index] = 0U; index++; } } @@ -274,20 +272,20 @@ void reset_h2f(void) * enables output which will mirror PLIC input. PLIC mapping given above for reference * @param source_int */ -void enable_h2f_int_output(uint32_t source_int) +void enable_m2f_int_output(uint32_t source_int) { - uint32_t output_signal = get_corresponding_h2f_output(source_int); + uint32_t output_signal = get_corresponding_m2f_output(source_int); - if(output_signal != H2F_MAPPING_INVALID) + if(output_signal != M2F_MAPPING_INVALID) { source_int -= OFFSET_TO_MSS_GLOBAL_INTS; /* enable the input */ - H2F_CONTROLLER->PLENABLE[source_int/32U] |= (0x01U << (source_int % 32U)); + M2F_CONTROLLER->PLENABLE[source_int/32U] |= (0x01U << (source_int % 32U)); /* enable the output */ - H2F_CONTROLLER->ENABLE |= ((output_signal<<16U) | 0x01U); + M2F_CONTROLLER->ENABLE |= ((output_signal<<16U) | 0x01U); } } @@ -296,16 +294,16 @@ void enable_h2f_int_output(uint32_t source_int) * enables output which will mirror PLIC input. PLIC mapping given above for reference * @param source_int */ -void disable_h2f_int_output(uint32_t source_int) +void disable_m2f_int_output(uint32_t source_int) { - uint32_t output_signal = get_corresponding_h2f_output(source_int); + uint32_t output_signal = get_corresponding_m2f_output(source_int); - if(output_signal != H2F_MAPPING_INVALID) + if(output_signal != M2F_MAPPING_INVALID) { /* enable the input */ - H2F_CONTROLLER->PLENABLE[source_int/32U] &= ~(source_int % 32U); + M2F_CONTROLLER->PLENABLE[source_int/32U] &= ~(source_int % 32U); /* enable the output */ - H2F_CONTROLLER->ENABLE &= ~(((output_signal<<16U))); + M2F_CONTROLLER->ENABLE &= ~(((output_signal<<16U))); } } @@ -313,7 +311,4 @@ void disable_h2f_int_output(uint32_t source_int) } #endif -#endif - - diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.h index 280e465b..b89963f2 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_h2f.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -9,16 +9,16 @@ /******************************************************************************* * - * @file mss_h2f.h + * @file mss_m2f.h * @author Microchip-FPGA Embedded Systems Solutions - * @brief H2F access data structures and functions. + * @brief M2F access data structures and functions. * * Definitions and functions associated with host to fabric interrupt controller. * */ -#ifndef MSS_H2F_H -#define MSS_H2F_H +#ifndef MSS_M2F_H +#define MSS_M2F_H #include "mpfs_hal_config/mss_sw_config.h" @@ -27,7 +27,7 @@ extern "C" { #endif /* -H2F line Group Ored (no of interrupts ored to one output line) +M2F line Group Ored (no of interrupts ored to one output line) 0 GPIO 41 1 MMUART,SPI,CAN 9 2 I2C 6 @@ -57,32 +57,32 @@ H2F line Group Ored (no of interrupts ored to one output line) typedef struct { - volatile uint32_t ENABLE; /* bit o: Enables all the H2FINT outputs, bit 31:16 Enables individual H2F outputs */ - volatile uint32_t H2FSTATUS; /* 15:0 Read back of the 16-bit H2F Interrupts before the H2F and global enable */ + volatile uint32_t ENABLE; /* bit o: Enables all the M2FINT outputs, bit 31:16 Enables individual M2F outputs */ + volatile uint32_t M2FSTATUS; /* 15:0 Read back of the 16-bit M2F Interrupts before the M2F and global enable */ uint32_t filler[2U]; /* fill the gap in the memory map */ volatile uint32_t PLSTATUS[4U]; /* Indicates that the PLINT interrupt is active before the PLINT enable i.e. direct read of the PLINT inputs [31:0] from PLSTATUS[0] direct read of the PLINT inputs [63:32] from PLSTATUS[1] etc */ volatile uint32_t PLENABLE[4U]; /* Enables PLINT interrupts PLENABLE[0] 31:0, PLENABLE[1] 63:32, 95:64, 127:96 */ -} H2F_CONTROLLER_Type; +} M2F_CONTROLLER_Type; -#ifndef H2F_BASE_ADDRESS +#ifndef M2F_BASE_ADDRESS #if (LIBERO_SETTING_APBBUS_CR & (1U<<23U)) -#define H2F_BASE_ADDRESS 0x28126000 +#define M2F_BASE_ADDRESS 0x28126000 #else -#define H2F_BASE_ADDRESS 0x20126000 +#define M2F_BASE_ADDRESS 0x20126000 #endif #endif -#define H2F_CONTROLLER ((H2F_CONTROLLER_Type *)H2F_BASE_ADDRESS) +#define M2F_CONTROLLER ((M2F_CONTROLLER_Type *)M2F_BASE_ADDRESS) -void reset_h2f(void); -void enable_h2f_int_output(uint32_t source_int); -void disable_h2f_int_output(uint32_t source_int); +void reset_m2f(void); +void enable_m2f_int_output(uint32_t source_int); +void disable_m2f_int_output(uint32_t source_int); #ifdef __cplusplus } #endif -#endif /* MSS_H2F_H */ +#endif /* MSS_M2F_H */ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h index c559d193..1939c829 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -25,350 +25,332 @@ extern "C" { #endif -typedef struct BEU_Type_ -{ - volatile uint64_t CAUSE; - volatile uint64_t VALUE; - volatile uint64_t ENABLE; - volatile uint64_t PLIC_INT; - volatile uint64_t ACCRUED; - volatile uint64_t LOCAL_INT; - volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)]; -} BEU_Type; - -typedef struct BEU_Types_ -{ - volatile BEU_Type regs[5]; -} BEU_Types; - -#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL -#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL -#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL -#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL -#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL - -#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) - /* - * Interrupt numbers U0 + * Local Interrupt offsets for the E51 */ -#define MAINTENANCE_E51_INT 0 -#define USOC_SMB_INTERRUPT_E51_INT 1 -#define USOC_VC_INTERRUPT_E51_INT 2 -#define G5C_MESSAGE_E51_INT 3 -#define G5C_DEVRST_E51_INT 4 -#define WDOG4_TOUT_E51_INT 5 -#define WDOG3_TOUT_E51_INT 6 -#define WDOG2_TOUT_E51_INT 7 -#define WDOG1_TOUT_E51_INT 8 -#define WDOG0_TOUT_E51_INT 9 -#define WDOG0_MVRP_E51_INT 10 -#define MMUART0_E51_INT 11 -#define ENVM_E51_INT 12 -#define ECC_CORRECT_E51_INT 13 -#define ECC_ERROR_E51_INT 14 -#define scb_INTERRUPT_E51_INT 15 -#define FABRIC_F2H_32_E51_INT 16 -#define FABRIC_F2H_33_E51_INT 17 -#define FABRIC_F2H_34_E51_INT 18 -#define FABRIC_F2H_35_E51_INT 19 -#define FABRIC_F2H_36_E51_INT 20 -#define FABRIC_F2H_37_E51_INT 21 -#define FABRIC_F2H_38_E51_INT 22 -#define FABRIC_F2H_39_E51_INT 23 -#define FABRIC_F2H_40_E51_INT 24 -#define FABRIC_F2H_41_E51_INT 25 - -#define FABRIC_F2H_42_E51_INT 26 -#define FABRIC_F2H_43_E51_INT 27 -#define FABRIC_F2H_44_E51_INT 28 -#define FABRIC_F2H_45_E51_INT 29 -#define FABRIC_F2H_46_E51_INT 30 -#define FABRIC_F2H_47_E51_INT 31 -#define FABRIC_F2H_48_E51_INT 32 -#define FABRIC_F2H_49_E51_INT 33 -#define FABRIC_F2H_50_E51_INT 34 -#define FABRIC_F2H_51_E51_INT 35 - -#define FABRIC_F2H_52_E51_INT 36 -#define FABRIC_F2H_53_E51_INT 37 -#define FABRIC_F2H_54_E51_INT 38 -#define FABRIC_F2H_55_E51_INT 39 -#define FABRIC_F2H_56_E51_INT 40 -#define FABRIC_F2H_57_E51_INT 41 -#define FABRIC_F2H_58_E51_INT 42 -#define FABRIC_F2H_59_E51_INT 43 -#define FABRIC_F2H_60_E51_INT 44 -#define FABRIC_F2H_61_E51_INT 45 - -#define FABRIC_F2H_62_E51_INT 46 -#define FABRIC_F2H_63_E51_INT 47 +#define E51_MAINTENANCE_INT_OFFSET 0 +#define E51_USOC_SMB_INTERRUPT_INT_OFFSET 1 +#define E51_USOC_VC_INTERRUPT_INT_OFFSET 2 +#define E51_G5C_MESSAGE_INT_OFFSET 3 +#define E51_G5C_DEVRST_INT_OFFSET 4 +#define E51_WDOG4_TOUT_INT_OFFSET 5 +#define E51_WDOG3_TOUT_INT_OFFSET 6 +#define E51_WDOG2_TOUT_INT_OFFSET 7 +#define E51_WDOG1_TOUT_INT_OFFSET 8 +#define E51_WDOG0_TOUT_INT_OFFSET 9 +#define E51_WDOG0_MVRP_INT_OFFSET 10 +#define E51_MMUART0_INT_OFFSET 11 +#define E51_ENVM_INT_OFFSET 12 +#define E51_ECC_CORRECT_INT_OFFSET 13 +#define E51_ECC_ERROR_INT_OFFSET 14 +#define E51_scb_INTERRUPT_INT_OFFSET 15 +#define E51_F2M_32_INT_OFFSET 16 +#define E51_F2M_33_INT_OFFSET 17 +#define E51_F2M_34_INT_OFFSET 18 +#define E51_F2M_35_INT_OFFSET 19 +#define E51_F2M_36_INT_OFFSET 20 +#define E51_F2M_37_INT_OFFSET 21 +#define E51_F2M_38_INT_OFFSET 22 +#define E51_F2M_39_INT_OFFSET 23 +#define E51_F2M_40_INT_OFFSET 24 +#define E51_F2M_41_INT_OFFSET 25 +#define E51_F2M_42_INT_OFFSET 26 +#define E51_F2M_43_INT_OFFSET 27 +#define E51_F2M_44_INT_OFFSET 28 +#define E51_F2M_45_INT_OFFSET 29 +#define E51_F2M_46_INT_OFFSET 30 +#define E51_F2M_47_INT_OFFSET 31 +#define E51_F2M_48_INT_OFFSET 32 +#define E51_F2M_49_INT_OFFSET 33 +#define E51_F2M_50_INT_OFFSET 34 +#define E51_F2M_51_INT_OFFSET 35 + +#define E51_F2M_52_INT_OFFSET 36 +#define E51_F2M_53_INT_OFFSET 37 +#define E51_F2M_54_INT_OFFSET 38 +#define E51_F2M_55_INT_OFFSET 39 +#define E51_F2M_56_INT_OFFSET 40 +#define E51_F2M_57_INT_OFFSET 41 +#define E51_F2M_58_INT_OFFSET 42 +#define E51_F2M_59_INT_OFFSET 43 +#define E51_F2M_60_INT_OFFSET 44 +#define E51_F2M_61_INT_OFFSET 45 + +#define E51_F2M_62_INT_OFFSET 46 +#define E51_F2M_63_INT_OFFSET 47 + +#define LOCAL_INT_MAX 47U /* Highest numbered */ +#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */ -#define LOCAL_INT_MAX 47U /* Highest numbered */ -#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */ /* * Interrupts associated with - * MAINTENANCE_E51_INT + * MAINTENANCE_INT_OFFSET + * This maps to the E51_maintenance_local_IRQHandler(void) handler + * + * A group of interrupt events are grouped into a single maintenance interrupt + * to the E51 CPU. + * These interrupts are individually enabled using the following MSS system + * register: + * SYSREG->MAINTENANCE_INTEN_CR + * On receiving this interrupt the E51 should read the following system register + * to determine the source of the interrupt + * SYSREG->MAINTENANCE_INT_SR + * The bit defines associated with the MAINTENANCE_INTEN_CR and + * MAINTENANCE_INT_SR registers are listed in the file mss_sysreg.h + * see: + * MAINTENANCE_INTEN_CR_PLL_MASK (0x01 << 0x0) + * MAINTENANCE_INTEN_CR_MPU_MASK (0x01 << 0x1) + * MAINTENANCE_INTEN_CR_DECODE_MASK (0x01 << 0x2) + * MAINTENANCE_INTEN_CR_LP_STATE_ENTER_MASK (0x01 << 0x3) + * MAINTENANCE_INTEN_CR_LP_STATE_EXIT_MASK (0x01 << 0x4) + * MAINTENANCE_INTEN_CR_FF_START_MASK (0x01 << 0x5) + * MAINTENANCE_INTEN_CR_FF_END_MASK (0x01 << 0x6) + * MAINTENANCE_INTEN_CR_FPGA_ON_MASK (0x01 << 0x7) + * MAINTENANCE_INTEN_CR_FPGA_OFF_MASK (0x01 << 0x8) + * MAINTENANCE_INTEN_CR_SCB_ERROR_MASK (0x01 << 0x9) + * MAINTENANCE_INTEN_CR_SCB_FAULT_MASK (0x01 << 0xA) + * MAINTENANCE_INTEN_CR_MESH_ERROR_MASK (0x01 << 0xB) + * MAINTENANCE_INTEN_CR_IO_BANK_B2_ON_MASK (0x01 << 0xC) + * MAINTENANCE_INTEN_CR_IO_BANK_B4_ON_MASK (0x01 << 0xD) + * MAINTENANCE_INTEN_CR_IO_BANK_B5_ON_MASK (0x01 << 0xE) + * MAINTENANCE_INTEN_CR_IO_BANK_B6_ON_MASK (0x01 << 0xF) + * MAINTENANCE_INTEN_CR_IO_BANK_B2_OFF_MASK (0x01 << 0x10) + * MAINTENANCE_INTEN_CR_IO_BANK_B4_OFF_MASK (0x01 << 0x11) + * MAINTENANCE_INTEN_CR_IO_BANK_B5_OFF_MASK (0x01 << 0x12) + * MAINTENANCE_INTEN_CR_IO_BANK_B6_OFF_MASK (0x01 << 0x13) + * MAINTENANCE_INTEN_CR_DLL_MASK (0x01 << 0x14) + * + * The PLL, MPU and DLL maintenance interrupts have their own sub group + * registers for enabling and clearing multiple associated events + * See the defines for + * SYSREG->PLL_STATUS_INTEN_CR + * SYSREG->PLL_STATUS_SR + * + * SYSREG->MPU_VIOLATION_INTEN_CR + * SYSREG->MPU_VIOLATION_SR + * + * SYSREG->DLL_STATUS_CR + * SYSREG->DLL_STATUS_SR * - * A group of interrupt events are grouped into a single maintenance interrupt to the E51 CPU, - * on receiving this interrupt the E51 should read the maintenance system register to find out - * the interrupt source. The maintenance interrupts are defined below - */ -#define MAINTENANCE_E51_pll_INT 0 -#define MAINTENANCE_E51_mpu_INT 1 -#define MAINTENANCE_E51_lp_state_enter_INT 2 -#define MAINTENANCE_E51_lp_state_exit_INT 3 -#define MAINTENANCE_E51_ff_start_INT 4 -#define MAINTENANCE_E51_ff_end_INT 5 -#define MAINTENANCE_E51_fpga_on_INT 6 -#define MAINTENANCE_E51_fpga_off_INT 7 -#define MAINTENANCE_E51_scb_error_INT 8 -#define MAINTENANCE_E51_scb_fault_INT 9 -#define MAINTENANCE_E51_mesh_error_INT 10 -#define MAINTENANCE_E51_io_bank_b2_on_INT 12 -#define MAINTENANCE_E51_io_bank_b4_on_INT 13 -#define MAINTENANCE_E51_io_bank_b5_on_INT 14 -#define MAINTENANCE_E51_io_bank_b6_on_INT 15 -#define MAINTENANCE_E51_io_bank_b2_off_INT 16 -#define MAINTENANCE_E51_io_bank_b4_off_INT 17 -#define MAINTENANCE_E51_io_bank_b5_off_INT 18 -#define MAINTENANCE_E51_io_bank_b6_off_INT 19 - - -/* - * E51-0 is Maintenance Interrupt CPU needs to read status register to determine exact cause: - * These defines added here for clarity need to replay with status register defines - * for determining interrupt cause */ -#ifndef FOR_CLARITY -# define FOR_CLARITY 0 -#endif - -#if FOR_CLARITY -# define mpu_fail_plic 0 -# define lp_state_enter_plic 1 -# define lp_state_exit_plic 2 -# define ff_start_plic 3 -# define ff_end_plic 4 -# define fpga_on_plic 5 -# define fpga_off_plic 6 -# define scb_error_plic 7 -# define scb_fault_plic 8 -# define mesh_fail_plic 9 -#endif /* * Interrupt numbers U54's */ /* U0 (first U54) and U1 connected to mac0 */ -#define MAC0_INT_U54_INT 8 /* determine source mac using hart ID */ -#define MAC0_QUEUE1_U54_INT 7 -#define MAC0_QUEUE2_U54_INT 6 -#define MAC0_QUEUE3_U54_INT 5 -#define MAC0_EMAC_U54_INT 4 -#define MAC0_MMSL_U54_INT 3 +#define U54_MAC0_INT_INT_OFFSET 8 /* determine source mac using hart ID */ +#define U54_MAC0_QUEUE1_INT_OFFSET 7 +#define U54_MAC0_QUEUE2_INT_OFFSET 6 +#define U54_MAC0_QUEUE3_INT_OFFSET 5 +#define U54_MAC0_EMAC_INT_OFFSET 4 +#define U54_MAC0_MMSL_INT_OFFSET 3 /* U2 and U3 connected to mac1 */ -#define MAC1_INT_U54_INT 8 /* determine source mac using hart ID */ -#define MAC1_QUEUE1_U54_INT 7 -#define MAC1_QUEUE2_U54_INT 6 -#define MAC1_QUEUE3_U54_INT 5 -#define MAC1_EMAC_U54_INT 4 -#define MAC1_MMSL_U54_INT 3 +#define U54_MAC1_INT_INT_OFFSET 8 /* determine source mac using hart ID */ +#define U54_MAC1_QUEUE1_INT_OFFSET 7 +#define U54_MAC1_QUEUE2_INT_OFFSET 6 +#define U54_MAC1_QUEUE3_INT_OFFSET 5 +#define U54_MAC1_EMAC_INT_OFFSET 4 +#define U54_MAC1_MMSL_INT_OFFSET 3 /* MMUART1 connected to U54 0 */ /* MMUART2 connected to U54 1 */ /* MMUART3 connected to U54 2 */ /* MMUART4 connected to U54 3 */ -#define MMUARTx_U54_INT 11 /* MMUART1 connected to U54 0 */ -#define WDOGx_MVRP_U54_INT 10 /* determine source mac using hart ID */ -#define WDOGx_TOUT_U54_INT 9 /* determine source mac using hart ID */ - -#define H2_FABRIC_F2H_0_U54_INT 16 -#define H2_FABRIC_F2H_1_U54_INT 17 -#define H2_FABRIC_F2H_2_U54_INT 18 -#define H2_FABRIC_F2H_3_U54_INT 19 -#define H2_FABRIC_F2H_4_U54_INT 20 -#define H2_FABRIC_F2H_5_U54_INT 21 -#define H2_FABRIC_F2H_6_U54_INT 22 -#define H2_FABRIC_F2H_7_U54_INT 23 -#define H2_FABRIC_F2H_8_U54_INT 24 -#define H2_FABRIC_F2H_9_U54_INT 25 - -#define H2_FABRIC_F2H_10_U54_INT 26 -#define H2_FABRIC_F2H_11_U54_INT 27 -#define H2_FABRIC_F2H_12_U54_INT 28 -#define H2_FABRIC_F2H_13_U54_INT 29 -#define H2_FABRIC_F2H_14_U54_INT 30 -#define H2_FABRIC_F2H_15_U54_INT 31 -#define H2_FABRIC_F2H_16_U54_INT 32 -#define H2_FABRIC_F2H_17_U54_INT 33 -#define H2_FABRIC_F2H_18_U54_INT 34 -#define H2_FABRIC_F2H_19_U54_INT 35 - -#define H2_FABRIC_F2H_20_U54_INT 36 -#define H2_FABRIC_F2H_21_U54_INT 37 -#define H2_FABRIC_F2H_22_U54_INT 38 -#define H2_FABRIC_F2H_23_U54_INT 39 -#define H2_FABRIC_F2H_24_U54_INT 40 -#define H2_FABRIC_F2H_25_U54_INT 41 -#define H2_FABRIC_F2H_26_U54_INT 42 -#define H2_FABRIC_F2H_27_U54_INT 43 -#define H2_FABRIC_F2H_28_U54_INT 44 -#define H2_FABRIC_F2H_29_U54_INT 45 - -#define H2_FABRIC_F2H_30_U54_INT 46 -#define H2_FABRIC_F2H_31_U54_INT 47 +#define U54_MMUARTx_INT_OFFSET 11 /* MMUART1 connected to U54 0 */ +#define U54_WDOGx_MVRP_INT_OFFSET 10 /* determine source mac using hart ID */ +#define U54_WDOGx_TOUT_INT_OFFSET 9 /* determine source mac using hart ID */ + +#define U54_F2M_0_INT_OFFSET 16 +#define U54_F2M_1_INT_OFFSET 17 +#define U54_F2M_2_INT_OFFSET 18 +#define U54_F2M_3_INT_OFFSET 19 +#define U54_F2M_4_INT_OFFSET 20 +#define U54_F2M_5_INT_OFFSET 21 +#define U54_F2M_6_INT_OFFSET 22 +#define U54_F2M_7_INT_OFFSET 23 +#define U54_F2M_8_INT_OFFSET 24 +#define U54_F2M_9_INT_OFFSET 25 + +#define U54_F2M_10_INT_OFFSET 26 +#define U54_F2M_11_INT_OFFSET 27 +#define U54_F2M_12_INT_OFFSET 28 +#define U54_F2M_13_INT_OFFSET 29 +#define U54_F2M_14_INT_OFFSET 30 +#define U54_F2M_15_INT_OFFSET 31 +#define U54_F2M_16_INT_OFFSET 32 +#define U54_F2M_17_INT_OFFSET 33 +#define U54_F2M_18_INT_OFFSET 34 +#define U54_F2M_19_INT_OFFSET 35 + +#define U54_F2M_20_INT_OFFSET 36 +#define U54_F2M_21_INT_OFFSET 37 +#define U54_F2M_22_INT_OFFSET 38 +#define U54_F2M_23_INT_OFFSET 39 +#define U54_F2M_24_INT_OFFSET 40 +#define U54_F2M_25_INT_OFFSET 41 +#define U54_F2M_26_INT_OFFSET 42 +#define U54_F2M_27_INT_OFFSET 43 +#define U54_F2M_28_INT_OFFSET 44 +#define U54_F2M_29_INT_OFFSET 45 + +#define U54_F2M_30_INT_OFFSET 46 +#define U54_F2M_31_INT_OFFSET 47 void handle_m_ext_interrupt(void); -void Software_h0_IRQHandler(void); -void Software_h1_IRQHandler(void); -void Software_h2_IRQHandler(void); -void Software_h3_IRQHandler(void); -void Software_h4_IRQHandler(void); -void SysTick_Handler_h0_IRQHandler(void); -void SysTick_Handler_h1_IRQHandler(void); -void SysTick_Handler_h2_IRQHandler(void); -void SysTick_Handler_h3_IRQHandler(void); -void SysTick_Handler_h4_IRQHandler(void); +void E51_software_IRQHandler(void); +void U54_1_software_IRQHandler(void); +void U54_2_software_IRQHandler(void); +void U54_3_software_IRQHandler(void); +void U54_4_software_IRQHandler(void); +void E51_sysTick_IRQHandler(void); +void U54_1_sysTick_IRQHandler(void); +void U54_2_sysTick_IRQHandler(void); +void U54_3_sysTick_IRQHandler(void); +void U54_4_sysTick_IRQHandler(void); /* * * Local interrupt defines * */ -void maintenance_e51_local_IRQHandler_0(void); -void usoc_smb_interrupt_e51_local_IRQHandler_1(void); -void usoc_vc_interrupt_e51_local_IRQHandler_2(void); -void g5c_message_e51_local_IRQHandler_3(void); -void g5c_devrst_e51_local_IRQHandler_4(void); -void wdog4_tout_e51_local_IRQHandler_5(void); -void wdog3_tout_e51_local_IRQHandler_6(void); -void wdog2_tout_e51_local_IRQHandler_7(void); -void wdog1_tout_e51_local_IRQHandler_8(void); -void wdog0_tout_e51_local_IRQHandler_9(void); -void wdog0_mvrp_e51_local_IRQHandler_10(void); -void mmuart0_e51_local_IRQHandler_11(void); -void envm_e51_local_IRQHandler_12(void); -void ecc_correct_e51_local_IRQHandler_13(void); -void ecc_error_e51_local_IRQHandler_14(void); -void scb_interrupt_e51_local_IRQHandler_15(void); -void fabric_f2h_32_e51_local_IRQHandler_16(void); -void fabric_f2h_33_e51_local_IRQHandler_17(void); -void fabric_f2h_34_e51_local_IRQHandler_18(void); -void fabric_f2h_35_e51_local_IRQHandler_19(void); -void fabric_f2h_36_e51_local_IRQHandler_20(void); -void fabric_f2h_37_e51_local_IRQHandler_21(void); -void fabric_f2h_38_e51_local_IRQHandler_22(void); -void fabric_f2h_39_e51_local_IRQHandler_23(void); -void fabric_f2h_40_e51_local_IRQHandler_24(void); -void fabric_f2h_41_e51_local_IRQHandler_25(void); -void fabric_f2h_42_e51_local_IRQHandler_26(void); -void fabric_f2h_43_e51_local_IRQHandler_27(void); -void fabric_f2h_44_e51_local_IRQHandler_28(void); -void fabric_f2h_45_e51_local_IRQHandler_29(void); -void fabric_f2h_46_e51_local_IRQHandler_30(void); -void fabric_f2h_47_e51_local_IRQHandler_31(void); -void fabric_f2h_48_e51_local_IRQHandler_32(void); -void fabric_f2h_49_e51_local_IRQHandler_33(void); -void fabric_f2h_50_e51_local_IRQHandler_34(void); -void fabric_f2h_51_e51_local_IRQHandler_35(void); -void fabric_f2h_52_e51_local_IRQHandler_36(void); -void fabric_f2h_53_e51_local_IRQHandler_37(void); -void fabric_f2h_54_e51_local_IRQHandler_38(void); -void fabric_f2h_55_e51_local_IRQHandler_39(void); -void fabric_f2h_56_e51_local_IRQHandler_40(void); -void fabric_f2h_57_e51_local_IRQHandler_41(void); -void fabric_f2h_58_e51_local_IRQHandler_42(void); -void fabric_f2h_59_e51_local_IRQHandler_43(void); -void fabric_f2h_60_e51_local_IRQHandler_44(void); -void fabric_f2h_61_e51_local_IRQHandler_45(void); -void fabric_f2h_62_e51_local_IRQHandler_46(void); -void fabric_f2h_63_e51_local_IRQHandler_47(void); +void E51_maintenance_local_IRQHandler(void); +void E51_usoc_smb_local_IRQHandler(void); +void E51_usoc_vc_local_IRQHandler(void); +void E51_g5c_message_local_IRQHandler(void); +void E51_g5c_devrst_local_IRQHandler(void); +void E51_wdog4_tout_local_IRQHandler(void); +void E51_wdog3_tout_local_IRQHandler(void); +void E51_wdog2_tout_local_IRQHandler(void); +void E51_wdog1_tout_local_IRQHandler(void); +void E51_wdog0_tout_local_IRQHandler(void); +void E51_wdog0_mvrp_local_IRQHandler(void); +void E51_mmuart0_local_IRQHandler(void); +void E51_envm_local_IRQHandler(void); +void E51_ecc_correct_local_IRQHandler(void); +void E51_ecc_error_local_IRQHandler(void); +void E51_scb_local_IRQHandler(void); +void E51_f2m_32_local_IRQHandler(void); +void E51_f2m_33_local_IRQHandler(void); +void E51_f2m_34_local_IRQHandler(void); +void E51_f2m_35_local_IRQHandler(void); +void E51_f2m_36_local_IRQHandler(void); +void E51_f2m_37_local_IRQHandler(void); +void E51_f2m_38_local_IRQHandler(void); +void E51_f2m_39_local_IRQHandler(void); +void E51_f2m_40_local_IRQHandler(void); +void E51_f2m_41_local_IRQHandler(void); +void E51_f2m_42_local_IRQHandler(void); +void E51_f2m_43_local_IRQHandler(void); +void E51_f2m_44_local_IRQHandler(void); +void E51_f2m_45_local_IRQHandler(void); +void E51_f2m_46_local_IRQHandler(void); +void E51_f2m_47_local_IRQHandler(void); +void E51_f2m_48_local_IRQHandler(void); +void E51_f2m_49_local_IRQHandler(void); +void E51_f2m_50_local_IRQHandler(void); +void E51_f2m_51_local_IRQHandler(void); +void E51_f2m_52_local_IRQHandler(void); +void E51_f2m_53_local_IRQHandler(void); +void E51_f2m_54_local_IRQHandler(void); +void E51_f2m_55_local_IRQHandler(void); +void E51_f2m_56_local_IRQHandler(void); +void E51_f2m_57_local_IRQHandler(void); +void E51_f2m_58_local_IRQHandler(void); +void E51_f2m_59_local_IRQHandler(void); +void E51_f2m_60_local_IRQHandler(void); +void E51_f2m_61_local_IRQHandler(void); +void E51_f2m_62_local_IRQHandler(void); +void E51_f2m_63_local_IRQHandler(void); /* * U54 */ -void spare_u54_local_IRQHandler_0(void); -void spare_u54_local_IRQHandler_1(void); -void spare_u54_local_IRQHandler_2(void); - -void mac_mmsl_u54_1_local_IRQHandler_3(void); -void mac_emac_u54_1_local_IRQHandler_4(void); -void mac_queue3_u54_1_local_IRQHandler_5(void); -void mac_queue2_u54_1_local_IRQHandler_6(void); -void mac_queue1_u54_1_local_IRQHandler_7(void); -void mac_int_u54_1_local_IRQHandler_8(void); - -void mac_mmsl_u54_2_local_IRQHandler_3(void); -void mac_emac_u54_2_local_IRQHandler_4(void); -void mac_queue3_u54_2_local_IRQHandler_5(void); -void mac_queue2_u54_2_local_IRQHandler_6(void); -void mac_queue1_u54_2_local_IRQHandler_7(void); -void mac_int_u54_2_local_IRQHandler_8(void); - -void mac_mmsl_u54_3_local_IRQHandler_3(void); -void mac_emac_u54_3_local_IRQHandler_4(void); -void mac_queue3_u54_3_local_IRQHandler_5(void); -void mac_queue2_u54_3_local_IRQHandler_6(void); -void mac_queue1_u54_3_local_IRQHandler_7(void); -void mac_int_u54_3_local_IRQHandler_8(void); - -void mac_mmsl_u54_4_local_IRQHandler_3(void); -void mac_emac_u54_4_local_IRQHandler_4(void); -void mac_queue3_u54_4_local_IRQHandler_5(void); -void mac_queue2_u54_4_local_IRQHandler_6(void); -void mac_queue1_u54_4_local_IRQHandler_7(void); -void mac_int_u54_4_local_IRQHandler_8(void); +void U54_spare_0_local_IRQHandler(void); +void U54_spare_1_local_IRQHandler(void); +void U54_spare_2_local_IRQHandler(void); + +void U54_1_mac0_mmsl_local_IRQHandler(void); +void U54_1_mac0_emac_local_IRQHandler(void); +void U54_1_mac0_queue3_local_IRQHandler(void); +void U54_1_mac0_queue2_local_IRQHandler(void); +void U54_1_mac0_queue1_local_IRQHandler(void); +void U54_1_mac0_int_local_IRQHandler(void); + +void U54_2_mac0_mmsl_local_IRQHandler(void); +void U54_2_mac0_emac_local_IRQHandler(void); +void U54_2_mac0_queue3_local_IRQHandler(void); +void U54_2_mac0_queue2_local_IRQHandler(void); +void U54_2_mac0_queue1_local_IRQHandler(void); +void U54_2_mac0_int_local_IRQHandler(void); + +void U54_3_mac1_mmsl_local_IRQHandler(void); +void U54_3_mac1_emac_local_IRQHandler(void); +void U54_3_mac1_queue3_local_IRQHandler(void); +void U54_3_mac1_queue2_local_IRQHandler(void); +void U54_3_mac1_queue1_local_IRQHandler(void); +void U54_3_mac1_int_local_IRQHandler(void); + +void U54_4_mac1_mmsl_local_IRQHandler(void); +void U54_4_mac1_emac_local_IRQHandler(void); +void U54_4_mac1_queue3_local_IRQHandler(void); +void U54_4_mac1_queue2_local_IRQHandler(void); +void U54_4_mac1_queue1_local_IRQHandler(void); +void U54_4_mac1_int_local_IRQHandler(void); + +void U54_1_wdog_tout_local_IRQHandler(void); +void U54_2_wdog_tout_local_IRQHandler(void); +void U54_3_wdog_tout_local_IRQHandler(void); +void U54_4_wdog_tout_local_IRQHandler(void); +void mvrp_u54_local_IRQHandler_10(void); /* legacy name */ +void U54_1_wdog_mvrp_local_IRQHandler(void); +void U54_2_wdog_mvrp_local_IRQHandler(void); +void U54_3_wdog_mvrp_local_IRQHandler(void); +void U54_4_wdog_mvrp_local_IRQHandler(void); +void U54_1_mmuart1_local_IRQHandler(void); +void U54_2_mmuart2_local_IRQHandler(void); +void U54_3_mmuart3_local_IRQHandler(void); +void U54_4_mmuart4_local_IRQHandler(void); +void U54_spare_3_local_IRQHandler(void); +void U54_spare_4_local_IRQHandler(void); +void U54_spare_5_local_IRQHandler(void); +void U54_spare_6_local_IRQHandler(void); +void U54_f2m_0_local_IRQHandler(void); +void U54_f2m_1_local_IRQHandler(void); +void U54_f2m_2_local_IRQHandler(void); +void U54_f2m_3_local_IRQHandler(void); +void U54_f2m_4_local_IRQHandler(void); +void U54_f2m_5_local_IRQHandler(void); +void U54_f2m_6_local_IRQHandler(void); +void U54_f2m_7_local_IRQHandler(void); +void U54_f2m_8_local_IRQHandler(void); +void U54_f2m_9_local_IRQHandler(void); +void U54_f2m_10_local_IRQHandler(void); +void U54_f2m_11_local_IRQHandler(void); +void U54_f2m_12_local_IRQHandler(void); +void U54_f2m_13_local_IRQHandler(void); +void U54_f2m_14_local_IRQHandler(void); +void U54_f2m_15_local_IRQHandler(void); +void U54_f2m_16_local_IRQHandler(void); +void U54_f2m_17_local_IRQHandler(void); +void U54_f2m_18_local_IRQHandler(void); +void U54_f2m_19_local_IRQHandler(void); +void U54_f2m_20_local_IRQHandler(void); +void U54_f2m_21_local_IRQHandler(void); +void U54_f2m_22_local_IRQHandler(void); +void U54_f2m_23_local_IRQHandler(void); +void U54_f2m_24_local_IRQHandler(void); +void U54_f2m_25_local_IRQHandler(void); +void U54_f2m_26_local_IRQHandler(void); +void U54_f2m_27_local_IRQHandler(void); +void U54_f2m_28_local_IRQHandler(void); +void U54_f2m_29_local_IRQHandler(void); +void U54_f2m_30_local_IRQHandler(void); +void U54_f2m_31_local_IRQHandler(void); -void wdog_tout_u54_h1_local_IRQHandler_9(void); -void wdog_tout_u54_h2_local_IRQHandler_9(void); -void wdog_tout_u54_h3_local_IRQHandler_9(void); -void wdog_tout_u54_h4_local_IRQHandler_9(void); -void mvrp_u54_local_IRQHandler_10(void); -void mmuart_u54_h1_local_IRQHandler_11(void); -void mmuart_u54_h2_local_IRQHandler_11(void); -void mmuart_u54_h3_local_IRQHandler_11(void); -void mmuart_u54_h4_local_IRQHandler_11(void); -void spare_u54_local_IRQHandler_12(void); -void spare_u54_local_IRQHandler_13(void); -void spare_u54_local_IRQHandler_14(void); -void spare_u54_local_IRQHandler_15(void); -void fabric_f2h_0_u54_local_IRQHandler_16(void); -void fabric_f2h_1_u54_local_IRQHandler_17(void); -void fabric_f2h_2_u54_local_IRQHandler_18(void); -void fabric_f2h_3_u54_local_IRQHandler_19(void); -void fabric_f2h_4_u54_local_IRQHandler_20(void); -void fabric_f2h_5_u54_local_IRQHandler_21(void); -void fabric_f2h_6_u54_local_IRQHandler_22(void); -void fabric_f2h_7_u54_local_IRQHandler_23(void); -void fabric_f2h_8_u54_local_IRQHandler_24(void); -void fabric_f2h_9_u54_local_IRQHandler_25(void); -void fabric_f2h_10_u54_local_IRQHandler_26(void); -void fabric_f2h_11_u54_local_IRQHandler_27(void); -void fabric_f2h_12_u54_local_IRQHandler_28(void); -void fabric_f2h_13_u54_local_IRQHandler_29(void); -void fabric_f2h_14_u54_local_IRQHandler_30(void); -void fabric_f2h_15_u54_local_IRQHandler_31(void); -void fabric_f2h_16_u54_local_IRQHandler_32(void); -void fabric_f2h_17_u54_local_IRQHandler_33(void); -void fabric_f2h_18_u54_local_IRQHandler_34(void); -void fabric_f2h_19_u54_local_IRQHandler_35(void); -void fabric_f2h_20_u54_local_IRQHandler_36(void); -void fabric_f2h_21_u54_local_IRQHandler_37(void); -void fabric_f2h_22_u54_local_IRQHandler_38(void); -void fabric_f2h_23_u54_local_IRQHandler_39(void); -void fabric_f2h_24_u54_local_IRQHandler_40(void); -void fabric_f2h_25_u54_local_IRQHandler_41(void); -void fabric_f2h_26_u54_local_IRQHandler_42(void); -void fabric_f2h_27_u54_local_IRQHandler_43(void); -void fabric_f2h_28_u54_local_IRQHandler_44(void); -void fabric_f2h_29_u54_local_IRQHandler_45(void); -void fabric_f2h_30_u54_local_IRQHandler_46(void); -void fabric_f2h_31_u54_local_IRQHandler_47(void); #ifdef __cplusplus } diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c index 6194ae57..3cf7f592 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -28,1404 +28,1169 @@ __attribute__((weak)) void handle_m_ext_interrupt(void) } -__attribute__((weak)) void Software_h0_IRQHandler(void) +__attribute__((weak)) void E51_software_IRQHandler(void) { } -__attribute__((weak)) void Software_h1_IRQHandler(void) +__attribute__((weak)) void U54_1_software_IRQHandler(void) { } -__attribute__((weak)) void Software_h2_IRQHandler(void) +__attribute__((weak)) void U54_2_software_IRQHandler(void) { } -__attribute__((weak)) void Software_h3_IRQHandler(void) +__attribute__((weak)) void U54_3_software_IRQHandler(void) { } -__attribute__((weak)) void Software_h4_IRQHandler(void) +__attribute__((weak)) void U54_4_software_IRQHandler(void) { } -__attribute__((weak)) void SysTick_Handler_h0_IRQHandler(void) +__attribute__((weak)) void E51_sysTick_IRQHandler(void) { } -__attribute__((weak)) void SysTick_Handler_h1_IRQHandler(void) +__attribute__((weak)) void U54_1_sysTick_IRQHandler(void) { } -__attribute__((weak)) void SysTick_Handler_h2_IRQHandler(void) +__attribute__((weak)) void U54_2_sysTick_IRQHandler(void) { } -__attribute__((weak)) void SysTick_Handler_h3_IRQHandler(void) +__attribute__((weak)) void U54_3_sysTick_IRQHandler(void) { } -__attribute__((weak)) void SysTick_Handler_h4_IRQHandler(void) +__attribute__((weak)) void U54_4_sysTick_IRQHandler(void) { } -__attribute__((weak)) uint8_t Invalid_IRQHandler(void) -{ - return(0U); -} -#ifdef SIFIVE_HIFIVE_UNLEASHED -__attribute__((weak)) uint8_t External_1_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_2_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_3_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t USART0_plic_4_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_5_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_6_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_7_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_8_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_9_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_10_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_11_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_12_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_13_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_14_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_15_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_16_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_17_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_18_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_19_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_20_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_21_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_22_IRQHandler(void) -{ - return(0U); -} -#endif - -__attribute__((weak)) uint8_t dma_ch0_DONE_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_Invalid_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch0_ERR_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch0_DONE_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch1_DONE_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch0_ERR_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch1_ERR_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch1_DONE_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch2_DONE_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch1_ERR_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch2_ERR_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch2_DONE_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch3_DONE_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch2_ERR_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t dma_ch3_ERR_IRQHandler(void) -{ - return(0U); -} -#ifdef SIFIVE_HIFIVE_UNLEASHED -__attribute__((weak)) uint8_t External_31_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch3_DONE_IRQHandler(void) { return(0U); } - -__attribute__((weak)) uint8_t External_32_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_dma_ch3_ERR_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_33_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_l2_metadata_corr_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_34_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_l2_metadata_uncorr_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_35_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_l2_data_corr_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_36_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_l2_data_uncorr_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_37_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit0_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_38_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_39_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_40_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_41_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_42_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_43_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_44_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_45_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_46_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_47_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_48_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_49_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_50_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_51_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t External_52_IRQHandler(void) -{ - return(0U); -} - - -__attribute__((weak)) uint8_t MAC0_plic_53_IRQHandler(void) -{ - return(0U); -} -#endif - -#ifndef SIFIVE_HIFIVE_UNLEASHED -__attribute__((weak)) uint8_t l2_metadata_corr_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t l2_metadata_uncorr_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t l2_data_corr_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t l2_data_uncorr_IRQHandler(void) -{ - return(0U); -} -#endif /* ifndef SIFIVE_HIFIVE_UNLEASHED */ - - - -#ifndef SIFIVE_HIFIVE_UNLEASHED -__attribute__((weak)) uint8_t gpio0_bit0_or_gpio2_bit13_plic_0_IRQHandler(void) -{ - return(0U); -} - -__attribute__((weak)) uint8_t gpio0_bit1_or_gpio2_bit13_plic_1_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit1_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit2_or_gpio2_bit13_plic_2_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit2_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit3_or_gpio2_bit13_plic_3_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit3_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit4_or_gpio2_bit13_plic_4_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit4_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit5_or_gpio2_bit13_plic_5_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit5_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit6_or_gpio2_bit13_plic_6_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit6_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit7_or_gpio2_bit13_plic_7_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit7_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit8_or_gpio2_bit13_plic_8_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit8_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit9_or_gpio2_bit13_plic_9_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit9_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit10_or_gpio2_bit13_plic_10_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit10_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit11_or_gpio2_bit13_plic_11_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit11_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit12_or_gpio2_bit13_plic_12_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit12_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_bit13_or_gpio2_bit13_plic_13_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_bit13_or_gpio2_bit13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit0_or_gpio2_bit14_plic_14_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit0_or_gpio2_bit14_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit1_or_gpio2_bit15_plic_15_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit1_or_gpio2_bit15_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit2_or_gpio2_bit16_plic_16_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit2_or_gpio2_bit16_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit3_or_gpio2_bit17_plic_17_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit3_or_gpio2_bit17_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit4_or_gpio2_bit18_plic_18_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit4_or_gpio2_bit18_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit5_or_gpio2_bit19_plic_19_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit5_or_gpio2_bit19_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit6_or_gpio2_bit20_plic_20_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit6_or_gpio2_bit20_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit7_or_gpio2_bit21_plic_21_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit7_or_gpio2_bit21_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit8_or_gpio2_bit22_plic_22_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit8_or_gpio2_bit22_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit9_or_gpio2_bit23_plic_23_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit9_or_gpio2_bit23_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit10_or_gpio2_bit24_plic_24_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit10_or_gpio2_bit24_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit11_or_gpio2_bit25_plic_25_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit11_or_gpio2_bit25_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit12_or_gpio2_bit26_plic_26_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit12_or_gpio2_bit26_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit13_or_gpio2_bit27_plic_27_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit13_or_gpio2_bit27_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit14_or_gpio2_bit28_plic_28_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit14_or_gpio2_bit28_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit15_or_gpio2_bit29_plic_29_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit15_or_gpio2_bit29_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit16_or_gpio2_bit30_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit17_or_gpio2_bit31_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit18_plic_32_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit18_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit19_plic_33_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit19_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit20_plic_34_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit20_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit21_plic_35_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit21_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit22_plic_36_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit22_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_bit23_plic_37_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_bit23_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio0_non_direct_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio0_non_direct_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio1_non_direct_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio1_non_direct_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t gpio2_non_direct_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_gpio2_non_direct_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t spi0_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_spi0_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t spi1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_spi1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t external_can0_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_external_can0_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t can1_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_can1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_i2c0_main_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_External_i2c0_main_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t External_i2c0_alert_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_External_i2c0_alert_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t i2c0_sus_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_i2c0_sus_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t i2c1_main_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_i2c1_main_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t i2c1_alert_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_i2c1_alert_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t i2c1_sus_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_i2c1_sus_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac0_int_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac0_int_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac0_queue1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac0_queue1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac0_queue2_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac0_queue2_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac0_queue3_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac0_queue3_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac0_emac_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac0_emac_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac0_mmsl_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac0_mmsl_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac1_int_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac1_int_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac1_queue1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac1_queue1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac1_queue2_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac1_queue2_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac1_queue3_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac1_queue3_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac1_emac_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac1_emac_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mac1_mmsl_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mac1_mmsl_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t ddrc_train_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_ddrc_train_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t scb_interrupt_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_scb_interrupt_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t ecc_error_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_ecc_error_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t ecc_correct_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_ecc_correct_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t rtc_wakeup_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_rtc_wakeup_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t rtc_match_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_rtc_match_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t timer1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_timer1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t timer2_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_timer2_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t envm_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_envm_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t qspi_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_qspi_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t usb_dma_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_usb_dma_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t usb_mc_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_usb_mc_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmc_main_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmc_main_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmc_wakeup_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmc_wakeup_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmuart0_plic_77_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmuart0_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmuart1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmuart1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmuart2_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmuart2_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmuart3_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmuart3_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t mmuart4_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_mmuart4_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t g5c_devrst_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_devrst_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t g5c_message_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_g5c_message_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t usoc_vc_interrupt_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_usoc_vc_interrupt_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t usoc_smb_interrupt_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_usoc_smb_interrupt_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t e51_0_Maintence_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_E51_Maintence_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog0_mvrp_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog0_mvrp_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog1_mvrp_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog1_mvrp_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog2_mvrp_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog2_mvrp_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog3_mvrp_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog3_mvrp_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog4_mvrp_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog4_mvrp_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog0_tout_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog0_tout_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog1_tout_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog1_tout_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog2_tout_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog2_tout_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog3_tout_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog3_tout_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t wdog4_tout_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_wdog4_tout_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t g5c_mss_spi_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_g5c_mss_spi_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t volt_temp_alarm_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_volt_temp_alarm_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t athena_complete_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_athena_complete_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t athena_alarm_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_athena_alarm_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t athena_bus_error_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_athena_bus_error_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t usoc_axic_us_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_usoc_axic_us_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t usoc_axic_ds_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_usoc_axic_ds_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t reserved_104_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_reserved_104_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_0_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_0_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_1_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_2_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_2_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_3_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_3_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_4_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_4_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_5_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_5_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_6_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_6_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_7_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_7_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_8_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_8_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_9_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_9_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_10_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_10_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_11_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_11_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_12_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_12_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_13_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_13_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_14_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_14_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_15_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_15_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_16_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_16_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_17_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_17_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_18_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_18_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_19_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_19_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_20_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_20_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_21_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_21_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_22_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_22_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_23_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_23_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_24_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_24_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_25_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_25_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_26_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_26_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_27_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_27_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_28_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_28_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_29_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_29_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_30_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_30_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_31_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_31_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_32_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_32_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_33_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_33_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_34_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_34_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_35_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_35_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_36_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_36_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_37_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_37_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_38_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_38_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_39_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_39_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_40_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_40_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_41_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_41_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_42_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_42_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_43_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_43_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_44_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_44_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_45_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_45_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_46_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_46_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_47_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_47_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_48_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_48_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_49_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_49_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_50_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_50_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_51_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_51_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_52_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_52_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_53_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_53_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_54_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_54_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_55_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_55_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_56_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_56_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_57_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_57_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_58_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_58_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_59_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_59_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_60_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_60_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_61_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_61_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_62_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_62_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t fabric_f2h_63_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_f2m_63_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t bus_error_unit_hart_0_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_E51_bus_error_unit_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t bus_error_unit_hart_1_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_U54_1_bus_error_unit_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t bus_error_unit_hart_2_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_U54_2_bus_error_unit_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t bus_error_unit_hart_3_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_U54_3_bus_error_unit_IRQHandler(void) { return(0U); } -__attribute__((weak)) uint8_t bus_error_unit_hart_4_plic_IRQHandler(void) +__attribute__((weak)) uint8_t PLIC_U54_4_bus_error_unit_IRQHandler(void) { return(0U); } - /* Local interrupt stubs */ -__attribute__((weak)) void maintenance_e51_local_IRQHandler_0(void) +__attribute__((weak)) void E51_maintenance_local_IRQHandler(void) { } -__attribute__((weak)) void usoc_smb_interrupt_e51_local_IRQHandler_1(void) +__attribute__((weak)) void E51_usoc_smb_local_IRQHandler(void) { } -__attribute__((weak)) void usoc_vc_interrupt_e51_local_IRQHandler_2(void) +__attribute__((weak)) void E51_usoc_vc_local_IRQHandler(void) { } -__attribute__((weak)) void g5c_message_e51_local_IRQHandler_3(void) +__attribute__((weak)) void E51_g5c_message_local_IRQHandler(void) { } -__attribute__((weak)) void g5c_devrst_e51_local_IRQHandler_4(void) +__attribute__((weak)) void E51_g5c_devrst_local_IRQHandler(void) { } -__attribute__((weak)) void wdog4_tout_e51_local_IRQHandler_5(void) +__attribute__((weak)) void E51_wdog4_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog3_tout_e51_local_IRQHandler_6(void) +__attribute__((weak)) void E51_wdog3_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog2_tout_e51_local_IRQHandler_7(void) +__attribute__((weak)) void E51_wdog2_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog1_tout_e51_local_IRQHandler_8(void) +__attribute__((weak)) void E51_wdog1_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog0_tout_e51_local_IRQHandler_9(void) +__attribute__((weak)) void E51_wdog0_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog0_mvrp_e51_local_IRQHandler_10(void) +__attribute__((weak)) void E51_wdog0_mvrp_local_IRQHandler(void) { } -__attribute__((weak)) void mmuart0_e51_local_IRQHandler_11(void) +__attribute__((weak)) void E51_mmuart0_local_IRQHandler(void) { } -__attribute__((weak)) void envm_e51_local_IRQHandler_12(void) +__attribute__((weak)) void E51_envm_local_IRQHandler(void) { } -__attribute__((weak)) void ecc_correct_e51_local_IRQHandler_13(void) +__attribute__((weak)) void E51_ecc_correct_local_IRQHandler(void) { } -__attribute__((weak)) void ecc_error_e51_local_IRQHandler_14(void) +__attribute__((weak)) void E51_ecc_error_local_IRQHandler(void) { } -__attribute__((weak)) void scb_interrupt_e51_local_IRQHandler_15(void) +__attribute__((weak)) void E51_scb_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_32_e51_local_IRQHandler_16(void) +__attribute__((weak)) void E51_f2m_32_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_33_e51_local_IRQHandler_17(void) +__attribute__((weak)) void E51_f2m_33_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_34_e51_local_IRQHandler_18(void) +__attribute__((weak)) void E51_f2m_34_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_35_e51_local_IRQHandler_19(void) +__attribute__((weak)) void E51_f2m_35_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_36_e51_local_IRQHandler_20(void) +__attribute__((weak)) void E51_f2m_36_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_37_e51_local_IRQHandler_21(void) +__attribute__((weak)) void E51_f2m_37_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_38_e51_local_IRQHandler_22(void) +__attribute__((weak)) void E51_f2m_38_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_39_e51_local_IRQHandler_23(void) +__attribute__((weak)) void E51_f2m_39_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_40_e51_local_IRQHandler_24(void) +__attribute__((weak)) void E51_f2m_40_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_41_e51_local_IRQHandler_25(void) +__attribute__((weak)) void E51_f2m_41_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_42_e51_local_IRQHandler_26(void) +__attribute__((weak)) void E51_f2m_42_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_43_e51_local_IRQHandler_27(void) +__attribute__((weak)) void E51_f2m_43_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_44_e51_local_IRQHandler_28(void) +__attribute__((weak)) void E51_f2m_44_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_45_e51_local_IRQHandler_29(void) +__attribute__((weak)) void E51_f2m_45_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_46_e51_local_IRQHandler_30(void) +__attribute__((weak)) void E51_f2m_46_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_47_e51_local_IRQHandler_31(void) +__attribute__((weak)) void E51_f2m_47_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_48_e51_local_IRQHandler_32(void) +__attribute__((weak)) void E51_f2m_48_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_49_e51_local_IRQHandler_33(void) +__attribute__((weak)) void E51_f2m_49_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_50_e51_local_IRQHandler_34(void) +__attribute__((weak)) void E51_f2m_50_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_51_e51_local_IRQHandler_35(void) +__attribute__((weak)) void E51_f2m_51_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_52_e51_local_IRQHandler_36(void) +__attribute__((weak)) void E51_f2m_52_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_53_e51_local_IRQHandler_37(void) +__attribute__((weak)) void E51_f2m_53_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_54_e51_local_IRQHandler_38(void) +__attribute__((weak)) void E51_f2m_54_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_55_e51_local_IRQHandler_39(void) +__attribute__((weak)) void E51_f2m_55_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_56_e51_local_IRQHandler_40(void) +__attribute__((weak)) void E51_f2m_56_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_57_e51_local_IRQHandler_41(void) +__attribute__((weak)) void E51_f2m_57_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_58_e51_local_IRQHandler_42(void) +__attribute__((weak)) void E51_f2m_58_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_59_e51_local_IRQHandler_43(void) +__attribute__((weak)) void E51_f2m_59_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_60_e51_local_IRQHandler_44(void) +__attribute__((weak)) void E51_f2m_60_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_61_e51_local_IRQHandler_45(void) +__attribute__((weak)) void E51_f2m_61_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_62_e51_local_IRQHandler_46(void) +__attribute__((weak)) void E51_f2m_62_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_63_e51_local_IRQHandler_47(void) +__attribute__((weak)) void E51_f2m_63_local_IRQHandler(void) { } @@ -1433,231 +1198,246 @@ __attribute__((weak)) void fabric_f2h_63_e51_local_IRQHandler_47(void) /* * U54 */ -__attribute__((weak)) void spare_u54_local_IRQHandler_0(void) +__attribute__((weak)) void U54_spare_0_local_IRQHandler(void) { } -__attribute__((weak)) void spare_u54_local_IRQHandler_1(void) +__attribute__((weak)) void U54_spare_1_local_IRQHandler(void) { } -__attribute__((weak)) void spare_u54_local_IRQHandler_2(void) +__attribute__((weak)) void U54_spare_2_local_IRQHandler(void) { } /* Ethernet MACs - GEM0 is on U54s 1 and 2, GEM1 is on U54s 3 and 4 */ /* U54 1 */ -__attribute__((weak)) void mac_mmsl_u54_1_local_IRQHandler_3(void) +__attribute__((weak)) void U54_1_mac0_mmsl_local_IRQHandler(void) { } -__attribute__((weak)) void mac_emac_u54_1_local_IRQHandler_4(void) +__attribute__((weak)) void U54_1_mac0_emac_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue3_u54_1_local_IRQHandler_5(void) +__attribute__((weak)) void U54_1_mac0_queue3_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue2_u54_1_local_IRQHandler_6(void) +__attribute__((weak)) void U54_1_mac0_queue2_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue1_u54_1_local_IRQHandler_7(void) +__attribute__((weak)) void U54_1_mac0_queue1_local_IRQHandler(void) { } -__attribute__((weak)) void mac_int_u54_1_local_IRQHandler_8(void) +__attribute__((weak)) void U54_1_mac0_int_local_IRQHandler(void) { } /* U54 2 */ -__attribute__((weak)) void mac_mmsl_u54_2_local_IRQHandler_3(void) +__attribute__((weak)) void U54_2_mac0_mmsl_local_IRQHandler(void) { } -__attribute__((weak)) void mac_emac_u54_2_local_IRQHandler_4(void) +__attribute__((weak)) void U54_2_mac0_emac_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue3_u54_2_local_IRQHandler_5(void) +__attribute__((weak)) void U54_2_mac0_queue3_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue2_u54_2_local_IRQHandler_6(void) +__attribute__((weak)) void U54_2_mac0_queue2_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue1_u54_2_local_IRQHandler_7(void) +__attribute__((weak)) void U54_2_mac0_queue1_local_IRQHandler(void) { } -__attribute__((weak)) void mac_int_u54_2_local_IRQHandler_8(void) +__attribute__((weak)) void U54_2_mac0_int_local_IRQHandler(void) { } /* U54 3 */ -__attribute__((weak)) void mac_mmsl_u54_3_local_IRQHandler_3(void) +__attribute__((weak)) void U54_3_mac1_mmsl_local_IRQHandler(void) { } -__attribute__((weak)) void mac_emac_u54_3_local_IRQHandler_4(void) +__attribute__((weak)) void U54_3_mac1_emac_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue3_u54_3_local_IRQHandler_5(void) +__attribute__((weak)) void U54_3_mac1_queue3_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue2_u54_3_local_IRQHandler_6(void) +__attribute__((weak)) void U54_3_mac1_queue2_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue1_u54_3_local_IRQHandler_7(void) +__attribute__((weak)) void U54_3_mac1_queue1_local_IRQHandler(void) { } -__attribute__((weak)) void mac_int_u54_3_local_IRQHandler_8(void) +__attribute__((weak)) void U54_3_mac1_int_local_IRQHandler(void) { } /* U54 4 */ -__attribute__((weak)) void mac_mmsl_u54_4_local_IRQHandler_3(void) +__attribute__((weak)) void U54_4_mac1_mmsl_local_IRQHandler(void) { } -__attribute__((weak)) void mac_emac_u54_4_local_IRQHandler_4(void) +__attribute__((weak)) void U54_4_mac1_emac_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue3_u54_4_local_IRQHandler_5(void) +__attribute__((weak)) void U54_4_mac1_queue3_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue2_u54_4_local_IRQHandler_6(void) +__attribute__((weak)) void U54_4_mac1_queue2_local_IRQHandler(void) { } -__attribute__((weak)) void mac_queue1_u54_4_local_IRQHandler_7(void) +__attribute__((weak)) void U54_4_mac1_queue1_local_IRQHandler(void) { } -__attribute__((weak)) void mac_int_u54_4_local_IRQHandler_8(void) +__attribute__((weak)) void U54_4_mac1_int_local_IRQHandler(void) { } -__attribute__((weak)) void wdog_tout_u54_h1_local_IRQHandler_9(void) +__attribute__((weak)) void U54_1_wdog_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog_tout_u54_h2_local_IRQHandler_9(void) +__attribute__((weak)) void U54_2_wdog_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog_tout_u54_h3_local_IRQHandler_9(void) +__attribute__((weak)) void U54_3_wdog_tout_local_IRQHandler(void) { } -__attribute__((weak)) void wdog_tout_u54_h4_local_IRQHandler_9(void) +__attribute__((weak)) void U54_4_wdog_tout_local_IRQHandler(void) { } __attribute__((weak)) void mvrp_u54_local_IRQHandler_10(void) { } -__attribute__((weak)) void mmuart_u54_h1_local_IRQHandler_11(void) +__attribute__((weak)) void U54_1_wdog_mvrp_local_IRQHandler(void) +{ + mvrp_u54_local_IRQHandler_10(); +} +__attribute__((weak)) void U54_2_wdog_mvrp_local_IRQHandler(void) +{ + mvrp_u54_local_IRQHandler_10(); +} +__attribute__((weak)) void U54_3_wdog_mvrp_local_IRQHandler(void) +{ + mvrp_u54_local_IRQHandler_10(); +} +__attribute__((weak)) void U54_4_wdog_mvrp_local_IRQHandler(void) +{ + mvrp_u54_local_IRQHandler_10(); +} +__attribute__((weak)) void U54_1_mmuart1_local_IRQHandler(void) { } -__attribute__((weak)) void mmuart_u54_h2_local_IRQHandler_11(void) +__attribute__((weak)) void U54_2_mmuart2_local_IRQHandler(void) { } -__attribute__((weak)) void mmuart_u54_h3_local_IRQHandler_11(void) +__attribute__((weak)) void U54_3_mmuart3_local_IRQHandler(void) { } -__attribute__((weak)) void mmuart_u54_h4_local_IRQHandler_11(void) +__attribute__((weak)) void U54_4_mmuart4_local_IRQHandler(void) { } -__attribute__((weak)) void spare_u54_local_IRQHandler_12(void) +__attribute__((weak)) void U54_spare_3_local_IRQHandler(void) { } -__attribute__((weak)) void spare_u54_local_IRQHandler_13(void) +__attribute__((weak)) void U54_spare_4_local_IRQHandler(void) { } -__attribute__((weak)) void spare_u54_local_IRQHandler_14(void) +__attribute__((weak)) void U54_spare_5_local_IRQHandler(void) { } -__attribute__((weak)) void spare_u54_local_IRQHandler_15(void) +__attribute__((weak)) void U54_spare_6_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_0_u54_local_IRQHandler_16(void) +__attribute__((weak)) void U54_f2m_0_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_1_u54_local_IRQHandler_17(void) +__attribute__((weak)) void U54_f2m_1_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_2_u54_local_IRQHandler_18(void) +__attribute__((weak)) void U54_f2m_2_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_3_u54_local_IRQHandler_19(void) +__attribute__((weak)) void U54_f2m_3_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_4_u54_local_IRQHandler_20(void) +__attribute__((weak)) void U54_f2m_4_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_5_u54_local_IRQHandler_21(void) +__attribute__((weak)) void U54_f2m_5_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_6_u54_local_IRQHandler_22(void) +__attribute__((weak)) void U54_f2m_6_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_7_u54_local_IRQHandler_23(void) +__attribute__((weak)) void U54_f2m_7_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_8_u54_local_IRQHandler_24(void) +__attribute__((weak)) void U54_f2m_8_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_9_u54_local_IRQHandler_25(void) +__attribute__((weak)) void U54_f2m_9_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_10_u54_local_IRQHandler_26(void) +__attribute__((weak)) void U54_f2m_10_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_11_u54_local_IRQHandler_27(void) +__attribute__((weak)) void U54_f2m_11_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_12_u54_local_IRQHandler_28(void) +__attribute__((weak)) void U54_f2m_12_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_13_u54_local_IRQHandler_29(void) +__attribute__((weak)) void U54_f2m_13_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_14_u54_local_IRQHandler_30(void) +__attribute__((weak)) void U54_f2m_14_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_15_u54_local_IRQHandler_31(void) +__attribute__((weak)) void U54_f2m_15_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_16_u54_local_IRQHandler_32(void) +__attribute__((weak)) void U54_f2m_16_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_17_u54_local_IRQHandler_33(void) +__attribute__((weak)) void U54_f2m_17_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_18_u54_local_IRQHandler_34(void) +__attribute__((weak)) void U54_f2m_18_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_19_u54_local_IRQHandler_35(void) +__attribute__((weak)) void U54_f2m_19_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_20_u54_local_IRQHandler_36(void) +__attribute__((weak)) void U54_f2m_20_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_21_u54_local_IRQHandler_37(void) +__attribute__((weak)) void U54_f2m_21_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_22_u54_local_IRQHandler_38(void) +__attribute__((weak)) void U54_f2m_22_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_23_u54_local_IRQHandler_39(void) +__attribute__((weak)) void U54_f2m_23_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_24_u54_local_IRQHandler_40(void) +__attribute__((weak)) void U54_f2m_24_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_25_u54_local_IRQHandler_41(void) +__attribute__((weak)) void U54_f2m_25_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_26_u54_local_IRQHandler_42(void) +__attribute__((weak)) void U54_f2m_26_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_27_u54_local_IRQHandler_43(void) +__attribute__((weak)) void U54_f2m_27_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_28_u54_local_IRQHandler_44(void) +__attribute__((weak)) void U54_f2m_28_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_29_u54_local_IRQHandler_45(void) +__attribute__((weak)) void U54_f2m_29_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_30_u54_local_IRQHandler_46(void) +__attribute__((weak)) void U54_f2m_30_local_IRQHandler(void) { } -__attribute__((weak)) void fabric_f2h_31_u54_local_IRQHandler_47(void) +__attribute__((weak)) void U54_f2m_31_local_IRQHandler(void) { } -#endif /* ifndef SIFIVE_HIFIVE_UNLEASHED */ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c index d51efed0..af4b00ec 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -20,6 +20,7 @@ #include #include +#include #include "mpfs_hal/mss_hal.h" #include "mss_l2_cache.h" @@ -46,8 +47,14 @@ static void check_config_l2_scratchpad(void); */ __attribute__((weak)) void config_l2_cache(void) { - ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U); - + static_assert(LIBERO_SETTING_WAY_ENABLE < 16U, "Too many ways"); + /* + * confirm the amount of l2lim used in the Linker script has been allocated + * in the MSS Configurator + */ + ASSERT(((const uint64_t)&__l2lim_end - (const uint64_t)&__l2lim_start)\ + <= ((15U - LIBERO_SETTING_WAY_ENABLE) * WAY_BYTE_LENGTH)); + /* * Set the number of ways that will be shared between cache and scratchpad. */ @@ -63,12 +70,10 @@ __attribute__((weak)) void config_l2_cache(void) /* If you are not using scratchpad, no need to include the following code */ - ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS); - - + static_assert(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS, "Scratchpad Missing"); /* - * Compute the mask used to specify ways that will be used by the + * Compute the mask (In HSS CONFIG_SERVICE_SCRUB=y) used to specify ways that will be used by the * scratchpad. */ @@ -191,107 +196,3 @@ static void check_config_l2_scratchpad(void) ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways); } - -#if 0 // todo - remove, no longer used - - -/*============================================================================== - * Reserve a number of cache ways to be used as scratchpad memory. - * - * @param nways - * Number of ways to be used as scratchpad. One way is 128Kbytes. - * - * @param scratchpad_start - * Start address within the Zero Device memory range in which the scratchpad - * will be located. - */ -static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) -{ - uint8_t way_enable; - uint64_t available_ways = 1; - uint64_t scratchpad_ways = 0; - uint64_t non_scratchpad_ways; - uint32_t inc; - - ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM); - ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP); - - /* - * Ensure at least one way remains available as cache. - */ - way_enable = CACHE_CTRL->WAY_ENABLE; - ASSERT(nways <= way_enable); - if(nways <= way_enable) - { - /* - * Compute the mask used to specify ways that will be used by the - * scratchpad. - */ - - for(inc = 0; inc < way_enable; ++inc) - { - available_ways = (available_ways << 1) | (uint64_t)0x01; - if(inc < nways) - { - scratchpad_ways = (scratchpad_ways << 1) | (uint64_t)0x01; - } - } - - /* - * Prevent other masters from evicting cache lines from scratchpad ways. - * Only allow E51 to evict from scratchpad ways. - */ - non_scratchpad_ways = available_ways & ~scratchpad_ways; - - CACHE_CTRL->WAY_MASK_DMA = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_E51_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_1_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_1_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_2_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_2_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_3_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_3_ICACHE = non_scratchpad_ways; - - CACHE_CTRL->WAY_MASK_U54_4_DCACHE = non_scratchpad_ways; - CACHE_CTRL->WAY_MASK_U54_4_ICACHE = non_scratchpad_ways; - - /* - * Assign ways to Zero Device - */ - uint64_t * p_scratchpad = scratchpad_start; - int ways_inc; - uint64_t current_way = 1; - for(ways_inc = 0; ways_inc < nways; ++ways_inc) - { - /* - * Populate the scratchpad memory one way at a time. - */ - CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way; - /* - * Write to the first 64-bit location of each cache block. - */ - for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc) - { - *p_scratchpad = g_init_marker + inc; - p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH; - } - current_way = current_way << 1U; - mb(); - } - - /* - * Prevent E51 from evicting from scratchpad ways. - */ - CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways; - } -} -#endif diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h index 16d618d6..d25bb15f 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_legacy_defines.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_legacy_defines.h new file mode 100644 index 00000000..fe2479eb --- /dev/null +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_legacy_defines.h @@ -0,0 +1,710 @@ +/******************************************************************************* + * Copyright 2021-2022 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/******************************************************************************* + * + * @file mss_hart_ints.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief MPFS legacy defines + * + * Mapping of older defines to newer defines to allow older code compile + * + */ +#ifndef MSS_LEGACY_DEFINES_H +#define MSS_LEGACY_DEFINES_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define maintenance_e51_local_IRQHandler_0 E51_maintenance_local_IRQHandler +#define usoc_smb_interrupt_e51_local_IRQHandler_1 E51_usoc_smb_local_IRQHandler +#define usoc_vc_interrupt_e51_local_IRQHandler_2 E51_usoc_vc_local_IRQHandler +#define g5c_message_e51_local_IRQHandler_3 E51_g5c_message_local_IRQHandler +#define g5c_devrst_e51_local_IRQHandler_4 E51_g5c_devrst_local_IRQHandler +#define wdog4_tout_e51_local_IRQHandler_5 E51_wdog4_tout_local_IRQHandler +#define wdog3_tout_e51_local_IRQHandler_6 E51_wdog3_tout_local_IRQHandler +#define wdog2_tout_e51_local_IRQHandler_7 E51_wdog2_tout_local_IRQHandler +#define wdog1_tout_e51_local_IRQHandler_8 E51_wdog1_tout_local_IRQHandler +#define wdog0_tout_e51_local_IRQHandler_9 E51_wdog0_tout_local_IRQHandler +#define wdog0_mvrp_e51_local_IRQHandler_10 E51_wdog0_mvrp_local_IRQHandler +#define mmuart0_e51_local_IRQHandler_11 E51_mmuart0_local_IRQHandler +#define envm_e51_local_IRQHandler_12 E51_envm_local_IRQHandler +#define ecc_correct_e51_local_IRQHandler_13 E51_ecc_correct_local_IRQHandler +#define ecc_error_e51_local_IRQHandler_14 E51_ecc_error_local_IRQHandler +#define scb_interrupt_e51_local_IRQHandler_15 E51_scb_local_IRQHandler +#define fabric_f2h_32_e51_local_IRQHandler_16 E51_f2m_32_local_IRQHandler +#define fabric_f2h_33_e51_local_IRQHandler_17 E51_f2m_33_local_IRQHandler +#define fabric_f2h_34_e51_local_IRQHandler_18 E51_f2m_34_local_IRQHandler +#define fabric_f2h_35_e51_local_IRQHandler_19 E51_f2m_35_local_IRQHandler +#define fabric_f2h_36_e51_local_IRQHandler_20 E51_f2m_36_local_IRQHandler +#define fabric_f2h_37_e51_local_IRQHandler_21 E51_f2m_37_local_IRQHandler +#define fabric_f2h_38_e51_local_IRQHandler_22 E51_f2m_38_local_IRQHandler +#define fabric_f2h_39_e51_local_IRQHandler_23 E51_f2m_39_local_IRQHandler +#define fabric_f2h_40_e51_local_IRQHandler_24 E51_f2m_40_local_IRQHandler +#define fabric_f2h_41_e51_local_IRQHandler_25 E51_f2m_41_local_IRQHandler +#define fabric_f2h_42_e51_local_IRQHandler_26 E51_f2m_42_local_IRQHandler +#define fabric_f2h_43_e51_local_IRQHandler_27 E51_f2m_43_local_IRQHandler +#define fabric_f2h_44_e51_local_IRQHandler_28 E51_f2m_44_local_IRQHandler +#define fabric_f2h_45_e51_local_IRQHandler_29 E51_f2m_45_local_IRQHandler +#define fabric_f2h_46_e51_local_IRQHandler_30 E51_f2m_46_local_IRQHandler +#define fabric_f2h_47_e51_local_IRQHandler_31 E51_f2m_47_local_IRQHandler +#define fabric_f2h_48_e51_local_IRQHandler_32 E51_f2m_48_local_IRQHandler +#define fabric_f2h_49_e51_local_IRQHandler_33 E51_f2m_49_local_IRQHandler +#define fabric_f2h_50_e51_local_IRQHandler_34 E51_f2m_50_local_IRQHandler +#define fabric_f2h_51_e51_local_IRQHandler_35 E51_f2m_51_local_IRQHandler +#define fabric_f2h_52_e51_local_IRQHandler_36 E51_f2m_52_local_IRQHandler +#define fabric_f2h_53_e51_local_IRQHandler_37 E51_f2m_53_local_IRQHandler +#define fabric_f2h_54_e51_local_IRQHandler_38 E51_f2m_54_local_IRQHandler +#define fabric_f2h_55_e51_local_IRQHandler_39 E51_f2m_55_local_IRQHandler +#define fabric_f2h_56_e51_local_IRQHandler_40 E51_f2m_56_local_IRQHandler +#define fabric_f2h_57_e51_local_IRQHandler_41 E51_f2m_57_local_IRQHandler +#define fabric_f2h_58_e51_local_IRQHandler_42 E51_f2m_58_local_IRQHandler +#define fabric_f2h_59_e51_local_IRQHandler_43 E51_f2m_59_local_IRQHandler +#define fabric_f2h_60_e51_local_IRQHandler_44 E51_f2m_60_local_IRQHandler +#define fabric_f2h_61_e51_local_IRQHandler_45 E51_f2m_61_local_IRQHandler +#define fabric_f2h_62_e51_local_IRQHandler_46 E51_f2m_62_local_IRQHandler +#define fabric_f2h_63_e51_local_IRQHandler_47 E51_f2m_63_local_IRQHandler + +#define spare_u54_local_IRQHandler_0 U54_spare_0_local_IRQHandler +#define spare_u54_local_IRQHandler_1 U54_spare_1_local_IRQHandler +#define spare_u54_local_IRQHandler_2 U54_spare_2_local_IRQHandler + +#define mac_mmsl_u54_1_local_IRQHandler_3 U54_1_mac0_mmsl_local_IRQHandler +#define mac_emac_u54_1_local_IRQHandler_4 U54_1_mac0_emac_local_IRQHandler +#define mac_queue3_u54_1_local_IRQHandler_5 U54_1_mac0_queue3_local_IRQHandler +#define mac_queue2_u54_1_local_IRQHandler_6 U54_1_mac0_queue2_local_IRQHandler +#define mac_queue1_u54_1_local_IRQHandler_7 U54_1_mac0_queue1_local_IRQHandler +#define mac_int_u54_1_local_IRQHandler_8 U54_1_mac0_int_local_IRQHandler + +#define mac_mmsl_u54_2_local_IRQHandler_3 U54_2_mac0_mmsl_local_IRQHandler +#define mac_emac_u54_2_local_IRQHandler_4 U54_2_mac0_emac_local_IRQHandler +#define mac_queue3_u54_2_local_IRQHandler_5 U54_2_mac0_queue3_local_IRQHandler +#define mac_queue2_u54_2_local_IRQHandler_6 U54_2_mac0_queue2_local_IRQHandler +#define mac_queue1_u54_2_local_IRQHandler_7 U54_2_mac0_queue1_local_IRQHandler +#define mac_int_u54_2_local_IRQHandler_8 U54_2_mac0_int_local_IRQHandler + +#define mac_mmsl_u54_3_local_IRQHandler_3 U54_3_mac1_mmsl_local_IRQHandler +#define mac_emac_u54_3_local_IRQHandler_4 U54_3_mac1_emac_local_IRQHandler +#define mac_queue3_u54_3_local_IRQHandler_5 U54_3_mac1_queue3_local_IRQHandler +#define mac_queue2_u54_3_local_IRQHandler_6 U54_3_mac1_queue2_local_IRQHandler +#define mac_queue1_u54_3_local_IRQHandler_7 U54_3_mac1_queue1_local_IRQHandler +#define mac_int_u54_3_local_IRQHandler_8 U54_3_mac1_int_local_IRQHandler + +#define mac_mmsl_u54_4_local_IRQHandler_3 U54_4_mac1_mmsl_local_IRQHandler +#define mac_emac_u54_4_local_IRQHandler_4 U54_4_mac1_emac_local_IRQHandler +#define mac_queue3_u54_4_local_IRQHandler_5 U54_4_mac1_queue3_local_IRQHandler +#define mac_queue2_u54_4_local_IRQHandler_6 U54_4_mac1_queue2_local_IRQHandler +#define mac_queue1_u54_4_local_IRQHandler_7 U54_4_mac1_queue1_local_IRQHandler +#define mac_int_u54_4_local_IRQHandler_8 U54_4_mac1_int_local_IRQHandler + +#define wdog_tout_u54_h1_local_IRQHandler_9 U54_1_wdog_tout_local_IRQHandler + +/* + * Update your watchdog code if using mvrp_u54_local_IRQHandler_10() + * to use the following instead: + * U54_1_wdog_mvrp_local_IRQHandler() + * U54_2_wdog_mvrp_local_IRQHandler() + * U54_3_wdog_mvrp_local_IRQHandler() + * U54_4_wdog_mvrp_local_IRQHandler() + */ +#define mmuart_u54_h1_local_IRQHandler_11 U54_1_mmuart1_local_IRQHandler + +#define wdog_tout_u54_h2_local_IRQHandler_9 U54_2_wdog_tout_local_IRQHandler +#define mmuart_u54_h2_local_IRQHandler_11 U54_2_mmuart2_local_IRQHandler + +#define wdog_tout_u54_h3_local_IRQHandler_9 U54_3_wdog_tout_local_IRQHandler +#define mmuart_u54_h3_local_IRQHandler_11 U54_3_mmuart3_local_IRQHandler + +#define wdog_tout_u54_h4_local_IRQHandler_9 U54_4_wdog_tout_local_IRQHandler +#define mmuart_u54_h4_local_IRQHandler_11 U54_4_mmuart4_local_IRQHandler + +#define spare_u54_local_IRQHandler_12 U54_spare_3_local_IRQHandler +#define spare_u54_local_IRQHandler_13 U54_spare_4_local_IRQHandler +#define spare_u54_local_IRQHandler_14 U54_spare_5_local_IRQHandler +#define spare_u54_local_IRQHandler_15 U54_spare_6_local_IRQHandler +#define fabric_f2h_0_u54_local_IRQHandler_16 U54_f2m_0_local_IRQHandler +#define fabric_f2h_1_u54_local_IRQHandler_17 U54_f2m_1_local_IRQHandler +#define fabric_f2h_2_u54_local_IRQHandler_18 U54_f2m_2_local_IRQHandler +#define fabric_f2h_3_u54_local_IRQHandler_19 U54_f2m_3_local_IRQHandler +#define fabric_f2h_4_u54_local_IRQHandler_20 U54_f2m_4_local_IRQHandler +#define fabric_f2h_5_u54_local_IRQHandler_21 U54_f2m_5_local_IRQHandler +#define fabric_f2h_6_u54_local_IRQHandler_22 U54_f2m_6_local_IRQHandler +#define fabric_f2h_7_u54_local_IRQHandler_23 U54_f2m_7_local_IRQHandler +#define fabric_f2h_8_u54_local_IRQHandler_24 U54_f2m_8_local_IRQHandler +#define fabric_f2h_9_u54_local_IRQHandler_25 U54_f2m_9_local_IRQHandler +#define fabric_f2h_10_u54_local_IRQHandler_26 U54_f2m_10_local_IRQHandler +#define fabric_f2h_11_u54_local_IRQHandler_27 U54_f2m_11_local_IRQHandler +#define fabric_f2h_12_u54_local_IRQHandler_28 U54_f2m_12_local_IRQHandler +#define fabric_f2h_13_u54_local_IRQHandler_29 U54_f2m_13_local_IRQHandler +#define fabric_f2h_14_u54_local_IRQHandler_30 U54_f2m_14_local_IRQHandler +#define fabric_f2h_15_u54_local_IRQHandler_31 U54_f2m_15_local_IRQHandler +#define fabric_f2h_16_u54_local_IRQHandler_32 U54_f2m_16_local_IRQHandler +#define fabric_f2h_17_u54_local_IRQHandler_33 U54_f2m_17_local_IRQHandler +#define fabric_f2h_18_u54_local_IRQHandler_34 U54_f2m_18_local_IRQHandler +#define fabric_f2h_19_u54_local_IRQHandler_35 U54_f2m_19_local_IRQHandler +#define fabric_f2h_20_u54_local_IRQHandler_36 U54_f2m_20_local_IRQHandler +#define fabric_f2h_21_u54_local_IRQHandler_37 U54_f2m_21_local_IRQHandler +#define fabric_f2h_22_u54_local_IRQHandler_38 U54_f2m_22_local_IRQHandler +#define fabric_f2h_23_u54_local_IRQHandler_39 U54_f2m_23_local_IRQHandler +#define fabric_f2h_24_u54_local_IRQHandler_40 U54_f2m_24_local_IRQHandler +#define fabric_f2h_25_u54_local_IRQHandler_41 U54_f2m_25_local_IRQHandler +#define fabric_f2h_26_u54_local_IRQHandler_42 U54_f2m_26_local_IRQHandler +#define fabric_f2h_27_u54_local_IRQHandler_43 U54_f2m_27_local_IRQHandler +#define fabric_f2h_28_u54_local_IRQHandler_44 U54_f2m_28_local_IRQHandler +#define fabric_f2h_29_u54_local_IRQHandler_45 U54_f2m_29_local_IRQHandler +#define fabric_f2h_30_u54_local_IRQHandler_46 U54_f2m_30_local_IRQHandler +#define fabric_f2h_31_u54_local_IRQHandler_47 U54_f2m_31_local_IRQHandler + +#define MAINTENANCE_E51_INT 0 +#define USOC_SMB_INTERRUPT_E51_INT 1 +#define USOC_VC_INTERRUPT_E51_INT 2 +#define G5C_MESSAGE_E51_INT 3 +#define G5C_DEVRST_E51_INT 4 +#define WDOG4_TOUT_E51_INT 5 +#define WDOG3_TOUT_E51_INT 6 +#define WDOG2_TOUT_E51_INT 7 +#define WDOG1_TOUT_E51_INT 8 +#define WDOG0_TOUT_E51_INT 9 +#define WDOG0_MVRP_E51_INT 10 +#define MMUART0_E51_INT 11 +#define ENVM_E51_INT 12 +#define ECC_CORRECT_E51_INT 13 +#define ECC_ERROR_E51_INT 14 +#define scb_INTERRUPT_E51_INT 15 +#define FABRIC_F2H_32_E51_INT 16 +#define FABRIC_F2H_33_E51_INT 17 +#define FABRIC_F2H_34_E51_INT 18 +#define FABRIC_F2H_35_E51_INT 19 +#define FABRIC_F2H_36_E51_INT 20 +#define FABRIC_F2H_37_E51_INT 21 +#define FABRIC_F2H_38_E51_INT 22 +#define FABRIC_F2H_39_E51_INT 23 +#define FABRIC_F2H_40_E51_INT 24 +#define FABRIC_F2H_41_E51_INT 25 + +#define FABRIC_F2H_42_E51_INT 26 +#define FABRIC_F2H_43_E51_INT 27 +#define FABRIC_F2H_44_E51_INT 28 +#define FABRIC_F2H_45_E51_INT 29 +#define FABRIC_F2H_46_E51_INT 30 +#define FABRIC_F2H_47_E51_INT 31 +#define FABRIC_F2H_48_E51_INT 32 +#define FABRIC_F2H_49_E51_INT 33 +#define FABRIC_F2H_50_E51_INT 34 +#define FABRIC_F2H_51_E51_INT 35 + +#define FABRIC_F2H_52_E51_INT 36 +#define FABRIC_F2H_53_E51_INT 37 +#define FABRIC_F2H_54_E51_INT 38 +#define FABRIC_F2H_55_E51_INT 39 +#define FABRIC_F2H_56_E51_INT 40 +#define FABRIC_F2H_57_E51_INT 41 +#define FABRIC_F2H_58_E51_INT 42 +#define FABRIC_F2H_59_E51_INT 43 +#define FABRIC_F2H_60_E51_INT 44 +#define FABRIC_F2H_61_E51_INT 45 + +#define FABRIC_F2H_62_E51_INT 46 +#define FABRIC_F2H_63_E51_INT 47 + +/* U0 (first U54) and U1 connected to mac0 */ +#define MAC0_INT_U54_INT 8 /* determine source mac using hart ID */ +#define MAC0_QUEUE1_U54_INT 7 +#define MAC0_QUEUE2_U54_INT 6 +#define MAC0_QUEUE3_U54_INT 5 +#define MAC0_EMAC_U54_INT 4 +#define MAC0_MMSL_U54_INT 3 + +/* U2 and U3 connected to mac1 */ +#define MAC1_INT_U54_INT 8 /* determine source mac using hart ID */ +#define MAC1_QUEUE1_U54_INT 7 +#define MAC1_QUEUE2_U54_INT 6 +#define MAC1_QUEUE3_U54_INT 5 +#define MAC1_EMAC_U54_INT 4 +#define MAC1_MMSL_U54_INT 3 + +/* MMUART1 connected to U54 0 */ +/* MMUART2 connected to U54 1 */ +/* MMUART3 connected to U54 2 */ +/* MMUART4 connected to U54 3 */ +#define MMUARTx_U54_INT 11 /* MMUART1 connected to U54 0 */ +#define WDOGx_MVRP_U54_INT 10 /* determine source mac using hart ID */ +#define WDOGx_TOUT_U54_INT 9 /* determine source mac using hart ID */ + +#define H2_FABRIC_F2H_0_U54_INT 16 +#define H2_FABRIC_F2H_1_U54_INT 17 +#define H2_FABRIC_F2H_2_U54_INT 18 +#define H2_FABRIC_F2H_3_U54_INT 19 +#define H2_FABRIC_F2H_4_U54_INT 20 +#define H2_FABRIC_F2H_5_U54_INT 21 +#define H2_FABRIC_F2H_6_U54_INT 22 +#define H2_FABRIC_F2H_7_U54_INT 23 +#define H2_FABRIC_F2H_8_U54_INT 24 +#define H2_FABRIC_F2H_9_U54_INT 25 + +#define H2_FABRIC_F2H_10_U54_INT 26 +#define H2_FABRIC_F2H_11_U54_INT 27 +#define H2_FABRIC_F2H_12_U54_INT 28 +#define H2_FABRIC_F2H_13_U54_INT 29 +#define H2_FABRIC_F2H_14_U54_INT 30 +#define H2_FABRIC_F2H_15_U54_INT 31 +#define H2_FABRIC_F2H_16_U54_INT 32 +#define H2_FABRIC_F2H_17_U54_INT 33 +#define H2_FABRIC_F2H_18_U54_INT 34 +#define H2_FABRIC_F2H_19_U54_INT 35 + +#define H2_FABRIC_F2H_20_U54_INT 36 +#define H2_FABRIC_F2H_21_U54_INT 37 +#define H2_FABRIC_F2H_22_U54_INT 38 +#define H2_FABRIC_F2H_23_U54_INT 39 +#define H2_FABRIC_F2H_24_U54_INT 40 +#define H2_FABRIC_F2H_25_U54_INT 41 +#define H2_FABRIC_F2H_26_U54_INT 42 +#define H2_FABRIC_F2H_27_U54_INT 43 +#define H2_FABRIC_F2H_28_U54_INT 44 +#define H2_FABRIC_F2H_29_U54_INT 45 + +#define H2_FABRIC_F2H_30_U54_INT 46 +#define H2_FABRIC_F2H_31_U54_INT 47 + + + +#define Invalid_IRQHandler PLIC_Invalid_IRQHandler +#define l2_metadata_corr_IRQHandler PLIC_l2_metadata_corr_IRQHandler +#define l2_metadata_uncorr_IRQHandler PLIC_l2_metadata_uncorr_IRQHandler +#define l2_data_corr_IRQHandler PLIC_l2_data_corr_IRQHandler +#define l2_data_uncorr_IRQHandler PLIC_l2_data_uncorr_IRQHandler +#define dma_ch0_DONE_IRQHandler PLIC_dma_ch0_DONE_IRQHandler +#define dma_ch0_ERR_IRQHandler PLIC_dma_ch0_ERR_IRQHandler +#define dma_ch1_DONE_IRQHandler PLIC_dma_ch1_DONE_IRQHandler +#define dma_ch1_ERR_IRQHandler PLIC_dma_ch1_ERR_IRQHandler +#define dma_ch2_DONE_IRQHandler PLIC_dma_ch2_DONE_IRQHandler +#define dma_ch2_ERR_IRQHandler PLIC_dma_ch2_ERR_IRQHandler +#define dma_ch3_DONE_IRQHandler PLIC_dma_ch3_DONE_IRQHandler +#define dma_ch3_ERR_IRQHandler PLIC_dma_ch3_ERR_IRQHandler +#define gpio0_bit0_or_gpio2_bit13_plic_0_IRQHandler PLIC_gpio0_bit0_or_gpio2_bit13_IRQHandler +#define gpio0_bit1_or_gpio2_bit13_plic_1_IRQHandler PLIC_gpio0_bit1_or_gpio2_bit13_IRQHandler +#define gpio0_bit2_or_gpio2_bit13_plic_2_IRQHandler PLIC_gpio0_bit2_or_gpio2_bit13_IRQHandler +#define gpio0_bit3_or_gpio2_bit13_plic_3_IRQHandler PLIC_gpio0_bit3_or_gpio2_bit13_IRQHandler +#define gpio0_bit4_or_gpio2_bit13_plic_4_IRQHandler PLIC_gpio0_bit4_or_gpio2_bit13_IRQHandler +#define gpio0_bit5_or_gpio2_bit13_plic_5_IRQHandler PLIC_gpio0_bit5_or_gpio2_bit13_IRQHandler +#define gpio0_bit6_or_gpio2_bit13_plic_6_IRQHandler PLIC_gpio0_bit6_or_gpio2_bit13_IRQHandler +#define gpio0_bit7_or_gpio2_bit13_plic_7_IRQHandler PLIC_gpio0_bit7_or_gpio2_bit13_IRQHandler +#define gpio0_bit8_or_gpio2_bit13_plic_8_IRQHandler PLIC_gpio0_bit8_or_gpio2_bit13_IRQHandler +#define gpio0_bit9_or_gpio2_bit13_plic_9_IRQHandler PLIC_gpio0_bit9_or_gpio2_bit13_IRQHandler +#define gpio0_bit10_or_gpio2_bit13_plic_10_IRQHandler PLIC_gpio0_bit10_or_gpio2_bit13_IRQHandler +#define gpio0_bit11_or_gpio2_bit13_plic_11_IRQHandler PLIC_gpio0_bit11_or_gpio2_bit13_IRQHandler +#define gpio0_bit12_or_gpio2_bit13_plic_12_IRQHandler PLIC_gpio0_bit12_or_gpio2_bit13_IRQHandler + +#define gpio0_bit13_or_gpio2_bit13_plic_13_IRQHandler PLIC_gpio0_bit13_or_gpio2_bit13_IRQHandler +#define gpio1_bit0_or_gpio2_bit14_plic_14_IRQHandler PLIC_gpio1_bit0_or_gpio2_bit14_IRQHandler +#define gpio1_bit1_or_gpio2_bit15_plic_15_IRQHandler PLIC_gpio1_bit1_or_gpio2_bit15_IRQHandler +#define gpio1_bit2_or_gpio2_bit16_plic_16_IRQHandler PLIC_gpio1_bit2_or_gpio2_bit16_IRQHandler +#define gpio1_bit3_or_gpio2_bit17_plic_17_IRQHandler PLIC_gpio1_bit3_or_gpio2_bit17_IRQHandler +#define gpio1_bit4_or_gpio2_bit18_plic_18_IRQHandler PLIC_gpio1_bit4_or_gpio2_bit18_IRQHandler +#define gpio1_bit5_or_gpio2_bit19_plic_19_IRQHandler PLIC_gpio1_bit5_or_gpio2_bit19_IRQHandler +#define gpio1_bit6_or_gpio2_bit20_plic_20_IRQHandler PLIC_gpio1_bit6_or_gpio2_bit20_IRQHandler +#define gpio1_bit7_or_gpio2_bit21_plic_21_IRQHandler PLIC_gpio1_bit7_or_gpio2_bit21_IRQHandler +#define gpio1_bit8_or_gpio2_bit22_plic_22_IRQHandler PLIC_gpio1_bit8_or_gpio2_bit22_IRQHandler +#define gpio1_bit9_or_gpio2_bit23_plic_23_IRQHandler PLIC_gpio1_bit9_or_gpio2_bit23_IRQHandler +#define gpio1_bit10_or_gpio2_bit24_plic_24_IRQHandler PLIC_gpio1_bit10_or_gpio2_bit24_IRQHandler +#define gpio1_bit11_or_gpio2_bit25_plic_25_IRQHandler PLIC_gpio1_bit11_or_gpio2_bit25_IRQHandler +#define gpio1_bit12_or_gpio2_bit26_plic_26_IRQHandler PLIC_gpio1_bit12_or_gpio2_bit26_IRQHandler +#define gpio1_bit13_or_gpio2_bit27_plic_27_IRQHandler PLIC_gpio1_bit13_or_gpio2_bit27_IRQHandler + +#define gpio1_bit14_or_gpio2_bit28_plic_28_IRQHandler PLIC_gpio1_bit14_or_gpio2_bit28_IRQHandler +#define gpio1_bit15_or_gpio2_bit29_plic_29_IRQHandler PLIC_gpio1_bit15_or_gpio2_bit29_IRQHandler +#define gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler PLIC_gpio1_bit16_or_gpio2_bit30_IRQHandler +#define gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler PLIC_gpio1_bit17_or_gpio2_bit31_IRQHandler + +#define gpio1_bit18_plic_32_IRQHandler PLIC_gpio1_bit18_IRQHandler +#define gpio1_bit19_plic_33_IRQHandler PLIC_gpio1_bit19_IRQHandler +#define gpio1_bit20_plic_34_IRQHandler PLIC_gpio1_bit20_IRQHandler +#define gpio1_bit21_plic_35_IRQHandler PLIC_gpio1_bit21_IRQHandler +#define gpio1_bit22_plic_36_IRQHandler PLIC_gpio1_bit22_IRQHandler +#define gpio1_bit23_plic_37_IRQHandler PLIC_gpio1_bit23_IRQHandler + +#define gpio0_non_direct_plic_IRQHandler PLIC_gpio0_non_direct_IRQHandler +#define gpio1_non_direct_plic_IRQHandler PLIC_gpio1_non_direct_IRQHandler +#define gpio2_non_direct_plic_IRQHandler PLIC_gpio2_non_direct_IRQHandler + +#define spi0_plic_IRQHandler PLIC_spi0_IRQHandler +#define spi1_plic_IRQHandler PLIC_spi1_IRQHandler +#define external_can0_plic_IRQHandler PLIC_external_can0_IRQHandler +#define can1_IRQHandler PLIC_can1_IRQHandler +#define External_i2c0_main_plic_IRQHandler PLIC_External_i2c0_main_IRQHandler +#define External_i2c0_alert_plic_IRQHandler PLIC_External_i2c0_alert_IRQHandler +#define i2c0_sus_plic_IRQHandler PLIC_i2c0_sus_IRQHandler +#define i2c1_main_plic_IRQHandler PLIC_i2c1_main_IRQHandler +#define i2c1_alert_plic_IRQHandler PLIC_i2c1_alert_IRQHandler +#define i2c1_sus_plic_IRQHandler PLIC_i2c1_sus_IRQHandler +#define mac0_int_plic_IRQHandler PLIC_mac0_int_IRQHandler +#define mac0_queue1_plic_IRQHandler PLIC_mac0_queue1_IRQHandler +#define mac0_queue2_plic_IRQHandler PLIC_mac0_queue2_IRQHandler +#define mac0_queue3_plic_IRQHandler PLIC_mac0_queue3_IRQHandler +#define mac0_emac_plic_IRQHandler PLIC_mac0_emac_IRQHandler +#define mac0_mmsl_plic_IRQHandler PLIC_mac0_mmsl_IRQHandler +#define mac1_int_plic_IRQHandler PLIC_mac1_int_IRQHandler +#define mac1_queue1_plic_IRQHandler PLIC_mac1_queue1_IRQHandler +#define mac1_queue2_plic_IRQHandler PLIC_mac1_queue2_IRQHandler +#define mac1_queue3_plic_IRQHandler PLIC_mac1_queue3_IRQHandler +#define mac1_emac_plic_IRQHandler PLIC_mac1_emac_IRQHandler +#define mac1_mmsl_plic_IRQHandler PLIC_mac1_mmsl_IRQHandler +#define ddrc_train_plic_IRQHandler PLIC_ddrc_train_IRQHandler +#define scb_interrupt_plic_IRQHandler PLIC_scb_interrupt_IRQHandler +#define ecc_error_plic_IRQHandler PLIC_ecc_error_IRQHandler +#define ecc_correct_plic_IRQHandler PLIC_ecc_correct_IRQHandler +#define rtc_wakeup_plic_IRQHandler PLIC_rtc_wakeup_IRQHandler +#define rtc_match_plic_IRQHandler PLIC_rtc_match_IRQHandler +#define timer1_plic_IRQHandler PLIC_timer1_IRQHandler +#define timer2_plic_IRQHandler PLIC_timer2_IRQHandler +#define envm_plic_IRQHandler PLIC_envm_IRQHandler +#define qspi_plic_IRQHandler PLIC_qspi_IRQHandler +#define usb_dma_plic_IRQHandler PLIC_usb_dma_IRQHandler +#define usb_mc_plic_IRQHandler PLIC_usb_mc_IRQHandler +#define mmc_main_plic_IRQHandler PLIC_mmc_main_IRQHandler +#define mmc_wakeup_plic_IRQHandler PLIC_mmc_wakeup_IRQHandler +#define mmuart0_plic_77_IRQHandler PLIC_mmuart0_IRQHandler +#define mmuart1_plic_IRQHandler PLIC_mmuart1_IRQHandler +#define mmuart2_plic_IRQHandler PLIC_mmuart2_IRQHandler +#define mmuart3_plic_IRQHandler PLIC_mmuart3_IRQHandler +#define mmuart4_plic_IRQHandler PLIC_mmuart4_IRQHandler +#define g5c_devrst_plic_IRQHandler PLIC_devrst_IRQHandler +#define g5c_message_plic_IRQHandler PLIC_g5c_message_IRQHandler +#define usoc_vc_interrupt_plic_IRQHandler PLIC_usoc_vc_interrupt_IRQHandler +#define usoc_smb_interrupt_plic_IRQHandler PLIC_usoc_smb_interrupt_IRQHandler +#define e51_0_Maintence_plic_IRQHandler PLIC_E51_Maintence_IRQHandler + +#define wdog0_mvrp_plic_IRQHandler PLIC_wdog0_mvrp_IRQHandler +#define wdog1_mvrp_plic_IRQHandler PLIC_wdog1_mvrp_IRQHandler +#define wdog2_mvrp_plic_IRQHandler PLIC_wdog2_mvrp_IRQHandler +#define wdog3_mvrp_plic_IRQHandler PLIC_wdog3_mvrp_IRQHandler +#define wdog4_mvrp_plic_IRQHandler PLIC_wdog4_mvrp_IRQHandler +#define wdog0_tout_plic_IRQHandler PLIC_wdog0_tout_IRQHandler +#define wdog1_tout_plic_IRQHandler PLIC_wdog1_tout_IRQHandler +#define wdog2_tout_plic_IRQHandler PLIC_wdog2_tout_IRQHandler +#define wdog3_tout_plic_IRQHandler PLIC_wdog3_tout_IRQHandler +#define wdog4_tout_plic_IRQHandler PLIC_wdog4_tout_IRQHandler +#define g5c_mss_spi_plic_IRQHandler PLIC_g5c_mss_spi_IRQHandler +#define volt_temp_alarm_plic_IRQHandler PLIC_volt_temp_alarm_IRQHandler + +#define athena_complete_plic_IRQHandler PLIC_athena_complete_IRQHandler +#define athena_alarm_plic_IRQHandler PLIC_athena_alarm_IRQHandler +#define athena_bus_error_plic_IRQHandler PLIC_athena_bus_error_IRQHandler +#define usoc_axic_us_plic_IRQHandler PLIC_usoc_axic_us_IRQHandler +#define usoc_axic_ds_plic_IRQHandler PLIC_usoc_axic_ds_IRQHandler + +#define reserved_104_plic_IRQHandler PLIC_reserved_104_IRQHandler + +#define fabric_f2h_0_plic_IRQHandler PLIC_f2m_0_IRQHandler +#define fabric_f2h_1_plic_IRQHandler PLIC_f2m_1_IRQHandler +#define fabric_f2h_2_plic_IRQHandler PLIC_f2m_2_IRQHandler +#define fabric_f2h_3_plic_IRQHandler PLIC_f2m_3_IRQHandler +#define fabric_f2h_4_plic_IRQHandler PLIC_f2m_4_IRQHandler +#define fabric_f2h_5_plic_IRQHandler PLIC_f2m_5_IRQHandler +#define fabric_f2h_6_plic_IRQHandler PLIC_f2m_6_IRQHandler +#define fabric_f2h_7_plic_IRQHandler PLIC_f2m_7_IRQHandler +#define fabric_f2h_8_plic_IRQHandler PLIC_f2m_8_IRQHandler +#define fabric_f2h_9_plic_IRQHandler PLIC_f2m_9_IRQHandler + +#define fabric_f2h_10_plic_IRQHandler PLIC_f2m_10_IRQHandler +#define fabric_f2h_11_plic_IRQHandler PLIC_f2m_11_IRQHandler +#define fabric_f2h_12_plic_IRQHandler PLIC_f2m_12_IRQHandler +#define fabric_f2h_13_plic_IRQHandler PLIC_f2m_13_IRQHandler +#define fabric_f2h_14_plic_IRQHandler PLIC_f2m_14_IRQHandler +#define fabric_f2h_15_plic_IRQHandler PLIC_f2m_15_IRQHandler +#define fabric_f2h_16_plic_IRQHandler PLIC_f2m_16_IRQHandler +#define fabric_f2h_17_plic_IRQHandler PLIC_f2m_17_IRQHandler +#define fabric_f2h_18_plic_IRQHandler PLIC_f2m_18_IRQHandler +#define fabric_f2h_19_plic_IRQHandler PLIC_f2m_19_IRQHandler + +#define fabric_f2h_20_plic_IRQHandler PLIC_f2m_20_IRQHandler +#define fabric_f2h_21_plic_IRQHandler PLIC_f2m_21_IRQHandler +#define fabric_f2h_22_plic_IRQHandler PLIC_f2m_22_IRQHandler +#define fabric_f2h_23_plic_IRQHandler PLIC_f2m_23_IRQHandler +#define fabric_f2h_24_plic_IRQHandler PLIC_f2m_24_IRQHandler +#define fabric_f2h_25_plic_IRQHandler PLIC_f2m_25_IRQHandler +#define fabric_f2h_26_plic_IRQHandler PLIC_f2m_26_IRQHandler +#define fabric_f2h_27_plic_IRQHandler PLIC_f2m_27_IRQHandler +#define fabric_f2h_28_plic_IRQHandler PLIC_f2m_28_IRQHandler +#define fabric_f2h_29_plic_IRQHandler PLIC_f2m_29_IRQHandler + +#define fabric_f2h_30_plic_IRQHandler PLIC_f2m_30_IRQHandler +#define fabric_f2h_31_plic_IRQHandler PLIC_f2m_31_IRQHandler + +#define fabric_f2h_32_plic_IRQHandler PLIC_f2m_32_IRQHandler +#define fabric_f2h_33_plic_IRQHandler PLIC_f2m_33_IRQHandler +#define fabric_f2h_34_plic_IRQHandler PLIC_f2m_34_IRQHandler +#define fabric_f2h_35_plic_IRQHandler PLIC_f2m_35_IRQHandler +#define fabric_f2h_36_plic_IRQHandler PLIC_f2m_36_IRQHandler +#define fabric_f2h_37_plic_IRQHandler PLIC_f2m_37_IRQHandler +#define fabric_f2h_38_plic_IRQHandler PLIC_f2m_38_IRQHandler +#define fabric_f2h_39_plic_IRQHandler PLIC_f2m_39_IRQHandler +#define fabric_f2h_40_plic_IRQHandler PLIC_f2m_40_IRQHandler +#define fabric_f2h_41_plic_IRQHandler PLIC_f2m_41_IRQHandler + +#define fabric_f2h_42_plic_IRQHandler PLIC_f2m_42_IRQHandler +#define fabric_f2h_43_plic_IRQHandler PLIC_f2m_43_IRQHandler +#define fabric_f2h_44_plic_IRQHandler PLIC_f2m_44_IRQHandler +#define fabric_f2h_45_plic_IRQHandler PLIC_f2m_45_IRQHandler +#define fabric_f2h_46_plic_IRQHandler PLIC_f2m_46_IRQHandler +#define fabric_f2h_47_plic_IRQHandler PLIC_f2m_47_IRQHandler +#define fabric_f2h_48_plic_IRQHandler PLIC_f2m_48_IRQHandler +#define fabric_f2h_49_plic_IRQHandler PLIC_f2m_49_IRQHandler +#define fabric_f2h_50_plic_IRQHandler PLIC_f2m_50_IRQHandler +#define fabric_f2h_51_plic_IRQHandler PLIC_f2m_51_IRQHandler + +#define fabric_f2h_52_plic_IRQHandler PLIC_f2m_52_IRQHandler +#define fabric_f2h_53_plic_IRQHandler PLIC_f2m_53_IRQHandler +#define fabric_f2h_54_plic_IRQHandler PLIC_f2m_54_IRQHandler +#define fabric_f2h_55_plic_IRQHandler PLIC_f2m_55_IRQHandler +#define fabric_f2h_56_plic_IRQHandler PLIC_f2m_56_IRQHandler +#define fabric_f2h_57_plic_IRQHandler PLIC_f2m_57_IRQHandler +#define fabric_f2h_58_plic_IRQHandler PLIC_f2m_58_IRQHandler +#define fabric_f2h_59_plic_IRQHandler PLIC_f2m_59_IRQHandler +#define fabric_f2h_60_plic_IRQHandler PLIC_f2m_60_IRQHandler +#define fabric_f2h_61_plic_IRQHandler PLIC_f2m_61_IRQHandler + +#define fabric_f2h_62_plic_IRQHandler PLIC_f2m_62_IRQHandler +#define fabric_f2h_63_plic_IRQHandler PLIC_f2m_63_IRQHandler + +#define bus_error_unit_hart_0_plic_IRQHandler PLIC_E51_bus_error_unit_hart_0_IRQHandler +#define bus_error_unit_hart_1_plic_IRQHandler PLIC_U54_1_bus_error_unit_IRQHandler +#define bus_error_unit_hart_2_plic_IRQHandler PLIC_U54_2_bus_error_unit_IRQHandler +#define bus_error_unit_hart_3_plic_IRQHandler PLIC_U54_3_bus_error_unit_IRQHandler +#define bus_error_unit_hart_4_plic_IRQHandler PLIC_U54_4_bus_error_unit_IRQHandler + +#define INVALID_IRQn PLIC_INVALID_INT_OFFSET +#define L2_METADATA_CORR_IRQn PLIC_L2_METADATA_CORR_INT_OFFSET +#define L2_METADAT_UNCORR_IRQn PLIC_L2_METADAT_UNCORR_INT_OFFSET +#define L2_DATA_CORR_IRQn PLIC_L2_DATA_CORR_INT_OFFSET +#define L2_DATA_UNCORR_IRQn PLIC_L2_DATA_UNCORR_INT_OFFSET +#define DMA_CH0_DONE_IRQn PLIC_DMA_CH0_DONE_INT_OFFSET +#define DMA_CH0_ERR_IRQn PLIC_DMA_CH0_ERR_INT_OFFSET +#define DMA_CH1_DONE_IRQn PLIC_DMA_CH1_DONE_INT_OFFSET +#define DMA_CH1_ERR_IRQn PLIC_DMA_CH1_ERR_INT_OFFSET +#define DMA_CH2_DONE_IRQn PLIC_DMA_CH2_DONE_INT_OFFSET +#define DMA_CH2_ERR_IRQn PLIC_DMA_CH2_ERR_INT_OFFSET +#define DMA_CH3_DONE_IRQn PLIC_DMA_CH3_DONE_INT_OFFSET +#define DMA_CH3_ERR_IRQn PLIC_DMA_CH3_ERR_INT_OFFSET + +#define GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 PLIC_GPIO0_BIT0_or_GPIO2_BIT0_INT_OFFSET +#define GPIO0_BIT1_or_GPIO2_BIT1_PLIC_1 PLIC_GPIO0_BIT1_or_GPIO2_BIT1_INT_OFFSET +#define GPIO0_BIT2_or_GPIO2_BIT2_PLIC_2 PLIC_GPIO0_BIT2_or_GPIO2_BIT2_INT_OFFSET +#define GPIO0_BIT3_or_GPIO2_BIT3_PLIC_3 PLIC_GPIO0_BIT3_or_GPIO2_BIT3_INT_OFFSET +#define GPIO0_BIT4_or_GPIO2_BIT4_PLIC_4 PLIC_GPIO0_BIT4_or_GPIO2_BIT4_INT_OFFSET +#define GPIO0_BIT5_or_GPIO2_BIT5_PLIC_5 PLIC_GPIO0_BIT5_or_GPIO2_BIT5_INT_OFFSET +#define GPIO0_BIT6_or_GPIO2_BIT6_PLIC_6 PLIC_GPIO0_BIT6_or_GPIO2_BIT6_INT_OFFSET +#define GPIO0_BIT7_or_GPIO2_BIT7_PLIC_7 PLIC_GPIO0_BIT7_or_GPIO2_BIT7_INT_OFFSET +#define GPIO0_BIT8_or_GPIO2_BIT8_PLIC_8 PLIC_GPIO0_BIT8_or_GPIO2_BIT8_INT_OFFSET +#define GPIO0_BIT9_or_GPIO2_BIT9_PLIC_9 PLIC_GPIO0_BIT9_or_GPIO2_BIT9_INT_OFFSET +#define GPIO0_BIT10_or_GPIO2_BIT10_PLIC_10 PLIC_GPIO0_BIT10_or_GPIO2_BIT10_INT_OFFSET +#define GPIO0_BIT11_or_GPIO2_BIT11_PLIC_11 PLIC_GPIO0_BIT11_or_GPIO2_BIT11_INT_OFFSET +#define GPIO0_BIT12_or_GPIO2_BIT12_PLIC_12 PLIC_GPIO0_BIT12_or_GPIO2_BIT12_INT_OFFSET + +#define GPIO0_BIT13_or_GPIO2_BIT13_PLIC_13 PLIC_GPIO0_BIT13_or_GPIO2_BIT13_INT_OFFSET +#define GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14 PLIC_GPIO1_BIT0_or_GPIO2_BIT14_INT_OFFSET +#define GPIO1_BIT1_or_GPIO2_BIT15_PLIC_15 PLIC_GPIO1_BIT1_or_GPIO2_BIT15_INT_OFFSET +#define GPIO1_BIT2_or_GPIO2_BIT16_PLIC_16 PLIC_GPIO1_BIT2_or_GPIO2_BIT16_INT_OFFSET +#define GPIO1_BIT3_or_GPIO2_BIT17_PLIC_17 PLIC_GPIO1_BIT3_or_GPIO2_BIT17_INT_OFFSET +#define GPIO1_BIT4_or_GPIO2_BIT18_PLIC_18 PLIC_GPIO1_BIT4_or_GPIO2_BIT18_INT_OFFSET +#define GPIO1_BIT5_or_GPIO2_BIT19_PLIC_19 PLIC_GPIO1_BIT5_or_GPIO2_BIT19_INT_OFFSET +#define GPIO1_BIT6_or_GPIO2_BIT20_PLIC_20 PLIC_GPIO1_BIT6_or_GPIO2_BIT20_INT_OFFSET +#define GPIO1_BIT7_or_GPIO2_BIT21_PLIC_21 PLIC_GPIO1_BIT7_or_GPIO2_BIT21_INT_OFFSET +#define GPIO1_BIT8_or_GPIO2_BIT22_PLIC_22 PLIC_GPIO1_BIT8_or_GPIO2_BIT22_INT_OFFSET +#define GPIO1_BIT9_or_GPIO2_BIT23_PLIC_23 PLIC_GPIO1_BIT9_or_GPIO2_BIT23_INT_OFFSET +#define GPIO1_BIT10_or_GPIO2_BIT24_PLIC_24 PLIC_GPIO1_BIT10_or_GPIO2_BIT24_INT_OFFSET +#define GPIO1_BIT11_or_GPIO2_BIT25_PLIC_25 PLIC_GPIO1_BIT11_or_GPIO2_BIT25_INT_OFFSET +#define GPIO1_BIT12_or_GPIO2_BIT26_PLIC_26 PLIC_GPIO1_BIT12_or_GPIO2_BIT26_INT_OFFSET +#define GPIO1_BIT13_or_GPIO2_BIT27_PLIC_27 PLIC_GPIO1_BIT13_or_GPIO2_BIT27_INT_OFFSET + +#define GPIO1_BIT14_or_GPIO2_BIT28_PLIC_28 PLIC_GPIO1_BIT14_or_GPIO2_BIT28_INT_OFFSET +#define GPIO1_BIT15_or_GPIO2_BIT29_PLIC_29 PLIC_GPIO1_BIT15_or_GPIO2_BIT29_INT_OFFSET +#define GPIO1_BIT16_or_GPIO2_BIT30_PLIC_30 PLIC_GPIO1_BIT16_or_GPIO2_BIT30_INT_OFFSET +#define GPIO1_BIT17_or_GPIO2_BIT31_PLIC_31 PLIC_GPIO1_BIT17_or_GPIO2_BIT31_INT_OFFSET + +#define GPIO1_BIT18_PLIC_32 PLIC_GPIO1_BIT18_INT_OFFSET +#define GPIO1_BIT19_PLIC_33 PLIC_GPIO1_BIT19_INT_OFFSET +#define GPIO1_BIT20_PLIC_34 PLIC_GPIO1_BIT20_INT_OFFSET +#define GPIO1_BIT21_PLIC_35 PLIC_GPIO1_BIT21_INT_OFFSET +#define GPIO1_BIT22_PLIC_36 PLIC_GPIO1_BIT22_INT_OFFSET +#define GPIO1_BIT23_PLIC_37 PLIC_GPIO1_BIT23_INT_OFFSET + +#define GPIO0_NON_DIRECT_PLIC PLIC_GPIO0_NON_DIRECT_INT_OFFSET +#define GPIO1_NON_DIRECT_PLIC PLIC_GPIO1_NON_DIRECT_INT_OFFSET +#define GPIO2_NON_DIRECT_PLIC PLIC_GPIO2_NON_DIRECT_INT_OFFSET + +#define SPI0_PLIC PLIC_SPI0_INT_OFFSET +#define SPI1_PLIC PLIC_SPI1_INT_OFFSET +#define CAN0_PLIC PLIC_CAN0_INT_OFFSET +#define CAN1_PLIC PLIC_CAN1_INT_OFFSET +#define I2C0_MAIN_PLIC PLIC_I2C0_MAIN_INT_OFFSET +#define I2C0_ALERT_PLIC PLIC_I2C0_ALERT_INT_OFFSET +#define I2C0_SUS_PLIC PLIC_I2C0_SUS_INT_OFFSET +#define I2C1_MAIN_PLIC PLIC_I2C1_MAIN_INT_OFFSET +#define I2C1_ALERT_PLIC PLIC_I2C1_ALERT_INT_OFFSET +#define I2C1_SUS_PLIC PLIC_I2C1_SUS_INT_OFFSET +#define MAC0_INT_PLIC PLIC_MAC0_INT_INT_OFFSET +#define MAC0_QUEUE1_PLIC PLIC_MAC0_QUEUE1_INT_OFFSET +#define MAC0_QUEUE2_PLIC PLIC_MAC0_QUEUE2_INT_OFFSET +#define MAC0_QUEUE3_PLIC PLIC_MAC0_QUEUE3_INT_OFFSET +#define MAC0_EMAC_PLIC PLIC_MAC0_EMAC_INT_OFFSET +#define MAC0_MMSL_PLIC PLIC_MAC0_MMSL_INT_OFFSET +#define MAC1_INT_PLIC PLIC_MAC1_INT_INT_OFFSET +#define MAC1_QUEUE1_PLIC PLIC_MAC1_QUEUE1_INT_OFFSET +#define MAC1_QUEUE2_PLIC PLIC_MAC1_QUEUE2_INT_OFFSET +#define MAC1_QUEUE3_PLIC PLIC_MAC1_QUEUE3_INT_OFFSET +#define MAC1_EMAC_PLIC PLIC_MAC1_EMAC_INT_OFFSET +#define MAC1_MMSL_PLIC PLIC_MAC1_MMSL_INT_OFFSET +#define DDRC_TRAIN_PLIC PLIC_DDRC_TRAIN_INT_OFFSET +#define SCB_INTERRUPT_PLIC PLIC_SCB_INTERRUPT_INT_OFFSET +#define ECC_ERROR_PLIC PLIC_ECC_ERROR_INT_OFFSET +#define ECC_CORRECT_PLIC PLIC_ECC_CORRECT_INT_OFFSET +#define RTC_WAKEUP_PLIC PLIC_RTC_WAKEUP_INT_OFFSET +#define RTC_MATCH_PLIC PLIC_RTC_MATCH_INT_OFFSET +#define TIMER1_PLIC PLIC_TIMER1_INT_OFFSET +#define TIMER2_PLIC PLIC_TIMER2_INT_OFFSET +#define ENVM_PLIC PLIC_ENVM_INT_OFFSET +#define QSPI_PLIC PLIC_QSPI_INT_OFFSET +#define USB_DMA_PLIC PLIC_USB_DMA_INT_OFFSET +#define USB_MC_PLIC PLIC_USB_MC_INT_OFFSET +#define MMC_main_PLIC PLIC_MMC_main_INT_OFFSET +#define MMC_wakeup_PLIC PLIC_MMC_wakeup_INT_OFFSET +#define MMUART0_PLIC_77 PLIC_MMUART0_INT_OFFSET +#define MMUART1_PLIC PLIC_MMUART1_INT_OFFSET +#define MMUART2_PLIC PLIC_MMUART2_INT_OFFSET +#define MMUART3_PLIC PLIC_MMUART3_INT_OFFSET +#define MMUART4_PLIC PLIC_MMUART4_INT_OFFSET + +#define G5C_DEVRST_PLIC G5C_DEVRST_INT_OFFSET +#define g5c_MESSAGE_PLIC g5c_MESSAGE_INT_OFFSET +#define USOC_VC_INTERRUPT_PLIC USOC_VC_INTERRUPT_INT_OFFSET +#define USOC_SMB_INTERRUPT_PLIC USOC_SMB_INTERRUPT_INT_OFFSET + +#define E51_0_MAINTENACE_PLIC E51_0_MAINTENACE_INT_OFFSET + +#define WDOG0_MRVP_PLIC PLIC_WDOG0_MRVP_INT_OFFSET +#define WDOG1_MRVP_PLIC PLIC_WDOG1_MRVP_INT_OFFSET +#define WDOG2_MRVP_PLIC PLIC_WDOG2_MRVP_INT_OFFSET +#define WDOG3_MRVP_PLIC PLIC_WDOG3_MRVP_INT_OFFSET +#define WDOG4_MRVP_PLIC PLIC_WDOG4_MRVP_INT_OFFSET +#define WDOG0_TOUT_PLIC PLIC_WDOG0_TOUT_INT_OFFSET +#define WDOG1_TOUT_PLIC PLIC_WDOG1_TOUT_INT_OFFSET +#define WDOG2_TOUT_PLIC PLIC_WDOG2_TOUT_INT_OFFSET +#define WDOG3_TOUT_PLIC PLIC_WDOG3_TOUT_INT_OFFSET +#define WDOG4_TOUT_PLIC PLIC_WDOG4_TOUT_INT_OFFSET +#define G5C_MSS_SPI_PLIC G5C_MSS_SPI_INT_OFFSET +#define VOLT_TEMP_ALARM_PLIC VOLT_TEMP_ALARM_INT_OFFSET +#define ATHENA_COMPLETE_PLIC ATHENA_COMPLETE_INT_OFFSET +#define ATHENA_ALARM_PLIC ATHENA_ALARM_INT_OFFSET +#define ATHENA_BUS_ERROR_PLIC ATHENA_BUS_ERROR_INT_OFFSET +#define USOC_AXIC_US_PLIC USOC_AXIC_US_INT_OFFSET +#define USOC_AXIC_DS_PLIC USOC_AXIC_DS_INT_OFFSET + +#define FABRIC_F2H_0_PLIC PLIC_F2M_0_INT_OFFSET +#define FABRIC_F2H_1_PLIC PLIC_F2M_1_INT_OFFSET +#define FABRIC_F2H_2_PLIC PLIC_F2M_2_INT_OFFSET +#define FABRIC_F2H_3_PLIC PLIC_F2M_3_INT_OFFSET +#define FABRIC_F2H_4_PLIC PLIC_F2M_4_INT_OFFSET +#define FABRIC_F2H_5_PLIC PLIC_F2M_5_INT_OFFSET +#define FABRIC_F2H_6_PLIC PLIC_F2M_6_INT_OFFSET +#define FABRIC_F2H_7_PLIC PLIC_F2M_7_INT_OFFSET +#define FABRIC_F2H_8_PLIC PLIC_F2M_8_INT_OFFSET +#define FABRIC_F2H_9_PLIC PLIC_F2M_9_INT_OFFSET + +#define FABRIC_F2H_10_PLIC PLIC_F2M_10_INT_OFFSET +#define FABRIC_F2H_11_PLIC PLIC_F2M_11_INT_OFFSET +#define FABRIC_F2H_12_PLIC PLIC_F2M_12_INT_OFFSET +#define FABRIC_F2H_13_PLIC PLIC_F2M_13_INT_OFFSET +#define FABRIC_F2H_14_PLIC PLIC_F2M_14_INT_OFFSET +#define FABRIC_F2H_15_PLIC PLIC_F2M_15_INT_OFFSET +#define FABRIC_F2H_16_PLIC PLIC_F2M_16_INT_OFFSET +#define FABRIC_F2H_17_PLIC PLIC_F2M_17_INT_OFFSET +#define FABRIC_F2H_18_PLIC PLIC_F2M_18_INT_OFFSET +#define FABRIC_F2H_19_PLIC PLIC_F2M_19_INT_OFFSET + +#define FABRIC_F2H_20_PLIC PLIC_F2M_20_INT_OFFSET +#define FABRIC_F2H_21_PLIC PLIC_F2M_21_INT_OFFSET +#define FABRIC_F2H_22_PLIC PLIC_F2M_22_INT_OFFSET +#define FABRIC_F2H_23_PLIC PLIC_F2M_23_INT_OFFSET +#define FABRIC_F2H_24_PLIC PLIC_F2M_24_INT_OFFSET +#define FABRIC_F2H_25_PLIC PLIC_F2M_25_INT_OFFSET +#define FABRIC_F2H_26_PLIC PLIC_F2M_26_INT_OFFSET +#define FABRIC_F2H_27_PLIC PLIC_F2M_27_INT_OFFSET +#define FABRIC_F2H_28_PLIC PLIC_F2M_28_INT_OFFSET +#define FABRIC_F2H_29_PLIC PLIC_F2M_29_INT_OFFSET + +#define FABRIC_F2H_30_PLIC PLIC_F2M_30_INT_OFFSET +#define FABRIC_F2H_31_PLIC PLIC_F2M_31_INT_OFFSET + +#define FABRIC_F2H_32_PLIC PLIC_F2M_32_INT_OFFSET +#define FABRIC_F2H_33_PLIC PLIC_F2M_33_INT_OFFSET +#define FABRIC_F2H_34_PLIC PLIC_F2M_34_INT_OFFSET +#define FABRIC_F2H_35_PLIC PLIC_F2M_35_INT_OFFSET +#define FABRIC_F2H_36_PLIC PLIC_F2M_36_INT_OFFSET +#define FABRIC_F2H_37_PLIC PLIC_F2M_37_INT_OFFSET +#define FABRIC_F2H_38_PLIC PLIC_F2M_38_INT_OFFSET +#define FABRIC_F2H_39_PLIC PLIC_F2M_39_INT_OFFSET +#define FABRIC_F2H_40_PLIC PLIC_F2M_40_INT_OFFSET +#define FABRIC_F2H_41_PLIC PLIC_F2M_41_INT_OFFSET + +#define FABRIC_F2H_42_PLIC PLIC_F2M_42_INT_OFFSET +#define FABRIC_F2H_43_PLIC PLIC_F2M_43_INT_OFFSET +#define FABRIC_F2H_44_PLIC PLIC_F2M_44_INT_OFFSET +#define FABRIC_F2H_45_PLIC PLIC_F2M_45_INT_OFFSET +#define FABRIC_F2H_46_PLIC PLIC_F2M_46_INT_OFFSET +#define FABRIC_F2H_47_PLIC PLIC_F2M_47_INT_OFFSET +#define FABRIC_F2H_48_PLIC PLIC_F2M_48_INT_OFFSET +#define FABRIC_F2H_49_PLIC PLIC_F2M_49_INT_OFFSET +#define FABRIC_F2H_50_PLIC PLIC_F2M_50_INT_OFFSET +#define FABRIC_F2H_51_PLIC PLIC_F2M_51_INT_OFFSET + +#define FABRIC_F2H_52_PLIC PLIC_F2M_52_INT_OFFSET +#define FABRIC_F2H_53_PLIC PLIC_F2M_53_INT_OFFSET +#define FABRIC_F2H_54_PLIC PLIC_F2M_54_INT_OFFSET +#define FABRIC_F2H_55_PLIC PLIC_F2M_55_INT_OFFSET +#define FABRIC_F2H_56_PLIC PLIC_F2M_56_INT_OFFSET +#define FABRIC_F2H_57_PLIC PLIC_F2M_57_INT_OFFSET +#define FABRIC_F2H_58_PLIC PLIC_F2M_58_INT_OFFSET +#define FABRIC_F2H_59_PLIC PLIC_F2M_59_INT_OFFSET +#define FABRIC_F2H_60_PLIC PLIC_F2M_60_INT_OFFSET +#define FABRIC_F2H_61_PLIC PLIC_F2M_61_INT_OFFSET + +#define FABRIC_F2H_62_PLIC PLIC_F2M_62_INT_OFFSET +#define FABRIC_F2H_63_PLIC PLIC_F2M_63_INT_OFFSET + +#define BUS_ERROR_UNIT_HART_0 PLIC_E51_BUS_ERROR_UNIT_OFFSET +#define BUS_ERROR_UNIT_HART_1 PLIC_U54_1_BUS_ERROR_UNIT_OFFSET +#define BUS_ERROR_UNIT_HART_2 PLIC_U54_2_BUS_ERROR_UNIT_OFFSET +#define BUS_ERROR_UNIT_HART_3 PLIC_U54_3_BUS_ERROR_UNIT_OFFSET +#define BUS_ERROR_UNIT_HART_4 PLIC_U54_4_BUS_ERROR_UNIT_OFFSET + +#define Software_h0_IRQHandler E51_software_IRQHandler +#define Software_h1_IRQHandler U54_1_software_IRQHandler +#define Software_h2_IRQHandler U54_2_software_IRQHandler +#define Software_h3_IRQHandler U54_3_software_IRQHandler +#define Software_h4_IRQHandler U54_4_software_IRQHandler + + +#define SysTick_Handler_h0_IRQHandler E51_sysTick_IRQHandler +#define SysTick_Handler_h1_IRQHandler U54_1_sysTick_IRQHandler +#define SysTick_Handler_h2_IRQHandler U54_2_sysTick_IRQHandler +#define SysTick_Handler_h3_IRQHandler U54_3_sysTick_IRQHandler +#define SysTick_Handler_h4_IRQHandler U54_4_sysTick_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif /* MSS_HART_INTS_H */ + diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.c index 1e5b55e7..1a10d00b 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -20,8 +20,6 @@ #include #include "mpfs_hal/mss_hal.h" -#ifndef SIFIVE_HIFIVE_UNLEASHED - static uint64_t pmp_get_napot_base_and_range(uint64_t reg, uint64_t *range); uint8_t num_pmp_lut[10U] = {16U,16U,8U,4U,8U,8U,4U,4U,8U,2U}; @@ -324,4 +322,3 @@ static uint64_t pmp_get_napot_base_and_range(uint64_t reg, uint64_t *range) return (base << 2U); } -#endif diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.h index 6b4e1abb..85bbf167 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mpu.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -26,8 +26,6 @@ extern "C" { #endif -#ifndef SIFIVE_HIFIVE_UNLEASHED - /***************************************************************************//** */ @@ -198,7 +196,6 @@ static inline MPU_FailStatus_TypeDef MSS_MPU_get_failstatus(mss_mpu_mport_t mast return (MSS_MPU(master_port)->STATUS); } -#endif /* ! SIFIVE_HIFIVE_UNLEASHED */ #ifdef __cplusplus } diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c index 2226d7bf..27a04ac3 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -7,7 +7,7 @@ * */ -/*************************************************************************** +/******************************************************************************* * * @file mss_mtrap.c * @author Microchip-FPGA Embedded Systems Solutions @@ -20,8 +20,6 @@ extern "C" { #endif - - void handle_local_interrupt(uint8_t interrupt_no); void handle_m_soft_interrupt(void); void handle_m_timer_interrupt(void); @@ -32,7 +30,6 @@ void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc); - void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc) { (void)regs; @@ -86,598 +83,537 @@ void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc) /*------------------------------------------------------------------------------ * RISC-V interrupt handler for external interrupts. */ -#ifndef SIFIVE_HIFIVE_UNLEASHED uint8_t (*ext_irq_handler_table[PLIC_NUM_SOURCES])(void) = { - Invalid_IRQHandler, - l2_metadata_corr_IRQHandler, - l2_metadata_uncorr_IRQHandler, - l2_data_corr_IRQHandler, - l2_data_uncorr_IRQHandler, - dma_ch0_DONE_IRQHandler, - dma_ch0_ERR_IRQHandler, - dma_ch1_DONE_IRQHandler, - dma_ch1_ERR_IRQHandler, - dma_ch2_DONE_IRQHandler, - dma_ch2_ERR_IRQHandler, - dma_ch3_DONE_IRQHandler, - dma_ch3_ERR_IRQHandler, - gpio0_bit0_or_gpio2_bit13_plic_0_IRQHandler, - gpio0_bit1_or_gpio2_bit13_plic_1_IRQHandler, - gpio0_bit2_or_gpio2_bit13_plic_2_IRQHandler, - gpio0_bit3_or_gpio2_bit13_plic_3_IRQHandler, - gpio0_bit4_or_gpio2_bit13_plic_4_IRQHandler, - gpio0_bit5_or_gpio2_bit13_plic_5_IRQHandler, - gpio0_bit6_or_gpio2_bit13_plic_6_IRQHandler, - gpio0_bit7_or_gpio2_bit13_plic_7_IRQHandler, - gpio0_bit8_or_gpio2_bit13_plic_8_IRQHandler, - gpio0_bit9_or_gpio2_bit13_plic_9_IRQHandler, - gpio0_bit10_or_gpio2_bit13_plic_10_IRQHandler, - gpio0_bit11_or_gpio2_bit13_plic_11_IRQHandler, - gpio0_bit12_or_gpio2_bit13_plic_12_IRQHandler, - - gpio0_bit13_or_gpio2_bit13_plic_13_IRQHandler, - gpio1_bit0_or_gpio2_bit14_plic_14_IRQHandler, - gpio1_bit1_or_gpio2_bit15_plic_15_IRQHandler, - gpio1_bit2_or_gpio2_bit16_plic_16_IRQHandler, - gpio1_bit3_or_gpio2_bit17_plic_17_IRQHandler, - gpio1_bit4_or_gpio2_bit18_plic_18_IRQHandler, - gpio1_bit5_or_gpio2_bit19_plic_19_IRQHandler, - gpio1_bit6_or_gpio2_bit20_plic_20_IRQHandler, - gpio1_bit7_or_gpio2_bit21_plic_21_IRQHandler, - gpio1_bit8_or_gpio2_bit22_plic_22_IRQHandler, - gpio1_bit9_or_gpio2_bit23_plic_23_IRQHandler, - gpio1_bit10_or_gpio2_bit24_plic_24_IRQHandler, - gpio1_bit11_or_gpio2_bit25_plic_25_IRQHandler, - gpio1_bit12_or_gpio2_bit26_plic_26_IRQHandler, - gpio1_bit13_or_gpio2_bit27_plic_27_IRQHandler, - - gpio1_bit14_or_gpio2_bit28_plic_28_IRQHandler, - gpio1_bit15_or_gpio2_bit29_plic_29_IRQHandler, - gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler, - gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler, - - gpio1_bit18_plic_32_IRQHandler, - gpio1_bit19_plic_33_IRQHandler, - gpio1_bit20_plic_34_IRQHandler, - gpio1_bit21_plic_35_IRQHandler, - gpio1_bit22_plic_36_IRQHandler, - gpio1_bit23_plic_37_IRQHandler, - - gpio0_non_direct_plic_IRQHandler, - gpio1_non_direct_plic_IRQHandler, - gpio2_non_direct_plic_IRQHandler, - - spi0_plic_IRQHandler, - spi1_plic_IRQHandler, - external_can0_plic_IRQHandler, - can1_IRQHandler, - External_i2c0_main_plic_IRQHandler, - External_i2c0_alert_plic_IRQHandler, - i2c0_sus_plic_IRQHandler, - i2c1_main_plic_IRQHandler, - i2c1_alert_plic_IRQHandler, - i2c1_sus_plic_IRQHandler, - mac0_int_plic_IRQHandler, - mac0_queue1_plic_IRQHandler, - mac0_queue2_plic_IRQHandler, - mac0_queue3_plic_IRQHandler, - mac0_emac_plic_IRQHandler, - mac0_mmsl_plic_IRQHandler, - mac1_int_plic_IRQHandler, - mac1_queue1_plic_IRQHandler, - mac1_queue2_plic_IRQHandler, - mac1_queue3_plic_IRQHandler, - mac1_emac_plic_IRQHandler, - mac1_mmsl_plic_IRQHandler, - ddrc_train_plic_IRQHandler, - scb_interrupt_plic_IRQHandler, - ecc_error_plic_IRQHandler, - ecc_correct_plic_IRQHandler, - rtc_wakeup_plic_IRQHandler, - rtc_match_plic_IRQHandler, - timer1_plic_IRQHandler, - timer2_plic_IRQHandler, - envm_plic_IRQHandler, - qspi_plic_IRQHandler, - usb_dma_plic_IRQHandler, - usb_mc_plic_IRQHandler, - mmc_main_plic_IRQHandler, - mmc_wakeup_plic_IRQHandler, - mmuart0_plic_77_IRQHandler, - mmuart1_plic_IRQHandler, - mmuart2_plic_IRQHandler, - mmuart3_plic_IRQHandler, - mmuart4_plic_IRQHandler, - - g5c_devrst_plic_IRQHandler, - g5c_message_plic_IRQHandler, - usoc_vc_interrupt_plic_IRQHandler, - usoc_smb_interrupt_plic_IRQHandler, - e51_0_Maintence_plic_IRQHandler, - - wdog0_mvrp_plic_IRQHandler, - wdog1_mvrp_plic_IRQHandler, /*100 contains multiple interrupts- */ - wdog2_mvrp_plic_IRQHandler, - wdog3_mvrp_plic_IRQHandler, - wdog4_mvrp_plic_IRQHandler, - wdog0_tout_plic_IRQHandler, - wdog1_tout_plic_IRQHandler, - wdog2_tout_plic_IRQHandler, - wdog3_tout_plic_IRQHandler, - wdog4_tout_plic_IRQHandler, - - g5c_mss_spi_plic_IRQHandler, - volt_temp_alarm_plic_IRQHandler, - athena_complete_plic_IRQHandler, - athena_alarm_plic_IRQHandler, - athena_bus_error_plic_IRQHandler, - usoc_axic_us_plic_IRQHandler, - usoc_axic_ds_plic_IRQHandler, - - reserved_104_plic_IRQHandler, - - fabric_f2h_0_plic_IRQHandler, - fabric_f2h_1_plic_IRQHandler, - fabric_f2h_2_plic_IRQHandler, - fabric_f2h_3_plic_IRQHandler, - fabric_f2h_4_plic_IRQHandler, - fabric_f2h_5_plic_IRQHandler, - fabric_f2h_6_plic_IRQHandler, - fabric_f2h_7_plic_IRQHandler, - fabric_f2h_8_plic_IRQHandler, - fabric_f2h_9_plic_IRQHandler, - - fabric_f2h_10_plic_IRQHandler, - fabric_f2h_11_plic_IRQHandler, - fabric_f2h_12_plic_IRQHandler, - fabric_f2h_13_plic_IRQHandler, - fabric_f2h_14_plic_IRQHandler, - fabric_f2h_15_plic_IRQHandler, - fabric_f2h_16_plic_IRQHandler, - fabric_f2h_17_plic_IRQHandler, - fabric_f2h_18_plic_IRQHandler, - fabric_f2h_19_plic_IRQHandler, - - fabric_f2h_20_plic_IRQHandler, - fabric_f2h_21_plic_IRQHandler, - fabric_f2h_22_plic_IRQHandler, - fabric_f2h_23_plic_IRQHandler, - fabric_f2h_24_plic_IRQHandler, - fabric_f2h_25_plic_IRQHandler, - fabric_f2h_26_plic_IRQHandler, - fabric_f2h_27_plic_IRQHandler, - fabric_f2h_28_plic_IRQHandler, - fabric_f2h_29_plic_IRQHandler, - - fabric_f2h_30_plic_IRQHandler, - fabric_f2h_31_plic_IRQHandler, - - fabric_f2h_32_plic_IRQHandler, - fabric_f2h_33_plic_IRQHandler, - fabric_f2h_34_plic_IRQHandler, - fabric_f2h_35_plic_IRQHandler, - fabric_f2h_36_plic_IRQHandler, - fabric_f2h_37_plic_IRQHandler, - fabric_f2h_38_plic_IRQHandler, - fabric_f2h_39_plic_IRQHandler, - fabric_f2h_40_plic_IRQHandler, - fabric_f2h_41_plic_IRQHandler, - - fabric_f2h_42_plic_IRQHandler, - fabric_f2h_43_plic_IRQHandler, - fabric_f2h_44_plic_IRQHandler, - fabric_f2h_45_plic_IRQHandler, - fabric_f2h_46_plic_IRQHandler, - fabric_f2h_47_plic_IRQHandler, - fabric_f2h_48_plic_IRQHandler, - fabric_f2h_49_plic_IRQHandler, - fabric_f2h_50_plic_IRQHandler, - fabric_f2h_51_plic_IRQHandler, - - fabric_f2h_52_plic_IRQHandler, - fabric_f2h_53_plic_IRQHandler, - fabric_f2h_54_plic_IRQHandler, - fabric_f2h_55_plic_IRQHandler, - fabric_f2h_56_plic_IRQHandler, - fabric_f2h_57_plic_IRQHandler, - fabric_f2h_58_plic_IRQHandler, - fabric_f2h_59_plic_IRQHandler, - fabric_f2h_60_plic_IRQHandler, - fabric_f2h_61_plic_IRQHandler, - - fabric_f2h_62_plic_IRQHandler, - fabric_f2h_63_plic_IRQHandler, - - bus_error_unit_hart_0_plic_IRQHandler, - bus_error_unit_hart_1_plic_IRQHandler, - bus_error_unit_hart_2_plic_IRQHandler, - bus_error_unit_hart_3_plic_IRQHandler, - bus_error_unit_hart_4_plic_IRQHandler + PLIC_Invalid_IRQHandler, + PLIC_l2_metadata_corr_IRQHandler, + PLIC_l2_metadata_uncorr_IRQHandler, + PLIC_l2_data_corr_IRQHandler, + PLIC_l2_data_uncorr_IRQHandler, + PLIC_dma_ch0_DONE_IRQHandler, + PLIC_dma_ch0_ERR_IRQHandler, + PLIC_dma_ch1_DONE_IRQHandler, + PLIC_dma_ch1_ERR_IRQHandler, + PLIC_dma_ch2_DONE_IRQHandler, + PLIC_dma_ch2_ERR_IRQHandler, + PLIC_dma_ch3_DONE_IRQHandler, + PLIC_dma_ch3_ERR_IRQHandler, + PLIC_gpio0_bit0_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit1_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit2_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit3_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit4_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit5_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit6_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit7_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit8_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit9_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit10_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit11_or_gpio2_bit13_IRQHandler, + PLIC_gpio0_bit12_or_gpio2_bit13_IRQHandler, + + PLIC_gpio0_bit13_or_gpio2_bit13_IRQHandler, + PLIC_gpio1_bit0_or_gpio2_bit14_IRQHandler, + PLIC_gpio1_bit1_or_gpio2_bit15_IRQHandler, + PLIC_gpio1_bit2_or_gpio2_bit16_IRQHandler, + PLIC_gpio1_bit3_or_gpio2_bit17_IRQHandler, + PLIC_gpio1_bit4_or_gpio2_bit18_IRQHandler, + PLIC_gpio1_bit5_or_gpio2_bit19_IRQHandler, + PLIC_gpio1_bit6_or_gpio2_bit20_IRQHandler, + PLIC_gpio1_bit7_or_gpio2_bit21_IRQHandler, + PLIC_gpio1_bit8_or_gpio2_bit22_IRQHandler, + PLIC_gpio1_bit9_or_gpio2_bit23_IRQHandler, + PLIC_gpio1_bit10_or_gpio2_bit24_IRQHandler, + PLIC_gpio1_bit11_or_gpio2_bit25_IRQHandler, + PLIC_gpio1_bit12_or_gpio2_bit26_IRQHandler, + PLIC_gpio1_bit13_or_gpio2_bit27_IRQHandler, + + PLIC_gpio1_bit14_or_gpio2_bit28_IRQHandler, + PLIC_gpio1_bit15_or_gpio2_bit29_IRQHandler, + PLIC_gpio1_bit16_or_gpio2_bit30_IRQHandler, + PLIC_gpio1_bit17_or_gpio2_bit31_IRQHandler, + + PLIC_gpio1_bit18_IRQHandler, + PLIC_gpio1_bit19_IRQHandler, + PLIC_gpio1_bit20_IRQHandler, + PLIC_gpio1_bit21_IRQHandler, + PLIC_gpio1_bit22_IRQHandler, + PLIC_gpio1_bit23_IRQHandler, + + PLIC_gpio0_non_direct_IRQHandler, + PLIC_gpio1_non_direct_IRQHandler, + PLIC_gpio2_non_direct_IRQHandler, + + PLIC_spi0_IRQHandler, + PLIC_spi1_IRQHandler, + PLIC_external_can0_IRQHandler, + PLIC_can1_IRQHandler, + PLIC_External_i2c0_main_IRQHandler, + PLIC_External_i2c0_alert_IRQHandler, + PLIC_i2c0_sus_IRQHandler, + PLIC_i2c1_main_IRQHandler, + PLIC_i2c1_alert_IRQHandler, + PLIC_i2c1_sus_IRQHandler, + PLIC_mac0_int_IRQHandler, + PLIC_mac0_queue1_IRQHandler, + PLIC_mac0_queue2_IRQHandler, + PLIC_mac0_queue3_IRQHandler, + PLIC_mac0_emac_IRQHandler, + PLIC_mac0_mmsl_IRQHandler, + PLIC_mac1_int_IRQHandler, + PLIC_mac1_queue1_IRQHandler, + PLIC_mac1_queue2_IRQHandler, + PLIC_mac1_queue3_IRQHandler, + PLIC_mac1_emac_IRQHandler, + PLIC_mac1_mmsl_IRQHandler, + PLIC_ddrc_train_IRQHandler, + PLIC_scb_interrupt_IRQHandler, + PLIC_ecc_error_IRQHandler, + PLIC_ecc_correct_IRQHandler, + PLIC_rtc_wakeup_IRQHandler, + PLIC_rtc_match_IRQHandler, + PLIC_timer1_IRQHandler, + PLIC_timer2_IRQHandler, + PLIC_envm_IRQHandler, + PLIC_qspi_IRQHandler, + PLIC_usb_dma_IRQHandler, + PLIC_usb_mc_IRQHandler, + PLIC_mmc_main_IRQHandler, + PLIC_mmc_wakeup_IRQHandler, + PLIC_mmuart0_IRQHandler, + PLIC_mmuart1_IRQHandler, + PLIC_mmuart2_IRQHandler, + PLIC_mmuart3_IRQHandler, + PLIC_mmuart4_IRQHandler, + + PLIC_devrst_IRQHandler, + PLIC_g5c_message_IRQHandler, + PLIC_usoc_vc_interrupt_IRQHandler, + PLIC_usoc_smb_interrupt_IRQHandler, + PLIC_E51_Maintence_IRQHandler, + + PLIC_wdog0_mvrp_IRQHandler, + PLIC_wdog1_mvrp_IRQHandler, /*100 contains multiple interrupts- */ + PLIC_wdog2_mvrp_IRQHandler, + PLIC_wdog3_mvrp_IRQHandler, + PLIC_wdog4_mvrp_IRQHandler, + PLIC_wdog0_tout_IRQHandler, + PLIC_wdog1_tout_IRQHandler, + PLIC_wdog2_tout_IRQHandler, + PLIC_wdog3_tout_IRQHandler, + PLIC_wdog4_tout_IRQHandler, + + PLIC_g5c_mss_spi_IRQHandler, + PLIC_volt_temp_alarm_IRQHandler, + PLIC_athena_complete_IRQHandler, + PLIC_athena_alarm_IRQHandler, + PLIC_athena_bus_error_IRQHandler, + PLIC_usoc_axic_us_IRQHandler, + PLIC_usoc_axic_ds_IRQHandler, + + PLIC_reserved_104_IRQHandler, + + PLIC_f2m_0_IRQHandler, + PLIC_f2m_1_IRQHandler, + PLIC_f2m_2_IRQHandler, + PLIC_f2m_3_IRQHandler, + PLIC_f2m_4_IRQHandler, + PLIC_f2m_5_IRQHandler, + PLIC_f2m_6_IRQHandler, + PLIC_f2m_7_IRQHandler, + PLIC_f2m_8_IRQHandler, + PLIC_f2m_9_IRQHandler, + + PLIC_f2m_10_IRQHandler, + PLIC_f2m_11_IRQHandler, + PLIC_f2m_12_IRQHandler, + PLIC_f2m_13_IRQHandler, + PLIC_f2m_14_IRQHandler, + PLIC_f2m_15_IRQHandler, + PLIC_f2m_16_IRQHandler, + PLIC_f2m_17_IRQHandler, + PLIC_f2m_18_IRQHandler, + PLIC_f2m_19_IRQHandler, + + PLIC_f2m_20_IRQHandler, + PLIC_f2m_21_IRQHandler, + PLIC_f2m_22_IRQHandler, + PLIC_f2m_23_IRQHandler, + PLIC_f2m_24_IRQHandler, + PLIC_f2m_25_IRQHandler, + PLIC_f2m_26_IRQHandler, + PLIC_f2m_27_IRQHandler, + PLIC_f2m_28_IRQHandler, + PLIC_f2m_29_IRQHandler, + + PLIC_f2m_30_IRQHandler, + PLIC_f2m_31_IRQHandler, + + PLIC_f2m_32_IRQHandler, + PLIC_f2m_33_IRQHandler, + PLIC_f2m_34_IRQHandler, + PLIC_f2m_35_IRQHandler, + PLIC_f2m_36_IRQHandler, + PLIC_f2m_37_IRQHandler, + PLIC_f2m_38_IRQHandler, + PLIC_f2m_39_IRQHandler, + PLIC_f2m_40_IRQHandler, + PLIC_f2m_41_IRQHandler, + + PLIC_f2m_42_IRQHandler, + PLIC_f2m_43_IRQHandler, + PLIC_f2m_44_IRQHandler, + PLIC_f2m_45_IRQHandler, + PLIC_f2m_46_IRQHandler, + PLIC_f2m_47_IRQHandler, + PLIC_f2m_48_IRQHandler, + PLIC_f2m_49_IRQHandler, + PLIC_f2m_50_IRQHandler, + PLIC_f2m_51_IRQHandler, + + PLIC_f2m_52_IRQHandler, + PLIC_f2m_53_IRQHandler, + PLIC_f2m_54_IRQHandler, + PLIC_f2m_55_IRQHandler, + PLIC_f2m_56_IRQHandler, + PLIC_f2m_57_IRQHandler, + PLIC_f2m_58_IRQHandler, + PLIC_f2m_59_IRQHandler, + PLIC_f2m_60_IRQHandler, + PLIC_f2m_61_IRQHandler, + + PLIC_f2m_62_IRQHandler, + PLIC_f2m_63_IRQHandler, + + PLIC_E51_bus_error_unit_IRQHandler, + PLIC_U54_1_bus_error_unit_IRQHandler, + PLIC_U54_2_bus_error_unit_IRQHandler, + PLIC_U54_3_bus_error_unit_IRQHandler, + PLIC_U54_4_bus_error_unit_IRQHandler }; #define E51_LOCAL_NUM_SOURCES 48U -void (*local_irq_handler_e51_table[E51_LOCAL_NUM_SOURCES])(void) = +void (*E51_local_irq_handler_table[E51_LOCAL_NUM_SOURCES])(void) = { - maintenance_e51_local_IRQHandler_0, /* reference multiple interrupts */ - usoc_smb_interrupt_e51_local_IRQHandler_1, - usoc_vc_interrupt_e51_local_IRQHandler_2, - g5c_message_e51_local_IRQHandler_3, - g5c_devrst_e51_local_IRQHandler_4, - wdog4_tout_e51_local_IRQHandler_5, - wdog3_tout_e51_local_IRQHandler_6, - wdog2_tout_e51_local_IRQHandler_7, - wdog1_tout_e51_local_IRQHandler_8, - wdog0_tout_e51_local_IRQHandler_9, - wdog0_mvrp_e51_local_IRQHandler_10, - mmuart0_e51_local_IRQHandler_11, - envm_e51_local_IRQHandler_12, - ecc_correct_e51_local_IRQHandler_13, - ecc_error_e51_local_IRQHandler_14, - scb_interrupt_e51_local_IRQHandler_15, - fabric_f2h_32_e51_local_IRQHandler_16, - fabric_f2h_33_e51_local_IRQHandler_17, - fabric_f2h_34_e51_local_IRQHandler_18, - fabric_f2h_35_e51_local_IRQHandler_19, - fabric_f2h_36_e51_local_IRQHandler_20, - fabric_f2h_37_e51_local_IRQHandler_21, - fabric_f2h_38_e51_local_IRQHandler_22, - fabric_f2h_39_e51_local_IRQHandler_23, - fabric_f2h_40_e51_local_IRQHandler_24, - fabric_f2h_41_e51_local_IRQHandler_25, - - fabric_f2h_42_e51_local_IRQHandler_26, - fabric_f2h_43_e51_local_IRQHandler_27, - fabric_f2h_44_e51_local_IRQHandler_28, - fabric_f2h_45_e51_local_IRQHandler_29, - fabric_f2h_46_e51_local_IRQHandler_30, - fabric_f2h_47_e51_local_IRQHandler_31, - fabric_f2h_48_e51_local_IRQHandler_32, - fabric_f2h_49_e51_local_IRQHandler_33, - fabric_f2h_50_e51_local_IRQHandler_34, - fabric_f2h_51_e51_local_IRQHandler_35, - - fabric_f2h_52_e51_local_IRQHandler_36, - fabric_f2h_53_e51_local_IRQHandler_37, - fabric_f2h_54_e51_local_IRQHandler_38, - fabric_f2h_55_e51_local_IRQHandler_39, - fabric_f2h_56_e51_local_IRQHandler_40, - fabric_f2h_57_e51_local_IRQHandler_41, - fabric_f2h_58_e51_local_IRQHandler_42, - fabric_f2h_59_e51_local_IRQHandler_43, - fabric_f2h_60_e51_local_IRQHandler_44, - fabric_f2h_61_e51_local_IRQHandler_45, - - fabric_f2h_62_e51_local_IRQHandler_46, - fabric_f2h_63_e51_local_IRQHandler_47 + E51_maintenance_local_IRQHandler, /* reference multiple interrupts */ + E51_usoc_smb_local_IRQHandler, + E51_usoc_vc_local_IRQHandler, + E51_g5c_message_local_IRQHandler, + E51_g5c_devrst_local_IRQHandler, + E51_wdog4_tout_local_IRQHandler, + E51_wdog3_tout_local_IRQHandler, + E51_wdog2_tout_local_IRQHandler, + E51_wdog1_tout_local_IRQHandler, + E51_wdog0_tout_local_IRQHandler, + E51_wdog0_mvrp_local_IRQHandler, + E51_mmuart0_local_IRQHandler, + E51_envm_local_IRQHandler, + E51_ecc_correct_local_IRQHandler, + E51_ecc_error_local_IRQHandler, + E51_scb_local_IRQHandler, + E51_f2m_32_local_IRQHandler, + E51_f2m_33_local_IRQHandler, + E51_f2m_34_local_IRQHandler, + E51_f2m_35_local_IRQHandler, + E51_f2m_36_local_IRQHandler, + E51_f2m_37_local_IRQHandler, + E51_f2m_38_local_IRQHandler, + E51_f2m_39_local_IRQHandler, + E51_f2m_40_local_IRQHandler, + E51_f2m_41_local_IRQHandler, + + E51_f2m_42_local_IRQHandler, + E51_f2m_43_local_IRQHandler, + E51_f2m_44_local_IRQHandler, + E51_f2m_45_local_IRQHandler, + E51_f2m_46_local_IRQHandler, + E51_f2m_47_local_IRQHandler, + E51_f2m_48_local_IRQHandler, + E51_f2m_49_local_IRQHandler, + E51_f2m_50_local_IRQHandler, + E51_f2m_51_local_IRQHandler, + + E51_f2m_52_local_IRQHandler, + E51_f2m_53_local_IRQHandler, + E51_f2m_54_local_IRQHandler, + E51_f2m_55_local_IRQHandler, + E51_f2m_56_local_IRQHandler, + E51_f2m_57_local_IRQHandler, + E51_f2m_58_local_IRQHandler, + E51_f2m_59_local_IRQHandler, + E51_f2m_60_local_IRQHandler, + E51_f2m_61_local_IRQHandler, + + E51_f2m_62_local_IRQHandler, + E51_f2m_63_local_IRQHandler }; typedef void (*local_int_p_t)(void); /* U54 1 */ -local_int_p_t local_irq_handler_u54_1_table[E51_LOCAL_NUM_SOURCES] = +local_int_p_t local_irq_handler_1_table[E51_LOCAL_NUM_SOURCES] = { /*reference multiple interrupts*/ - spare_u54_local_IRQHandler_0, - spare_u54_local_IRQHandler_1, - spare_u54_local_IRQHandler_2, + U54_spare_0_local_IRQHandler, + U54_spare_1_local_IRQHandler, + U54_spare_2_local_IRQHandler, /*parse hart ID to discover which mac is the source*/ - mac_mmsl_u54_1_local_IRQHandler_3, - mac_emac_u54_1_local_IRQHandler_4, - mac_queue3_u54_1_local_IRQHandler_5, - mac_queue2_u54_1_local_IRQHandler_6, - mac_queue1_u54_1_local_IRQHandler_7, - mac_int_u54_1_local_IRQHandler_8, + U54_1_mac0_mmsl_local_IRQHandler, + U54_1_mac0_emac_local_IRQHandler, + U54_1_mac0_queue3_local_IRQHandler, + U54_1_mac0_queue2_local_IRQHandler, + U54_1_mac0_queue1_local_IRQHandler, + U54_1_mac0_int_local_IRQHandler, /*parse hart ID to discover which wdog is the source*/ - wdog_tout_u54_h1_local_IRQHandler_9, - mvrp_u54_local_IRQHandler_10, - mmuart_u54_h1_local_IRQHandler_11, - - spare_u54_local_IRQHandler_12, - spare_u54_local_IRQHandler_13, - spare_u54_local_IRQHandler_14, - spare_u54_local_IRQHandler_15, - - fabric_f2h_0_u54_local_IRQHandler_16, - fabric_f2h_1_u54_local_IRQHandler_17, - fabric_f2h_2_u54_local_IRQHandler_18, - fabric_f2h_3_u54_local_IRQHandler_19, - fabric_f2h_4_u54_local_IRQHandler_20, - fabric_f2h_5_u54_local_IRQHandler_21, - fabric_f2h_6_u54_local_IRQHandler_22, - fabric_f2h_7_u54_local_IRQHandler_23, - fabric_f2h_8_u54_local_IRQHandler_24, - fabric_f2h_9_u54_local_IRQHandler_25, - - fabric_f2h_10_u54_local_IRQHandler_26, - fabric_f2h_11_u54_local_IRQHandler_27, - fabric_f2h_12_u54_local_IRQHandler_28, - fabric_f2h_13_u54_local_IRQHandler_29, - fabric_f2h_14_u54_local_IRQHandler_30, - fabric_f2h_15_u54_local_IRQHandler_31, - fabric_f2h_16_u54_local_IRQHandler_32, - fabric_f2h_17_u54_local_IRQHandler_33, - fabric_f2h_18_u54_local_IRQHandler_34, - fabric_f2h_19_u54_local_IRQHandler_35, - - fabric_f2h_20_u54_local_IRQHandler_36, - fabric_f2h_21_u54_local_IRQHandler_37, - fabric_f2h_22_u54_local_IRQHandler_38, - fabric_f2h_23_u54_local_IRQHandler_39, - fabric_f2h_24_u54_local_IRQHandler_40, - fabric_f2h_25_u54_local_IRQHandler_41, - fabric_f2h_26_u54_local_IRQHandler_42, - fabric_f2h_27_u54_local_IRQHandler_43, - fabric_f2h_28_u54_local_IRQHandler_44, - fabric_f2h_29_u54_local_IRQHandler_45, - - fabric_f2h_30_u54_local_IRQHandler_46, - fabric_f2h_31_u54_local_IRQHandler_47 + U54_1_wdog_tout_local_IRQHandler, + U54_1_wdog_mvrp_local_IRQHandler, + U54_1_mmuart1_local_IRQHandler, + + U54_spare_3_local_IRQHandler, + U54_spare_4_local_IRQHandler, + U54_spare_5_local_IRQHandler, + U54_spare_6_local_IRQHandler, + + U54_f2m_0_local_IRQHandler, + U54_f2m_1_local_IRQHandler, + U54_f2m_2_local_IRQHandler, + U54_f2m_3_local_IRQHandler, + U54_f2m_4_local_IRQHandler, + U54_f2m_5_local_IRQHandler, + U54_f2m_6_local_IRQHandler, + U54_f2m_7_local_IRQHandler, + U54_f2m_8_local_IRQHandler, + U54_f2m_9_local_IRQHandler, + + U54_f2m_10_local_IRQHandler, + U54_f2m_11_local_IRQHandler, + U54_f2m_12_local_IRQHandler, + U54_f2m_13_local_IRQHandler, + U54_f2m_14_local_IRQHandler, + U54_f2m_15_local_IRQHandler, + U54_f2m_16_local_IRQHandler, + U54_f2m_17_local_IRQHandler, + U54_f2m_18_local_IRQHandler, + U54_f2m_19_local_IRQHandler, + + U54_f2m_20_local_IRQHandler, + U54_f2m_21_local_IRQHandler, + U54_f2m_22_local_IRQHandler, + U54_f2m_23_local_IRQHandler, + U54_f2m_24_local_IRQHandler, + U54_f2m_25_local_IRQHandler, + U54_f2m_26_local_IRQHandler, + U54_f2m_27_local_IRQHandler, + U54_f2m_28_local_IRQHandler, + U54_f2m_29_local_IRQHandler, + + U54_f2m_30_local_IRQHandler, + U54_f2m_31_local_IRQHandler }; /* U54 2 */ -local_int_p_t local_irq_handler_u54_2_table[E51_LOCAL_NUM_SOURCES] = +local_int_p_t local_irq_handler_2_table[E51_LOCAL_NUM_SOURCES] = { /*reference multiple interrupts*/ - spare_u54_local_IRQHandler_0, - spare_u54_local_IRQHandler_1, - spare_u54_local_IRQHandler_2, + U54_spare_0_local_IRQHandler, + U54_spare_1_local_IRQHandler, + U54_spare_2_local_IRQHandler, /*parse hart ID to discover which mac is the source*/ - mac_mmsl_u54_2_local_IRQHandler_3, - mac_emac_u54_2_local_IRQHandler_4, - mac_queue3_u54_2_local_IRQHandler_5, - mac_queue2_u54_2_local_IRQHandler_6, - mac_queue1_u54_2_local_IRQHandler_7, - mac_int_u54_2_local_IRQHandler_8, + U54_2_mac0_mmsl_local_IRQHandler, + U54_2_mac0_emac_local_IRQHandler, + U54_2_mac0_queue3_local_IRQHandler, + U54_2_mac0_queue2_local_IRQHandler, + U54_2_mac0_queue1_local_IRQHandler, + U54_2_mac0_int_local_IRQHandler, /*parse hart ID to discover which wdog is the source*/ - wdog_tout_u54_h2_local_IRQHandler_9, - mvrp_u54_local_IRQHandler_10, - mmuart_u54_h2_local_IRQHandler_11, - - spare_u54_local_IRQHandler_12, - spare_u54_local_IRQHandler_13, - spare_u54_local_IRQHandler_14, - spare_u54_local_IRQHandler_15, - - fabric_f2h_0_u54_local_IRQHandler_16, - fabric_f2h_1_u54_local_IRQHandler_17, - fabric_f2h_2_u54_local_IRQHandler_18, - fabric_f2h_3_u54_local_IRQHandler_19, - fabric_f2h_4_u54_local_IRQHandler_20, - fabric_f2h_5_u54_local_IRQHandler_21, - fabric_f2h_6_u54_local_IRQHandler_22, - fabric_f2h_7_u54_local_IRQHandler_23, - fabric_f2h_8_u54_local_IRQHandler_24, - fabric_f2h_9_u54_local_IRQHandler_25, - - fabric_f2h_10_u54_local_IRQHandler_26, - fabric_f2h_11_u54_local_IRQHandler_27, - fabric_f2h_12_u54_local_IRQHandler_28, - fabric_f2h_13_u54_local_IRQHandler_29, - fabric_f2h_14_u54_local_IRQHandler_30, - fabric_f2h_15_u54_local_IRQHandler_31, - fabric_f2h_16_u54_local_IRQHandler_32, - fabric_f2h_17_u54_local_IRQHandler_33, - fabric_f2h_18_u54_local_IRQHandler_34, - fabric_f2h_19_u54_local_IRQHandler_35, - - fabric_f2h_20_u54_local_IRQHandler_36, - fabric_f2h_21_u54_local_IRQHandler_37, - fabric_f2h_22_u54_local_IRQHandler_38, - fabric_f2h_23_u54_local_IRQHandler_39, - fabric_f2h_24_u54_local_IRQHandler_40, - fabric_f2h_25_u54_local_IRQHandler_41, - fabric_f2h_26_u54_local_IRQHandler_42, - fabric_f2h_27_u54_local_IRQHandler_43, - fabric_f2h_28_u54_local_IRQHandler_44, - fabric_f2h_29_u54_local_IRQHandler_45, - - fabric_f2h_30_u54_local_IRQHandler_46, - fabric_f2h_31_u54_local_IRQHandler_47 + U54_2_wdog_tout_local_IRQHandler, + U54_2_wdog_mvrp_local_IRQHandler, + U54_2_mmuart2_local_IRQHandler, + + U54_spare_3_local_IRQHandler, + U54_spare_4_local_IRQHandler, + U54_spare_5_local_IRQHandler, + U54_spare_6_local_IRQHandler, + + U54_f2m_0_local_IRQHandler, + U54_f2m_1_local_IRQHandler, + U54_f2m_2_local_IRQHandler, + U54_f2m_3_local_IRQHandler, + U54_f2m_4_local_IRQHandler, + U54_f2m_5_local_IRQHandler, + U54_f2m_6_local_IRQHandler, + U54_f2m_7_local_IRQHandler, + U54_f2m_8_local_IRQHandler, + U54_f2m_9_local_IRQHandler, + + U54_f2m_10_local_IRQHandler, + U54_f2m_11_local_IRQHandler, + U54_f2m_12_local_IRQHandler, + U54_f2m_13_local_IRQHandler, + U54_f2m_14_local_IRQHandler, + U54_f2m_15_local_IRQHandler, + U54_f2m_16_local_IRQHandler, + U54_f2m_17_local_IRQHandler, + U54_f2m_18_local_IRQHandler, + U54_f2m_19_local_IRQHandler, + + U54_f2m_20_local_IRQHandler, + U54_f2m_21_local_IRQHandler, + U54_f2m_22_local_IRQHandler, + U54_f2m_23_local_IRQHandler, + U54_f2m_24_local_IRQHandler, + U54_f2m_25_local_IRQHandler, + U54_f2m_26_local_IRQHandler, + U54_f2m_27_local_IRQHandler, + U54_f2m_28_local_IRQHandler, + U54_f2m_29_local_IRQHandler, + + U54_f2m_30_local_IRQHandler, + U54_f2m_31_local_IRQHandler }; /* U54 3 */ -local_int_p_t local_irq_handler_u54_3_table[E51_LOCAL_NUM_SOURCES] = +local_int_p_t local_irq_handler_3_table[E51_LOCAL_NUM_SOURCES] = { /*reference multiple interrupts*/ - spare_u54_local_IRQHandler_0, - spare_u54_local_IRQHandler_1, - spare_u54_local_IRQHandler_2, + U54_spare_0_local_IRQHandler, + U54_spare_1_local_IRQHandler, + U54_spare_2_local_IRQHandler, /*parse hart ID to discover which mac is the source*/ - mac_mmsl_u54_3_local_IRQHandler_3, - mac_emac_u54_3_local_IRQHandler_4, - mac_queue3_u54_3_local_IRQHandler_5, - mac_queue2_u54_3_local_IRQHandler_6, - mac_queue1_u54_3_local_IRQHandler_7, - mac_int_u54_3_local_IRQHandler_8, + U54_3_mac1_mmsl_local_IRQHandler, + U54_3_mac1_emac_local_IRQHandler, + U54_3_mac1_queue3_local_IRQHandler, + U54_3_mac1_queue2_local_IRQHandler, + U54_3_mac1_queue1_local_IRQHandler, + U54_3_mac1_int_local_IRQHandler, /*parse hart ID to discover which wdog is the source*/ - wdog_tout_u54_h3_local_IRQHandler_9, - mvrp_u54_local_IRQHandler_10, - mmuart_u54_h3_local_IRQHandler_11, - - spare_u54_local_IRQHandler_12, - spare_u54_local_IRQHandler_13, - spare_u54_local_IRQHandler_14, - spare_u54_local_IRQHandler_15, - - fabric_f2h_0_u54_local_IRQHandler_16, - fabric_f2h_1_u54_local_IRQHandler_17, - fabric_f2h_2_u54_local_IRQHandler_18, - fabric_f2h_3_u54_local_IRQHandler_19, - fabric_f2h_4_u54_local_IRQHandler_20, - fabric_f2h_5_u54_local_IRQHandler_21, - fabric_f2h_6_u54_local_IRQHandler_22, - fabric_f2h_7_u54_local_IRQHandler_23, - fabric_f2h_8_u54_local_IRQHandler_24, - fabric_f2h_9_u54_local_IRQHandler_25, - - fabric_f2h_10_u54_local_IRQHandler_26, - fabric_f2h_11_u54_local_IRQHandler_27, - fabric_f2h_12_u54_local_IRQHandler_28, - fabric_f2h_13_u54_local_IRQHandler_29, - fabric_f2h_14_u54_local_IRQHandler_30, - fabric_f2h_15_u54_local_IRQHandler_31, - fabric_f2h_16_u54_local_IRQHandler_32, - fabric_f2h_17_u54_local_IRQHandler_33, - fabric_f2h_18_u54_local_IRQHandler_34, - fabric_f2h_19_u54_local_IRQHandler_35, - - fabric_f2h_20_u54_local_IRQHandler_36, - fabric_f2h_21_u54_local_IRQHandler_37, - fabric_f2h_22_u54_local_IRQHandler_38, - fabric_f2h_23_u54_local_IRQHandler_39, - fabric_f2h_24_u54_local_IRQHandler_40, - fabric_f2h_25_u54_local_IRQHandler_41, - fabric_f2h_26_u54_local_IRQHandler_42, - fabric_f2h_27_u54_local_IRQHandler_43, - fabric_f2h_28_u54_local_IRQHandler_44, - fabric_f2h_29_u54_local_IRQHandler_45, - - fabric_f2h_30_u54_local_IRQHandler_46, - fabric_f2h_31_u54_local_IRQHandler_47 + U54_3_wdog_tout_local_IRQHandler, + U54_3_wdog_mvrp_local_IRQHandler, + U54_3_mmuart3_local_IRQHandler, + + U54_spare_3_local_IRQHandler, + U54_spare_4_local_IRQHandler, + U54_spare_5_local_IRQHandler, + U54_spare_6_local_IRQHandler, + + U54_f2m_0_local_IRQHandler, + U54_f2m_1_local_IRQHandler, + U54_f2m_2_local_IRQHandler, + U54_f2m_3_local_IRQHandler, + U54_f2m_4_local_IRQHandler, + U54_f2m_5_local_IRQHandler, + U54_f2m_6_local_IRQHandler, + U54_f2m_7_local_IRQHandler, + U54_f2m_8_local_IRQHandler, + U54_f2m_9_local_IRQHandler, + + U54_f2m_10_local_IRQHandler, + U54_f2m_11_local_IRQHandler, + U54_f2m_12_local_IRQHandler, + U54_f2m_13_local_IRQHandler, + U54_f2m_14_local_IRQHandler, + U54_f2m_15_local_IRQHandler, + U54_f2m_16_local_IRQHandler, + U54_f2m_17_local_IRQHandler, + U54_f2m_18_local_IRQHandler, + U54_f2m_19_local_IRQHandler, + + U54_f2m_20_local_IRQHandler, + U54_f2m_21_local_IRQHandler, + U54_f2m_22_local_IRQHandler, + U54_f2m_23_local_IRQHandler, + U54_f2m_24_local_IRQHandler, + U54_f2m_25_local_IRQHandler, + U54_f2m_26_local_IRQHandler, + U54_f2m_27_local_IRQHandler, + U54_f2m_28_local_IRQHandler, + U54_f2m_29_local_IRQHandler, + + U54_f2m_30_local_IRQHandler, + U54_f2m_31_local_IRQHandler }; /* U54 4 */ -local_int_p_t local_irq_handler_u54_4_table[E51_LOCAL_NUM_SOURCES] = +local_int_p_t local_irq_handler_4_table[E51_LOCAL_NUM_SOURCES] = { /*reference multiple interrupts*/ - spare_u54_local_IRQHandler_0, - spare_u54_local_IRQHandler_1, - spare_u54_local_IRQHandler_2, + U54_spare_0_local_IRQHandler, + U54_spare_1_local_IRQHandler, + U54_spare_2_local_IRQHandler, /*parse hart ID to discover which mac is the source*/ - mac_mmsl_u54_4_local_IRQHandler_3, - mac_emac_u54_4_local_IRQHandler_4, - mac_queue3_u54_4_local_IRQHandler_5, - mac_queue2_u54_4_local_IRQHandler_6, - mac_queue1_u54_4_local_IRQHandler_7, - mac_int_u54_4_local_IRQHandler_8, + U54_4_mac1_mmsl_local_IRQHandler, + U54_4_mac1_emac_local_IRQHandler, + U54_4_mac1_queue3_local_IRQHandler, + U54_4_mac1_queue2_local_IRQHandler, + U54_4_mac1_queue1_local_IRQHandler, + U54_4_mac1_int_local_IRQHandler, /*parse hart ID to discover which wdog is the source*/ - wdog_tout_u54_h4_local_IRQHandler_9, - mvrp_u54_local_IRQHandler_10, - mmuart_u54_h4_local_IRQHandler_11, - - spare_u54_local_IRQHandler_12, - spare_u54_local_IRQHandler_13, - spare_u54_local_IRQHandler_14, - spare_u54_local_IRQHandler_15, - - fabric_f2h_0_u54_local_IRQHandler_16, - fabric_f2h_1_u54_local_IRQHandler_17, - fabric_f2h_2_u54_local_IRQHandler_18, - fabric_f2h_3_u54_local_IRQHandler_19, - fabric_f2h_4_u54_local_IRQHandler_20, - fabric_f2h_5_u54_local_IRQHandler_21, - fabric_f2h_6_u54_local_IRQHandler_22, - fabric_f2h_7_u54_local_IRQHandler_23, - fabric_f2h_8_u54_local_IRQHandler_24, - fabric_f2h_9_u54_local_IRQHandler_25, - - fabric_f2h_10_u54_local_IRQHandler_26, - fabric_f2h_11_u54_local_IRQHandler_27, - fabric_f2h_12_u54_local_IRQHandler_28, - fabric_f2h_13_u54_local_IRQHandler_29, - fabric_f2h_14_u54_local_IRQHandler_30, - fabric_f2h_15_u54_local_IRQHandler_31, - fabric_f2h_16_u54_local_IRQHandler_32, - fabric_f2h_17_u54_local_IRQHandler_33, - fabric_f2h_18_u54_local_IRQHandler_34, - fabric_f2h_19_u54_local_IRQHandler_35, - - fabric_f2h_20_u54_local_IRQHandler_36, - fabric_f2h_21_u54_local_IRQHandler_37, - fabric_f2h_22_u54_local_IRQHandler_38, - fabric_f2h_23_u54_local_IRQHandler_39, - fabric_f2h_24_u54_local_IRQHandler_40, - fabric_f2h_25_u54_local_IRQHandler_41, - fabric_f2h_26_u54_local_IRQHandler_42, - fabric_f2h_27_u54_local_IRQHandler_43, - fabric_f2h_28_u54_local_IRQHandler_44, - fabric_f2h_29_u54_local_IRQHandler_45, - - fabric_f2h_30_u54_local_IRQHandler_46, - fabric_f2h_31_u54_local_IRQHandler_47 + U54_4_wdog_tout_local_IRQHandler, + U54_4_wdog_mvrp_local_IRQHandler, + U54_4_mmuart4_local_IRQHandler, + + U54_spare_3_local_IRQHandler, + U54_spare_4_local_IRQHandler, + U54_spare_5_local_IRQHandler, + U54_spare_6_local_IRQHandler, + + U54_f2m_0_local_IRQHandler, + U54_f2m_1_local_IRQHandler, + U54_f2m_2_local_IRQHandler, + U54_f2m_3_local_IRQHandler, + U54_f2m_4_local_IRQHandler, + U54_f2m_5_local_IRQHandler, + U54_f2m_6_local_IRQHandler, + U54_f2m_7_local_IRQHandler, + U54_f2m_8_local_IRQHandler, + U54_f2m_9_local_IRQHandler, + + U54_f2m_10_local_IRQHandler, + U54_f2m_11_local_IRQHandler, + U54_f2m_12_local_IRQHandler, + U54_f2m_13_local_IRQHandler, + U54_f2m_14_local_IRQHandler, + U54_f2m_15_local_IRQHandler, + U54_f2m_16_local_IRQHandler, + U54_f2m_17_local_IRQHandler, + U54_f2m_18_local_IRQHandler, + U54_f2m_19_local_IRQHandler, + + U54_f2m_20_local_IRQHandler, + U54_f2m_21_local_IRQHandler, + U54_f2m_22_local_IRQHandler, + U54_f2m_23_local_IRQHandler, + U54_f2m_24_local_IRQHandler, + U54_f2m_25_local_IRQHandler, + U54_f2m_26_local_IRQHandler, + U54_f2m_27_local_IRQHandler, + U54_f2m_28_local_IRQHandler, + U54_f2m_29_local_IRQHandler, + + U54_f2m_30_local_IRQHandler, + U54_f2m_31_local_IRQHandler }; local_int_p_t *local_int_mux[5] = { - local_irq_handler_e51_table, - local_irq_handler_u54_1_table, - local_irq_handler_u54_2_table, - local_irq_handler_u54_3_table, - local_irq_handler_u54_4_table + E51_local_irq_handler_table, + local_irq_handler_1_table, + local_irq_handler_2_table, + local_irq_handler_3_table, + local_irq_handler_4_table }; -#else -uint8_t (*ext_irq_handler_table[PLIC_NUM_SOURCES])(void) = -{ - Invalid_IRQHandler, - External_1_IRQHandler, - External_2_IRQHandler, - External_3_IRQHandler, - USART0_plic_4_IRQHandler, - External_5_IRQHandler, - External_6_IRQHandler, - External_7_IRQHandler, - External_8_IRQHandler, - External_9_IRQHandler, - External_10_IRQHandler, - External_11_IRQHandler, - External_12_IRQHandler, - External_13_IRQHandler, - External_14_IRQHandler, - External_15_IRQHandler, - External_16_IRQHandler, - External_17_IRQHandler, - External_18_IRQHandler, - External_19_IRQHandler, - External_20_IRQHandler, - External_21_IRQHandler, - External_22_IRQHandler, - dma_ch0_DONE_IRQHandler, - dma_ch0_ERR_IRQHandler, - dma_ch1_DONE_IRQHandler, - dma_ch1_ERR_IRQHandler, - dma_ch2_DONE_IRQHandler, - dma_ch2_ERR_IRQHandler, - dma_ch3_DONE_IRQHandler, - dma_ch3_ERR_IRQHandler, - External_31_IRQHandler, - External_32_IRQHandler, - External_33_IRQHandler, - External_34_IRQHandler, - External_35_IRQHandler, - External_36_IRQHandler, - External_37_IRQHandler, - External_38_IRQHandler, - External_39_IRQHandler, - External_40_IRQHandler, - External_41_IRQHandler, - External_42_IRQHandler, - External_43_IRQHandler, - External_44_IRQHandler, - External_45_IRQHandler, - External_46_IRQHandler, - External_47_IRQHandler, - External_48_IRQHandler, - External_49_IRQHandler, - External_50_IRQHandler, - External_51_IRQHandler, - External_52_IRQHandler, - MAC0_plic_53_IRQHandler - -}; -#endif /*------------------------------------------------------------------------------ * */ @@ -686,17 +622,13 @@ void handle_m_ext_interrupt(void) volatile uint32_t int_num = PLIC_ClaimIRQ(); - if (INVALID_IRQn == int_num) + if (PLIC_INVALID_INT_OFFSET == int_num) { return; } uint8_t disable = EXT_IRQ_KEEP_ENABLED; -#ifndef SIFIVE_HIFIVE_UNLEASHED - disable = ext_irq_handler_table[int_num /* + OFFSET_TO_MSS_GLOBAL_INTS Think this was required in early bitfile */](); -#else disable = ext_irq_handler_table[int_num](); -#endif PLIC_CompleteIRQ(int_num); @@ -713,14 +645,11 @@ void handle_m_ext_interrupt(void) */ void handle_local_interrupt(uint8_t interrupt_no) { -#ifndef SIFIVE_HIFIVE_UNLEASHED /* no local interrupts on unleashed */ uint64_t mhart_id = read_csr(mhartid); uint8_t local_interrupt_no = (uint8_t)(interrupt_no - 16U); local_int_p_t *local_int_table = local_int_mux[mhart_id]; (*local_int_table[local_interrupt_no])(); - -#endif } /*------------------------------------------------------------------------------ @@ -730,32 +659,41 @@ void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc) { volatile uintptr_t mcause = read_csr(mcause); - if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) + if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) >=\ + IRQ_M_LOCAL_MIN)&& ((mcause & MCAUSE_CAUSE) <= IRQ_M_LOCAL_MAX)) { handle_local_interrupt((uint8_t)(mcause & MCAUSE_CAUSE)); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_EXT)) { handle_m_ext_interrupt(); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_SOFT)) { handle_m_soft_interrupt(); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_TIMER)) { handle_m_timer_interrupt(); } + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE)\ + == IRQ_M_BEU )) + { + handle_local_beu_interrupt(); + } else { uint32_t i = 0U; - while(1) + while(1U) { /* wait for watchdog */ - i++; /* added some code as SC debugger hangs if in loop doing nothing */ + i++; if(i == 0x1000U) { - i = mcause; /* so mcause is not optimised out */ + i = (uint32_t)mcause; /* so mcause is not optimised out */ } } switch(mcause) diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.h index 3d68eb12..4d201b6b 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_mtrap.h @@ -45,6 +45,10 @@ extern "C" { #define IPI_FENCE_I 0x02 #define IPI_SFENCE_VMA 0x04 +#define IRQ_M_BEU 0x80 +#define IRQ_M_LOCAL_MIN 16 +#define IRQ_M_LOCAL_MAX 63 + #define MACHINE_STACK_SIZE (RISCV_PGSIZE) /* this is 4k for HLS and 4k for the stack*/ #define MENTRY_HLS_OFFSET (INTEGER_CONTEXT_SIZE + SOFT_FLOAT_CONTEXT_SIZE) #define MENTRY_FRAME_SIZE (MENTRY_HLS_OFFSET + HLS_SIZE) diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.c index 307cd0ee..d22c4ce6 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -56,7 +56,7 @@ const uint32_t PERIPHERAL_SETUP[][4U] = { {MSS_PERIPH_GPIO1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_GPIO1,SUBBLK_CLOCK_CR_GPIO1_MASK}, {MSS_PERIPH_GPIO2,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_GPIO2,SUBBLK_CLOCK_CR_GPIO2_MASK}, {MSS_PERIPH_RTC,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_RTC,SUBBLK_CLOCK_CR_RTC_MASK}, - {MSS_PERIPH_H2FINT,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_H2FINT, SUBBLK_CLOCK_NA_MASK}, + {MSS_PERIPH_M2FINT,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_M2FINT, SUBBLK_CLOCK_NA_MASK}, {MSS_PERIPH_CRYPTO,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_CRYPTO,SUBBLK_CLOCK_CR_ATHENA_MASK}, {MSS_PERIPH_USB,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_USB,SUBBLK_CLOCK_CR_USB_MASK}, {MSS_PERIPH_QSPIXIP,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_QSPIXIP,SUBBLK_CLOCK_CR_QSPI_MASK}, @@ -78,7 +78,7 @@ const uint32_t PERIPHERAL_SETUP[][4U] = { * @param hart The hart ID of origin of request. * @return */ -static inline uint8_t verify_context_enable(uint8_t option, uint32_t periph_context_mask , uint32_t hart) +static inline uint8_t verify_context_enable(uint8_t option, uint32_t periph_context_mask , uint8_t hart) { uint8_t result = 1U; #if ((LIBERO_SETTING_MEM_CONFIGS_ENABLED & PMP_ENABLED_MASK) == PMP_ENABLED_MASK) @@ -146,7 +146,7 @@ __attribute__((weak)) uint8_t mss_config_clk_rst(mss_peripherals peripheral, ui ASSERT(PERIPHERAL_SETUP[peripheral][PERIPHERAL_INDEX_OFFSET] == peripheral); - result = verify_context_enable(PERIPHERAL_SETUP[peripheral][CONTEXT_EN_INDEX_OFFSET], PERIPHERAL_SETUP[peripheral][CONTEXT_MASK_INDEX_OFFSET] , hart); + result = verify_context_enable((uint8_t)PERIPHERAL_SETUP[peripheral][CONTEXT_EN_INDEX_OFFSET], PERIPHERAL_SETUP[peripheral][CONTEXT_MASK_INDEX_OFFSET] , hart); if (result == 0U) { @@ -155,3 +155,37 @@ __attribute__((weak)) uint8_t mss_config_clk_rst(mss_peripherals peripheral, ui return result; } +/***************************************************************************//** + * See mss_peripherals.h for details of how to use this function. + */ +__attribute__((weak)) void mss_enable_fabric(void) +{ + /* Remove soft reset */ + SYSREG->SOFT_RESET_CR &= (uint32_t)~(SOFT_RESET_CR_FPGA_MASK); +} + +/***************************************************************************//** + * See mss_peripherals.h for details of how to use this function. + */ +__attribute__((weak)) void mss_disable_fabric(void) +{ + /* Apply reset */ + SYSREG->SOFT_RESET_CR |= SOFT_RESET_CR_FPGA_MASK; +} + +/***************************************************************************//** + * See mss_peripherals.h for details of how to use this function. + */ +__attribute__((weak)) void mss_set_apb_bus_cr(uint32_t reg_value) +{ + SYSREG->APBBUS_CR = reg_value; +} + +/***************************************************************************//** + * See mss_peripherals.h for details of how to use this function. + */ +__attribute__((weak)) uint32_t mss_get_apb_bus_cr(void) +{ + return (SYSREG->APBBUS_CR); +} + diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.h index 0f6f217c..bf8a696a 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_peripherals.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -76,7 +76,7 @@ typedef enum mss_peripherals_ { MSS_PERIPH_GPIO1 = 20U, MSS_PERIPH_GPIO2 = 21U, MSS_PERIPH_RTC = 22U, - MSS_PERIPH_H2FINT = 23U, + MSS_PERIPH_M2FINT = 23U, MSS_PERIPH_CRYPTO = 24U, MSS_PERIPH_USB = 25U, MSS_PERIPH_QSPIXIP = 26U, @@ -120,6 +120,54 @@ typedef enum mss_peripherals_ { */ uint8_t mss_config_clk_rst(mss_peripherals peripheral, uint8_t hart, PERIPH_RESET_STATE req_state); +/***************************************************************************//** + This function is used to turn on the fabric enable + + Example: + @code + (void)mss_config_clk_rst(MSS_PERIPH_FIC3, (uint8_t)MPFS_HAL_FIRST_HART, PERIPHERAL_ON); + mss_enable_fabric(); + @endcode + */ +void mss_enable_fabric(void); + +/***************************************************************************//** + This function is used to turn on the fabric enable + + Example: + @code + mss_disable_fabric(); + @endcode + */ +void mss_disable_fabric(void); + +/***************************************************************************//** + This function is used to set the apb_bus_cr register value + + @param reg_value value of the register you want to set. + This value is available from the MSS configurator + LIBERO_SETTING_APBBUS_CR + + Example: + @code + mss_set_apb_bus_cr(LIBERO_SETTING_APBBUS_CR); + @endcode + */ +void mss_set_apb_bus_cr(uint32_t reg_value); + +/***************************************************************************//** + This function is used to get the apb_bus_cr register value + + @return Return the apb_bus_cr reg value + + Example: + @code + uint32_t cr_reg; + cr_reg = mss_get_apb_bus_cr(); + @endcode + */ +uint32_t mss_get_apb_bus_cr(void); + #ifdef __cplusplus } diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.c index 15297e97..ea8d2861 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.h index 16c16029..b0083d9d 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_plic.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -40,270 +40,210 @@ extern "C" { /*------------------------------------------------------------------------------ * */ -#ifndef SIFIVE_HIFIVE_UNLEASHED -uint8_t Invalid_IRQHandler(void); -uint8_t l2_metadata_corr_IRQHandler(void); -uint8_t l2_metadata_uncorr_IRQHandler(void); -uint8_t l2_data_corr_IRQHandler(void); -uint8_t l2_data_uncorr_IRQHandler(void); -uint8_t dma_ch0_DONE_IRQHandler(void); -uint8_t dma_ch0_ERR_IRQHandler(void); -uint8_t dma_ch1_DONE_IRQHandler(void); -uint8_t dma_ch1_ERR_IRQHandler(void); -uint8_t dma_ch2_DONE_IRQHandler(void); -uint8_t dma_ch2_ERR_IRQHandler(void); -uint8_t dma_ch3_DONE_IRQHandler(void); -uint8_t dma_ch3_ERR_IRQHandler(void); -uint8_t gpio0_bit0_or_gpio2_bit13_plic_0_IRQHandler(void); -uint8_t gpio0_bit1_or_gpio2_bit13_plic_1_IRQHandler(void); -uint8_t gpio0_bit2_or_gpio2_bit13_plic_2_IRQHandler(void); -uint8_t gpio0_bit3_or_gpio2_bit13_plic_3_IRQHandler(void); -uint8_t gpio0_bit4_or_gpio2_bit13_plic_4_IRQHandler(void); -uint8_t gpio0_bit5_or_gpio2_bit13_plic_5_IRQHandler(void); -uint8_t gpio0_bit6_or_gpio2_bit13_plic_6_IRQHandler(void); -uint8_t gpio0_bit7_or_gpio2_bit13_plic_7_IRQHandler(void); -uint8_t gpio0_bit8_or_gpio2_bit13_plic_8_IRQHandler(void); -uint8_t gpio0_bit9_or_gpio2_bit13_plic_9_IRQHandler(void); -uint8_t gpio0_bit10_or_gpio2_bit13_plic_10_IRQHandler(void); -uint8_t gpio0_bit11_or_gpio2_bit13_plic_11_IRQHandler(void); -uint8_t gpio0_bit12_or_gpio2_bit13_plic_12_IRQHandler(void); - -uint8_t gpio0_bit13_or_gpio2_bit13_plic_13_IRQHandler(void); -uint8_t gpio1_bit0_or_gpio2_bit14_plic_14_IRQHandler(void); -uint8_t gpio1_bit1_or_gpio2_bit15_plic_15_IRQHandler(void); -uint8_t gpio1_bit2_or_gpio2_bit16_plic_16_IRQHandler(void); -uint8_t gpio1_bit3_or_gpio2_bit17_plic_17_IRQHandler(void); -uint8_t gpio1_bit4_or_gpio2_bit18_plic_18_IRQHandler(void); -uint8_t gpio1_bit5_or_gpio2_bit19_plic_19_IRQHandler(void); -uint8_t gpio1_bit6_or_gpio2_bit20_plic_20_IRQHandler(void); -uint8_t gpio1_bit7_or_gpio2_bit21_plic_21_IRQHandler(void); -uint8_t gpio1_bit8_or_gpio2_bit22_plic_22_IRQHandler(void); -uint8_t gpio1_bit9_or_gpio2_bit23_plic_23_IRQHandler(void); -uint8_t gpio1_bit10_or_gpio2_bit24_plic_24_IRQHandler(void); -uint8_t gpio1_bit11_or_gpio2_bit25_plic_25_IRQHandler(void); -uint8_t gpio1_bit12_or_gpio2_bit26_plic_26_IRQHandler(void); -uint8_t gpio1_bit13_or_gpio2_bit27_plic_27_IRQHandler(void); - -uint8_t gpio1_bit14_or_gpio2_bit28_plic_28_IRQHandler(void); -uint8_t gpio1_bit15_or_gpio2_bit29_plic_29_IRQHandler(void); -uint8_t gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler(void); -uint8_t gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler(void); - -uint8_t gpio1_bit18_plic_32_IRQHandler(void); -uint8_t gpio1_bit19_plic_33_IRQHandler(void); -uint8_t gpio1_bit20_plic_34_IRQHandler(void); -uint8_t gpio1_bit21_plic_35_IRQHandler(void); -uint8_t gpio1_bit22_plic_36_IRQHandler(void); -uint8_t gpio1_bit23_plic_37_IRQHandler(void); - -uint8_t gpio0_non_direct_plic_IRQHandler(void); -uint8_t gpio1_non_direct_plic_IRQHandler(void); -uint8_t gpio2_non_direct_plic_IRQHandler(void); - -uint8_t spi0_plic_IRQHandler(void); -uint8_t spi1_plic_IRQHandler(void); -uint8_t external_can0_plic_IRQHandler(void); -uint8_t can1_IRQHandler(void); -uint8_t External_i2c0_main_plic_IRQHandler(void); -uint8_t External_i2c0_alert_plic_IRQHandler(void); -uint8_t i2c0_sus_plic_IRQHandler(void); -uint8_t i2c1_main_plic_IRQHandler(void); -uint8_t i2c1_alert_plic_IRQHandler(void); -uint8_t i2c1_sus_plic_IRQHandler(void); -uint8_t mac0_int_plic_IRQHandler(void); -uint8_t mac0_queue1_plic_IRQHandler(void); -uint8_t mac0_queue2_plic_IRQHandler(void); -uint8_t mac0_queue3_plic_IRQHandler(void); -uint8_t mac0_emac_plic_IRQHandler(void); -uint8_t mac0_mmsl_plic_IRQHandler(void); -uint8_t mac1_int_plic_IRQHandler(void); -uint8_t mac1_queue1_plic_IRQHandler(void); -uint8_t mac1_queue2_plic_IRQHandler(void); -uint8_t mac1_queue3_plic_IRQHandler(void); -uint8_t mac1_emac_plic_IRQHandler(void); -uint8_t mac1_mmsl_plic_IRQHandler(void); -uint8_t ddrc_train_plic_IRQHandler(void); -uint8_t scb_interrupt_plic_IRQHandler(void); -uint8_t ecc_error_plic_IRQHandler(void); -uint8_t ecc_correct_plic_IRQHandler(void); -uint8_t rtc_wakeup_plic_IRQHandler(void); -uint8_t rtc_match_plic_IRQHandler(void); -uint8_t timer1_plic_IRQHandler(void); -uint8_t timer2_plic_IRQHandler(void); -uint8_t envm_plic_IRQHandler(void); -uint8_t qspi_plic_IRQHandler(void); -uint8_t usb_dma_plic_IRQHandler(void); -uint8_t usb_mc_plic_IRQHandler(void); -uint8_t mmc_main_plic_IRQHandler(void); -uint8_t mmc_wakeup_plic_IRQHandler(void); -uint8_t mmuart0_plic_77_IRQHandler(void); -uint8_t mmuart1_plic_IRQHandler(void); -uint8_t mmuart2_plic_IRQHandler(void); -uint8_t mmuart3_plic_IRQHandler(void); -uint8_t mmuart4_plic_IRQHandler(void); -uint8_t g5c_devrst_plic_IRQHandler(void); -uint8_t g5c_message_plic_IRQHandler(void); -uint8_t usoc_vc_interrupt_plic_IRQHandler(void); -uint8_t usoc_smb_interrupt_plic_IRQHandler(void); -uint8_t e51_0_Maintence_plic_IRQHandler(void); - -uint8_t wdog0_mvrp_plic_IRQHandler(void); -uint8_t wdog1_mvrp_plic_IRQHandler(void); -uint8_t wdog2_mvrp_plic_IRQHandler(void); -uint8_t wdog3_mvrp_plic_IRQHandler(void); -uint8_t wdog4_mvrp_plic_IRQHandler(void); -uint8_t wdog0_tout_plic_IRQHandler(void); -uint8_t wdog1_tout_plic_IRQHandler(void); -uint8_t wdog2_tout_plic_IRQHandler(void); -uint8_t wdog3_tout_plic_IRQHandler(void); -uint8_t wdog4_tout_plic_IRQHandler(void); -uint8_t g5c_mss_spi_plic_IRQHandler(void); -uint8_t volt_temp_alarm_plic_IRQHandler(void); - -uint8_t athena_complete_plic_IRQHandler(void); -uint8_t athena_alarm_plic_IRQHandler(void); -uint8_t athena_bus_error_plic_IRQHandler(void); -uint8_t usoc_axic_us_plic_IRQHandler(void); -uint8_t usoc_axic_ds_plic_IRQHandler(void); - -uint8_t reserved_104_plic_IRQHandler(void); - -uint8_t fabric_f2h_0_plic_IRQHandler(void); -uint8_t fabric_f2h_1_plic_IRQHandler(void); -uint8_t fabric_f2h_2_plic_IRQHandler(void); -uint8_t fabric_f2h_3_plic_IRQHandler(void); -uint8_t fabric_f2h_4_plic_IRQHandler(void); -uint8_t fabric_f2h_5_plic_IRQHandler(void); -uint8_t fabric_f2h_6_plic_IRQHandler(void); -uint8_t fabric_f2h_7_plic_IRQHandler(void); -uint8_t fabric_f2h_8_plic_IRQHandler(void); -uint8_t fabric_f2h_9_plic_IRQHandler(void); - -uint8_t fabric_f2h_10_plic_IRQHandler(void); -uint8_t fabric_f2h_11_plic_IRQHandler(void); -uint8_t fabric_f2h_12_plic_IRQHandler(void); -uint8_t fabric_f2h_13_plic_IRQHandler(void); -uint8_t fabric_f2h_14_plic_IRQHandler(void); -uint8_t fabric_f2h_15_plic_IRQHandler(void); -uint8_t fabric_f2h_16_plic_IRQHandler(void); -uint8_t fabric_f2h_17_plic_IRQHandler(void); -uint8_t fabric_f2h_18_plic_IRQHandler(void); -uint8_t fabric_f2h_19_plic_IRQHandler(void); - -uint8_t fabric_f2h_20_plic_IRQHandler(void); -uint8_t fabric_f2h_21_plic_IRQHandler(void); -uint8_t fabric_f2h_22_plic_IRQHandler(void); -uint8_t fabric_f2h_23_plic_IRQHandler(void); -uint8_t fabric_f2h_24_plic_IRQHandler(void); -uint8_t fabric_f2h_25_plic_IRQHandler(void); -uint8_t fabric_f2h_26_plic_IRQHandler(void); -uint8_t fabric_f2h_27_plic_IRQHandler(void); -uint8_t fabric_f2h_28_plic_IRQHandler(void); -uint8_t fabric_f2h_29_plic_IRQHandler(void); - -uint8_t fabric_f2h_30_plic_IRQHandler(void); -uint8_t fabric_f2h_31_plic_IRQHandler(void); - -uint8_t fabric_f2h_32_plic_IRQHandler(void); -uint8_t fabric_f2h_33_plic_IRQHandler(void); -uint8_t fabric_f2h_34_plic_IRQHandler(void); -uint8_t fabric_f2h_35_plic_IRQHandler(void); -uint8_t fabric_f2h_36_plic_IRQHandler(void); -uint8_t fabric_f2h_37_plic_IRQHandler(void); -uint8_t fabric_f2h_38_plic_IRQHandler(void); -uint8_t fabric_f2h_39_plic_IRQHandler(void); -uint8_t fabric_f2h_40_plic_IRQHandler(void); -uint8_t fabric_f2h_41_plic_IRQHandler(void); - -uint8_t fabric_f2h_42_plic_IRQHandler(void); -uint8_t fabric_f2h_43_plic_IRQHandler(void); -uint8_t fabric_f2h_44_plic_IRQHandler(void); -uint8_t fabric_f2h_45_plic_IRQHandler(void); -uint8_t fabric_f2h_46_plic_IRQHandler(void); -uint8_t fabric_f2h_47_plic_IRQHandler(void); -uint8_t fabric_f2h_48_plic_IRQHandler(void); -uint8_t fabric_f2h_49_plic_IRQHandler(void); -uint8_t fabric_f2h_50_plic_IRQHandler(void); -uint8_t fabric_f2h_51_plic_IRQHandler(void); - -uint8_t fabric_f2h_52_plic_IRQHandler(void); -uint8_t fabric_f2h_53_plic_IRQHandler(void); -uint8_t fabric_f2h_54_plic_IRQHandler(void); -uint8_t fabric_f2h_55_plic_IRQHandler(void); -uint8_t fabric_f2h_56_plic_IRQHandler(void); -uint8_t fabric_f2h_57_plic_IRQHandler(void); -uint8_t fabric_f2h_58_plic_IRQHandler(void); -uint8_t fabric_f2h_59_plic_IRQHandler(void); -uint8_t fabric_f2h_60_plic_IRQHandler(void); -uint8_t fabric_f2h_61_plic_IRQHandler(void); - -uint8_t fabric_f2h_62_plic_IRQHandler(void); -uint8_t fabric_f2h_63_plic_IRQHandler(void); - -uint8_t bus_error_unit_hart_0_plic_IRQHandler(void); -uint8_t bus_error_unit_hart_1_plic_IRQHandler(void); -uint8_t bus_error_unit_hart_2_plic_IRQHandler(void); -uint8_t bus_error_unit_hart_3_plic_IRQHandler(void); -uint8_t bus_error_unit_hart_4_plic_IRQHandler(void); - - -#else -uint8_t Invalid_IRQHandler(void); -uint8_t External_1_IRQHandler(void); -uint8_t External_2_IRQHandler(void); -uint8_t External_3_IRQHandler(void); -uint8_t USART0_plic_4_IRQHandler(void); -uint8_t External_5_IRQHandler(void); -uint8_t External_6_IRQHandler(void); -uint8_t External_7_IRQHandler(void); -uint8_t External_8_IRQHandler(void); -uint8_t External_9_IRQHandler(void); -uint8_t External_10_IRQHandler(void); -uint8_t External_11_IRQHandler(void); -uint8_t External_12_IRQHandler(void); -uint8_t External_13_IRQHandler(void); -uint8_t External_14_IRQHandler(void); -uint8_t External_15_IRQHandler(void); -uint8_t External_16_IRQHandler(void); -uint8_t External_17_IRQHandler(void); -uint8_t External_18_IRQHandler(void); -uint8_t External_19_IRQHandler(void); -uint8_t External_20_IRQHandler(void); -uint8_t External_21_IRQHandler(void); -uint8_t External_22_IRQHandler(void); -uint8_t dma_ch0_DONE_IRQHandler(void); -uint8_t dma_ch0_ERR_IRQHandler(void); -uint8_t dma_ch1_DONE_IRQHandler(void); -uint8_t dma_ch1_ERR_IRQHandler(void); -uint8_t dma_ch2_DONE_IRQHandler(void); -uint8_t dma_ch2_ERR_IRQHandler(void); -uint8_t dma_ch3_DONE_IRQHandler(void); -uint8_t dma_ch3_ERR_IRQHandler(void); -uint8_t External_31_IRQHandler(void); -uint8_t External_32_IRQHandler(void); -uint8_t External_33_IRQHandler(void); -uint8_t External_34_IRQHandler(void); -uint8_t External_35_IRQHandler(void); -uint8_t External_36_IRQHandler(void); -uint8_t External_37_IRQHandler(void); -uint8_t External_38_IRQHandler(void); -uint8_t External_39_IRQHandler(void); -uint8_t External_40_IRQHandler(void); -uint8_t External_41_IRQHandler(void); -uint8_t External_42_IRQHandler(void); -uint8_t External_43_IRQHandler(void); -uint8_t External_44_IRQHandler(void); -uint8_t External_45_IRQHandler(void); -uint8_t External_46_IRQHandler(void); -uint8_t External_47_IRQHandler(void); -uint8_t External_48_IRQHandler(void); -uint8_t External_49_IRQHandler(void); -uint8_t External_50_IRQHandler(void); -uint8_t External_51_IRQHandler(void); -uint8_t External_52_IRQHandler(void); -uint8_t MAC0_plic_53_IRQHandler(void); - -#endif +uint8_t PLIC_Invalid_IRQHandler(void); +uint8_t PLIC_l2_metadata_corr_IRQHandler(void); +uint8_t PLIC_l2_metadata_uncorr_IRQHandler(void); +uint8_t PLIC_l2_data_corr_IRQHandler(void); +uint8_t PLIC_l2_data_uncorr_IRQHandler(void); +uint8_t PLIC_dma_ch0_DONE_IRQHandler(void); +uint8_t PLIC_dma_ch0_ERR_IRQHandler(void); +uint8_t PLIC_dma_ch1_DONE_IRQHandler(void); +uint8_t PLIC_dma_ch1_ERR_IRQHandler(void); +uint8_t PLIC_dma_ch2_DONE_IRQHandler(void); +uint8_t PLIC_dma_ch2_ERR_IRQHandler(void); +uint8_t PLIC_dma_ch3_DONE_IRQHandler(void); +uint8_t PLIC_dma_ch3_ERR_IRQHandler(void); +uint8_t PLIC_gpio0_bit0_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit1_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit2_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit3_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit4_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit5_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit6_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit7_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit8_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit9_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit10_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit11_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio0_bit12_or_gpio2_bit13_IRQHandler(void); + +uint8_t PLIC_gpio0_bit13_or_gpio2_bit13_IRQHandler(void); +uint8_t PLIC_gpio1_bit0_or_gpio2_bit14_IRQHandler(void); +uint8_t PLIC_gpio1_bit1_or_gpio2_bit15_IRQHandler(void); +uint8_t PLIC_gpio1_bit2_or_gpio2_bit16_IRQHandler(void); +uint8_t PLIC_gpio1_bit3_or_gpio2_bit17_IRQHandler(void); +uint8_t PLIC_gpio1_bit4_or_gpio2_bit18_IRQHandler(void); +uint8_t PLIC_gpio1_bit5_or_gpio2_bit19_IRQHandler(void); +uint8_t PLIC_gpio1_bit6_or_gpio2_bit20_IRQHandler(void); +uint8_t PLIC_gpio1_bit7_or_gpio2_bit21_IRQHandler(void); +uint8_t PLIC_gpio1_bit8_or_gpio2_bit22_IRQHandler(void); +uint8_t PLIC_gpio1_bit9_or_gpio2_bit23_IRQHandler(void); +uint8_t PLIC_gpio1_bit10_or_gpio2_bit24_IRQHandler(void); +uint8_t PLIC_gpio1_bit11_or_gpio2_bit25_IRQHandler(void); +uint8_t PLIC_gpio1_bit12_or_gpio2_bit26_IRQHandler(void); +uint8_t PLIC_gpio1_bit13_or_gpio2_bit27_IRQHandler(void); + +uint8_t PLIC_gpio1_bit14_or_gpio2_bit28_IRQHandler(void); +uint8_t PLIC_gpio1_bit15_or_gpio2_bit29_IRQHandler(void); +uint8_t PLIC_gpio1_bit16_or_gpio2_bit30_IRQHandler(void); +uint8_t PLIC_gpio1_bit17_or_gpio2_bit31_IRQHandler(void); + +uint8_t PLIC_gpio1_bit18_IRQHandler(void); +uint8_t PLIC_gpio1_bit19_IRQHandler(void); +uint8_t PLIC_gpio1_bit20_IRQHandler(void); +uint8_t PLIC_gpio1_bit21_IRQHandler(void); +uint8_t PLIC_gpio1_bit22_IRQHandler(void); +uint8_t PLIC_gpio1_bit23_IRQHandler(void); + +uint8_t PLIC_gpio0_non_direct_IRQHandler(void); +uint8_t PLIC_gpio1_non_direct_IRQHandler(void); +uint8_t PLIC_gpio2_non_direct_IRQHandler(void); + +uint8_t PLIC_spi0_IRQHandler(void); +uint8_t PLIC_spi1_IRQHandler(void); +uint8_t PLIC_external_can0_IRQHandler(void); +uint8_t PLIC_can1_IRQHandler(void); +uint8_t PLIC_External_i2c0_main_IRQHandler(void); +uint8_t PLIC_External_i2c0_alert_IRQHandler(void); +uint8_t PLIC_i2c0_sus_IRQHandler(void); +uint8_t PLIC_i2c1_main_IRQHandler(void); +uint8_t PLIC_i2c1_alert_IRQHandler(void); +uint8_t PLIC_i2c1_sus_IRQHandler(void); +uint8_t PLIC_mac0_int_IRQHandler(void); +uint8_t PLIC_mac0_queue1_IRQHandler(void); +uint8_t PLIC_mac0_queue2_IRQHandler(void); +uint8_t PLIC_mac0_queue3_IRQHandler(void); +uint8_t PLIC_mac0_emac_IRQHandler(void); +uint8_t PLIC_mac0_mmsl_IRQHandler(void); +uint8_t PLIC_mac1_int_IRQHandler(void); +uint8_t PLIC_mac1_queue1_IRQHandler(void); +uint8_t PLIC_mac1_queue2_IRQHandler(void); +uint8_t PLIC_mac1_queue3_IRQHandler(void); +uint8_t PLIC_mac1_emac_IRQHandler(void); +uint8_t PLIC_mac1_mmsl_IRQHandler(void); +uint8_t PLIC_ddrc_train_IRQHandler(void); +uint8_t PLIC_scb_interrupt_IRQHandler(void); +uint8_t PLIC_ecc_error_IRQHandler(void); +uint8_t PLIC_ecc_correct_IRQHandler(void); +uint8_t PLIC_rtc_wakeup_IRQHandler(void); +uint8_t PLIC_rtc_match_IRQHandler(void); +uint8_t PLIC_timer1_IRQHandler(void); +uint8_t PLIC_timer2_IRQHandler(void); +uint8_t PLIC_envm_IRQHandler(void); +uint8_t PLIC_qspi_IRQHandler(void); +uint8_t PLIC_usb_dma_IRQHandler(void); +uint8_t PLIC_usb_mc_IRQHandler(void); +uint8_t PLIC_mmc_main_IRQHandler(void); +uint8_t PLIC_mmc_wakeup_IRQHandler(void); +uint8_t PLIC_mmuart0_IRQHandler(void); +uint8_t PLIC_mmuart1_IRQHandler(void); +uint8_t PLIC_mmuart2_IRQHandler(void); +uint8_t PLIC_mmuart3_IRQHandler(void); +uint8_t PLIC_mmuart4_IRQHandler(void); +uint8_t PLIC_devrst_IRQHandler(void); +uint8_t PLIC_g5c_message_IRQHandler(void); +uint8_t PLIC_usoc_vc_interrupt_IRQHandler(void); +uint8_t PLIC_usoc_smb_interrupt_IRQHandler(void); +uint8_t PLIC_E51_Maintence_IRQHandler(void); + +uint8_t PLIC_wdog0_mvrp_IRQHandler(void); +uint8_t PLIC_wdog1_mvrp_IRQHandler(void); +uint8_t PLIC_wdog2_mvrp_IRQHandler(void); +uint8_t PLIC_wdog3_mvrp_IRQHandler(void); +uint8_t PLIC_wdog4_mvrp_IRQHandler(void); +uint8_t PLIC_wdog0_tout_IRQHandler(void); +uint8_t PLIC_wdog1_tout_IRQHandler(void); +uint8_t PLIC_wdog2_tout_IRQHandler(void); +uint8_t PLIC_wdog3_tout_IRQHandler(void); +uint8_t PLIC_wdog4_tout_IRQHandler(void); +uint8_t PLIC_g5c_mss_spi_IRQHandler(void); +uint8_t PLIC_volt_temp_alarm_IRQHandler(void); + +uint8_t PLIC_athena_complete_IRQHandler(void); +uint8_t PLIC_athena_alarm_IRQHandler(void); +uint8_t PLIC_athena_bus_error_IRQHandler(void); +uint8_t PLIC_usoc_axic_us_IRQHandler(void); +uint8_t PLIC_usoc_axic_ds_IRQHandler(void); + +uint8_t PLIC_reserved_104_IRQHandler(void); + +uint8_t PLIC_f2m_0_IRQHandler(void); +uint8_t PLIC_f2m_1_IRQHandler(void); +uint8_t PLIC_f2m_2_IRQHandler(void); +uint8_t PLIC_f2m_3_IRQHandler(void); +uint8_t PLIC_f2m_4_IRQHandler(void); +uint8_t PLIC_f2m_5_IRQHandler(void); +uint8_t PLIC_f2m_6_IRQHandler(void); +uint8_t PLIC_f2m_7_IRQHandler(void); +uint8_t PLIC_f2m_8_IRQHandler(void); +uint8_t PLIC_f2m_9_IRQHandler(void); + +uint8_t PLIC_f2m_10_IRQHandler(void); +uint8_t PLIC_f2m_11_IRQHandler(void); +uint8_t PLIC_f2m_12_IRQHandler(void); +uint8_t PLIC_f2m_13_IRQHandler(void); +uint8_t PLIC_f2m_14_IRQHandler(void); +uint8_t PLIC_f2m_15_IRQHandler(void); +uint8_t PLIC_f2m_16_IRQHandler(void); +uint8_t PLIC_f2m_17_IRQHandler(void); +uint8_t PLIC_f2m_18_IRQHandler(void); +uint8_t PLIC_f2m_19_IRQHandler(void); + +uint8_t PLIC_f2m_20_IRQHandler(void); +uint8_t PLIC_f2m_21_IRQHandler(void); +uint8_t PLIC_f2m_22_IRQHandler(void); +uint8_t PLIC_f2m_23_IRQHandler(void); +uint8_t PLIC_f2m_24_IRQHandler(void); +uint8_t PLIC_f2m_25_IRQHandler(void); +uint8_t PLIC_f2m_26_IRQHandler(void); +uint8_t PLIC_f2m_27_IRQHandler(void); +uint8_t PLIC_f2m_28_IRQHandler(void); +uint8_t PLIC_f2m_29_IRQHandler(void); + +uint8_t PLIC_f2m_30_IRQHandler(void); +uint8_t PLIC_f2m_31_IRQHandler(void); + +uint8_t PLIC_f2m_32_IRQHandler(void); +uint8_t PLIC_f2m_33_IRQHandler(void); +uint8_t PLIC_f2m_34_IRQHandler(void); +uint8_t PLIC_f2m_35_IRQHandler(void); +uint8_t PLIC_f2m_36_IRQHandler(void); +uint8_t PLIC_f2m_37_IRQHandler(void); +uint8_t PLIC_f2m_38_IRQHandler(void); +uint8_t PLIC_f2m_39_IRQHandler(void); +uint8_t PLIC_f2m_40_IRQHandler(void); +uint8_t PLIC_f2m_41_IRQHandler(void); + +uint8_t PLIC_f2m_42_IRQHandler(void); +uint8_t PLIC_f2m_43_IRQHandler(void); +uint8_t PLIC_f2m_44_IRQHandler(void); +uint8_t PLIC_f2m_45_IRQHandler(void); +uint8_t PLIC_f2m_46_IRQHandler(void); +uint8_t PLIC_f2m_47_IRQHandler(void); +uint8_t PLIC_f2m_48_IRQHandler(void); +uint8_t PLIC_f2m_49_IRQHandler(void); +uint8_t PLIC_f2m_50_IRQHandler(void); +uint8_t PLIC_f2m_51_IRQHandler(void); + +uint8_t PLIC_f2m_52_IRQHandler(void); +uint8_t PLIC_f2m_53_IRQHandler(void); +uint8_t PLIC_f2m_54_IRQHandler(void); +uint8_t PLIC_f2m_55_IRQHandler(void); +uint8_t PLIC_f2m_56_IRQHandler(void); +uint8_t PLIC_f2m_57_IRQHandler(void); +uint8_t PLIC_f2m_58_IRQHandler(void); +uint8_t PLIC_f2m_59_IRQHandler(void); +uint8_t PLIC_f2m_60_IRQHandler(void); +uint8_t PLIC_f2m_61_IRQHandler(void); + +uint8_t PLIC_f2m_62_IRQHandler(void); +uint8_t PLIC_f2m_63_IRQHandler(void); + +uint8_t PLIC_E51_bus_error_unit_IRQHandler(void); +uint8_t PLIC_U54_1_bus_error_unit_IRQHandler(void); +uint8_t PLIC_U54_2_bus_error_unit_IRQHandler(void); +uint8_t PLIC_U54_3_bus_error_unit_IRQHandler(void); +uint8_t PLIC_U54_4_bus_error_unit_IRQHandler(void); /***************************************************************************//** * PLIC source Interrupt numbers: @@ -312,304 +252,214 @@ uint8_t MAC0_plic_53_IRQHandler(void); #define OFFSET_TO_MSS_GLOBAL_INTS 13U typedef enum { -#ifndef SIFIVE_HIFIVE_UNLEASHED - INVALID_IRQn = 0, - L2_METADATA_CORR_IRQn = 1, - L2_METADAT_UNCORR_IRQn = 2, - L2_DATA_CORR_IRQn = 3, - L2_DATA_UNCORR_IRQn = 4, - DMA_CH0_DONE_IRQn = 5, - DMA_CH0_ERR_IRQn = 6, - DMA_CH1_DONE_IRQn = 7, - DMA_CH1_ERR_IRQn = 8, - DMA_CH2_DONE_IRQn = 9, - DMA_CH2_ERR_IRQn = 10, - DMA_CH3_DONE_IRQn = 11, - DMA_CH3_ERR_IRQn = 12, - /* see GPIO Interrupt Multiplexing in the User Guide */ - GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 = 0 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT1_or_GPIO2_BIT1_PLIC_1 = 1 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT2_or_GPIO2_BIT2_PLIC_2 = 2 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT3_or_GPIO2_BIT3_PLIC_3 = 3 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT4_or_GPIO2_BIT4_PLIC_4 = 4 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT5_or_GPIO2_BIT5_PLIC_5 = 5 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT6_or_GPIO2_BIT6_PLIC_6 = 6 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT7_or_GPIO2_BIT7_PLIC_7 = 7 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT8_or_GPIO2_BIT8_PLIC_8 = 8 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT9_or_GPIO2_BIT9_PLIC_9 = 9 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT10_or_GPIO2_BIT10_PLIC_10 = 10 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT11_or_GPIO2_BIT11_PLIC_11 = 11 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO0_BIT12_or_GPIO2_BIT12_PLIC_12 = 12 + OFFSET_TO_MSS_GLOBAL_INTS, - - GPIO0_BIT13_or_GPIO2_BIT13_PLIC_13 = 13 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14 = 14 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT1_or_GPIO2_BIT15_PLIC_15 = 15 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT2_or_GPIO2_BIT16_PLIC_16 = 16 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT3_or_GPIO2_BIT17_PLIC_17 = 17 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT4_or_GPIO2_BIT18_PLIC_18 = 18 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT5_or_GPIO2_BIT19_PLIC_19 = 19 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT6_or_GPIO2_BIT20_PLIC_20 = 20 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT7_or_GPIO2_BIT21_PLIC_21 = 21 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT8_or_GPIO2_BIT22_PLIC_22 = 22 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT9_or_GPIO2_BIT23_PLIC_23 = 23 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT10_or_GPIO2_BIT24_PLIC_24 = 24 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT11_or_GPIO2_BIT25_PLIC_25 = 25 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT12_or_GPIO2_BIT26_PLIC_26 = 26 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT13_or_GPIO2_BIT27_PLIC_27 = 27 + OFFSET_TO_MSS_GLOBAL_INTS, - - GPIO1_BIT14_or_GPIO2_BIT28_PLIC_28 = 28 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT15_or_GPIO2_BIT29_PLIC_29 = 29 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT16_or_GPIO2_BIT30_PLIC_30 = 30 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT17_or_GPIO2_BIT31_PLIC_31 = 31 + OFFSET_TO_MSS_GLOBAL_INTS, - - GPIO1_BIT18_PLIC_32 = 32 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT19_PLIC_33 = 33 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT20_PLIC_34 = 34 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT21_PLIC_35 = 35 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT22_PLIC_36 = 36 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_BIT23_PLIC_37 = 37 + OFFSET_TO_MSS_GLOBAL_INTS, - - GPIO0_NON_DIRECT_PLIC = 38 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO1_NON_DIRECT_PLIC = 39 + OFFSET_TO_MSS_GLOBAL_INTS, - GPIO2_NON_DIRECT_PLIC = 40 + OFFSET_TO_MSS_GLOBAL_INTS, - - SPI0_PLIC = 41 + OFFSET_TO_MSS_GLOBAL_INTS, - SPI1_PLIC = 42 + OFFSET_TO_MSS_GLOBAL_INTS, - CAN0_PLIC = 43 + OFFSET_TO_MSS_GLOBAL_INTS, - CAN1_PLIC = 44 + OFFSET_TO_MSS_GLOBAL_INTS, - I2C0_MAIN_PLIC = 45 + OFFSET_TO_MSS_GLOBAL_INTS, - I2C0_ALERT_PLIC = 46 + OFFSET_TO_MSS_GLOBAL_INTS, - I2C0_SUS_PLIC = 47 + OFFSET_TO_MSS_GLOBAL_INTS, - I2C1_MAIN_PLIC = 48 + OFFSET_TO_MSS_GLOBAL_INTS, - I2C1_ALERT_PLIC = 49 + OFFSET_TO_MSS_GLOBAL_INTS, - I2C1_SUS_PLIC = 50 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC0_INT_PLIC = 51 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC0_QUEUE1_PLIC = 52 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC0_QUEUE2_PLIC = 53 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC0_QUEUE3_PLIC = 54 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC0_EMAC_PLIC = 55 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC0_MMSL_PLIC = 56 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC1_INT_PLIC = 57 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC1_QUEUE1_PLIC = 58 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC1_QUEUE2_PLIC = 59 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC1_QUEUE3_PLIC = 60 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC1_EMAC_PLIC = 61 + OFFSET_TO_MSS_GLOBAL_INTS, - MAC1_MMSL_PLIC = 62 + OFFSET_TO_MSS_GLOBAL_INTS, - DDRC_TRAIN_PLIC = 63 + OFFSET_TO_MSS_GLOBAL_INTS, - SCB_INTERRUPT_PLIC = 64 + OFFSET_TO_MSS_GLOBAL_INTS, - ECC_ERROR_PLIC = 65 + OFFSET_TO_MSS_GLOBAL_INTS, - ECC_CORRECT_PLIC = 66 + OFFSET_TO_MSS_GLOBAL_INTS, - RTC_WAKEUP_PLIC = 67 + OFFSET_TO_MSS_GLOBAL_INTS, - RTC_MATCH_PLIC = 68 + OFFSET_TO_MSS_GLOBAL_INTS, - TIMER1_PLIC = 69 + OFFSET_TO_MSS_GLOBAL_INTS, - TIMER2_PLIC = 70 + OFFSET_TO_MSS_GLOBAL_INTS, - ENVM_PLIC = 71 + OFFSET_TO_MSS_GLOBAL_INTS, - QSPI_PLIC = 72 + OFFSET_TO_MSS_GLOBAL_INTS, - USB_DMA_PLIC = 73 + OFFSET_TO_MSS_GLOBAL_INTS, - USB_MC_PLIC = 74 + OFFSET_TO_MSS_GLOBAL_INTS, - MMC_main_PLIC = 75 + OFFSET_TO_MSS_GLOBAL_INTS, - MMC_wakeup_PLIC = 76 + OFFSET_TO_MSS_GLOBAL_INTS, - MMUART0_PLIC_77 = 77 + OFFSET_TO_MSS_GLOBAL_INTS, - MMUART1_PLIC = 78 + OFFSET_TO_MSS_GLOBAL_INTS, - MMUART2_PLIC = 79 + OFFSET_TO_MSS_GLOBAL_INTS, - MMUART3_PLIC = 80 + OFFSET_TO_MSS_GLOBAL_INTS, - MMUART4_PLIC = 81 + OFFSET_TO_MSS_GLOBAL_INTS, - - G5C_DEVRST_PLIC = 82 + OFFSET_TO_MSS_GLOBAL_INTS, - g5c_MESSAGE_PLIC = 83 + OFFSET_TO_MSS_GLOBAL_INTS, - USOC_VC_INTERRUPT_PLIC = 84 + OFFSET_TO_MSS_GLOBAL_INTS, - USOC_SMB_INTERRUPT_PLIC = 85 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_INVALID_INT_OFFSET = 0, + PLIC_L2_METADATA_CORR_INT_OFFSET = 1, + PLIC_L2_METADAT_UNCORR_INT_OFFSET = 2, + PLIC_L2_DATA_CORR_INT_OFFSET = 3, + PLIC_L2_DATA_UNCORR_INT_OFFSET = 4, + PLIC_DMA_CH0_DONE_INT_OFFSET = 5, + PLIC_DMA_CH0_ERR_INT_OFFSET = 6, + PLIC_DMA_CH1_DONE_INT_OFFSET = 7, + PLIC_DMA_CH1_ERR_INT_OFFSET = 8, + PLIC_DMA_CH2_DONE_INT_OFFSET = 9, + PLIC_DMA_CH2_ERR_INT_OFFSET = 10, + PLIC_DMA_CH3_DONE_INT_OFFSET = 11, + PLIC_DMA_CH3_ERR_INT_OFFSET = 12, + /* see PLIC_I2C Interrupt Multiplexing in the User Guide */ + PLIC_GPIO0_BIT0_or_GPIO2_BIT0_INT_OFFSET = 0 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT1_or_GPIO2_BIT1_INT_OFFSET = 1 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT2_or_GPIO2_BIT2_INT_OFFSET = 2 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT3_or_GPIO2_BIT3_INT_OFFSET = 3 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT4_or_GPIO2_BIT4_INT_OFFSET = 4 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT5_or_GPIO2_BIT5_INT_OFFSET = 5 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT6_or_GPIO2_BIT6_INT_OFFSET = 6 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT7_or_GPIO2_BIT7_INT_OFFSET = 7 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT8_or_GPIO2_BIT8_INT_OFFSET = 8 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT9_or_GPIO2_BIT9_INT_OFFSET = 9 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT10_or_GPIO2_BIT10_INT_OFFSET = 10 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT11_or_GPIO2_BIT11_INT_OFFSET = 11 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO0_BIT12_or_GPIO2_BIT12_INT_OFFSET = 12 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_GPIO0_BIT13_or_GPIO2_BIT13_INT_OFFSET = 13 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT0_or_GPIO2_BIT14_INT_OFFSET = 14 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT1_or_GPIO2_BIT15_INT_OFFSET = 15 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT2_or_GPIO2_BIT16_INT_OFFSET = 16 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT3_or_GPIO2_BIT17_INT_OFFSET = 17 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT4_or_GPIO2_BIT18_INT_OFFSET = 18 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT5_or_GPIO2_BIT19_INT_OFFSET = 19 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT6_or_GPIO2_BIT20_INT_OFFSET = 20 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT7_or_GPIO2_BIT21_INT_OFFSET = 21 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT8_or_GPIO2_BIT22_INT_OFFSET = 22 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT9_or_GPIO2_BIT23_INT_OFFSET = 23 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT10_or_GPIO2_BIT24_INT_OFFSET = 24 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT11_or_GPIO2_BIT25_INT_OFFSET = 25 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT12_or_GPIO2_BIT26_INT_OFFSET = 26 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT13_or_GPIO2_BIT27_INT_OFFSET = 27 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_GPIO1_BIT14_or_GPIO2_BIT28_INT_OFFSET = 28 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT15_or_GPIO2_BIT29_INT_OFFSET = 29 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT16_or_GPIO2_BIT30_INT_OFFSET = 30 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT17_or_GPIO2_BIT31_INT_OFFSET = 31 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_GPIO1_BIT18_INT_OFFSET = 32 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT19_INT_OFFSET = 33 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT20_INT_OFFSET = 34 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT21_INT_OFFSET = 35 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT22_INT_OFFSET = 36 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_BIT23_INT_OFFSET = 37 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_GPIO0_NON_DIRECT_INT_OFFSET = 38 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO1_NON_DIRECT_INT_OFFSET = 39 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_GPIO2_NON_DIRECT_INT_OFFSET = 40 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_SPI0_INT_OFFSET = 41 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_SPI1_INT_OFFSET = 42 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_CAN0_INT_OFFSET = 43 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_CAN1_INT_OFFSET = 44 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_I2C0_MAIN_INT_OFFSET = 45 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_I2C0_ALERT_INT_OFFSET = 46 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_I2C0_SUS_INT_OFFSET = 47 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_I2C1_MAIN_INT_OFFSET = 48 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_I2C1_ALERT_INT_OFFSET = 49 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_I2C1_SUS_INT_OFFSET = 50 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC0_INT_INT_OFFSET = 51 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC0_QUEUE1_INT_OFFSET = 52 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC0_QUEUE2_INT_OFFSET = 53 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC0_QUEUE3_INT_OFFSET = 54 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC0_EMAC_INT_OFFSET = 55 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC0_MMSL_INT_OFFSET = 56 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC1_INT_INT_OFFSET = 57 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC1_QUEUE1_INT_OFFSET = 58 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC1_QUEUE2_INT_OFFSET = 59 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC1_QUEUE3_INT_OFFSET = 60 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC1_EMAC_INT_OFFSET = 61 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MAC1_MMSL_INT_OFFSET = 62 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_DDRC_TRAIN_INT_OFFSET = 63 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_SCB_INTERRUPT_INT_OFFSET = 64 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_ECC_ERROR_INT_OFFSET = 65 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_ECC_CORRECT_INT_OFFSET = 66 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_RTC_WAKEUP_INT_OFFSET = 67 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_RTC_MATCH_INT_OFFSET = 68 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_TIMER1_INT_OFFSET = 69 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_TIMER2_INT_OFFSET = 70 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_ENVM_INT_OFFSET = 71 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_QSPI_INT_OFFSET = 72 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_USB_DMA_INT_OFFSET = 73 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_USB_MC_INT_OFFSET = 74 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMC_main_INT_OFFSET = 75 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMC_wakeup_INT_OFFSET = 76 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMUART0_INT_OFFSET = 77 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMUART1_INT_OFFSET = 78 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMUART2_INT_OFFSET = 79 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMUART3_INT_OFFSET = 80 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_MMUART4_INT_OFFSET = 81 + OFFSET_TO_MSS_GLOBAL_INTS, + + G5C_DEVRST_INT_OFFSET = 82 + OFFSET_TO_MSS_GLOBAL_INTS, + g5c_MESSAGE_INT_OFFSET = 83 + OFFSET_TO_MSS_GLOBAL_INTS, + USOC_VC_INTERRUPT_INT_OFFSET = 84 + OFFSET_TO_MSS_GLOBAL_INTS, + USOC_SMB_INTERRUPT_INT_OFFSET = 85 + OFFSET_TO_MSS_GLOBAL_INTS, /* contains multiple interrupts- */ - E51_0_MAINTENACE_PLIC = 86 + OFFSET_TO_MSS_GLOBAL_INTS, - - WDOG0_MRVP_PLIC = 87 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG1_MRVP_PLIC = 88 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG2_MRVP_PLIC = 89 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG3_MRVP_PLIC = 90 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG4_MRVP_PLIC = 91 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG0_TOUT_PLIC = 92 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG1_TOUT_PLIC = 93 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG2_TOUT_PLIC = 94 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG3_TOUT_PLIC = 95 + OFFSET_TO_MSS_GLOBAL_INTS, - WDOG4_TOUT_PLIC = 96 + OFFSET_TO_MSS_GLOBAL_INTS, - G5C_MSS_SPI_PLIC = 97 + OFFSET_TO_MSS_GLOBAL_INTS, - VOLT_TEMP_ALARM_PLIC = 98 + OFFSET_TO_MSS_GLOBAL_INTS, - ATHENA_COMPLETE_PLIC = 99 + OFFSET_TO_MSS_GLOBAL_INTS, - ATHENA_ALARM_PLIC = 100 + OFFSET_TO_MSS_GLOBAL_INTS, - ATHENA_BUS_ERROR_PLIC = 101 + OFFSET_TO_MSS_GLOBAL_INTS, - USOC_AXIC_US_PLIC = 102 + OFFSET_TO_MSS_GLOBAL_INTS, - USOC_AXIC_DS_PLIC = 103 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_0_PLIC = 105 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_1_PLIC = 106 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_2_PLIC = 107 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_3_PLIC = 108 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_4_PLIC = 109 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_5_PLIC = 110 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_6_PLIC = 111 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_7_PLIC = 112 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_8_PLIC = 113 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_9_PLIC = 114 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_10_PLIC = 115 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_11_PLIC = 116 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_12_PLIC = 117 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_13_PLIC = 118 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_14_PLIC = 119 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_15_PLIC = 120 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_16_PLIC = 121 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_17_PLIC = 122 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_18_PLIC = 123 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_19_PLIC = 124 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_20_PLIC = 125 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_21_PLIC = 126 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_22_PLIC = 127 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_23_PLIC = 128 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_24_PLIC = 129 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_25_PLIC = 130 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_26_PLIC = 131 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_27_PLIC = 132 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_28_PLIC = 133 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_29_PLIC = 134 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_30_PLIC = 135 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_31_PLIC = 136 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_32_PLIC = 137 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_33_PLIC = 138 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_34_PLIC = 139 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_35_PLIC = 140 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_36_PLIC = 141 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_37_PLIC = 142 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_38_PLIC = 143 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_39_PLIC = 144 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_40_PLIC = 145 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_41_PLIC = 146 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_42_PLIC = 147 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_43_PLIC = 148 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_44_PLIC = 149 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_45_PLIC = 150 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_46_PLIC = 151 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_47_PLIC = 152 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_48_PLIC = 153 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_49_PLIC = 154 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_50_PLIC = 155 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_51_PLIC = 156 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_52_PLIC = 157 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_53_PLIC = 158 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_54_PLIC = 159 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_55_PLIC = 160 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_56_PLIC = 161 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_57_PLIC = 162 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_58_PLIC = 163 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_59_PLIC = 164 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_60_PLIC = 165 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_61_PLIC = 166 + OFFSET_TO_MSS_GLOBAL_INTS, - - FABRIC_F2H_62_PLIC = 167 + OFFSET_TO_MSS_GLOBAL_INTS, - FABRIC_F2H_63_PLIC = 168 + OFFSET_TO_MSS_GLOBAL_INTS, - - BUS_ERROR_UNIT_HART_0 = 182, - BUS_ERROR_UNIT_HART_1 = 183, - BUS_ERROR_UNIT_HART_2 = 184, - BUS_ERROR_UNIT_HART_3 = 185, - BUS_ERROR_UNIT_HART_4 = 186 - -#else - INVALID_IRQn = 0, - L2Cache_0_PLIC_1 = 1, - L2Cache_1_PLIC_2 = 2, - L2Cache_2__PLIC_3 = 3, - USART0_PLIC_4 = 4, - USART1_PLIC_5 = 5, - QSPI_12_PLIC_6 = 6, - - gpio_PLIC_7 = 7, - gpio_PLIC_8 = 8, - gpio_PLIC_9 = 9, - gpio_10 = 10, - gpio_11 = 11, - gpio_12 = 12, - gpio_PLIC_13 = 13, - gpio_PLIC_14 = 14, - gpio_PLIC_15 = 15, - gpio_PLIC_16 = 16, - gpio_PLIC_17 = 17, - gpio_PLIC_18 = 18, - gpio_PLIC_19 = 19, - gpio_PLIC_20 = 20, - gpio_PLIC_21 = 21, - gpio_PLIC_22 = 22, - - dma_PLIC_23 = 23, - dma_PLIC_24 = 24, - dma_PLIC_25 = 25, - dma_PLIC_26 = 26, - dma_PLIC_27 = 27, - dma_PLIC_28 = 28, - dma_PLIC_29 = 29, - dma_PLIC_30 = 30, - - ddr_subsytem_PLIC_31 = 31, - - chiplink_msi_PLIC_32 = 32, - chiplink_msi_PLIC_33 = 33, - chiplink_msi_PLIC_34 = 34, - chiplink_msi_PLIC_35 = 35, - chiplink_msi_PLIC_36 = 36, - chiplink_msi_PLIC_37 = 37, - chiplink_msi_PLIC_38 = 38, - chiplink_msi_PLIC_39 = 39, - chiplink_msi_PLIC_40 = 40, - chiplink_msi_PLIC_41 = 41, - - pwm0_PLIC_42 = 42, - pwm0_PLIC_43 = 43, - pwm0_PLIC_44 = 44, - pwm0_PLIC_45 = 45, - - pwm1_PLIC_46 = 46, - pwm1_PLIC_47 = 47, - pwm1_PLIC_48 = 48, - pwm1_PLIC_49 = 49, - - i2c_PLIC_50 = 50, - QSPI0_PLIC_51 = 51, - QSPI1_PLIC_52 = 52, - ethernet_PLIC_53 = 53 - -#endif + E51_0_MAINTENACE_INT_OFFSET = 86 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_WDOG0_MRVP_INT_OFFSET = 87 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG1_MRVP_INT_OFFSET = 88 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG2_MRVP_INT_OFFSET = 89 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG3_MRVP_INT_OFFSET = 90 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG4_MRVP_INT_OFFSET = 91 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG0_TOUT_INT_OFFSET = 92 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG1_TOUT_INT_OFFSET = 93 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG2_TOUT_INT_OFFSET = 94 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG3_TOUT_INT_OFFSET = 95 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_WDOG4_TOUT_INT_OFFSET = 96 + OFFSET_TO_MSS_GLOBAL_INTS, + G5C_MSS_SPI_INT_OFFSET = 97 + OFFSET_TO_MSS_GLOBAL_INTS, + VOLT_TEMP_ALARM_INT_OFFSET = 98 + OFFSET_TO_MSS_GLOBAL_INTS, + ATHENA_COMPLETE_INT_OFFSET = 99 + OFFSET_TO_MSS_GLOBAL_INTS, + ATHENA_ALARM_INT_OFFSET = 100 + OFFSET_TO_MSS_GLOBAL_INTS, + ATHENA_BUS_ERROR_INT_OFFSET = 101 + OFFSET_TO_MSS_GLOBAL_INTS, + USOC_AXIC_US_INT_OFFSET = 102 + OFFSET_TO_MSS_GLOBAL_INTS, + USOC_AXIC_DS_INT_OFFSET = 103 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_0_INT_OFFSET = 105 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_1_INT_OFFSET = 106 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_2_INT_OFFSET = 107 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_3_INT_OFFSET = 108 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_4_INT_OFFSET = 109 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_5_INT_OFFSET = 110 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_6_INT_OFFSET = 111 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_7_INT_OFFSET = 112 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_8_INT_OFFSET = 113 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_9_INT_OFFSET = 114 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_10_INT_OFFSET = 115 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_11_INT_OFFSET = 116 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_12_INT_OFFSET = 117 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_13_INT_OFFSET = 118 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_14_INT_OFFSET = 119 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_15_INT_OFFSET = 120 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_16_INT_OFFSET = 121 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_17_INT_OFFSET = 122 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_18_INT_OFFSET = 123 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_19_INT_OFFSET = 124 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_20_INT_OFFSET = 125 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_21_INT_OFFSET = 126 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_22_INT_OFFSET = 127 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_23_INT_OFFSET = 128 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_24_INT_OFFSET = 129 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_25_INT_OFFSET = 130 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_26_INT_OFFSET = 131 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_27_INT_OFFSET = 132 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_28_INT_OFFSET = 133 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_29_INT_OFFSET = 134 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_30_INT_OFFSET = 135 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_31_INT_OFFSET = 136 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_32_INT_OFFSET = 137 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_33_INT_OFFSET = 138 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_34_INT_OFFSET = 139 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_35_INT_OFFSET = 140 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_36_INT_OFFSET = 141 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_37_INT_OFFSET = 142 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_38_INT_OFFSET = 143 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_39_INT_OFFSET = 144 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_40_INT_OFFSET = 145 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_41_INT_OFFSET = 146 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_42_INT_OFFSET = 147 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_43_INT_OFFSET = 148 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_44_INT_OFFSET = 149 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_45_INT_OFFSET = 150 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_46_INT_OFFSET = 151 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_47_INT_OFFSET = 152 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_48_INT_OFFSET = 153 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_49_INT_OFFSET = 154 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_50_INT_OFFSET = 155 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_51_INT_OFFSET = 156 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_52_INT_OFFSET = 157 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_53_INT_OFFSET = 158 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_54_INT_OFFSET = 159 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_55_INT_OFFSET = 160 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_56_INT_OFFSET = 161 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_57_INT_OFFSET = 162 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_58_INT_OFFSET = 163 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_59_INT_OFFSET = 164 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_60_INT_OFFSET = 165 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_61_INT_OFFSET = 166 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_F2M_62_INT_OFFSET = 167 + OFFSET_TO_MSS_GLOBAL_INTS, + PLIC_F2M_63_INT_OFFSET = 168 + OFFSET_TO_MSS_GLOBAL_INTS, + + PLIC_E51_BUS_ERROR_UNIT_OFFSET = 182, + PLIC_U54_1_BUS_ERROR_UNIT_OFFSET = 183, + PLIC_U54_2_BUS_ERROR_UNIT_OFFSET = 184, + PLIC_U54_3_BUS_ERROR_UNIT_OFFSET = 185, + PLIC_U54_4_BUS_ERROR_UNIT_OFFSET = 186 } PLIC_IRQn_Type; -#ifndef SIFIVE_HIFIVE_UNLEASHED -#define MAX_PLIC_INT BUS_ERROR_UNIT_HART_4 -#else -#define MAX_PLIC_INT ethernet_PLIC_53 -#endif - -/***************************************************************************//** - * E51-0 is Maintenance Interrupt, CPU needs to read status register to - * determine exact cause: - * This structure added here for clarity, need to replay with status register - * defines for determining interrupt cause - */ -typedef enum -{ - mpu_fail_plic =0, - lp_state_enter_plic =1, - lp_state_exit_plic =2, - ff_start_plic =3, - ff_end_plic =4, - fpga_on_plic =5, - fpga_off_plic =6, - scb_error_plic =7, - scb_fault_plic =8, - mesh_fail_plic =9 -} PLIC_IRQ86_Type; +#define MAX_PLIC_INT PLIC_U54_4_BUS_ERROR_UNIT_OFFSET typedef struct { @@ -623,17 +473,10 @@ typedef struct volatile uint32_t ENABLES[32U]; } Target_Enables_Type; -#ifndef SIFIVE_HIFIVE_UNLEASHED + #define PLIC_SET_UP_REGISTERS 6U -#else -#define PLIC_SET_UP_REGISTERS 2U -#endif -#ifndef SIFIVE_HIFIVE_UNLEASHED #define PLIC_NUM_SOURCES 187U -#else -#define PLIC_NUM_SOURCES 54U /* 53 actual, source 0 is not used */ -#endif #define PLIC_NUM_PRIORITIES 7U #define NUM_CLAIM_REGS 9U @@ -887,7 +730,7 @@ static inline void PLIC_DisableIRQ(PLIC_IRQn_Type IRQn) */ static inline void PLIC_SetPriority(PLIC_IRQn_Type IRQn, uint32_t priority) { - if((IRQn > INVALID_IRQn) && (IRQn < PLIC_NUM_SOURCES)) + if((IRQn > PLIC_INVALID_INT_OFFSET) && (IRQn < PLIC_NUM_SOURCES)) { PLIC->SOURCE_PRIORITY[IRQn-1] = priority; } @@ -901,7 +744,7 @@ static inline uint32_t PLIC_GetPriority(PLIC_IRQn_Type IRQn) { uint32_t ret_val = 0U; - if((IRQn > INVALID_IRQn) && (IRQn < PLIC_NUM_SOURCES)) + if((IRQn > PLIC_INVALID_INT_OFFSET) && (IRQn < PLIC_NUM_SOURCES)) { ret_val = PLIC->SOURCE_PRIORITY[IRQn-1]; } @@ -969,7 +812,7 @@ static inline void PLIC_ClearPendingIRQ(void) volatile uint32_t int_num = PLIC_ClaimIRQ(); volatile int32_t wait_possible_int; - while ( int_num != INVALID_IRQn) + while ( int_num != PLIC_INVALID_INT_OFFSET) { PLIC_CompleteIRQ(int_num); wait_possible_int = 0xFU; diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.c index 2e21f5bb..cbf20720 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -132,10 +132,10 @@ uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */ #if ((LIBERO_SETTING_MEM_CONFIGS_ENABLED & PMP_ENABLED_MASK) == PMP_ENABLED_MASK) uint64_t pmp0cfg; #endif - /* make sure enables are off */ + /* make sure enables are off */ write_csr(pmpcfg0, 0); write_csr(pmpcfg2, 0); - /* set required addressing */ + /* set required addressing */ write_csr(pmpaddr0, pmp_values[hart_id][2]); write_csr(pmpaddr1, pmp_values[hart_id][3]); write_csr(pmpaddr2, pmp_values[hart_id][4]); @@ -157,6 +157,8 @@ uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */ pmp_master_configs(hart_id, &pmp0cfg); write_csr(pmpcfg0, pmp0cfg); write_csr(pmpcfg2, pmp_values[hart_id][1]); +#else + write_csr(pmpcfg0, pmp_values[hart_id][0]); #endif return(0); diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.h index d4319a04..f9dfd528 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_pmp.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -59,7 +59,7 @@ extern "C" { #define CONTEXT_EN_MASK_GPIO1 (1U<<20) #define CONTEXT_EN_MASK_GPIO2 (1U<<21) #define CONTEXT_EN_MASK_RTC (1U<<22) -#define CONTEXT_EN_MASK_H2FINT (1U<<23) +#define CONTEXT_EN_MASK_M2FINT (1U<<23) #define CONTEXT_EN_MASK_CRYPTO (1U<<24) #define CONTEXT_EN_MASK_USB (1U<<25) #define CONTEXT_EN_MASK_QSPIXIP (1U<<26) diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_seg.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_seg.h index 32534501..2e518503 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_seg.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_seg.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h index 7a255e25..b72f0baf 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -138,29 +138,31 @@ extern "C" { #define RESET_SR_OFFSET 0x20 /* Reset was caused by the SCB periphery reset signal*/ #define RESET_SR_SCB_PERIPH_RESET_OFFSET 0x0 - #define RESET_SR_SCB_PERIPH_RESET_MASK (0x01 << 0x0) + #define RESET_SR_SCB_PERIPH_RESET_MASK (0x01 << RESET_SR_SCB_PERIPH_RESET_OFFSET) /* Reset was caused by the SCB MSS reset register*/ #define RESET_SR_SCB_MSS_RESET_OFFSET 0x1 - #define RESET_SR_SCB_MSS_RESET_MASK (0x01 << 0x1) + #define RESET_SR_SCB_MSS_RESET_MASK (0x01 << RESET_SR_SCB_MSS_RESET_OFFSET) /* Reset was caused by the SCB CPU reset register*/ #define RESET_SR_SCB_CPU_RESET_OFFSET 0x2 - #define RESET_SR_SCB_CPU_RESET_MASK (0x01 << 0x2) + #define RESET_SR_SCB_CPU_RESET_MASK (0x01 << RESET_SR_SCB_CPU_RESET_OFFSET) /* Reset was caused by the Risc-V Debugger*/ #define RESET_SR_DEBUGER_RESET_OFFSET 0x3 - #define RESET_SR_DEBUGER_RESET_MASK (0x01 << 0x3) + #define RESET_SR_DEBUGER_RESET_MASK (0x01 << RESET_SR_DEBUGER_RESET_OFFSET) /* Reset was caused by the fabric*/ #define RESET_SR_FABRIC_RESET_OFFSET 0x4 - #define RESET_SR_FABRIC_RESET_MASK (0x01 << 0x4) + #define RESET_SR_FABRIC_RESET_MASK (0x01 << RESET_SR_FABRIC_RESET_OFFSET) /* Reset was caused by the watchdog*/ #define RESET_SR_WDOG_RESET_OFFSET 0x5 - #define RESET_SR_WDOG_RESET_MASK (0x01 << 0x5) + #define RESET_SR_WDOG_RESET_MASK (0x01 << RESET_SR_WDOG_RESET_OFFSET) /* Indicates that fabric asserted the GPIO reset inputs*/ #define RESET_SR_GPIO_RESET_OFFSET 0x6 - #define RESET_SR_GPIO_RESET_MASK (0x01 << 0x6) + #define RESET_SR_GPIO_RESET_MASK (0x01 << RESET_SR_GPIO_RESET_OFFSET) /* Indicates that SCB bus reset occurred (which causes warm reset of MS S)*/ #define RESET_SR_SCB_BUS_RESET_OFFSET 0x7 - #define RESET_SR_SCB_BUS_RESET_MASK (0x01 << 0x7) + #define RESET_SR_SCB_BUS_RESET_MASK (0x01 << RESET_SR_SCB_BUS_RESET_OFFSET) + #define RESET_SR_CPU_SOFT_RESET_OFFSET 0x8 + #define RESET_SR_CPU_SOFTCB_BUS_RESET_MASK (0x01 << RESET_SR_CPU_SOFT_RESET_OFFSET) /*Indicates the device status in particular the state of the FPGA fabric an d the MSS IO banks*/ @@ -200,25 +202,25 @@ extern "C" { /*U54-1 Fabric interrupt enable*/ #define FAB_INTEN_U54_1_OFFSET 0x40 - /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ + /* Enables the F2M_interrupts[31:0] to interrupt U54_1 directly*/ #define FAB_INTEN_U54_1_ENABLE_OFFSET 0x0 #define FAB_INTEN_U54_1_ENABLE_MASK (0xFFFFFFFF << 0x0) /*U54-2 Fabric interrupt enable*/ #define FAB_INTEN_U54_2_OFFSET 0x44 - /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ + /* Enables the F2M_interrupts[31:0] to interrupt U54_1 directly*/ #define FAB_INTEN_U54_2_ENABLE_OFFSET 0x0 #define FAB_INTEN_U54_2_ENABLE_MASK (0xFFFFFFFF << 0x0) /*U54-3 Fabric interrupt enable*/ #define FAB_INTEN_U54_3_OFFSET 0x48 - /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ + /* Enables the F2M_interrupts[31:0] to interrupt U54_1 directly*/ #define FAB_INTEN_U54_3_ENABLE_OFFSET 0x0 #define FAB_INTEN_U54_3_ENABLE_MASK (0xFFFFFFFF << 0x0) /*U54-4 Fabric interrupt enable*/ #define FAB_INTEN_U54_4_OFFSET 0x4C - /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ + /* Enables the F2M_interrupts[31:0] to interrupt U54_1 directly*/ #define FAB_INTEN_U54_4_ENABLE_OFFSET 0x0 #define FAB_INTEN_U54_4_ENABLE_MASK (0xFFFFFFFF << 0x0) @@ -323,8 +325,8 @@ extern "C" { #define APBBUS_CR_RTC_OFFSET 0x16 #define APBBUS_CR_RTC_MASK (0x01 << 0x16) /* */ - #define APBBUS_CR_H2FINT_OFFSET 0x17 - #define APBBUS_CR_H2FINT_MASK (0x01 << 0x17) + #define APBBUS_CR_M2FINT_OFFSET 0x17 + #define APBBUS_CR_M2FINT_MASK (0x01 << 0x17) /*"Enables the clock to the MSS peripheral. By turning clocks off dynamic power can be saved. When the clock is off the peripheral should not be accessed @@ -3506,49 +3508,49 @@ extern "C" { #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_BYPASS_EN_OFFSET 0x1E #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_BYPASS_EN_MASK (0x01 << 0x1E) -/*Sets H2F [31:0] Spares out signals*/ +/*Sets M2F [31:0] Spares out signals*/ #define MSS_SPARE0_CR_OFFSET 0x2A8 /* See MSS MAS specification for full description*/ #define MSS_SPARE0_CR_DATA_OFFSET 0x0 #define MSS_SPARE0_CR_DATA_MASK (0xFFFFFFFF << 0x0) -/*Sets H2F [37:32] Spares out signals*/ +/*Sets M2F [37:32] Spares out signals*/ #define MSS_SPARE1_CR_OFFSET 0x2AC /* See MSS MAS specification for full description*/ #define MSS_SPARE1_CR_DATA_OFFSET 0x0 #define MSS_SPARE1_CR_DATA_MASK (0x3F << 0x0) -/*Read H2F [31:0] Spares out signals*/ +/*Read M2F [31:0] Spares out signals*/ #define MSS_SPARE0_SR_OFFSET 0x2B0 /* See MSS MAS specification for full description*/ #define MSS_SPARE0_SR_DATA_OFFSET 0x0 #define MSS_SPARE0_SR_DATA_MASK (0xFFFFFFFF << 0x0) -/*Read H2F [37:32] Spares out signals*/ +/*Read M2F [37:32] Spares out signals*/ #define MSS_SPARE1_SR_OFFSET 0x2B4 /* See MSS MAS specification for full description*/ #define MSS_SPARE1_SR_DATA_OFFSET 0x0 #define MSS_SPARE1_SR_DATA_MASK (0x3F << 0x0) -/*Read F2H [31:0] Spares in1 signals*/ +/*Read F2M [31:0] Spares in1 signals*/ #define MSS_SPARE2_SR_OFFSET 0x2B8 /* See MSS MAS specification for full description*/ #define MSS_SPARE2_SR_DATA_OFFSET 0x0 #define MSS_SPARE2_SR_DATA_MASK (0xFFFFFFFF << 0x0) -/*Read F2H [37:32] Spares in1 signals*/ +/*Read F2M [37:32] Spares in1 signals*/ #define MSS_SPARE3_SR_OFFSET 0x2BC /* See MSS MAS specification for full description*/ #define MSS_SPARE3_SR_DATA_OFFSET 0x0 #define MSS_SPARE3_SR_DATA_MASK (0x3F << 0x0) -/*Read F2H [31:0] Spares in2 signals*/ +/*Read F2M [31:0] Spares in2 signals*/ #define MSS_SPARE4_SR_OFFSET 0x2C0 /* See MSS MAS specification for full description*/ #define MSS_SPARE4_SR_DATA_OFFSET 0x0 #define MSS_SPARE4_SR_DATA_MASK (0xFFFFFFFF << 0x0) -/*Read F2H [37:32] Spares in2 signals*/ +/*Read F2M [37:32] Spares in2 signals*/ #define MSS_SPARE5_SR_OFFSET 0x2C4 /* See MSS MAS specification for full description*/ #define MSS_SPARE5_SR_DATA_OFFSET 0x0 @@ -4002,28 +4004,28 @@ typedef struct _mss_sysreg __I uint32_t RESERVEDREG32B_81; __I uint32_t RESERVEDREG32B_82; - /*Sets H2F [31:0] Spares out signals*/ + /*Sets M2F [31:0] Spares out signals*/ __IO uint32_t MSS_SPARE0_CR; - /*Sets H2F [37:32] Spares out signals*/ + /*Sets M2F [37:32] Spares out signals*/ __IO uint32_t MSS_SPARE1_CR; - /*Read H2F [31:0] Spares out signals*/ + /*Read M2F [31:0] Spares out signals*/ __IO uint32_t MSS_SPARE0_SR; - /*Read H2F [37:32] Spares out signals*/ + /*Read M2F [37:32] Spares out signals*/ __IO uint32_t MSS_SPARE1_SR; - /*Read F2H [31:0] Spares in1 signals*/ + /*Read F2M [31:0] Spares in1 signals*/ __IO uint32_t MSS_SPARE2_SR; - /*Read F2H [37:32] Spares in1 signals*/ + /*Read F2M [37:32] Spares in1 signals*/ __IO uint32_t MSS_SPARE3_SR; - /*Read F2H [31:0] Spares in2 signals*/ + /*Read F2M [31:0] Spares in2 signals*/ __IO uint32_t MSS_SPARE4_SR; - /*Read F2H [37:32] Spares in2 signals*/ + /*Read F2M [37:32] Spares in2 signals*/ __IO uint32_t MSS_SPARE5_SR; /* Padding reserved 32-bit registers.*/ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.c index cb706149..5e5d503f 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -74,9 +74,36 @@ void __enable_irq(void) */ void __enable_local_irq(uint8_t local_interrupt) { + ASSERT(local_interrupt > (int8_t)0); + ASSERT( (local_interrupt <= LOCAL_INT_MAX)); + + uint8_t mhart_id = (uint8_t)read_csr(mhartid); + if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX)) { - set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */ + + set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */ + + /* Enable F2M interrupts as local instead of PLIC interrupts */ + if (local_interrupt >= LOCAL_INT_F2M_OFFSET) + { + if (mhart_id == 1) + { + SYSREG->FAB_INTEN_U54_1 |= (1u << (local_interrupt - LOCAL_INT_F2M_OFFSET)); + } + else if (mhart_id == 2) + { + SYSREG->FAB_INTEN_U54_2 |= (1u << (local_interrupt - LOCAL_INT_F2M_OFFSET)); + } + else if (mhart_id == 3) + { + SYSREG->FAB_INTEN_U54_3 |= (1u << (local_interrupt - LOCAL_INT_F2M_OFFSET)); + } + else if (mhart_id == 4) + { + SYSREG->FAB_INTEN_U54_4 |= (1u << (local_interrupt - LOCAL_INT_F2M_OFFSET)); + } + } } } @@ -85,9 +112,12 @@ void __enable_local_irq(uint8_t local_interrupt) */ void __disable_local_irq(uint8_t local_interrupt) { + ASSERT(local_interrupt > (int8_t)0); + ASSERT( (local_interrupt <= LOCAL_INT_MAX)); + if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX)) { - clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */ + clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */ } } @@ -161,53 +191,6 @@ uint64_t get_tp_reg(void) return (tp_reg_val); } -/** - * mpfs_sync_bool_compare_and_swap() - * this works on the E51 / U54s, and operates equivalently to the - * __sync_bool_compare_and_swap() intrinsic. - * @param ptr - * @param oldval - * @param newval - * @return - */ -bool mpfs_sync_bool_compare_and_swap(volatile long *ptr, long oldval, long newval) -{ - static long lock = 0; - bool result = false; - - if (!__sync_lock_test_and_set(&lock, 1)) { // amoswap.d.aq - if (*ptr == oldval) { - *ptr = newval; - } - - __sync_lock_release(&lock); // fence iorw,ow; ampswap.d - result = true; - } - - return result; -} - -/** - * mpfs_sync_val_compare_and_swap() - * this works on the E51 / U54s, and operates equivalently to the - * __sync_val_compare_and_swap() intrinsic. It works by using a separate - * static lock, and then emulating the behaviour of the lr.w.aq instruction - * Required as lr/sr instructions are not supported on the E51 and are only - * supported on L1 cached back memory types. These limitations are not present - * with this function. - * @param ptr - * @param oldval - * @param newval - */ -long mpfs_sync_val_compare_and_swap(volatile long *ptr, long oldval, long newval) -{ - long result = *ptr; - - (void)mpfs_sync_bool_compare_and_swap(ptr, oldval, newval); - - return result; -} - #ifdef PRINTF_DEBUG_SUPPORTED void display_address_of_interest(uint64_t * address_of_interest, int nb_locations) { uint64_t * p_addr_of_interest = address_of_interest; @@ -221,6 +204,24 @@ void display_address_of_interest(uint64_t * address_of_interest, int nb_location } #endif +/*------------------------------------------------------------------------------ + * This function disables dynamic branch prediction on the hart from which it + * executes. It is enabled by default. + */ +void disable_branch_prediction(void) +{ + write_csr(0x7C0, 0x1u); +} + +/*------------------------------------------------------------------------------ + * This function enables dynamic branch prediction on the hart from which it + * executes. + */ +void enable_branch_prediction(void) +{ + write_csr(0x7C0, 0x0u); +} + #ifdef __cplusplus } #endif diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.h index a418faae..957f26c0 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/mss_util.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -37,6 +37,12 @@ extern "C" { #define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y)) #define READ_REG64(x) (*((volatile uint64_t *)(x))) +/* + * Local defines + */ +#define LOCAL_INT_OFFSET_IN_MIE 16U /* Offset from start of MIE for local irq enables */ +#define LOCAL_INT_F2M_OFFSET 16U /* Offset from 0 for fabric to MSS local interrupts */ + /* * return mcycle */ @@ -64,24 +70,26 @@ void __disable_all_irqs(void); void __enable_irq(void); void __enable_local_irq(uint8_t local_interrupt); void __disable_local_irq(uint8_t local_interrupt); +void disable_branch_prediction(void); +void enable_branch_prediction(void); -bool mpfs_sync_bool_compare_and_swap(volatile long *ptr, long oldval, long newval); -long mpfs_sync_val_compare_and_swap(volatile long *ptr, long oldval, long newval); - -static inline void spinunlock(volatile long *lock) +static inline void spinunlock(volatile long *pLock) { - *lock = 0; + __sync_lock_release(pLock); } -static inline void spinlock(volatile long *lock) +static inline void spinlock(volatile long *pLock) { - while(!mpfs_sync_bool_compare_and_swap(lock, 0, 1)) + while(__sync_lock_test_and_set(pLock, 1)) { /* add yield if OS */ +#if defined USING_FREERTOS + taskYIELD(); +#endif } - *lock = 1; } + #ifdef __cplusplus } #endif diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c index 3ad42107..8bd4b381 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * */ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.h index 1429da6c..13abecbc 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * */ /*=========================================================================*//** diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c index 6dce7432..c67539a2 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -13,9 +13,14 @@ * @brief DDR related code * */ +//#define PRINT_CA_VREF_WINDOW "1" +#define MOVE_CK +#define MANUAL_ADDCMD_TRAINIG +//#define FABRIC_NOISE_TEST #include #include #include "mpfs_hal/mss_hal.h" +#include "mss_nwc_init.h" #ifdef DDR_SUPPORT #include "mss_ddr_debug.h" #include "simulation.h" @@ -27,8 +32,80 @@ * Local Defines */ /* This string is updated if any change to ddr driver */ -#define DDR_DRIVER_VERSION_STRING "0.2.003" +#define DDR_DRIVER_VERSION_STRING "0.4.019" +const char DDR_DRIVER_VERSION[] = DDR_DRIVER_VERSION_STRING; /* Version | Comment */ +/* 0.4.019 | Added full memory initalization function */ +/* 0.4.018 | Corrected error introduced for DDR3 in 0.4.14 */ +/* 0.4.017 | made SW_TRAING_BCLK_SCLK_OFFSET seperate for each mem type */ +/* 0.4.016 | DDR3-Added support for DDR3L removed in v0.3.027 */ +/* | Corrected dpc value update during write leveling */ +/* 0.4.015 | Added some debug feedback in verify state. */ +/* 0.4.014 | Tidy-up, replace some majic numbers.No functional change. */ +/* 0.4.013 | ddr3- Corrected dpc value update during write leveling */ +/* 0.4.012 | ADD_CMD_CLK_MOVE_ORDER 0,1,2 for 1333Mhz, 1,2,0 for 1600MHz */ +/* | LIBERO_SETTING_RPC_156_VALUE 1 for 1333Mhz, 6 for 1600MHz */ +/* 0.4.011 | ADD_CMD_CLK_MOVE_ORDER changed from 0,1,2 to 1,2,0 */ +/* 0.4.010 | LIBERO_SETTING_RPC_156_VALUE default changed from 1 to 6 */ +/* 0.4.009 | vrgen, modify during write leveling for DDR3 corrected */ +/* 0.4.008 | DQ/DQS push order has been parameterised */ +/* 0.4.007 | Corrected write_latency print message */ +/* 0.4.006 | Refactored delay() routine, skips extra checking in write */ +/* | calibration once a failure has occured to shorten training */ +/* | time. */ +/* 0.4.005 | When LIBERO_FAST_START, now slects random as opposed to */ +/* | counting pattern. */ +/* 0.4.004 | Upadted tip_register_status() to show dual ranks */ +/* 0.4.003 | Added FAST_START option - can reduce post training checks */ +/* 0.4.002 | Added stat recording ddr training time */ +/* 0.4.001 | Fixed DDR3 DDR_1333_MHZ define to match Libero gen version */ +/* 0.4.000 | corrected incorrect offset introduced in last commit */ +/* 0.3.030 | Added setting of rpc136, required for board tuning to pass */ +/* | DQ/DQS Window when too small. Moves test start from the */ +/* | starting edge. */ +/* 0.3.029 | LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS changed 2 to 1 */ +/* 0.3.028 | ddr3_address_cmd_training() routine added */ +/* 0.3.027 | ddr3 mod- vrgen, modify during write leveling */ +/* 0.3.026 | SW_TRAING_BCLK_SCLK_OFFSET changed from 0 to 5 */ +/* 0.3.025 | LPDDR4@1600 ref clk offsets 4,3,2,4 changed to 3,4,2,5 */ +/* 0.3.024 | lpddr4_manual_training() improved */ +/* 0.3.023 | Changing the common mode of the Receiver to low common mode */ +/* 0.3.022 | DDR_VERIFY_PATTERN_IN_CACHE added tests */ +/* 0.3.021 | Turn off ODT during write leveling */ +/* 0.3.020 | added for retrain reset */ +/* 0.3.019 | SAR122487 training not converging at 125C Min condition on */ +/* | rev-c devices. */ +/* 0.3.018 | SAR121393 relates to DDR3 robustness when ECC not being used*/ +/* | Note: DDR3 with no ECC only affected varient */ +/* 0.3.017 | Removed some warnings, some tidy-up, removed sweep code */ +/* | as not being used. */ +/* | restriced INIT_AUTOINIT_DISABLE=0x1; in DDR_TRAINING_RESET */ +/* | state to lpddr4 only, as only in lpddr4 DCT version */ +/* | and causes issue for DDR3 */ +/* 0.3.016 | Multiple LPDDR4 updates. */ +/* 0.3.015 | REFCLK change for LPDDR3, rpc168 = 0x0U for LPDDR3 */ +/* 0.3.014 | DDR3 WPU/WPD overridden, REFCLK (0,1) -> (7,0) */ +/* 0.3.013 | DDR4 refclk offsets updated by dct */ +/* 0.3.012 | DDR Controller reset toggled on start-up, DDR refclk */ +/* | default offsets updated */ +/* 0.3.011 | Update to DDR4 ADD CMD sweep @800 <0,7,1> to <7,0> */ +/* 0.3.010 | Update to LPDDR4 ADD CMD sweep values <5,4,6,3> to <1,5,1,5>*/ +/* 0.3.009 | Corrected refclk_offset used for lower frequecies */ +/* | See function: ddr_manual_addcmd_refclk_offset() */ +/* 0.3.008 | Removed weak rand() function, which continually returned 0 */ +/* 0.3.007 | Updated DDR3 add cmd offsets */ +/* | Updated DDR4 add cmd offsets */ +/* 0.3.006 | modified debug printing after failure */ +/* 0.3.005 | modified addcmd offsets DDR3/DDR3L @ 1333 = 0,1 */ +/* | DDR3/DDR3L to 0,1 */ +/* | Also some ADD CMD training improvments from Jaswanth */ +/* 0.3.004 | Removed dq setting before claibration for DDR3/4 and lpddr3 */ +/* | Some tidy up */ +/* 0.3.003 | Modified latency sweep from 0-8 to 0-3. Speeded u[p MCC test*/ +/* | when faulure */ +/* 0.3.002 | Move refclk offset outside manual training loop */ +/* 0.3.001 | wip - adding in manual add cmd training */ +/* 0.3.000 | wip - adding in manual add cmd training */ /* 0.2.003 | Updated SEG setup to match Libero 12.7, Removed warnings, */ /* | shortened timeout in mtc_test */ /* 0.2.002 | MTC_test() update -added more tests */ @@ -56,12 +133,18 @@ * Calibration data records calculated write calibration values during training */ mss_ddr_calibration calib_data; +mss_ddr_diag ddr_diag; /* rx lane FIFO used for tuning */ #if (TUNE_RPC_166_VALUE == 1) static uint32_t rpc_166_fifo_offset; #endif +/* auto tunes rpc156 when enabled */ +#ifdef TUNE_RPC_156_DQDQS_INIT_VALUE +static uint32_t rpc_156_dqdqs_init_offset = LIBERO_SETTING_MIN_RPC_156_VALUE; +#endif + /* * This string is used as a quick sanity check of write/read to DDR. * The memory test core is used for more comprehensive testing during and @@ -77,27 +160,18 @@ static const uint32_t test_string[] = { /******************************************************************************* * external functions */ -#ifdef DEBUG_DDR_INIT -extern mss_uart_instance_t *g_debug_uart; -extern uint32_t tip_register_status (mss_uart_instance_t *g_mss_uart_debug_pt); -#endif /* Use to record instance of errors during calibration */ static uint32_t ddr_error_count; -#ifdef SWEEP_ENABLED -uint8_t sweep_results[MAX_NUMBER_DPC_VS_GEN_SWEEPS]\ - [MAX_NUMBER_DPC_H_GEN_SWEEPS]\ - [MAX_NUMBER_DPC_V_GEN_SWEEPS]\ - [MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS]\ - [MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS]; -#define TOTAL_SWEEPS (MAX_NUMBER_DPC_H_GEN_SWEEPS*MAX_NUMBER_DPC_H_GEN_SWEEPS*\ - MAX_NUMBER_DPC_V_GEN_SWEEPS*MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS*\ - MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS) -#endif /******************************************************************************* * Local function declarations */ +#ifdef ZQ_CAL +static uint32_t zq_cal(void); +#endif +static uint32_t mode_register_masked_write(uint32_t address); +static uint32_t mode_register_masked_write_x5(uint32_t address); static uint32_t ddr_setup(void); static void init_ddrc(void); static uint8_t write_calibration_using_mtc(uint8_t num_of_lanes_to_calibrate); @@ -114,6 +188,9 @@ static uint8_t mtc_sanity_check(uint64_t start_address); #ifdef SET_VREF_LPDDR4_MODE_REGS static uint8_t mode_register_write(uint32_t MR_ADDR, uint32_t MR_DATA); #endif +#ifdef MODE_WRITE1_USED +static uint32_t mode_register_write1(uint32_t address, uint32_t data); +#endif #ifdef DDR_SANITY_CHECKS_EN static uint8_t memory_tests(void); #endif @@ -123,19 +200,18 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type); static uint8_t get_num_lanes(void); static void load_dq(uint8_t lane); static uint8_t use_software_bclk_sclk_training(DDR_TYPE ddr_type); +static uint8_t bclk_sclk_offset(DDR_TYPE ddr_type); static void config_ddr_io_pull_up_downs_rpc_bits(DDR_TYPE ddr_type); -#ifdef SWEEP_ENABLED -static uint8_t get_best_sweep(sweep_index *good_index); -#endif #ifdef MANUAL_ADDCMD_TRAINIG static uint8_t ddr_manual_addcmd_refclk_offset(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index); #endif +static void lpddr4_manual_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index, uint32_t retry_count, uint8_t *refclk_offset); +static void non_lpddr4_address_cmd_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index, uint32_t *bclk_phase, uint32_t *bclk90_phase, uint32_t *refclk_phase ); +static void ddr3_address_cmd_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index, uint32_t retry_count, uint32_t *bclk_phase, uint32_t *bclk90_phase, uint32_t *refclk_phase, uint8_t *refclk_offset); /******************************************************************************* * External function declarations */ -extern void delay(uint32_t n); - #ifdef DEBUG_DDR_INIT extern mss_uart_instance_t *g_debug_uart; #ifdef DEBUG_DDR_DDRCFG @@ -220,15 +296,12 @@ static uint32_t ddr_setup(void) static uint32_t dpc_vrgen_v_value; static uint32_t dpc_vrgen_h_value; static uint32_t dpc_vrgen_vs_value; -#endif -#ifdef SWEEP_ENABLED - static SWEEP_STATES sweep_state = INIT_SWEEP; #endif static uint32_t retry_count; static uint32_t write_latency; static uint32_t tip_cfg_params; static uint32_t dpc_bits; - static uint8_t last_sweep_status; + static uint64_t training_start_cycle; #if (TUNE_RPC_166_VALUE == 1) static uint8_t num_rpc_166_retires = 0U; #endif @@ -240,6 +313,7 @@ static uint32_t ddr_setup(void) DDR_TYPE ddr_type; uint32_t ret_status = 0U; uint8_t number_of_lanes_to_calibrate; + uint64_t mem_size; ddr_type = LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_MASK; @@ -249,6 +323,7 @@ static uint32_t ddr_setup(void) switch (ddr_training_state) { case DDR_TRAINING_INIT: + training_start_cycle = rdcycle(); tip_cfg_params = LIBERO_SETTING_TIP_CFG_PARAMS; dpc_bits = LIBERO_SETTING_DPC_BITS ; write_latency = LIBERO_SETTING_CFG_WRITE_LATENCY_SET; @@ -257,29 +332,15 @@ static uint32_t ddr_setup(void) #endif #ifdef MANUAL_ADDCMD_TRAINIG refclk_offset = LIBERO_SETTING_MAX_MANUAL_REF_CLK_PHASE_OFFSET + 1U; -#endif -#ifdef SWEEP_ENABLED - sweep_state = INIT_SWEEP; #endif ddr_error_count = 0U; error = 0U; memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&ddr_diag,0U,sizeof(ddr_diag)); retry_count = 0U; #ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, "\n\r Start training. TIP_CFG_PARAMS:"\ , LIBERO_SETTING_TIP_CFG_PARAMS); -#endif -#ifdef SWEEP_ENABLED - addr_cmd_value = LIBERO_SETTING_TIP_CFG_PARAMS\ - & ADDRESS_CMD_OFFSETT_MASK; - bclk_sclk_offset_value = (LIBERO_SETTING_TIP_CFG_PARAMS\ - & BCLK_SCLK_OFFSET_MASK)>>BCLK_SCLK_OFFSET_SHIFT; - dpc_vrgen_v_value = (LIBERO_SETTING_DPC_BITS & \ - BCLK_DPC_VRGEN_V_MASK)>>BCLK_DPC_VRGEN_V_SHIFT; - dpc_vrgen_h_value = (LIBERO_SETTING_DPC_BITS & \ - BCLK_DPC_VRGEN_H_MASK)>>BCLK_DPC_VRGEN_H_SHIFT; - dpc_vrgen_vs_value = (LIBERO_SETTING_DPC_BITS & \ - BCLK_DPC_VRGEN_VS_MASK)>>BCLK_DPC_VRGEN_VS_SHIFT; #endif ddr_training_state = DDR_TRAINING_CHECK_FOR_OFFMODE; break; @@ -368,15 +429,7 @@ static uint32_t ddr_setup(void) ddr_training_state = DDR_TRAINING_FAIL; #endif break; - case DDR_SWEEP_AGAIN: - retry_count++; - last_sweep_status = CALIBRATION_PASSED; - #ifdef DEBUG_DDR_INIT - (void)uprint32(g_debug_uart, "\n\r\n\r DDR_SWEEP_AGAIN: ",\ - ddr_training_state); - #endif - ddr_training_state = DDR_CHECK_TRAINING_SWEEP; - break; + case DDR_TRAINING_FAIL: #ifdef DEBUG_DDR_INIT { @@ -385,98 +438,19 @@ static uint32_t ddr_setup(void) } #endif + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; + delay(DELAY_CYCLES_5_MICRO); + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; + delay(DELAY_CYCLES_2MS); retry_count++; - if(last_sweep_status != CALIBRATION_SUCCESS) - { - last_sweep_status = CALIBRATION_FAILED; - } - #ifdef DEBUG_DDR_INIT + ddr_diag.num_retrains = retry_count; +#ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, "\n\r\n\r DDR_TRAINING_FAIL: ",\ ddr_training_state); (void)uprint32(g_debug_uart, "\n\r Retry Count: ", retry_count); - #endif - ddr_training_state = DDR_CHECK_TRAINING_SWEEP; - break; - - case DDR_CHECK_TRAINING_SWEEP: - { -#ifdef SWEEP_ENABLED - /* first check if we are finished */ - if(last_sweep_status == CALIBRATION_SUCCESS) - { - /* - * Try again with calculated values - */ - ddr_training_state = DDR_TRAINING_CHECK_FOR_OFFMODE; - } - else if(retry_count == TOTAL_SWEEPS) - { - sweep_index index; -#ifdef DEBUG_DDR_INIT - sweep_status(g_debug_uart); -#endif - /* - * Choose the best index - */ - if (get_best_sweep(&index) == 0U) - { -#ifdef DEBUG_DDR_INIT - (void)uprint32(g_debug_uart, "\n\r sweep success: ",\ - tip_cfg_params); -#endif - last_sweep_status = CALIBRATION_SUCCESS; - /* - * Use obtained settings - */ - addr_cmd_value = index.cmd_index +\ - LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET; - bclk_sclk_offset_value = index.bclk_sclk_index +\ - LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET; - dpc_vrgen_v_value = index.dpc_vgen_index +\ - LIBERO_SETTING_MIN_DPC_V_GEN; - dpc_vrgen_h_value = index.dpc_vgen_h_index +\ - LIBERO_SETTING_MIN_DPC_H_GEN; - dpc_vrgen_vs_value = index.dpc_vgen_vs_index +\ - LIBERO_SETTING_MIN_DPC_VS_GEN; - - tip_cfg_params = ((tip_cfg_params &\ - (~BCLK_SCLK_OFFSET_MASK))|\ - (bclk_sclk_offset_value<DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; - /* reset controller */ - DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; - CFG_DDR_SGMII_PHY->training_start.training_start = 0x0U; - } -#else /* we are not SWEEP_ENABLED */ + /* Init */ ddr_error_count = 0U; error = 0U; memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); @@ -486,188 +460,6 @@ static uint32_t ddr_setup(void) CFG_DDR_SGMII_PHY->training_start.training_start = 0x0U; ddr_training_state = DDR_TRAINING_CHECK_FOR_OFFMODE; - } -#endif - break; - - case DDR_TRAINING_SWEEP: -#ifdef SWEEP_ENABLED - { - static uint32_t sweep_count_cmd_offset; - static uint32_t sweep_count_bck_sclk; - static uint32_t sweep_count_dpc_v_bits; - static uint32_t sweep_count_dpc_h_bits; - static uint32_t sweep_count_dpc_vs_bits; - - switch(sweep_state) - { - case INIT_SWEEP: - /* - * Parameter values - */ - addr_cmd_value = LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET; - bclk_sclk_offset_value =\ - LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET; - dpc_vrgen_v_value = LIBERO_SETTING_MIN_DPC_V_GEN; - dpc_vrgen_h_value = LIBERO_SETTING_MIN_DPC_H_GEN; - dpc_vrgen_vs_value = LIBERO_SETTING_MIN_DPC_VS_GEN; - /* - * state counts - */ - sweep_count_cmd_offset = 0U; - sweep_count_bck_sclk = 0U; - sweep_count_dpc_v_bits = 0U; - sweep_count_dpc_h_bits = 0U; - sweep_count_dpc_vs_bits = 0U; - sweep_state = ADDR_CMD_OFFSET_SWEEP; - __attribute__((fallthrough)); /* deliberately fall through */ - case ADDR_CMD_OFFSET_SWEEP: - /* - * Record sweep result - */ - sweep_results[sweep_count_dpc_vs_bits][sweep_count_dpc_h_bits][sweep_count_dpc_v_bits]\ - [sweep_count_bck_sclk]\ - [sweep_count_cmd_offset] = last_sweep_status; - /* - * sweep: ADDR_CMD OFFSET - */ - addr_cmd_value++; - if (addr_cmd_value > \ - LIBERO_SETTING_MAX_ADDRESS_CMD_OFFSET) - { - addr_cmd_value = \ - LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET; - } - - tip_cfg_params = ((tip_cfg_params &\ - (~ADDRESS_CMD_OFFSETT_MASK))|(addr_cmd_value)); - sweep_count_cmd_offset++; - if(sweep_count_cmd_offset > MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS) - { - sweep_count_cmd_offset = 0U; - sweep_state = BCLK_SCLK_OFFSET_SWEEP; - } - else - { - /* - * Now do a sweep - */ - ddr_error_count = 0U; - error = 0U; - memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); - DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x00000000U; - /* reset controller */ - DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000000U; - CFG_DDR_SGMII_PHY->training_start.training_start = 0x00000000U; - ddr_training_state = DDR_TRAINING_CHECK_FOR_OFFMODE; - } - break; - case BCLK_SCLK_OFFSET_SWEEP: - /* - * sweep: BCLK_SCLK - */ - bclk_sclk_offset_value++; - if (bclk_sclk_offset_value > \ - LIBERO_SETTING_MAX_ADDRESS_BCLK_SCLK_OFFSET) - { - bclk_sclk_offset_value = \ - LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET; - } - tip_cfg_params = ((tip_cfg_params &\ - (~BCLK_SCLK_OFFSET_MASK))|\ - (bclk_sclk_offset_value< MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS) - { - sweep_count_bck_sclk = 0U; - sweep_state = DPC_VRGEN_V_SWEEP; - } - else - { - sweep_state = ADDR_CMD_OFFSET_SWEEP; - } - break; - case DPC_VRGEN_V_SWEEP: - /* - * sweep: DPC_VRGEN_V [4:6] - * LIBERO_SETTING_DPC_BITS - */ - dpc_vrgen_v_value++; - if (dpc_vrgen_v_value > \ - LIBERO_SETTING_MAX_DPC_V_GEN) - { - dpc_vrgen_v_value = \ - LIBERO_SETTING_MIN_DPC_V_GEN; - } - dpc_bits = ((dpc_bits &\ - (~BCLK_DPC_VRGEN_V_MASK))|\ - (dpc_vrgen_v_value< MAX_NUMBER_DPC_V_GEN_SWEEPS) - { - sweep_count_dpc_v_bits = 0U; - sweep_state = DPC_VRGEN_H_SWEEP; - } - else - { - sweep_state = BCLK_SCLK_OFFSET_SWEEP; - } - break; - case DPC_VRGEN_H_SWEEP: - /* - * sweep: DPC_VRGEN_V [4:6] - * LIBERO_SETTING_DPC_BITS - */ - dpc_vrgen_h_value++; - if (dpc_vrgen_h_value > \ - LIBERO_SETTING_MAX_DPC_H_GEN) - { - dpc_vrgen_h_value = \ - LIBERO_SETTING_MIN_DPC_H_GEN; - } - dpc_bits = ((dpc_bits &\ - (~BCLK_DPC_VRGEN_H_MASK))|\ - (dpc_vrgen_h_value< MAX_NUMBER_DPC_H_GEN_SWEEPS) - { - sweep_count_dpc_h_bits = 0U; - sweep_state = DPC_VRGEN_VS_SWEEP; - } - else - { - sweep_state = DPC_VRGEN_V_SWEEP; - } - break; - case DPC_VRGEN_VS_SWEEP: - /* - * sweep: DPC_VRGEN_V [4:6] - * LIBERO_SETTING_DPC_BITS - */ - dpc_vrgen_vs_value++; - if (dpc_vrgen_vs_value > \ - LIBERO_SETTING_MAX_DPC_VS_GEN) - { - dpc_vrgen_vs_value = \ - LIBERO_SETTING_MIN_DPC_VS_GEN; - } - dpc_bits = ((dpc_bits &\ - (~BCLK_DPC_VRGEN_VS_MASK))|\ - (dpc_vrgen_vs_value< MAX_NUMBER_DPC_VS_GEN_SWEEPS) - { - sweep_count_dpc_vs_bits = 0U; - } - sweep_state = DPC_VRGEN_H_SWEEP; - break; - case FINISHED_SWEEP: - break; - default: - break; - } - } -#endif /* SWEEP_ENABLED */ break; case DDR_TRAINING_CHECK_FOR_OFFMODE: @@ -724,14 +516,14 @@ static uint32_t ddr_setup(void) MSS_GPIO_init(GPIO2_LO); MSS_GPIO_config_all(GPIO2_LO, MSS_GPIO_OUTPUT_MODE); MSS_GPIO_set_outputs(GPIO2_LO, 0x00000UL); /* bits 15:0 - 0, noise logic disabled */ - delay(100); + delay(DELAY_CYCLES_5_MICRO); /*MSS_GPIO_set_outputs(GPIO2_LO, 0x00FFFUL);*/ /* bits 12:0 - 1, 56% enabled */ noise_ena = (1 << num_of_noise_blocks_en) - 1; MSS_GPIO_set_outputs(GPIO2_LO, noise_ena); /* num_of_noise_blocks_en * 4.72% */ fabric_noise_en = 0; } #endif /* FABRIC_NOISE_TEST */ - write_latency = MIN_LATENCY; + write_latency = DDR_CAL_MIN_LATENCY; ddr_training_state = DDR_TRAINING_SET_MODE_VS_BITS; } break; @@ -745,6 +537,19 @@ static uint32_t ddr_setup(void) * Set the training mode */ set_ddr_mode_reg_and_vs_bits(dpc_bits); + + if (ddr_type == LPDDR4) + { + /* vrgen, modify during write leveling, turns off ODT */ + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS =\ + (dpc_bits & ~DDR_DPC_VRGEN_H_MASK)| (DPC_VRGEN_H_LPDDR4_WR_LVL_VAL << DDR_DPC_VRGEN_H_SHIFT); + CFG_DDR_SGMII_PHY->rpc3_ODT.rpc3_ODT = 0x0; + } + else if ((ddr_type == DDR3)||(ddr_type == DDR3L)) + { + /* vrgen, modify during write leveling */ + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS = dpc_bits | (DPC_VRGEN_H_DDR3_WR_LVL_VAL<SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_DDRC_MASK; /* Remove soft reset */ + SYSREG->SOFT_RESET_CR |= (uint32_t)SOFT_RESET_CR_DDRC_MASK; SYSREG->SOFT_RESET_CR &= (uint32_t)~SOFT_RESET_CR_DDRC_MASK; ddr_training_state = DDR_TRAINING_SETUP_DDRC; break; @@ -860,6 +666,11 @@ static uint32_t ddr_setup(void) #ifndef SPECIAL_TRAINIG_RESET CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; #ifndef SOFT_RESET_PRE_TAG_172 + if (ddr_type == LPDDR4) + { + //ALISTER 7/16/21 + DDRCFG->MC_BASE2.INIT_AUTOINIT_DISABLE.INIT_AUTOINIT_DISABLE=0x1; + } DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ 0x00000000U; DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ @@ -871,14 +682,14 @@ static uint32_t ddr_setup(void) /* Assert FORCE_RESET */ DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; - delay(100); + delay(DELAY_CYCLES_5_MICRO); /* release reset to memory here, set INIT_FORCE_RESET to 0 */ DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; - delay(500000); + delay(DELAY_CYCLES_2MS); /* 2MS */ /* Enable CKE */ DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; - delay(1000); + delay(DELAY_CYCLES_50_MICRO); /* reset pin is bit [1] */ CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; @@ -1010,7 +821,7 @@ static uint32_t ddr_setup(void) * Initiate IP training and wait for dfi_init_complete */ /*asserting training_reset */ - if (ddr_type != DDR3) + if (!((ddr_type == DDR3)||(ddr_type == DDR3L))) { CFG_DDR_SGMII_PHY->training_reset.training_reset =\ 0x00000000U; @@ -1093,30 +904,255 @@ static uint32_t ddr_setup(void) * bclk_sclk_offset_value * BCLK_SCLK_OFFSET_BASE */ - if(LIBERO_SETTING_TRAINING_SKIP_SETTING & ADDCMD_BIT) - { - /* - * We are skipping add/cmd training so need to set - * refclk phase offset manually - * We may need to sweep this - */ - refclk_phase = (uint32_t)(((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET + 5U + LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET ) & 0x07UL) << 2U); - bclk_phase = ((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET) & 0x07UL ) << 8U; - bclk90_phase= ((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET+2U) & 0x07UL ) << 11U; - MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); - MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase | refclk_phase); - MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); - } - else { - bclk_phase = ((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET) & 0x07UL ) << 8U; - bclk90_phase=((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET+2U) & 0x07UL ) << 11U; + bclk_phase = ((bclk_answer+bclk_sclk_offset(ddr_type)) & 0x07UL ) << 8U; + bclk90_phase=((bclk_answer+bclk_sclk_offset(ddr_type)+2U) & 0x07UL ) << 11U; MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase); MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase); MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase); + + } +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r bclk_phase ", bclk_phase); + (void)uprint32(g_debug_uart, "\n\r bclk_sclk_offset value ", bclk_sclk_offset(ddr_type)); +#endif + /* SET Store DRV & VREF initial values (to be re-applied after CA training) */ + uint32_t ca_drv=CFG_DDR_SGMII_PHY->rpc1_DRV.rpc1_DRV; + uint32_t ca_vref=(CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS >>12)&0x3F; + + /* SET DRIVE TO MAX */ + { /* vref training begins */ + uint32_t dpc_bits_new; + uint32_t vref_answer; + uint32_t transition_a5_min_last = 129U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000001U; + for (uint32_t ca_indly=0;ca_indly < 30; ca_indly=ca_indly+5) + { + CFG_DDR_SGMII_PHY->rpc145.rpc145 = ca_indly;//TEMPORARY + CFG_DDR_SGMII_PHY->rpc147.rpc147 = ca_indly;//TEMPORARY + uint32_t break_loop=1; + uint32_t in_window=0; + vref_answer=128; + for (uint32_t vref=5;vref <30;vref++) //begin vref training + { + uint32_t transition_a5_max=0; + uint32_t transition_a5_min=128; + uint32_t rx_a5_last,rx_a5; + uint32_t transition_a5; + uint32_t range_a5=0; + + if(transition_a5_min_last > 128U) + { + transition_a5_min_last=128U; + } + + IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ + //SET VREF HERE + delay(DELAY_CYCLES_500_NS); + dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref <<12) | (0x1<<18); + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS=dpc_bits_new; + delay(DELAY_CYCLES_500_NS); + IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ + delay(DELAY_CYCLES_500_NS); + + + //ADDCMD Training improvement , adds delay on A9 loopback path - Suggested by Alister + //CFG_DDR_SGMII_PHY->rpc145.rpc145 = 0x8U; + + uint32_t deltat = 128UL; + + for (uint32_t j = 0; j<20 ; j++) + { + + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + // rx_a5_last=0x0; + rx_a5_last=0xF; + transition_a5=0; + deltat=128; + delay(DELAY_CYCLES_500_NS); + + for (uint32_t i=0; i < (128-ca_indly);i++) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + delay(DELAY_CYCLES_500_NS); + rx_a5 = (CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x0300) >> 8; + + if (transition_a5 != 0){ + if (((i - transition_a5) > 8) ){ //was 8 //////////// + break; + } + } + + if (transition_a5 ==0) { + // if ( ((rx_a5 ^ rx_a5_last) & (~rx_a5) ) ){ + if ( ((rx_a5 ^ rx_a5_last) & rx_a5 ) ){ + transition_a5 = i; + } + else{ + rx_a5_last=rx_a5; + } + } + else { + if ((i - transition_a5) == 4) //was 4 //////////// + //if (rx_a5!=rx_a5_last) //IF rx_ca not stable after 4 increments, set transition detected to 0 (false transition) + // if(!((rx_a5 ^ rx_a5_last) & (~rx_a5) )) + if(!((rx_a5 ^ rx_a5_last) & rx_a5 )) + { + transition_a5=0; //Continue looking for transition + rx_a5_last=rx_a5; + } + } + + + + }//delay loop ends here + if (transition_a5 !=0) + { + if (transition_a5 > transition_a5_max) + { + transition_a5_max = transition_a5; + } + if (transition_a5 < transition_a5_min) + { + + transition_a5_min = transition_a5; + } + } + }//Sample loop ends here + range_a5=transition_a5_max-transition_a5_min; + if (transition_a5_min < 10){ + break_loop=0; + } + + + if (range_a5 <=5) + { + //(min(transition_a5_min - transition_a5_min_last,transition_a5_min_last-transition_a5_min) <=4)) + if (transition_a5_min > transition_a5_min_last) + { + deltat=transition_a5_min-transition_a5_min_last; + } + else + { + deltat=transition_a5_min_last-transition_a5_min; + } + if (deltat <=5) + { + in_window=(in_window<<1)|1; + } + } + else + { + in_window=(in_window<<1)|0; + } + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r ca_indly ", ca_indly); + (void)uprint32(g_debug_uart, " vref ", vref); + (void)uprint32(g_debug_uart, " a5_dly_max:", transition_a5_max); + (void)uprint32(g_debug_uart, " a5_dly_min:", transition_a5_min); + (void)uprint32(g_debug_uart, " a5_dly_min_last:", transition_a5_min_last); + (void)uprint32(g_debug_uart, " range_a5:", range_a5); + (void)uprint32(g_debug_uart, " deltat:", deltat); + (void)uprint32(g_debug_uart, " in_window:", in_window); + (void)uprint32(g_debug_uart, " vref_answer:", vref_answer); +#endif + if(vref_answer==128) + { + if ((in_window &0x3)==0x3) //ALISTER CHANGE 2/17/2021 + { + vref_answer=vref; //ALISTER CHANGE +#ifndef PRINT_CA_VREF_WINDOW + break; +#endif + } + } + transition_a5_min_last=transition_a5_min; + } + if (break_loop) + { + break; + } + } +#ifdef DEBUG_DDR_INIT + if (vref_answer!=128U) + { + (void)uprint32(g_debug_uart, "\n\r vref_answer found", vref_answer); + } + else + { + (void)uprint32(g_debug_uart, "\n\r CA_VREF training failed! ", vref_answer); + + } +#endif + IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ + /* SET VREF HERE */ + delay(DELAY_CYCLES_500_NS); + if(vref_answer == 128U) + { + vref_answer = 0x10U; + dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12U) | (0x1<<18U); + } + else + { + dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12) | (0x1<<18U); + } + + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS=dpc_bits_new; + delay(DELAY_CYCLES_500_NS); + IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ + delay(DELAY_CYCLES_500_MICRO); + + }/* end vref_training; */ + + if ((ddr_type == DDR3)||(ddr_type == DDR3L)) + { + ddr3_address_cmd_training(ddr_type, &refclk_sweep_index, retry_count, &bclk_phase, &bclk90_phase, &refclk_phase, &refclk_offset ); + } + else if (ddr_type != LPDDR4) + { + non_lpddr4_address_cmd_training(ddr_type, &refclk_sweep_index, &bclk_phase, &bclk90_phase, &refclk_phase); + } /* END MANUAL BCLKSCLK TRAINING */ + else /* LPDDR4 */ + { + /* PRE_INITIALIZATION when using LPDDR4 */ + refclk_phase =(0x7U)<<2U; + bclk_phase=MSS_SCB_DDR_PLL->PLL_PHADJ & 0x700; + bclk90_phase=MSS_SCB_DDR_PLL->PLL_PHADJ & 0x3800; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase | refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); + delay(DELAY_CYCLES_500_NS); } + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r Returning FPGA CA VREF & CA drive to user setting.\n\r ", 0x0); +#endif + /* SET VREF BACK TO CONFIGURED VALUE */ + IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ + delay(DELAY_CYCLES_500_NS); + + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS=\ + ( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (ca_vref <<12U) | (0x1<<18U); + delay(DELAY_CYCLES_500_NS); + IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ + delay(DELAY_CYCLES_500_NS); + /* SET CA DRV BACK TO CONFIGURED VALUE */ + CFG_DDR_SGMII_PHY->rpc1_DRV.rpc1_DRV=ca_drv; //return ca_drv to original value ddr_training_state = DDR_TRAINING_IP_SM_START; - /* END MANUAL BCLKSCLK TRAINING */ } } if(--timeout == 0U) @@ -1128,28 +1164,26 @@ static uint32_t ddr_setup(void) { CFG_DDR_SGMII_PHY->training_skip.training_skip =\ LIBERO_SETTING_TRAINING_SKIP_SETTING; - if ((ddr_type == DDR3)||(ddr_type == LPDDR4)||(ddr_type == DDR4)) + if ((ddr_type == DDR3)||(ddr_type == DDR3L)||(ddr_type == LPDDR3)||(ddr_type == LPDDR4)||(ddr_type == DDR4)) { /* RX_MD_CLKN */ CFG_DDR_SGMII_PHY->rpc168.rpc168 = 0x0U; } + #ifdef DDR_TRAINING_IP_SM_START_DELAY - delay(100); + delay(DELAY_CYCLES_5_MICRO); #endif /* release reset to training */ CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000000U; #ifdef IP_SM_START_TRAINING_PAUSE - /* todo: pause removed at Alister's request for test. Will - * remove once verified not required after further testing - */ CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0xffU; - delay(100); + delay(DELAY_CYCLES_5_MICRO); CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause = 0x00000000U; CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause = 0x0000003FU; CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause = 0x00000000U; - delay(100); + delay(DELAY_CYCLES_5_MICRO); CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00U; - delay(100); + delay(DELAY_CYCLES_5_MICRO); #endif } { @@ -1180,6 +1214,10 @@ static uint32_t ddr_setup(void) CFG_DDR_SGMII_PHY->lane_alignment_fifo_control.lane_alignment_fifo_control = 0x00U; CFG_DDR_SGMII_PHY->lane_alignment_fifo_control.lane_alignment_fifo_control = 0x02U; #endif + if(ddr_type == LPDDR4) + { + lpddr4_manual_training(ddr_type, &refclk_sweep_index, retry_count, &refclk_offset); + } /* end of LPDDR4 exclusive */ #ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, \ @@ -1247,6 +1285,7 @@ static uint32_t ddr_setup(void) } break; case DDR_TRAINING_IP_SM_WRLVL: + //END VREFTRN if(LIBERO_SETTING_TRAINING_SKIP_SETTING & WRLVL_BIT) { timeout = 0xFFFF; @@ -1263,6 +1302,11 @@ static uint32_t ddr_setup(void) } break; case DDR_TRAINING_IP_SM_RDGATE: + /* vrgen, revert temp change during write leveling for lpddr4, + turn back on ODT */ + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS = dpc_bits ; + CFG_DDR_SGMII_PHY->rpc3_ODT.rpc3_ODT = LIBERO_SETTING_RPC_ODT_DQ; + /* end addition 11th Feb 22 */ if(LIBERO_SETTING_TRAINING_SKIP_SETTING & RDGATE_BIT) { timeout = 0xFFFF; @@ -1351,52 +1395,120 @@ static uint32_t ddr_setup(void) if(low_ca_dly_count > ABNORMAL_RETRAIN_CA_DLY_DECREASE_COUNT) { t_status = t_status | 0x01U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL ABNORMAL_RETRAIN_CA_DLY_DECREASE_COUNT : ",\ + low_ca_dly_count); +#endif } /* Retrain if abnormal CA training result detected */ if(decrease_count > ABNORMAL_RETRAIN_CA_DECREASE_COUNT) { - t_status = t_status | 0x01U; + t_status = t_status | 0x02U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL ABNORMAL_RETRAIN_CA_DECREASE_COUNT : ",\ + decrease_count); +#endif } } } /* Check that gate training passed without error */ - t_status =t_status |\ + t_status = t_status |\ CFG_DDR_SGMII_PHY->gt_err_comb.gt_err_comb; delay(10U); /* Check that DQ/DQS training passed without error */ if(CFG_DDR_SGMII_PHY->dq_dqs_err_done.dq_dqs_err_done != 8U) { t_status = t_status | 0x01U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL dq_dqs_err_done : ",\ + CFG_DDR_SGMII_PHY->dq_dqs_err_done.dq_dqs_err_done); +#endif } /* Check that DQ/DQS calculated window is above 5 taps. */ - if(CFG_DDR_SGMII_PHY->dqdqs_status1.dqdqs_status1 < \ + if(CFG_DDR_SGMII_PHY->dqdqs_status2.dqdqs_status2 < \ DQ_DQS_NUM_TAPS) { t_status = t_status | 0x01U; + /* + * Increment startin value to push past starting edge + */ +#ifdef TUNE_RPC_156_DQDQS_INIT_VALUE + if (rpc_156_dqdqs_init_offset <= LIBERO_SETTING_MAX_RPC_156_VALUE) + { + rpc_156_dqdqs_init_offset++; + } +#endif +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r\n\r Filtering failures DQDQS Windows is too small ",CFG_DDR_SGMII_PHY->dqdqs_status2.dqdqs_status2); +#ifdef TUNE_RPC_156_DQDQS_INIT_VALUE + (void)uprint32(g_debug_uart, \ + "\n\r\n\r rpc_156_dqdqs_init_offset = ",rpc_156_dqdqs_init_offset); +#endif +#endif } -#ifdef DCT_EXTRA_CHECKS /* todo: Theses checks was added by DCT */ + +#define DCT_EXTRA_CHECKS +#ifdef DCT_EXTRA_CHECKS + uint32_t temp = 0U, gt_clk_sel = (CFG_DDR_SGMII_PHY->gt_clk_sel.gt_clk_sel & 3U); if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly)&0xFFU) == 0U) // Gate training tx_dly check: AL { - t_status = t_status | 0x01U; + temp++; + if(gt_clk_sel == 0) + { + t_status = t_status | 0x01U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL gt_clk_sel : ",\ + gt_clk_sel); +#endif + } } if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly>>8U)&0xFFU) == 0U) { - t_status = t_status | 0x01U; + temp++; + if(gt_clk_sel == 1) + { + t_status = t_status | 0x01U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL gt_clk_sel : ",\ + gt_clk_sel); +#endif + } } if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly>>16U)&0xFFU) == 0U) { - t_status = t_status | 0x01U; + temp++; + if(gt_clk_sel == 2) + { + t_status = t_status | 0x01U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL gt_clk_sel : ",\ + gt_clk_sel); +#endif + } } if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly>>24U)&0xFFU) == 0U) + { + temp++; + if(gt_clk_sel == 3) + { + t_status = t_status | 0x01U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r SM_VERIFY FAIL gt_clk_sel : ",\ + gt_clk_sel); +#endif + } + } + if(temp > 1) { t_status = t_status | 0x01U; } #endif } - #ifdef RENODE_DEBUG +#ifdef RENODE_DEBUG t_status = 0U; /* Dummy success -move on to next stage */ - #endif +#endif if(t_status == 0U) { SIM_FEEDBACK1(21U); @@ -1466,46 +1578,124 @@ static uint32_t ddr_setup(void) /* * Now start the write calibration as training has been successful */ + /* Setting expert mode */ + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x0000008U; if(error == 0U) { + if((ddr_type == DDR3)||(ddr_type == DDR3L)) /* Changing WPU and WPD */ + { + /* only run when ECC is on - sar121393 */ + if (LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_ECC_MASK) + { + CFG_DDR_SGMII_PHY->ovrt16.ovrt16 = 0x00000F80UL; + CFG_DDR_SGMII_PHY->ovrt15.ovrt15 = 0x00000000UL; + CFG_DDR_SGMII_PHY->ovrt14.ovrt14 = 0x00000000UL; + CFG_DDR_SGMII_PHY->ovrt13.ovrt13 = 0x00000000UL; + CFG_DDR_SGMII_PHY->ovrt12.ovrt12 = 0x00000000UL; + } + } if (ddr_type == LPDDR4) { +#ifdef SWEEP_DQ_DELAY uint8_t lane; - /* Changed default value to centre dq/dqs on window */ - CFG_DDR_SGMII_PHY->rpc220.rpc220 = 0xCUL; - for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) + uint32_t dly_firstpass=0xFF; + uint32_t dly_right_edge=20U; + uint32_t pass=0U; + for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) //load DQ { load_dq(lane); } - SIM_FEEDBACK1(1U); -#ifdef SW_CONFIG_LPDDR_WR_CALIB_FN - error =\ - write_calibration_lpddr4_using_mtc(\ - number_of_lanes_to_calibrate); -#else - error =\ + delay(DELAY_CYCLES_50_MICRO); + for (uint32_t dq_dly=0U;dq_dly < 20U ; dq_dly=dq_dly+1U){ + CFG_DDR_SGMII_PHY->rpc220.rpc220 = dq_dly; //set DQ load value + for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) //load DQ + { + load_dq(lane); + } + SIM_FEEDBACK1(1U); + + delay(DELAY_CYCLES_50_MICRO); + pass =\ write_calibration_using_mtc(\ number_of_lanes_to_calibrate); +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r dq_dly ",\ + dq_dly); + (void)uprint32(g_debug_uart, " pass ",\ + pass); + (void)uprint32(g_debug_uart, " wr calib result ",\ + calib_data.write_cal.lane_calib_result); #endif - } - else - { - SIM_FEEDBACK1(2U); - error =\ - write_calibration_using_mtc(number_of_lanes_to_calibrate); - } - if(error) - { - ddr_error_count++; - SIM_FEEDBACK1(106U); - } - } -#if (EN_RETRY_ON_FIRST_TRAIN_PASS == 1) - if((error == 0U)&&(retry_count != 0U)) -#else - if(error == 0U) + if (dly_firstpass != 0xFFU) + { + if (pass !=0U) + { + dly_right_edge=dq_dly; + break; + } + } + if (dly_firstpass ==0xFFU) + { + if (pass==0U) + { + dly_firstpass=dq_dly; + } + } + + } + if(dly_firstpass == 0xFFU) + { + error = 1U; + } + else + { + CFG_DDR_SGMII_PHY->rpc220.rpc220 = (dly_firstpass + dly_right_edge)/2U; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r dq_dly_answer ",\ + CFG_DDR_SGMII_PHY->rpc220.rpc220); + //(void)uprint32(g_debug_uart, " vrefdq_answer ", (vref_firstpass + vref_right_edge)/2); + (void)uprint32(g_debug_uart, " wr calib result ",\ + calib_data.write_cal.lane_calib_result); #endif + for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) //load DQ + { + load_dq(lane); + } + delay(DELAY_CYCLES_50_MICRO); + error =\ + write_calibration_using_mtc(\ + number_of_lanes_to_calibrate); + } +#else /* alternate calibration */ + if(ddr_type == LPDDR4) + { + uint8_t lane; + /* Changed default value to centre dq/dqs on window */ + CFG_DDR_SGMII_PHY->rpc220.rpc220 = 0xCUL; + for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) + { + load_dq(lane); + } + } + error = write_calibration_using_mtc(number_of_lanes_to_calibrate); +#endif /* end of alternate calibration */ + } + else + { + SIM_FEEDBACK1(2U); + error =\ + write_calibration_using_mtc(number_of_lanes_to_calibrate); + } + + if(error) + { + ddr_error_count++; + SIM_FEEDBACK1(106U); + } + } + + if(error == 0U) { #ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, "\n\r\n\r wr calib result ",\ @@ -1533,10 +1723,11 @@ static uint32_t ddr_setup(void) /* * Try the next offset */ + write_latency = DDRCFG->DFI.CFG_DFI_T_PHY_WRLAT.CFG_DFI_T_PHY_WRLAT; write_latency++; - if (write_latency > MAX_LATENCY) + if (write_latency > DDR_CAL_MAX_LATENCY) { - write_latency = MIN_LATENCY; + write_latency = DDR_CAL_MIN_LATENCY; ddr_training_state = DDR_TRAINING_FAIL_MIN_LATENCY; } else @@ -1552,16 +1743,7 @@ static uint32_t ddr_setup(void) break; case DDR_SWEEP_CHECK: -#ifdef SWEEP_ENABLED - if((retry_count != 0U)&&(retry_count < (TOTAL_SWEEPS-1U))) - { - ddr_training_state = DDR_SWEEP_AGAIN; - } - else -#endif - { - ddr_training_state = DDR_SANITY_CHECKS; - } + ddr_training_state = DDR_SANITY_CHECKS; break; case DDR_SANITY_CHECKS: @@ -1604,6 +1786,8 @@ static uint32_t ddr_setup(void) error = MTC_test(mask, start_address, size, MTC_COUNTING_PATTERN, MTC_ADD_SEQUENTIAL, &error); /* Read using different patterns */ error = 0U; + error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM, MTC_ADD_SEQUENTIAL, &error); +#if ((LIBERO_FAST_START & 0x02) == 0U) error |= MTC_test(mask, start_address, size, MTC_COUNTING_PATTERN, MTC_ADD_SEQUENTIAL, &error); error |= MTC_test(mask, start_address, size, MTC_WALKING_ONE, MTC_ADD_SEQUENTIAL, &error); error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM, MTC_ADD_SEQUENTIAL, &error); @@ -1612,7 +1796,8 @@ static uint32_t ddr_setup(void) error |= MTC_test(mask, start_address, size, MTC_ALT_5_A, MTC_ADD_SEQUENTIAL, &error); error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM_16BIT, MTC_ADD_SEQUENTIAL, &error); error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM_8BIT, MTC_ADD_SEQUENTIAL, &error); - +#endif +#if ((LIBERO_FAST_START & 0x01) == 0U) error |= MTC_test(mask, start_address, size, MTC_COUNTING_PATTERN, MTC_ADD_RANDOM, &error); error |= MTC_test(mask, start_address, size, MTC_WALKING_ONE, MTC_ADD_RANDOM, &error); error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM, MTC_ADD_RANDOM, &error); @@ -1621,6 +1806,7 @@ static uint32_t ddr_setup(void) error |= MTC_test(mask, start_address, size, MTC_ALT_5_A, MTC_ADD_RANDOM, &error); error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM_16BIT, MTC_ADD_RANDOM, &error); error |= MTC_test(mask, start_address, size, MTC_PSEUDO_RANDOM_8BIT, MTC_ADD_RANDOM, &error); +#endif } if(error == 0U) { @@ -1644,9 +1830,16 @@ static uint32_t ddr_setup(void) */ { #if (DDR_FULL_32BIT_NC_CHECK_EN == 1) +#if ((LIBERO_FAST_START & 0x08) == 0U) error = ddr_read_write_fn((uint64_t*)LIBERO_SETTING_DDR_32_NON_CACHE,\ SW_CFG_NUM_READS_WRITES,\ SW_CONFIG_PATTERN); +#else + error = ddr_read_write_fn((uint64_t*)LIBERO_SETTING_DDR_32_NON_CACHE,\ + SW_CFG_NUM_READS_WRITES_FAST_START,\ + SW_CONFIG_PATTERN_FAST_START); + +#endif #endif } if(error == 0U) @@ -1678,7 +1871,9 @@ static uint32_t ddr_setup(void) } break; case DDR_LOAD_PATTERN_TO_CACHE: - load_ddr_pattern(LIBERO_SETTING_DDR_32_CACHE, SIZE_OF_PATTERN_TEST, SIZE_OF_PATTERN_OFFSET); + load_ddr_pattern(LIBERO_SETTING_DDR_32_CACHE,\ + SIZE_OF_PATTERN_TEST*2, DDR_TEST_FILL,\ + SIZE_OF_PATTERN_OFFSET); if(error == 0U) { ddr_training_state = DDR_VERIFY_PATTERN_IN_CACHE; @@ -1690,11 +1885,15 @@ static uint32_t ddr_setup(void) break; case DDR_VERIFY_PATTERN_IN_CACHE: error = test_ddr(NO_PATTERN_IN_CACHE_READS, SIZE_OF_PATTERN_TEST); +#if ((LIBERO_FAST_START & 0x04) == 0U) + error = error | test_ddr(NO_PATTERN_IN_CACHE_READS, SIZE_OF_PATTERN_TEST); + error = error | test_ddr(NO_PATTERN_IN_CACHE_READS, SIZE_OF_PATTERN_TEST); +#endif if(error == 0U) { #ifdef DEBUG_DDR_INIT (void)uprint32(g_debug_uart, "\n\r\n\r wr write latency ",\ - write_latency); + DDRCFG->DFI.CFG_DFI_T_PHY_WRLAT.CFG_DFI_T_PHY_WRLAT); #if (TUNE_RPC_166_VALUE == 1) (void)uprint32(g_debug_uart, "\n\r rpc_166_fifo_offset: ",\ rpc_166_fifo_offset); @@ -1731,14 +1930,16 @@ static uint32_t ddr_setup(void) ddr_training_state = DDR_TRAINING_FAIL; } CFG_DDR_SGMII_PHY->rpc166.rpc166 = rpc_166_fifo_offset; - //PAUSE to reset fifo (loads new RXPTR value). + + /* PAUSE to reset fifo (loads new RXPTR value).*/ + //CFG_DDR_SGMII_PHY->expert_dfi_status_override_to_shim.expert_dfi_status_override_to_shim = 0x07U; CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x1U; CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause =\ - 0x0000003EU; + 0x0000003EU ; CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause =\ 0x00000000U; CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x8U; - //delay(10); + delay(DELAY_CYCLES_50_MICRO); //END PAUSE #else if(num_rpc_166_retires < NUM_RPC_166_VALUES) @@ -1810,7 +2011,6 @@ static uint32_t ddr_setup(void) #ifdef VREFDQ_CALIB /* * This step is optional - * todo: Test once initial board verification complete */ error = VREFDQ_calibration_using_mtc(); if(error != 0U) @@ -1825,13 +2025,39 @@ static uint32_t ddr_setup(void) #ifdef FPGA_VREFDQ_CALIB /* * This step is optional - * todo: Test once initial board verification complete */ error = FPGA_VREFDQ_calibration_using_mtc(); if(error != 0U) { ddr_error_count++; } +#endif + ddr_training_state = DDR_TRAINING_INIT_ALL_MEMORY; + break; + + case DDR_TRAINING_INIT_ALL_MEMORY: +#ifdef DEBUG_DDR_INIT + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + (void)uprint64(g_debug_uart, " Init memory, size = , 0x",\ + (uint64_t)mem_size); +#endif + +#ifndef ENABLE_MEM_INIT_NON_ECC + /* Check if using ECC, if so, init all memory */ + if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_ECC_MASK) ==\ + DDRPHY_MODE_ECC_ON) + { + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + load_ddr_pattern(LIBERO_SETTING_DDR_64_NON_CACHE, mem_size,\ + DDR_INIT_FILL, 0U); + } +#else + mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +\ + (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U); + load_ddr_pattern(LIBERO_SETTING_DDR_64_NON_CACHE, mem_size,\ + DDR_INIT_FILL, 0U); #endif ddr_training_state = DDR_TRAINING_FINISH_CHECK; break; @@ -1840,12 +2066,19 @@ static uint32_t ddr_setup(void) /* * return status */ + ddr_diag.train_time = (uint64_t)(rdcycle() - training_start_cycle)\ + / (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK/1000); #ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r ddr train time (ms): ",\ + (uint32_t)ddr_diag.train_time); + (void)uprint32(g_debug_uart, "\n\r Number of retrains: ",\ + ddr_diag.num_retrains); { tip_register_status (g_debug_uart); - (void)uprint32(g_debug_uart, "\n\r\n\r DDR_TRAINING_PASS: ",\ - ddr_training_state); - (void)uprint32(g_debug_uart, "\n ****************************************************", 0); + uprint(g_debug_uart, "\n\r\n\r DDR_TRAINING_PASS: "); +#ifdef DEBUG_DDR_DDRCFG + debug_read_ddrcfg(); +#endif } #endif @@ -2171,7 +2404,6 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type) if ((LIBERO_SETTING_DDRPHY_MODE & DDRPHY_MODE_RANK_MASK) ==\ DDRPHY_MODE_TWO_RANKS) { - /* todo: need to verify this setting with verification */ CFG_DDR_SGMII_PHY->spio253.spio253 = 1; } @@ -2190,14 +2422,32 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type) * bits 15:14 connect to ibufmx DQ/DQS/DM * bits 13:12 connect to ibufmx CA/CK */ + CFG_DDR_SGMII_PHY->rpc226.rpc226 = 0x14U; CFG_DDR_SGMII_PHY->UNUSED_SPACE0[0] = 0xA000U; + /* for Skew debug at 125C MIN TTHH18->Changing the common mode of the Receiver + to low common mode to improve IO Performance of LPDDR4 */ + CFG_DDR_SGMII_PHY->SPARE0.SPARE0 = 0xA000U; } - break; } } +#ifdef TUNE_RPC_156_DQDQS_INIT_VALUE + CFG_DDR_SGMII_PHY->rpc156.rpc156 = rpc_156_dqdqs_init_offset; +#else + CFG_DDR_SGMII_PHY->rpc156.rpc156 = LIBERO_SETTING_RPC_156_VALUE; +#endif + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r\n\r CFG_DDR_SGMII_PHY->rpc156.rpc156 = ",CFG_DDR_SGMII_PHY->rpc156.rpc156); +#endif + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r\n\r Spare bit value: ",CFG_DDR_SGMII_PHY->SPARE0.SPARE0); +#endif { /* @@ -2395,7 +2645,7 @@ static uint8_t memory_tests(void) mult by (4 lanes) */ { SIM_FEEDBACK1(shift_walking_one); - start_address = (uint64_t)(0xC0000000U + (0x1U< 1G { SIM_FEEDBACK1(shift_walking_one); - start_address = (uint64_t)(0x1400000000U + (0x1U<= 4U) { - start_address = (uint64_t)(0x1400000000U + \ + start_address = (uint64_t)(BASE_ADDRESS_NON_CACHED_64_DDR + \ (((0x1U<<(shift_walking_one +1)) - 1U) -0x0F) ); error = rw_sanity_chk((uint64_t *)start_address , (uint32_t)0x5U); @@ -2507,21 +2757,6 @@ static uint8_t memory_tests(void) ddr_error_count++; SIM_FEEDBACK1(207U); } - -#if 0 /* this check will not work as written, need to look further into flushing - cache as part of this test */ - /* - * read back via axi switch datapath to make sure write through on - * cache occurred - */ - start_address = (uint64_t)(0x1400000000U + (0x1U<MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFFFFFF00U; - DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; - DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; + DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; } if (mask & 0x2U) { @@ -3479,7 +3679,7 @@ static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC * Set when test completes */ volatile uint64_t something_to_do = 0U; - #ifndef UNITTEST +#ifndef UNITTEST while (( DDRCFG->MEM_TEST.MT_DONE_ACK.MT_DONE_ACK & 0x01U) == 0U) { something_to_do++; @@ -3490,11 +3690,11 @@ static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC #endif return (MTC_TIMEOUT_ERROR); } - #ifdef RENODE_DEBUG +#ifdef RENODE_DEBUG break; - #endif +#endif } - #endif +#endif } } /* @@ -4240,6 +4440,39 @@ static uint8_t use_software_bclk_sclk_training(DDR_TYPE ddr_type) return(result); } +/** + * bclk_sclk_offset() + * @param ddr_type + * @return + */ +static uint8_t bclk_sclk_offset(DDR_TYPE ddr_type) +{ + uint8_t result = 0U; + switch (ddr_type) + { + default: + case DDR_OFF_MODE: + result = LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR4; + break; + case DDR3L: + result = LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3L; + break; + case DDR3: + result = LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3; + break; + case DDR4: + result = LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR4; + break; + case LPDDR3: + result = LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR3; + break; + case LPDDR4: + result = LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR4; + break; + } + return(result); +} + /** * config_ddr_io_pull_up_downs_rpc_bits() * @@ -4290,85 +4523,6 @@ static void config_ddr_io_pull_up_downs_rpc_bits(DDR_TYPE ddr_type) } } - -/** - * get the best sweep value - * @param good_index - * @return - */ -#ifdef SWEEP_ENABLED -static uint8_t get_best_sweep(sweep_index *good_index) -{ -#ifdef EXTRACT_SWEEP_RESULT - uint8_t cmd_index; - uint8_t bclk_sclk_index; - uint8_t dpc_vgen_index; - uint8_t dpc_vgen_h_index; - uint8_t dpc_vgen_vs_index; - uint8_t good_in_row; - - for (dpc_vgen_vs_index=0U; dpc_vgen_vs_index < MAX_NUMBER_DPC_VS_GEN_SWEEPS; dpc_vgen_vs_index++) - { - for (dpc_vgen_h_index=0U; dpc_vgen_h_index < MAX_NUMBER_DPC_H_GEN_SWEEPS; dpc_vgen_h_index++) - { - for (dpc_vgen_index=0U; dpc_vgen_index < MAX_NUMBER_DPC_V_GEN_SWEEPS; dpc_vgen_index++) - { - for (bclk_sclk_index=0U; bclk_sclk_index < MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS; bclk_sclk_index++) - { - good_in_row = 0U; - for (cmd_index=0U; cmd_index < MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS; cmd_index++) - { - if (sweep_results[dpc_vgen_vs_index][dpc_vgen_h_index][dpc_vgen_index][bclk_sclk_index][cmd_index]\ - == CALIBRATION_PASSED) - { - good_in_row++; - /* - * look for 3 in a row,in x and y direction and pick the - * middle one - * */ - if((good_in_row > 2U)&&(bclk_sclk_index>1)&&(bclk_sclk_indexdpc_vgen_vs_index = dpc_vgen_vs_index; - good_index->dpc_vgen_h_index = dpc_vgen_h_index; - good_index->bclk_sclk_index = bclk_sclk_index; - good_index->dpc_vgen_index = dpc_vgen_index; - good_index->cmd_index = cmd_index - 1U; - return(0U); - } - } - } - else - { - good_in_row = 0U; - } - } - } - } - } - } - return(1U); -#else /* EXTRACT_SWEEP_RESULT */ - good_index->dpc_vgen_vs_index = 0U; - good_index->dpc_vgen_h_index = 0U; - good_index->bclk_sclk_index = 0U; - good_index->dpc_vgen_index = 0U; - good_index->cmd_index = 0U; - return(0U); -#endif -} -#endif /* SWEEP_ENABLED */ - - #ifdef DDR_DIAGNOSTICS /* todo: add support for diagnostics below during board bring-up */ /*-------------------------------------------------------------------------*//** @@ -4434,11 +4588,11 @@ MSS_DDR_status * * Example: The call to - MSS_DDR_user_commands(USR_CMD_INC_DELAY_LINE, 0x01 , return_data) + MSS_DDR_user_commands(USR_CMD_INC_DELAY_CYCLES_LINE, 0x01 , return_data) will return 0 id successful and the DDR type in the first four bytes of the ret_mem area. @code - MSS_DDR_user_commands(USR_CMD_INC_DELAY_LINE, 0x01 , return_data); + MSS_DDR_user_commands(USR_CMD_INC_DELAY_CYCLES_LINE, 0x01 , return_data); @endcode */ uint8_t @@ -4539,7 +4693,6 @@ MSS_DDR_user_commands #endif #ifdef DEBUG_DDR_INIT -#ifdef DEBUG_DDR_DDRCFG void debug_read_ddrcfg(void) { (void)print_reg_array(g_debug_uart , @@ -4590,69 +4743,68 @@ void debug_read_ddrcfg(void) return; } #endif -#endif const uint8_t REFCLK_OFFSETS[][5U] = { - {LIBERO_SETTING_REFCLK_DDR3_1600_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_0, - LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_1, - LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_2, - LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_DDR3L_1600_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_0, - LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_1, - LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_2, - LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0, - LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1, - LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2, - LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_0, - LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_1, - LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_2, - LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0, - LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1, - LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2, - LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3}, - - {LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0, - LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1, - LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2, - LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0, - LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1, - LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2, - LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0, - LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1, - LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2, - LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0, - LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1, - LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2, - LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_3}, - { - LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS, - LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0, - LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1, - LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2, - LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3}, + {LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0, + LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1, + LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2, + LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0, + LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1, + LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2, + LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0, + LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1, + LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2, + LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_0, + LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_1, + LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_2, + LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0, + LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1, + LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2, + LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3}, + + {LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_0, + LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_1, + LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_2, + LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_DDR3L_1067_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_0, + LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_1, + LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_2, + LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0, + LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1, + LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2, + LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0, + LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1, + LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2, + LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_3}, + { + LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS, + LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0, + LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1, + LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2, + LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3}, }; /** @@ -4669,9 +4821,26 @@ static uint8_t ddr_manual_addcmd_refclk_offset(DDR_TYPE ddr_type, uint8_t * refc uint8_t type_array_index; type_array_index = (uint8_t)ddr_type; - if(LIBERO_SETTING_DDR_CLK == DDR_1333_MHZ) + switch (ddr_type) { - type_array_index = type_array_index + (uint8_t)LPDDR4; + case DDR3L: + case DDR3: + if(LIBERO_SETTING_DDR_CLK + DDR_FREQ_MARGIN < DDR_1333_MHZ) + { + type_array_index = (uint8_t)(type_array_index + (uint8_t)LPDDR4 + (uint8_t)1U); + } + break; + case DDR4: + case LPDDR3: + case LPDDR4: + if(LIBERO_SETTING_DDR_CLK + DDR_FREQ_MARGIN < DDR_1600_MHZ) + { + type_array_index = (uint8_t)(type_array_index + (uint8_t)LPDDR4 + (uint8_t)1U); + } + break; + default: + case DDR_OFF_MODE: + break; } if (*refclk_sweep_index >= REFCLK_OFFSETS[type_array_index][0U]) @@ -4681,12 +4850,1237 @@ static uint8_t ddr_manual_addcmd_refclk_offset(DDR_TYPE ddr_type, uint8_t * refc refclk_offset = REFCLK_OFFSETS[type_array_index][*refclk_sweep_index + 1U]; - *refclk_sweep_index = (*refclk_sweep_index + 1U); + *refclk_sweep_index = (uint8_t)(*refclk_sweep_index + 1U); return refclk_offset; } #endif +//ALISTER 7/16/21 +static uint32_t mode_register_masked_write(uint32_t address) +{ + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + DDRCFG->MC_BASE2.INIT_MR_WR_MASK.INIT_MR_WR_MASK=0xFFFFF; + DDRCFG->MC_BASE2.INIT_MR_ADDR.INIT_MR_ADDR=address; + DDRCFG->MC_BASE2.INIT_MR_WR_DATA.INIT_MR_WR_DATA=0x0; + DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ=0x1; + DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ=0x0; + delay(DELAY_CYCLES_5_MICRO); + + if(DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK!=0){ + return 0; + } + else { + return 1; + } +} + +static uint32_t mode_register_masked_write_x5(uint32_t address) +{ + uint32_t i; + uint32_t error=0; + for(i=0; i<10;i++) + { + error |= mode_register_masked_write(address); + } + return error; +} + +#ifdef MODE_WRITE1_USED +static uint32_t mode_register_write1(uint32_t address, uint32_t data) +{ + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + DDRCFG->MC_BASE2.INIT_MR_WR_MASK.INIT_MR_WR_MASK=0x00000; + DDRCFG->MC_BASE2.INIT_MR_ADDR.INIT_MR_ADDR=address; + DDRCFG->MC_BASE2.INIT_MR_WR_DATA.INIT_MR_WR_DATA= data; + DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ=0x1; + DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ=0x0; + delay(DELAY_CYCLES_5_MICRO); + + if(DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK!=0){ + return 0; + } + else { + return 1; + } +} +#endif + +#ifdef ZQ_CAL +static uint32_t zq_cal(void) +{ + uint32_t error=0; + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + + DDRCFG->MC_BASE2.INIT_ZQ_CAL_START.INIT_ZQ_CAL_START=0x1; + DDRCFG->MC_BASE2.INIT_ZQ_CAL_START.INIT_ZQ_CAL_START=0x0; + + delay(DELAY_CYCLES_500_MICRO); + error= (DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK==0x0); + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + DDRCFG->MC_BASE2.INIT_ZQ_CAL_REQ.INIT_ZQ_CAL_REQ=0x1; + DDRCFG->MC_BASE2.INIT_ZQ_CAL_REQ.INIT_ZQ_CAL_REQ=0x0; + delay(DELAY_CYCLES_500_MICRO); + error |= (DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK==0x0); + delay(DELAY_CYCLES_500_MICRO); + return error; +} +#endif + +/** + * LPDDR4 traing exclusive + * @param ddr_type + * @param refclk_sweep_index + */ +static void lpddr4_manual_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index, uint32_t retry_count, uint8_t *refclk_offset) +{ + //ALISTER 7/16/2021 + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; //moved up from below jan7th + delay(DELAY_CYCLES_5_MICRO); + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; + + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N = 1; + delay(DELAY_CYCLES_250_MICRO); /* requirement 200 uS */ + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; + delay(DELAY_CYCLES_2MS); /* require min. 2 ms */ + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; + delay(DELAY_CYCLES_150_MICRO); + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + + DDRCFG->MC_BASE2.CFG_AUTO_ZQ_CAL_EN.CFG_AUTO_ZQ_CAL_EN=0; + delay(DELAY_CYCLES_5_MICRO); + + /* Assert FORCE_RESET */ + delay(DELAY_CYCLES_5_MICRO); + uint32_t div0=MSS_SCB_DDR_PLL->PLL_DIV_0_1 & 0x3F00; + uint32_t div1=MSS_SCB_DDR_PLL->PLL_DIV_0_1 & 0x3F000000; + uint32_t div2=MSS_SCB_DDR_PLL->PLL_DIV_2_3 & 0x3F00; + uint32_t div3=MSS_SCB_DDR_PLL->PLL_DIV_2_3 & 0x3F000000; + + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; + delay(DELAY_CYCLES_50_MICRO); + uint32_t mult=2; + MSS_SCB_DDR_PLL->PLL_DIV_0_1 = (div0 | div1)*mult; + MSS_SCB_DDR_PLL->PLL_DIV_2_3 = (div2 | div3)*mult; + while ((CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN=CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN & 0x2000000UL) ==0){} + delay(DELAY_CYCLES_50_MICRO); + CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN=(uint32_t)(CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN & (~(0x0000003CUL))); + CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN=CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN | ((0x0000003CUL)); + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x9U; + CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause =\ + 0x0000003FU ; + CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause =\ + 0x00000000U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x8U; + delay(DELAY_CYCLES_50_MICRO); + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; + delay(DELAY_CYCLES_500_MICRO); +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r\n\r pll_phadj_during_init_2_3 ",\ + MSS_SCB_DDR_PLL->PLL_DIV_2_3); + (void)uprint32(g_debug_uart, \ + "\n\r\n\r pll_phadj_during_init_0_1 ",\ + MSS_SCB_DDR_PLL->PLL_DIV_0_1); +#endif + + DDRCFG->MC_BASE2.INIT_CS.INIT_CS = 0x1; + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; //moved up from below jan7th + delay(DELAY_CYCLES_5_MICRO); + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; + + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N = 1; + delay(DELAY_CYCLES_250_MICRO); /* req. 200uS */ + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; + delay(DELAY_CYCLES_2MS); /* req. 2MS */ + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; + delay(DELAY_CYCLES_150_MICRO); + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r Writing MR1 ", mode_register_masked_write_x5(1)); + (void)uprint32(g_debug_uart, "\n\r Writing MR2 ", mode_register_masked_write_x5(2)); + (void)uprint32(g_debug_uart, "\n\r Writing MR3 ", mode_register_masked_write_x5(3)); + (void)uprint32(g_debug_uart, "\n\r Writing MR4 ", mode_register_masked_write_x5(4)); + (void)uprint32(g_debug_uart, "\n\r Writing MR11 ", mode_register_masked_write_x5(11)); + (void)uprint32(g_debug_uart, "\n\r Writing MR16 ", mode_register_masked_write_x5(16)); + (void)uprint32(g_debug_uart, "\n\r Writing MR17 ", mode_register_masked_write_x5(17)); + (void)uprint32(g_debug_uart, "\n\r Writing MR22 ", mode_register_masked_write_x5(22)); + (void)uprint32(g_debug_uart, "\n\r Writing MR13 ", mode_register_masked_write_x5(13)); +#else + mode_register_masked_write_x5(1); + mode_register_masked_write_x5(2); + mode_register_masked_write_x5(3); + mode_register_masked_write_x5(4); + mode_register_masked_write_x5(11); + mode_register_masked_write_x5(16); + mode_register_masked_write_x5(17); + mode_register_masked_write_x5(22); + mode_register_masked_write_x5(13); +#endif + + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; + delay(DELAY_CYCLES_50_MICRO); + /* Revert to normal speed after mode reg writes */ + MSS_SCB_DDR_PLL->PLL_DIV_0_1 = div0 | div1; + MSS_SCB_DDR_PLL->PLL_DIV_2_3 = div2 | div3; + while ((CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN=CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN & 0x2000000) ==0){} + delay(DELAY_CYCLES_50_MICRO); + CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN=(uint32_t)(CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN & (~(0x0000003CUL))); + CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN=CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN | ((0x0000003C)); + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x9U; + CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause =\ + 0x0000003FU ; + CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause =\ + 0x00000000U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x8U; + delay(DELAY_CYCLES_50_MICRO); + + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; + delay(DELAY_CYCLES_500_MICRO); + + { /* vref training begins */ + uint32_t dpc_bits_new; + uint32_t vref_answer; + uint32_t transition_a5_min_last = 129U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000021U; + CFG_DDR_SGMII_PHY->expert_dfi_status_override_to_shim.expert_dfi_status_override_to_shim = 0x00000000U; + for (uint32_t ca_indly=0;ca_indly < 30; ca_indly=ca_indly+5) + { + CFG_DDR_SGMII_PHY->rpc145.rpc145 = ca_indly;//TEMPORARY + CFG_DDR_SGMII_PHY->rpc147.rpc147 = ca_indly;//TEMPORARY + uint32_t break_loop=1; + uint32_t in_window=0; + vref_answer=128; + for (uint32_t vref=5;vref <30;vref++) //begin vref training + { + uint32_t transition_a5_max=0; + uint32_t transition_a5_min=128; + uint32_t rx_a5_last,rx_a5; + uint32_t transition_a5; + uint32_t range_a5=0; + + if(transition_a5_min_last > 128U) + { + transition_a5_min_last=128U; + } + + IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ + //SET VREF HERE + delay(DELAY_CYCLES_500_NS); + dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref <<12) | (0x1<<18); + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS=dpc_bits_new; + delay(DELAY_CYCLES_500_NS); + IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ + delay(DELAY_CYCLES_500_NS); + + uint32_t deltat = 128UL; + for (uint32_t j = 0; j<20 ; j++) + { + + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + // rx_a5_last=0x0; + rx_a5_last=0xF; + transition_a5=0; + deltat=128; + delay(DELAY_CYCLES_500_NS); + + for (uint32_t i=0; i < (128-ca_indly);i++) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + delay(DELAY_CYCLES_500_NS); + rx_a5 = (CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x0300) >> 8; + + if (transition_a5 != 0){ + if (((i - transition_a5) > 8) ){ //was 8 //////////// + break; + } + } + + if (transition_a5 ==0) { + if ( ((rx_a5 ^ rx_a5_last) & rx_a5 ) ){ + transition_a5 = i; + } + else{ + rx_a5_last=rx_a5; + } + } + else { + if ((i - transition_a5) == 4) //was 4 //////////// + if(!((rx_a5 ^ rx_a5_last) & rx_a5 )) + { + transition_a5=0; //Continue looking for transition + rx_a5_last=rx_a5; + } + } + }//delay loop ends here + if (transition_a5 !=0) + { + if (transition_a5 > transition_a5_max) + { + transition_a5_max = transition_a5; + } + if (transition_a5 < transition_a5_min) + { + + transition_a5_min = transition_a5; + } + } + }//Sample loop ends here + range_a5=transition_a5_max-transition_a5_min; + if (transition_a5_min < 10){ + break_loop=0; + } + if (range_a5 <=5) + { + //(min(transition_a5_min - transition_a5_min_last,transition_a5_min_last-transition_a5_min) <=4)) + if (transition_a5_min > transition_a5_min_last) + { + deltat=transition_a5_min-transition_a5_min_last; + } + else + { + deltat=transition_a5_min_last-transition_a5_min; + } + if (deltat <=5) + { + in_window=(in_window<<1)|1; + } + } + else + { + in_window=(in_window<<1)|0; + } + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r ca_indly ", ca_indly); + (void)uprint32(g_debug_uart, " vref ", vref); + (void)uprint32(g_debug_uart, " a5_dly_max:", transition_a5_max); + (void)uprint32(g_debug_uart, " a5_dly_min:", transition_a5_min); + (void)uprint32(g_debug_uart, " a5_dly_min_last:", transition_a5_min_last); + (void)uprint32(g_debug_uart, " range_a5:", range_a5); + (void)uprint32(g_debug_uart, " deltat:", deltat); + (void)uprint32(g_debug_uart, " in_window:", in_window); + (void)uprint32(g_debug_uart, " vref_answer:", vref_answer); +#endif + if(vref_answer==128) + { + if ((in_window &0x3)==0x3) //ALISTER CHANGE 2/17/2021 + { + vref_answer=vref; //ALISTER CHANGE +#ifndef PRINT_CA_VREF_WINDOW + break; +#endif + } + } + transition_a5_min_last=transition_a5_min; + } + if (break_loop) + { + break; + } + } +#ifdef DEBUG_DDR_INIT + if (vref_answer!=128U) + { + (void)uprint32(g_debug_uart, "\n\r vref_answer found", vref_answer); + } + else + { + (void)uprint32(g_debug_uart, "\n\r CA_VREF training failed! ", vref_answer); + + } +#endif + IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ + /* SET VREF HERE */ + delay(DELAY_CYCLES_500_NS); + if(vref_answer == 128U) + { + vref_answer = 0x10U; + dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12U) | (0x1<<18U); + } + else + { + dpc_bits_new=( CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS & 0xFFFC0FFF ) | (vref_answer <<12) | (0x1<<18U); + } + + CFG_DDR_SGMII_PHY->DPC_BITS.DPC_BITS=dpc_bits_new; + delay(DELAY_CYCLES_500_NS); + IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ + delay(DELAY_CYCLES_500_MICRO); + + }/* end vref_training; */ + { + + /* Begin MANUAL ADDCMD TRAINING */ + uint32_t init_del_offset = 0x8U; + uint32_t a5_offset_status; + uint32_t rpc147_offset = 0x1U; + uint32_t rpc145_offset = 0x0U; + uint32_t bclk_phase=MSS_SCB_DDR_PLL->PLL_PHADJ & 0x700; + uint32_t bclk90_phase=MSS_SCB_DDR_PLL->PLL_PHADJ & 0x3800; + uint32_t refclk_phase; + + //ALISTER 1/12/2022 SWEEPING CK OFFSET BEFORE CHANING refclk_offset + if ((retry_count % 6) == 0){ + *refclk_offset = ddr_manual_addcmd_refclk_offset(ddr_type, refclk_sweep_index); + } + + a5_offset_status = DDR_ADD_CMD_A5_OFFSET_FAIL; + while(a5_offset_status != DDR_ADD_CMD_A5_OFFSET_PASS) + { + a5_offset_status = DDR_ADD_CMD_A5_OFFSET_PASS; + //ADDCMD Training improvement , adds delay on DDR clock loopback path + CFG_DDR_SGMII_PHY->rpc147.rpc147 = init_del_offset + rpc147_offset; + + //ADDCMD Training improvement , adds delay on A9 loopback path + CFG_DDR_SGMII_PHY->rpc145.rpc145 = init_del_offset + rpc145_offset; + + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000023U; //ENABLE DLY Control & PLL Control + + uint32_t rx_a5; + uint32_t rx_a5_last; + uint32_t rx_ck; + uint32_t rx_ck_last; + uint32_t transition_a5; + uint32_t transition_ck; + uint32_t i; + uint32_t j; + uint32_t difference [8]={0}; + uint32_t transition_ck_array [8]={0}; + + uint32_t transitions_found; + uint32_t transition_a5_max = 0U; + + for (j = 0U; j<16U ; j++) + { //Increase J loop to increase number of samples on transition_a5 (for noisy CA in LPDDR4) + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + refclk_phase = (j % 8U) << 2U; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase | refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); + rx_a5_last=0xFU; + rx_ck_last=0x5U; + transition_a5=0U; + transition_ck=0U; + + delay(100U); + transitions_found = 0U; + i = 0U; + while((!transitions_found) & (i < 128U)) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + delay(DELAY_CYCLES_500_NS); + rx_a5 = (CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x0300U) >> 8U; + rx_ck = CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x000F; + + if ((transition_a5 != 0U) && (transition_ck != 0U)) + { + if (((i - transition_a5) > 8U) && ((i - transition_ck) > 8U)) + { + //break; + transitions_found = 1U; + } + } + + if (transition_ck == 0U) { + if (rx_ck_last != 0x5U) //IF EDGE DETECTED + if (rx_ck == 0x5U) + transition_ck=i; //SET TRANSITION DETECTED AT I + rx_ck_last=rx_ck; + } + else { + if ( (i - transition_ck ) == 4U) + if (rx_ck != rx_ck_last) //IF rx_ck not stable after 4 increments, set transition detected to 0 (false transition) + { + transition_ck = 0U; //Continue looking for transition + rx_ck_last=rx_ck; + } + } + + if (transition_a5 == 0U) { + if ( ((rx_a5 ^ rx_a5_last) & rx_a5 ) ){ + transition_a5 = i; + } + else{ + rx_a5_last=rx_a5; + } + } + else { + if ((i - transition_a5) == 4U) + { + if(!((rx_a5 ^ rx_a5_last) & rx_a5 )) + { + transition_a5=0; //Continue looking for transition + rx_a5_last=rx_a5; + } + } + } + + + if ((transition_a5 != 0U) && (transition_ck != 0U)) + if ((i==transition_a5) || (i==transition_ck)) + { +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r rx_a5 ",\ + rx_a5); + (void)uprint32(g_debug_uart, \ + " rx_ck ",\ + rx_ck); + (void)uprint32(g_debug_uart, \ + " rx_ck_last ",\ + rx_ck_last); + (void)uprint32(g_debug_uart, \ + " transition_a5 ",\ + transition_a5); + (void)uprint32(g_debug_uart, \ + " transition_ck ",\ + transition_ck); + (void)uprint32(g_debug_uart, \ + " Iteration: ",\ + i); + (void)uprint32(g_debug_uart, \ + " REFCLK_PHASE: ",\ + j); +#endif + } + i++; + }/* delay loop ends here */ + if(transition_a5 > transition_a5_max) + transition_a5_max =transition_a5; + + if ((transition_a5 != 0U) && (transition_ck != 0U) && (j<8U)) + { + transition_ck_array[j]=transition_ck; + /* difference now calculated in separate loop with max a5 intstead of per offset-AL*/ + } + }/* phase loop ends here */ + + uint32_t min_diff=0xFFU; + uint32_t min_diffp1=0xFFU; + uint32_t min_diffp2=0xFFU; + uint32_t min_refclk=0x8U; + uint32_t min_refclkp1=0x8U; + uint32_t min_refclkp2=0x8U; + + if(transition_a5_max < TRANSITION_A5_THRESHOLD) + { + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL; + } + for (uint32_t k = 0U;k<8U;k++) + { + if(transition_a5_max >= transition_ck_array[k]) + difference[k]= transition_a5_max-transition_ck_array[k]; + else + difference[k]=0xff; + } + + for (uint32_t k = 0U;k<8U;k++) + { + + if (difference[k] < min_diff){ + //updated on Jan10 + min_refclk=k; + min_refclkp1=(k+1)&0x7UL; + min_refclkp2=(k+2)&0x7UL; + min_diff = difference[min_refclk]; + min_diffp1 = difference[min_refclkp1]; + min_diffp2 = difference[min_refclkp2]; + } +#ifdef DEBUG_DDR_INIT + + (void)uprint32(g_debug_uart, "\n\r difference ", difference[k]); + (void)uprint32(g_debug_uart, " REFCLK_PHASE ", k); +#endif + } + if(min_diff == 0xFFU) + { + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL; + } + if (min_refclk==0x8U) + { //If ADDCMD training fails due to extremely low frequency, use PLL to provide offset. + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL_LOW_FREQ; + } +#ifdef MOVE_CK + if ((retry_count%3) == LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ZERO){ //toggles between minimum CA delay and second smallest every 4 retrains. + //min_diff=second_diff; + min_diffp1=min_diff; + //min_refclk=(min_refclk-0x1UL)&&(0x7UL); + min_refclk=(min_refclk-0x1UL)&(0x7UL); +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r CK_PUSH = 0 degrees", 0x0UL); +#endif + } + else if ((retry_count%3) == LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ONE){ +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r CK_PUSH = 45 degrees", 0x0UL); +#endif + } + else if ((retry_count%3) == LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_TWO){ //toggles between minimum CA delay and second smallest every 4 retrains. + //min_diff=second_diff; + min_diffp1=min_diffp2; + //min_refclk=(min_refclk-0x1UL)&&(0x7UL); + min_refclk=min_refclkp1; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r CK_PUSH = 90 degrees", 0x0UL); +#endif + } +#endif + if(a5_offset_status == DDR_ADD_CMD_A5_OFFSET_PASS) + { + refclk_phase =((*refclk_offset+min_refclk) & 0x7U)<<2U; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase | refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + for (uint32_t m=0U;m < min_diffp1; m++) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + } + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000000U; //DISABLE DLY Control & PLL Control +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r MANUAL ADDCMD TRAINING Results:\r\n PLL OFFSET: ",min_refclk); + (void)uprint32(g_debug_uart, "\n\r transition_a5_max: ", transition_a5_max); + (void)uprint32(g_debug_uart, "\n\r CA Output Delay: ", min_diffp1); + (void)uprint32(g_debug_uart, "\n\r CA Offset: ", *refclk_offset); +#endif + } + else + { + if(a5_offset_status & DDR_ADD_CMD_A5_OFFSET_FAIL) + { + if(init_del_offset < 0xFFU ) + { + init_del_offset = init_del_offset + (transition_a5_max) + 5U; //if transition_a5 too low, increase indly offset on CK and CA and retrain + } + else + { + break; + } + } + } /* end of for (j = 0U; j<16U ; j++) */ + } // while(a5_offset_status != DDR_ADD_CMD_A5_OFFSET_PASS) + } //END MANUAL ADDCMD TRAINING + + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x0000008U; + CFG_DDR_SGMII_PHY->expert_dfi_status_override_to_shim.expert_dfi_status_override_to_shim = 0x00000000U; + + //POST_INITIALIZATION + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x9U; + CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause = 0x0000003FU ; + CFG_DDR_SGMII_PHY->expert_dlycnt_pause.expert_dlycnt_pause = 0x00000000U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x8U; + delay(DELAY_CYCLES_500_NS); + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; + delay(DELAY_CYCLES_500_MICRO); + +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r Writing MR1 ", mode_register_masked_write_x5(1)); + (void)uprint32(g_debug_uart, "\n\r Writing MR2 ", mode_register_masked_write_x5(2)); + (void)uprint32(g_debug_uart, "\n\r Writing MR3 ", mode_register_masked_write_x5(3)); + (void)uprint32(g_debug_uart, "\n\r Writing MR4 ", mode_register_masked_write_x5(4)); + (void)uprint32(g_debug_uart, "\n\r Writing MR11 ", mode_register_masked_write_x5(11)); + (void)uprint32(g_debug_uart, "\n\r Writing MR16 ", mode_register_masked_write_x5(16)); + (void)uprint32(g_debug_uart, "\n\r Writing MR17 ", mode_register_masked_write_x5(17)); + (void)uprint32(g_debug_uart, "\n\r Writing MR22 ", mode_register_masked_write_x5(22)); + (void)uprint32(g_debug_uart, "\n\r Writing MR13 ", mode_register_masked_write_x5(13)); +#else + mode_register_masked_write_x5(1); + mode_register_masked_write_x5(2); + mode_register_masked_write_x5(3); + mode_register_masked_write_x5(4); + mode_register_masked_write_x5(11); + mode_register_masked_write_x5(16); + mode_register_masked_write_x5(17); + mode_register_masked_write_x5(22); + mode_register_masked_write_x5(13); +#endif + + delay(10U); + + DDRCFG->MC_BASE2.INIT_ZQ_CAL_START.INIT_ZQ_CAL_START = 1U; + DDRCFG->MC_BASE2.INIT_AUTOINIT_DISABLE.INIT_AUTOINIT_DISABLE=0x0U; + + volatile uint32_t timeout = 0U; + while((DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK==0) && (timeout < 0xFFU)) + { + delay(10U); + timeout++; + } + DDRCFG->MC_BASE2.INIT_ZQ_CAL_START.INIT_ZQ_CAL_START = 0U; + + DDRCFG->MC_BASE2.CFG_AUTO_ZQ_CAL_EN.CFG_AUTO_ZQ_CAL_EN =\ + LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN; + +} /* end of LPDDR4 exclusive */ + +/** + * used for LPDDR3 and DDR4 only + * @param ddr_type + * @param refclk_sweep_index refclk index which is swept + * @param bclk_phase + * @param bclk90_phase + * @param refclk_phase + */ +static void non_lpddr4_address_cmd_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index, uint32_t *bclk_phase, uint32_t *bclk90_phase, uint32_t *refclk_phase ) +{ + /* Begin MANUAL ADDCMD TRAINING */ + uint8_t refclk_offset; + uint32_t init_del_offset = 0x8U; + uint32_t a5_offset_status; + uint32_t rpc147_offset = 0x2U; //4 //0 + uint32_t rpc145_offset = 0x0U; //0 //4 + + refclk_offset = ddr_manual_addcmd_refclk_offset(ddr_type, refclk_sweep_index); + a5_offset_status = DDR_ADD_CMD_A5_OFFSET_FAIL; + while(a5_offset_status != DDR_ADD_CMD_A5_OFFSET_PASS) + { + a5_offset_status = DDR_ADD_CMD_A5_OFFSET_PASS; + + //ADDCMD Training improvement , adds delay on DDR clock loopback path - Suggested by Alister + CFG_DDR_SGMII_PHY->rpc147.rpc147 = init_del_offset + rpc147_offset; + + //ADDCMD Training improvement , adds delay on A9 loopback path - Suggested by Alister + CFG_DDR_SGMII_PHY->rpc145.rpc145 = init_del_offset + rpc145_offset; + + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000003U; //ENABLE DLY Control & PLL Control + + uint32_t rx_a5; + uint32_t rx_a5_last; + uint32_t rx_ck; + uint32_t rx_ck_last; + uint32_t transition_a5; + uint32_t transition_ck; + uint32_t i; + uint32_t j; + uint32_t difference [8]={0}; + uint32_t transition_ck_array [8]={0}; + + uint32_t transitions_found; + uint32_t transition_a5_max = 0U; + + for (j = 0U; j<16U ; j++) + { //Increase J loop to increase number of samples on transition_a5 (for noisy CA in LPDDR4) + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + *refclk_phase = (j % 8U) << 2U; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + rx_a5_last=0xFU; + rx_ck_last=0x5U; + transition_a5=0U; + transition_ck=0U; + + delay(100U); + transitions_found = 0U; + i = 0U; + while((!transitions_found) & (i < 128U)) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + delay(DELAY_CYCLES_500_NS); + rx_a5 = (CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x0300U) >> 8U; + rx_ck = CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x000F; + + if ((transition_a5 != 0U) && (transition_ck != 0U)) + { + if (((i - transition_a5) > 8U) && ((i - transition_ck) > 8U)) + { + //break; + transitions_found = 1U; + } + } + + if (transition_ck == 0U) { + if (rx_ck_last != 0x5U) //IF EDGE DETECTED + if (rx_ck == 0x5U) + transition_ck=i; //SET TRANSITION DETECTED AT I + rx_ck_last=rx_ck; + } + else { + if ( (i - transition_ck ) == 4U) + if (rx_ck != rx_ck_last) //IF rx_ck not stable after 4 increments, set transition detected to 0 (false transition) + { + transition_ck = 0U; //Continue looking for transition + rx_ck_last=rx_ck; + } + } + + if (transition_a5 == 0U) { + if ( ((rx_a5 ^ rx_a5_last) & rx_a5 ) ){ + transition_a5 = i; + } + else{ + rx_a5_last=rx_a5; + } + } + else { + if ((i - transition_a5) == 4U) + if(!((rx_a5 ^ rx_a5_last) & rx_a5 )) + { + transition_a5=0; //Continue looking for transition + rx_a5_last=rx_a5; + } + } + + if ((transition_a5 != 0U) && (transition_ck != 0U)) + if ((i==transition_a5) || (i==transition_ck)) + { +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r rx_a5 ",\ + rx_a5); + (void)uprint32(g_debug_uart, \ + " rx_ck ",\ + rx_ck); + (void)uprint32(g_debug_uart, \ + " rx_ck_last ",\ + rx_ck_last); + (void)uprint32(g_debug_uart, \ + " transition_a5 ",\ + transition_a5); + (void)uprint32(g_debug_uart, \ + " transition_ck ",\ + transition_ck); + (void)uprint32(g_debug_uart, \ + " Iteration: ",\ + i); + (void)uprint32(g_debug_uart, \ + " REFCLK_PHASE: ",\ + j); +#endif + } + i++; + }/* delay loop ends here */ + if(transition_a5 > transition_a5_max) + transition_a5_max =transition_a5; + + if ((transition_a5 != 0U) && (transition_ck != 0U) && (j<8U)) + { + transition_ck_array[j]=transition_ck; + /* difference now calculated in separate loop with max a5 intstead of per offset-AL*/ + } + }/* phase loop ends here */ + + + uint32_t min_diff=0xFFU; + uint32_t min_refclk=0x8U; + + if(transition_a5_max < 5U) + { + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL; + } + for (uint32_t k = 0U;k<8U;k++) + { + if(transition_a5_max >= transition_ck_array[k]) + difference[k]= transition_a5_max-transition_ck_array[k]; + else + difference[k]=0xff; + + if (difference[k] < min_diff){ + min_diff=difference[k]; + min_refclk=k; + } +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r difference ", difference[k]); + (void)uprint32(g_debug_uart, " REFCLK_PHASE ", k); +#endif + } + if(min_diff == 0xFFU) + { + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL; + } + if (min_refclk==0x8U) + { //If ADDCMD training fails due to extremely low frequency, use PLL to provide offset. + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL_LOW_FREQ; + } + if(a5_offset_status == DDR_ADD_CMD_A5_OFFSET_PASS) + { + *refclk_phase =((refclk_offset+min_refclk) & 0x7U)<<2U; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + for (uint32_t m=0U;m < min_diff; m++) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + } + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000000U; //DISABLE DLY Control & PLL Control +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r MANUAL ADDCMD TRAINING Results:\r\n PLL OFFSET: ",min_refclk); + (void)uprint32(g_debug_uart, "\n\r transition_a5_max: ", transition_a5_max); + (void)uprint32(g_debug_uart, "\n\r CA Output Delay: ", min_diff); +#endif + } + else + { + if(a5_offset_status & DDR_ADD_CMD_A5_OFFSET_FAIL) + { + if(init_del_offset < 0xFFU ) + { + //if transition_a5 too low, increase indly offset on CK and CA and retrain + init_del_offset = init_del_offset + (transition_a5_max) + 5U; + } + else + { + break; + } + } + } + } +} /* END MANUAL BCLKSCLK TRAINING */ + + +/** + * ddr3_address_cmd_training() + * @param ddr_type DDR3 + * @param refclk_sweep_index + * @param retry_count + * @param bclk_phase + * @param bclk90_phase + * @param refclk_phase + * @param refclk_offset + */ +static void ddr3_address_cmd_training(DDR_TYPE ddr_type, uint8_t * refclk_sweep_index, uint32_t retry_count, uint32_t *bclk_phase, uint32_t *bclk90_phase, uint32_t *refclk_phase, uint8_t *refclk_offset ) +{ + /* Begin MANUAL ADDCMD TRAINING */ + uint32_t init_del_offset = 0x8U; + uint32_t a5_offset_status; + uint32_t rpc147_offset = 0x2U; //4 //0 input delays, cmd and clk + uint32_t rpc145_offset = 0x0U; //0 //4 + + if( (retry_count%3)==0) + { + *refclk_offset = ddr_manual_addcmd_refclk_offset(ddr_type, refclk_sweep_index); + } + + a5_offset_status = DDR_ADD_CMD_A5_OFFSET_FAIL; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r\n\r\r ADDCMD_OFFSET used in this testing ", *refclk_offset); + (void)uprint32(g_debug_uart, "\n\r\n\r\r BCLK_OFFSET used in this testing ",bclk_sclk_offset(ddr_type)); +#endif + while(a5_offset_status != DDR_ADD_CMD_A5_OFFSET_PASS) + { + a5_offset_status = DDR_ADD_CMD_A5_OFFSET_PASS; + //ADDCMD Training improvement , adds delay on DDR clock loopback path + CFG_DDR_SGMII_PHY->rpc147.rpc147 = init_del_offset + rpc147_offset; + //ADDCMD Training improvement , adds delay on A9 loopback path + CFG_DDR_SGMII_PHY->rpc145.rpc145 = init_del_offset + rpc145_offset; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000003U; //ENABLE DLY Control & PLL Control + + uint32_t rx_a5; + uint32_t rx_a5_last; + uint32_t rx_ck; + uint32_t rx_ck_last; + uint32_t transition_a5; + uint32_t transition_ck; + uint32_t i; + uint32_t j; + uint32_t difference [8]={0}; + uint32_t transition_ck_array [8]={0}; + uint32_t transitions_found; + uint32_t transition_a5_max = 0U; + + for (j = 0U; j<16U ; j++) + { //Increase J loop to increase number of samples on transition_a5 (for noisy CA in LPDDR4) + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + *refclk_phase = (j % 8U) << 2U; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + rx_a5_last=0xFU; + rx_ck_last=0x5U; + transition_a5=0U; + transition_ck=0U; + + delay(100U); + transitions_found = 0U; + i = 0U; + while((!transitions_found) & (i < 128U)) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + delay(DELAY_CYCLES_500_NS); + rx_a5 = (CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x0300U) >> 8U; + rx_ck = CFG_DDR_SGMII_PHY->expert_addcmd_ln_readback.expert_addcmd_ln_readback & 0x000F; + + if ((transition_a5 != 0U) && (transition_ck != 0U)) + { + if (((i - transition_a5) > 8U) && ((i - transition_ck) > 8U)) + { + //break; + transitions_found = 1U; + } + } + + if (transition_ck == 0U) { + if (rx_ck_last != 0x5U) //IF EDGE DETECTED + if (rx_ck == 0x5U) + transition_ck=i; //SET TRANSITION DETECTED AT I + rx_ck_last=rx_ck; + } + else { + if ( (i - transition_ck ) == 4U) + if (rx_ck != rx_ck_last) //IF rx_ck not stable after 4 increments, set transition detected to 0 (false transition) + { + transition_ck = 0U; //Continue looking for transition + rx_ck_last=rx_ck; + } + } + + if (transition_a5 == 0U) { + if ( ((rx_a5 ^ rx_a5_last) & rx_a5 ) ){ + transition_a5 = i; + } + else{ + rx_a5_last=rx_a5; + } + } + else { + if ((i - transition_a5) == 4U) + if(!((rx_a5 ^ rx_a5_last) & rx_a5 )) + { + transition_a5=0; //Continue looking for transition + rx_a5_last=rx_a5; + } + } + + if ((transition_a5 != 0U) && (transition_ck != 0U)) + if ((i==transition_a5) || (i==transition_ck)) + { +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, \ + "\n\r rx_a5 ",\ + rx_a5); + (void)uprint32(g_debug_uart, \ + " rx_ck ",\ + rx_ck); + (void)uprint32(g_debug_uart, \ + " rx_ck_last ",\ + rx_ck_last); + (void)uprint32(g_debug_uart, \ + " transition_a5 ",\ + transition_a5); + (void)uprint32(g_debug_uart, \ + " transition_ck ",\ + transition_ck); + (void)uprint32(g_debug_uart, \ + " Iteration: ",\ + i); + (void)uprint32(g_debug_uart, \ + " REFCLK_PHASE: ",\ + j); +#endif + } + i++; + }/* delay loop ends here */ + if(transition_a5 > transition_a5_max) + transition_a5_max =transition_a5; + + if ((transition_a5 != 0U) && (transition_ck != 0U) && (j<8U)) + { + transition_ck_array[j]=transition_ck; + /* difference now calculated in separate loop with max a5 intstead of per offset-AL*/ + } + }/* phase loop ends here */ + + + uint32_t min_diff=0xFFU; + uint32_t min_refclk=0x8U; + +#ifdef MOVE_CK + uint32_t second_diff=0xFFU; + uint32_t second_refclk=0x8U; + uint32_t third_diff=0xFFU; + uint32_t third_refclk=0x8U; + +#endif + if(transition_a5_max < TRANSITION_A5_THRESHOLD) + { + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL; + } + + for (uint32_t l = 0U;l<8U;l++) + { + uint32_t k=7-l; + if(transition_a5_max >= transition_ck_array[k]) + difference[k]= transition_a5_max-transition_ck_array[k]; + else + difference[k]=0xff; + } + for (uint32_t l = 0U;l<8U;l++) + { + uint32_t k=7-l; + if (difference[k] < min_diff){ + //ALISTER ADDED TO MOVE CK without changing CK/CA offset +#ifdef MOVE_CK + second_refclk=(k+1)&0x7UL; + second_diff=difference[second_refclk]; + + third_refclk=(k+2)&0x7UL; + third_diff=difference[third_refclk]; +#endif + min_refclk=k; + min_diff=difference[min_refclk]; + } +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r difference ", difference[k]); + (void)uprint32(g_debug_uart, " REFCLK_PHASE ", k); +#endif + } +#ifdef MOVE_CK + if (((retry_count)%3) == 0x1){ + min_diff=second_diff; + min_refclk=second_refclk; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r CK_PUSH = 45 degrees", 0x0UL); +#endif + } else if (((retry_count )%3) == 0x2){ + min_diff=third_diff; + min_refclk=third_refclk; +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r CK_PUSH = 90 degrees", 0x0UL); +#endif + } +#endif + if(min_diff == 0xFFU) + { + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL; + } + if (min_refclk==0x8U) + { //If ADDCMD training fails due to extremely low frequency, use PLL to provide offset. + a5_offset_status |= DDR_ADD_CMD_A5_OFFSET_FAIL_LOW_FREQ; + } + if(a5_offset_status == DDR_ADD_CMD_A5_OFFSET_PASS) + { + *refclk_phase =((*refclk_offset+min_refclk) & 0x7U)<<2U; + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | *bclk_phase | *bclk90_phase | *refclk_phase); + //LOAD INDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + + //LOAD OUTDLY + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_load_reg1.expert_dlycnt_load_reg1 = 0x000000U; + for (uint32_t m=0U;m < min_diff; m++) + { + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x180000U; + CFG_DDR_SGMII_PHY->expert_dlycnt_move_reg1.expert_dlycnt_move_reg1 = 0x0U; + } + CFG_DDR_SGMII_PHY->expert_dlycnt_direction_reg1.expert_dlycnt_direction_reg1 = 0x000000U; + CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000000U; //DISABLE DLY Control & PLL Control +#ifdef DEBUG_DDR_INIT + (void)uprint32(g_debug_uart, "\n\r MANUAL ADDCMD TRAINING Results:\r\n PLL OFFSET: ",min_refclk); + (void)uprint32(g_debug_uart, "\n\r transition_a5_max: ", transition_a5_max); + (void)uprint32(g_debug_uart, "\n\r CA Output Delay: ", min_diff); +#endif + } + else + { + if(a5_offset_status & DDR_ADD_CMD_A5_OFFSET_FAIL) + { + if(init_del_offset < 0xFFU ) + { + /* + * if transition_a5 too low, increase indly offset on CK + * and CA and retrain + */ + init_del_offset = init_del_offset + (transition_a5_max) + 5U; + } + else + { + break; + } + } + } + } +} /* END MANUAL BCLKSCLK TRAINING */ + #endif /* DDR_SUPPORT */ diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.h index da8cc8d9..f75bf85b 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -326,6 +326,11 @@ typedef enum DDR_MEMORY_ACCESS_ DDR_NC_WCB_2GB, } DDR_MEMORY_ACCESS; +/* DDR clk frequency - should come from */ +#if !defined (LIBERO_SETTING_DDR_CLK) +#define LIBERO_SETTING_DDR_CLK DDR_1600_MHZ +#endif + /* this is a fixed value, currently only 5 supported in the TIP */ #define MAX_POSSIBLE_TIP_TRAININGS 0x05U @@ -340,11 +345,26 @@ typedef enum DDR_MEMORY_ACCESS_ #define BCLK_DPC_VRGEN_V_MASK (0x3FU<<12U) #define BCLK_DPC_VRGEN_H_SHIFT (4U) -#define BCLK_DPC_VRGEN_H_MASK (0xFU<<4U) +#define BCLK_DPC_VRGEN_H_MASK (0x3FU<<4U) #define BCLK_DPC_VRGEN_VS_SHIFT (0U) #define BCLK_DPC_VRGEN_VS_MASK (0xFU<<0U) +/* offsets and masks LIBERO_SETTING_DPC_BITS */ +#define DDR_DPC_VS_SHIFT 0U +#define DDR_DPC_VRGEN_H_SHIFT 4U +#define DDR_DPC_VRGEN_EN_H_SHIFT 10U +#define DDR_DPC_MOVE_EN_H_SHIFT 11U +#define DDR_DPC_VRGEN_V_SHIFT 12U +#define DDR_DPC_VRGEN_EN_V_SHIFT 18U +#define DDR_DPC_MOVE_EN_V_SHIFT 19U +#define DDR_DPC_VS_MASK (0xFU << DDR_DPC_VS_SHIFT) +#define DDR_DPC_VRGEN_H_MASK (0x3FU << DDR_DPC_VRGEN_H_SHIFT) +#define DDR_DPC_VRGEN_EN_H_MASK (0x1U << DDR_DPC_VRGEN_EN_H_SHIFT) +#define DDR_DPC_MOVE_EN_H_MASK (0x1U << DDR_DPC_MOVE_EN_H_SHIFT) +#define DDR_DPC_VRGEN_V_MASK (0xFU << DDR_DPC_VRGEN_V_SHIFT) +#define DDR_DPC_VRGEN_EN_V_MASK (0x1U << DDR_DPC_VRGEN_EN_V_SHIFT) +#define DDR_DPC_MOVE_EN_V_MASK (0x1U << DDR_DPC_MOVE_EN_V_SHIFT) /* masks and associated values used with DDRPHY_MODE register */ #define DDRPHY_MODE_MASK 0x7U @@ -364,16 +384,16 @@ typedef enum DDR_MEMORY_ACCESS_ /* Write latency min/max settings If write calibration fails * For Libero setting, we iterate through these values looking for a * Calibration pass */ -#define MIN_LATENCY 0UL -#define MAX_LATENCY 3UL //ML fixme- agree this value with Alister +#define DDR_CAL_MIN_LATENCY 0UL +#define DDR_CAL_MAX_LATENCY 3UL #define MTC_TIMEOUT_ERROR 0x02U #define DDR_MODE_REG_VREF 0xCU -#define CALIBRATION_PASSED 0xFF -#define CALIBRATION_FAILED 0xFE -#define CALIBRATION_SUCCESS 0xFC +#define DDR_CALIBRATION_PASSED 0xFF +#define DDR_CALIBRATION_FAILED 0xFE +#define DDR_CALIBRATION_SUCCESS 0xFC /* * Some settings that are only used during testing in new DDR setup @@ -382,6 +402,22 @@ typedef enum DDR_MEMORY_ACCESS_ #define ABNORMAL_RETRAIN_CA_DECREASE_COUNT 2U #define ABNORMAL_RETRAIN_CA_DLY_DECREASE_COUNT 2U #define DQ_DQS_NUM_TAPS 5U +#if !defined (LIBERO_SETTING_MIN_RPC_156_VALUE) +#define LIBERO_SETTING_MIN_RPC_156_VALUE 1U +#endif +#if !defined (LIBERO_SETTING_MAX_RPC_156_VALUE) +#define LIBERO_SETTING_MAX_RPC_156_VALUE 9U +#endif +#if !defined (LIBERO_SETTING_RPC_156_VALUE) + +/* DDR clk frequency - should come from */ +#if (LIBERO_SETTING_DDR_CLK == DDR_1600_MHZ) +#define LIBERO_SETTING_RPC_156_VALUE 6U +#else +#define LIBERO_SETTING_RPC_156_VALUE 1U +#endif +#endif +/* #define SW_CONFIG_LPDDR_WR_CALIB_FN */ #if !defined (LIBERO_SETTING_MAX_MANUAL_REF_CLK_PHASE_OFFSET) #define LIBERO_SETTING_MAX_MANUAL_REF_CLK_PHASE_OFFSET 4U @@ -397,12 +433,17 @@ typedef enum DDR_MEMORY_ACCESS_ /* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */ #endif -/* - * We currently need at least one retrain, otherwise driver can get stuck in - * sanity check state - */ -#if !defined (EN_RETRY_ON_FIRST_TRAIN_PASS) -#define EN_RETRY_ON_FIRST_TRAIN_PASS 0 +#ifndef TRANSITION_A5_THRESHOLD +#define TRANSITION_A5_THRESHOLD 18U +#endif + +/* Value used during write leveling */ +#ifndef DPC_VRGEN_H_LPDDR4_WR_LVL_VAL +#define DPC_VRGEN_H_LPDDR4_WR_LVL_VAL 0x5U +#endif +/* Value used during write leveling */ +#ifndef DPC_VRGEN_H_DDR3_WR_LVL_VAL +#define DPC_VRGEN_H_DDR3_WR_LVL_VAL 0x2U #endif #if !defined (DDR_FULL_32BIT_NC_CHECK_EN) @@ -444,9 +485,21 @@ typedef enum DDR_MEMORY_ACCESS_ #define NUM_RPC_166_VALUES (MAX_RPC_166_VALUE - MIN_RPC_166_VALUE) -/* This is a fixed setting, will move into driver in next commit */ -#if !defined (SW_TRAING_BCLK_SCLK_OFFSET) -#define SW_TRAING_BCLK_SCLK_OFFSET 0x00000000UL +/* Offsets for each mem type- fixed values */ +#if !defined (LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR4) +#define LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR4 0x00000005UL +#endif +#if !defined (LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR3) +#define LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR3 0x00000007UL +#endif +#if !defined (LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR4) +#define LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR4 0x00000006UL +#endif +#if !defined (LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3) +#define LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3 0x00000006UL +#endif +#if !defined (LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3L) +#define LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3L 0x00000006UL #endif /* * 0x6DU => setting vref_ca to 40% @@ -459,7 +512,10 @@ typedef enum DDR_MEMORY_ACCESS_ /* number of test writes to perform */ #if !defined (SW_CFG_NUM_READS_WRITES) -#define SW_CFG_NUM_READS_WRITES 0x20000U +#define SW_CFG_NUM_READS_WRITES 0x20000U +#endif +#if !defined (SW_CFG_NUM_READS_WRITES_FAST_START) +#define SW_CFG_NUM_READS_WRITES_FAST_START 0x2000U #endif /* * what test patterns to write/read on start-up @@ -472,6 +528,42 @@ typedef enum DDR_MEMORY_ACCESS_ PATTERN_0xCCCCCCCC|\ PATTERN_0x55555555) #endif +#if !defined (SW_CONFIG_PATTERN_FAST_START) +#define SW_CONFIG_PATTERN_FAST_START (PATTERN_INCREMENTAL|\ + PATTERN_WALKING_ZERO) +#endif + +#if !defined (LIBERO_FAST_START) +#define LIBERO_FAST_START 0U +#endif + +/* + * Default order of ADDCMD clk pushes + * These will be overwritten when supported in Libero + * Currently (2022.03) if change of order required, define in mss_sw_config.h + * Define in mss_sw_config.h will take precedence + */ +#if (LIBERO_SETTING_DDR_CLK == DDR_1600_MHZ) +#if !defined (LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ZERO) +#define LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ZERO 1U +#endif +#if !defined (LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ONE) +#define LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ONE 2U +#endif +#if !defined (LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_TWO) +#define LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_TWO 0U +#endif +#else +#if !defined (LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ZERO) +#define LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ZERO 0U +#endif +#if !defined (LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ONE) +#define LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_ONE 1U +#endif +#if !defined (LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_TWO) +#define LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_TWO 2U +#endif +#endif /* * Sweep offsets @@ -484,9 +576,9 @@ typedef enum DDR_MEMORY_ACCESS_ * LPDDR3@1066 = 7,0,1 * LPDDR4@1600 = 5,4,6,3 * - * DDR3@1333 = 1,7,0,2 + * DDR3@1333 = 0,1 //1,7,0,2 * DDR4@1333 = 0,7,1 - * LPDDR3@1333 = 7,0,6 + * LPDDR3@1333 = 0,1 //7,0,6 * LPDDR4@1333 = 1,2,3 * */ @@ -506,14 +598,14 @@ typedef enum DDR_MEMORY_ACCESS_ #define CA_SWEEP_INCREMENT 5U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1600_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_DDR3_1600_NUM_OFFSETS 3U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS) +#define LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS 3U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1600_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_DDR3L_1600_NUM_OFFSETS 3U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS) +#define LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS 3U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS 3U +#define LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS 4U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS) #define LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS 3U @@ -521,56 +613,56 @@ typedef enum DDR_MEMORY_ACCESS_ #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS) #define LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS 4U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS 4U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS) +#define LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS 1U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS 3U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_NUM_OFFSETS) +#define LIBERO_SETTING_REFCLK_DDR3L_1067_NUM_OFFSETS 1U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS 3U +#define LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS 4U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS) -#define LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS 3U +#define LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS 2U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS) #define LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS 3U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_0) -#define LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_0 3U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0) +#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0 0U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_1) -#define LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_1 2U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1) +#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1 1U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_2) -#define LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_2 1U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2) +#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2 7U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_3) -#define LIBERO_SETTING_REFCLK_DDR3_1600_OFFSET_3 0U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3) +#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3 0U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_0) -#define LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_0 3U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0) +#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0 0U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_1) -#define LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_1 2U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1) +#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1 1U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_2) -#define LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_2 1U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2) +#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2 0U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_3) -#define LIBERO_SETTING_REFCLK_DDR3L_1600_OFFSET_3 0U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3) +#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3 0U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0) #define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0 7U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1) -#define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1 0U +#define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1 6U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2) -#define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2 1U +#define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2 5U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3) #define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3 0U @@ -586,69 +678,71 @@ typedef enum DDR_MEMORY_ACCESS_ #define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_2 1U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3) -#define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3 0U +#define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3 2U #endif //LPDDR4@1600 = 5,4,6,3 changed to 5,4,6,2 16th Feb Alister +//AUG Offsets changed to 4324 +//LPDDR4@1600 = 4,3,2,4 changed to 3,4,2,5 Feb 2022 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0) -#define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0 5U +#define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0 3U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1) #define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1 4U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2) -#define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2 6U +#define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2 2U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3) -#define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3 3U +#define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3 5U #endif /* * 1333 offset */ -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0) -#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0 1U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_0) +#define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_0 1U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1) -#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1 7U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_1) +#define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_1 2U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2) -#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2 0U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_2) +#define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_2 3U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3) -#define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3 2U +#if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_3) +#define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_3 2U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0) -#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0 1U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_0) +#define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_0 1U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1) -#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1 7U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_1) +#define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_1 2U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2) -#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2 0U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_2) +#define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_2 3U #endif -#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3) -#define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3 2U +#if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_3) +#define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_3 2U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0) #define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0 0U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1) -#define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1 7U +#define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1 1U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2) -#define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2 1U +#define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2 6U #endif #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3) -#define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3 0U +#define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3 7U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0) -#define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0 7U +#define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0 0U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1) -#define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1 0U +#define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1 1U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2) #define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2 6U @@ -658,10 +752,10 @@ typedef enum DDR_MEMORY_ACCESS_ #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0) -#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0 1U +#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0 2U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1) -#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1 2U +#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1 1U #endif #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2) #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 3U @@ -670,14 +764,6 @@ typedef enum DDR_MEMORY_ACCESS_ #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 0U #endif -/* Bit1 == 0 => 1600Mhz Bit1 == 1 => 1333Mhz */ -#if !defined (LIBERO_SETTING_DDR_CLK) -#define LIBERO_SETTING_DDR_CLK 1600000000 -#endif - -#define DDR_1333_MHZ 1333333333 -#define DDR_1600_MHZ 1600000000 - #ifndef NOT_A_FULL_RETRAIN #define NOT_A_FULL_RETRAIN #endif @@ -882,6 +968,7 @@ typedef enum DDR_TRAINING_SM_ DDR_TRAINING_VREFDQ_CALIB, DDR_TRAINING_FPGA_VREFDQ_CALIB, DDR_TRAINING_FINISH_CHECK, + DDR_TRAINING_INIT_ALL_MEMORY, DDR_TRAINING_FINISHED, DDR_TRAINING_FAIL_SM2_VERIFY, DDR_TRAINING_FAIL_SM_VERIFY, @@ -956,7 +1043,14 @@ typedef enum SEG_SETUP_{ LIBERO_SEG_SETUP } SEG_SETUP; +/***************************************************************************//** + */ +typedef struct mss_ddr_diags_{ + uint64_t train_time; + uint32_t num_retrains; + uint32_t padding; +} mss_ddr_diag; /***************************************************************************//** @@ -964,9 +1058,9 @@ typedef enum SEG_SETUP_{ typedef struct mss_ddr_fpga_vref_{ uint32_t status_lower; uint32_t status_upper; - uint32_t lower; - uint32_t upper; - uint32_t vref_result; + uint32_t lower; + uint32_t upper; + uint32_t vref_result; } mss_ddr_vref; /** @@ -1018,8 +1112,8 @@ typedef struct mss_ddr_calibration_{ /* CMSIS related defines identifying the UART hardware. */ mss_ddr_write_calibration write_cal; mss_lpddr4_dq_calibration dq_cal; - mss_ddr_vref fpga_vref; - mss_ddr_vref mem_vref; + mss_ddr_vref fpga_vref; + mss_ddr_vref mem_vref; } mss_ddr_calibration; /***************************************************************************//** diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c index 0c8951a1..5c8589b0 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -18,6 +18,7 @@ #include #include #include "mpfs_hal/mss_hal.h" +#include "mss_nwc_init.h" /******************************************************************************* * Local Defines @@ -38,21 +39,12 @@ static uint32_t g_test_buffer_not_cached[765]; /******************************************************************************* * External Defines */ -#ifdef DEBUG_DDR_INIT -#ifdef SWEEP_ENABLED -extern uint8_t sweep_results[MAX_NUMBER_DPC_VS_GEN_SWEEPS]\ - [MAX_NUMBER_DPC_H_GEN_SWEEPS]\ - [MAX_NUMBER_DPC_V_GEN_SWEEPS]\ - [MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS]\ - [MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS]; -#endif -#endif extern const uint32_t ddr_test_pattern[768]; +extern const uint32_t ddr_init_pattern[64U]; /******************************************************************************* * External function declarations */ -extern void delay(uint32_t n); extern void pdma_transfer(uint64_t destination, uint64_t source, uint64_t size_in_bytes, uint64_t base_address); extern void pdma_transfer_complete( uint64_t base_address); @@ -72,6 +64,15 @@ static uint32_t ddr_write ( volatile uint64_t *DDR_word_ptr,\ uint32_t no_of_access, uint8_t data_ptrn, DDR_ACCESS_SIZE data_size ); static uint32_t ddr_read ( volatile uint64_t *DDR_word_ptr,\ uint32_t no_of_access, uint8_t data_ptrn, DDR_ACCESS_SIZE data_size ); +static void load_test_buffers(uint32_t * p_cached_ddr,\ + uint32_t * p_not_cached_ddr, uint64_t length); + +#ifdef HSS +__attribute__((weak)) int rand(void) +{ + return(0); +} +#endif #ifdef DEBUG_DDR_INIT /***************************************************************************//** @@ -356,7 +357,7 @@ uint32_t ddr_read } if (data_ptrn == '4') { - delay(10); + delay(DELAY_CYCLES_500_NS); } for( i = 0; i< (no_of_access); i++) { @@ -554,6 +555,7 @@ uint32_t tip_register_status (mss_uart_instance_t *g_mss_uart_debug_pt) uint32_t t_status = 0U; uint32_t MSS_DDR_APB_ADDR; uint32_t ddr_lane_sel; + uint32_t rank_sel; uint32_t dq0_dly = 0U; uint32_t dq1_dly = 0U; uint32_t dq2_dly = 0U; @@ -562,7 +564,7 @@ uint32_t tip_register_status (mss_uart_instance_t *g_mss_uart_debug_pt) uint32_t dq5_dly = 0U; /* MSS_UART_polled_tx_string(g_mss_uart_debug_pt, "\n\n\r TIP register status \n"); - delay(1000);*/ + delay(DELAY_CYCLES_50_MICRO);*/ uprint32(g_mss_uart_debug_pt, "\n\r\n\r training status = ",\ CFG_DDR_SGMII_PHY->training_status.training_status); uprint32(g_mss_uart_debug_pt, "\n\r PCODE = ",\ @@ -580,179 +582,119 @@ uint32_t tip_register_status (mss_uart_instance_t *g_mss_uart_debug_pt) uprint32(g_mss_uart_debug_pt, "\n\r sro_slewf = ",\ (((CFG_DDR_SGMII_PHY->IOC_REG5.IOC_REG5) >> 24) & 0x3F)); - MSS_UART_polled_tx_string(g_mss_uart_debug_pt, \ - (const uint8_t*)"\n\n\r lane_select \t gt_err_comb \t gt_txdly \t gt_steps_180 \t gt_state \t wl_delay_0 \t dqdqs_err_done \t dqdqs_state \t delta0 \t delta1"); - - for (ddr_lane_sel=0U; ddr_lane_sel < LIBERO_SETTING_DATA_LANES_USED; ddr_lane_sel++) + for (rank_sel=0; rank_sel < LIBERO_SETTING_CFG_NUM_RANKS; rank_sel++) { - CFG_DDR_SGMII_PHY->lane_select.lane_select = ddr_lane_sel; - uprint32(g_mss_uart_debug_pt, "\n\r ",\ - CFG_DDR_SGMII_PHY->lane_select.lane_select); - delay(1000); - MSS_DDR_APB_ADDR = CFG_DDR_SGMII_PHY->gt_err_comb.gt_err_comb; - uprint32(g_mss_uart_debug_pt, "\t ", MSS_DDR_APB_ADDR); - t_status = t_status | MSS_DDR_APB_ADDR; - - MSS_DDR_APB_ADDR = CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly; - uprint32(g_mss_uart_debug_pt, "\t ", MSS_DDR_APB_ADDR); - - if((MSS_DDR_APB_ADDR & 0xFF) == 0) t_status = 1; - if((MSS_DDR_APB_ADDR & 0xFF00) == 0) t_status = 1; - if((MSS_DDR_APB_ADDR & 0xFF0000) == 0) t_status = 1; - if((MSS_DDR_APB_ADDR & 0xFF000000) == 0) t_status = 1; - - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->gt_steps_180.gt_steps_180); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->gt_state.gt_state); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->wl_delay_0.wl_delay_0); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->dq_dqs_err_done.dq_dqs_err_done); - t_status = t_status | (MSS_DDR_APB_ADDR != 8); - - uprint32(g_mss_uart_debug_pt, "\t\t ",\ - CFG_DDR_SGMII_PHY->dqdqs_state.dqdqs_state); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->delta0.delta0); - dq0_dly = (MSS_DDR_APB_ADDR & 0xFF); - dq1_dly = (MSS_DDR_APB_ADDR & 0xFF00) >> 8; - dq2_dly = (MSS_DDR_APB_ADDR & 0xFF0000) >> 16; - dq3_dly = (MSS_DDR_APB_ADDR & 0xFF000000) >> 24; - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->delta1.delta1); - dq4_dly = (MSS_DDR_APB_ADDR & 0xFF); - dq5_dly = (MSS_DDR_APB_ADDR & 0xFF00) >> 8; - dq2_dly = (MSS_DDR_APB_ADDR & 0xFF0000) >> 16; - dq3_dly = (MSS_DDR_APB_ADDR & 0xFF000000) >> 24; - } + CFG_DDR_SGMII_PHY->rank_select.rank_select=rank_sel; + uprint32(g_mss_uart_debug_pt, "\n\r\n\r rank number", rank_sel); + MSS_UART_polled_tx_string(g_mss_uart_debug_pt, \ + (const uint8_t*)"\n\n\r lane_select \t gt_err_comb \t gt_txdly \t gt_steps_180 \t gt_state \t wl_delay_0 \t dqdqs_err_done \t dqdqs_state \t delta0 \t delta1"); + for (ddr_lane_sel=0U; ddr_lane_sel < LIBERO_SETTING_DATA_LANES_USED; ddr_lane_sel++) + { + CFG_DDR_SGMII_PHY->lane_select.lane_select = ddr_lane_sel; + uprint32(g_mss_uart_debug_pt, "\n\r ", CFG_DDR_SGMII_PHY->lane_select.lane_select); + delay(DELAY_CYCLES_50_MICRO); + MSS_DDR_APB_ADDR = CFG_DDR_SGMII_PHY->gt_err_comb.gt_err_comb; + uprint32(g_mss_uart_debug_pt, "\t ", MSS_DDR_APB_ADDR); + t_status = t_status | MSS_DDR_APB_ADDR; + + MSS_DDR_APB_ADDR = CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly; + uprint32(g_mss_uart_debug_pt, "\t ", MSS_DDR_APB_ADDR); + + if((MSS_DDR_APB_ADDR & 0xFF) == 0) t_status = 1; + if((MSS_DDR_APB_ADDR & 0xFF00) == 0) t_status = 1; + if((MSS_DDR_APB_ADDR & 0xFF0000) == 0) t_status = 1; + if((MSS_DDR_APB_ADDR & 0xFF000000) == 0) t_status = 1; + + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->gt_steps_180.gt_steps_180); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->gt_state.gt_state); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->wl_delay_0.wl_delay_0); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->dq_dqs_err_done.dq_dqs_err_done); + t_status = t_status | (MSS_DDR_APB_ADDR != 8); + + uprint32(g_mss_uart_debug_pt, "\t\t ",\ + CFG_DDR_SGMII_PHY->dqdqs_state.dqdqs_state); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->delta0.delta0); + dq0_dly = (MSS_DDR_APB_ADDR & 0xFF); + dq1_dly = (MSS_DDR_APB_ADDR & 0xFF00) >> 8; + dq2_dly = (MSS_DDR_APB_ADDR & 0xFF0000) >> 16; + dq3_dly = (MSS_DDR_APB_ADDR & 0xFF000000) >> 24; + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->delta1.delta1); + dq4_dly = (MSS_DDR_APB_ADDR & 0xFF); + dq5_dly = (MSS_DDR_APB_ADDR & 0xFF00) >> 8; + dq2_dly = (MSS_DDR_APB_ADDR & 0xFF0000) >> 16; + dq3_dly = (MSS_DDR_APB_ADDR & 0xFF000000) >> 24; + } - MSS_UART_polled_tx_string(g_mss_uart_debug_pt, (const uint8_t*)"\n\r\n\r lane_select\t rdqdqs_status2\t addcmd_status0\t addcmd_status1\t addcmd_answer1\t dqdqs_status1\n\r"); - for (ddr_lane_sel=0U; ddr_lane_sel < LIBERO_SETTING_DATA_LANES_USED;\ - ddr_lane_sel++) - { - CFG_DDR_SGMII_PHY->lane_select.lane_select = ddr_lane_sel; - uprint32(g_mss_uart_debug_pt, "\n\r ",\ - CFG_DDR_SGMII_PHY->lane_select.lane_select); - delay(1000); - - if(dq0_dly > 20) t_status = 1; - if(dq1_dly > 20) t_status = 1; - if(dq2_dly > 20) t_status = 1; - if(dq3_dly > 20) t_status = 1; - if(dq4_dly > 20) t_status = 1; - if(dq5_dly > 20) t_status = 1; - - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->dqdqs_status2.dqdqs_status2); - - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->addcmd_status0.addcmd_status0); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->addcmd_status1.addcmd_status1); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->addcmd_answer.addcmd_answer); - uprint32(g_mss_uart_debug_pt, "\t ",\ - CFG_DDR_SGMII_PHY->dqdqs_status1.dqdqs_status1); + MSS_UART_polled_tx_string(g_mss_uart_debug_pt, (const uint8_t*)"\n\r\n\r lane_select\t rdqdqs_status2\t addcmd_status0\t addcmd_status1\t addcmd_answer1\t dqdqs_status1\n\r"); + for (ddr_lane_sel=0U; ddr_lane_sel < LIBERO_SETTING_DATA_LANES_USED;\ + ddr_lane_sel++) + { + CFG_DDR_SGMII_PHY->lane_select.lane_select = ddr_lane_sel; + uprint32(g_mss_uart_debug_pt, "\n\r ",\ + CFG_DDR_SGMII_PHY->lane_select.lane_select); + delay(DELAY_CYCLES_50_MICRO); + + if(dq0_dly > 20) t_status = 1; + if(dq1_dly > 20) t_status = 1; + if(dq2_dly > 20) t_status = 1; + if(dq3_dly > 20) t_status = 1; + if(dq4_dly > 20) t_status = 1; + if(dq5_dly > 20) t_status = 1; + + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->dqdqs_status2.dqdqs_status2); + + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->addcmd_status0.addcmd_status0); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->addcmd_status1.addcmd_status1); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->addcmd_answer.addcmd_answer); + uprint32(g_mss_uart_debug_pt, "\t ",\ + CFG_DDR_SGMII_PHY->dqdqs_status1.dqdqs_status1); - } + } + } /* end rank select */ return(t_status); } #endif -/***************************************************************************//** - * display sweep results - * - * @param g_mss_uart_debug_pt +/** + * Load a pattern to DDR */ -#ifdef DEBUG_DDR_INIT -#ifdef SWEEP_ENABLED -void sweep_status (mss_uart_instance_t *g_mss_uart_debug_pt) +void load_ddr_pattern(uint64_t base, uint64_t size, uint32_t pattern_type, \ + volatile uint8_t pattern_offset) { + int alive = 0; + uint32_t *pattern; + volatile uint32_t pattern_size; + uint8_t *p_ddr = (uint8_t *)base; - uint32_t t_status; - uint8_t cmd_index; - uint8_t bclk_sclk_index; - uint8_t dpc_vgen_index; - uint8_t dpc_vgen_h_index; - uint8_t dpc_vgen_vs_index; - - MSS_UART_polled_tx_string(g_mss_uart_debug_pt,\ - "\n\n\r dpc_vgen_vs dpc_vgen_h \t dpc_vgen_v \t bclk_sclk"); - for (cmd_index=0U; cmd_index < MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS; \ - cmd_index++) + if (pattern_type == DDR_TEST_FILL) { - uprint32(g_mss_uart_debug_pt, "\t ",\ - cmd_index + LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET); + pattern = (uint32_t *)ddr_test_pattern; + pattern_size = sizeof(ddr_test_pattern); } - MSS_UART_polled_tx_string(g_mss_uart_debug_pt,\ - "\n\r--------------------------------------------------------------------"); - - for (dpc_vgen_vs_index=0U; dpc_vgen_vs_index #include "mpfs_hal/mss_hal.h" +#ifdef LIBERO_SETTING_ALT_IOMUX1_CR +#if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) == (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) +static uint8_t io_mux_and_bank_config_alt(void); +#endif +#endif /******************************************************************************* * external functions @@ -38,6 +43,20 @@ IOMUX_CONFIG iomux_config_values = { are inverted on entry to the IOMUX structure */ }; +#ifdef LIBERO_SETTING_ALT_IOMUX1_CR +IOMUX_CONFIG iomux_alt_config_values = { + LIBERO_SETTING_ALT_IOMUX0_CR, /* Selects whether the peripheral is connected to + the Fabric or IOMUX structure. */ + LIBERO_SETTING_ALT_IOMUX1_CR, /* BNK4 SDV PAD 0 to 7, each IO has 4 bits */ + LIBERO_SETTING_ALT_IOMUX2_CR, /* BNK4 SDV PAD 8 to 13 */ + LIBERO_SETTING_ALT_IOMUX3_CR, /* BNK2 SDV PAD 14 to 21 */ + LIBERO_SETTING_ALT_IOMUX4_CR, /* BNK2 SDV PAD 22 to 29 */ + LIBERO_SETTING_ALT_IOMUX5_CR, /* BNK2 PAD 30 to 37 */ + LIBERO_SETTING_ALT_IOMUX6_CR /* Sets whether the MMC/SD Voltage select lines + are inverted on entry to the IOMUX structure */ +}; +#endif + /* * Bank 4 and 2 settings, the 38 MSSIO. */ @@ -63,6 +82,33 @@ MSSIO_BANK4_CONFIG mssio_bank4_io_config = { LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR, }; +/* + * Bank 4 and 2 settings, the 38 MSSIO. + */ +#ifdef LIBERO_SETTING_ALT_IOMUX1_CR +MSSIO_BANK4_CONFIG mssio_alt_bank4_io_config = { + /* LIBERO_SETTING_mssio_bank4_io_cfg_0_cr + x_vddi Ratio Rx<0-2> == 001 + drv<3-6> == 1111 + 7:clamp == 0 + enhyst == 0 + lockdn_en == 1 + 10:wpd == 0 + atp_en`== 0 + lpmd_ibuf == 0 + lpmd_obuf == 0 + persist == 0 + */ + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_0_1_CR, + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_2_3_CR, + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_4_5_CR, + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_6_7_CR, + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_8_9_CR, + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_10_11_CR, + LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_12_13_CR, +}; +#endif + /* * Bank 4 and 2 settings, the 38 MSSIO. */ @@ -93,6 +139,35 @@ MSSIO_BANK2_CONFIG mssio_bank2_io_config = { LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR }; +#ifdef LIBERO_SETTING_ALT_IOMUX1_CR +MSSIO_BANK2_CONFIG mssio_alt_bank2_io_config = { + /* LIBERO_SETTING_mssio_bank4_io_cfg_0_cr + x_vddi Ratio Rx<0-2> == 001 + drv<3-6> == 1111 + 7:clamp == 0 + enhyst == 0 + lockdn_en == 1 + 10:wpd == 0 + atp_en`== 0 + lpmd_ibuf == 0 + lpmd_obuf == 0 + persist == 0 + */ + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_0_1_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_2_3_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_4_5_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_6_7_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_8_9_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_10_11_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_12_13_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_14_15_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_16_17_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_18_19_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_20_21_CR, + LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_22_23_CR +}; +#endif + /******************************************************************************* * Local functions */ @@ -131,7 +206,7 @@ uint8_t mssio_setup(void) { uint8_t ret_status = 0U; ret_status = io_mux_and_bank_config(); - set_bank2_and_bank4_volts(); + set_bank2_and_bank4_volts(DEFAULT_MSSIO_CONFIGURATION); return (ret_status); } @@ -195,10 +270,80 @@ static uint8_t io_mux_and_bank_config(void) &(mssio_bank2_io_config), sizeof(MSSIO_BANK2_CONFIG)); - set_bank2_and_bank4_volts(); + set_bank2_and_bank4_volts(DEFAULT_MSSIO_CONFIGURATION); + + return(0L); +} + +/***************************************************************************//** + * io_mux_and_bank_config_alt(void) + * Configures alt setting + * @return + */ +#ifdef LIBERO_SETTING_ALT_IOMUX1_CR +#if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) == (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) +static uint8_t io_mux_and_bank_config_alt(void) +{ + /* Configure IO mux's + * + * IOMUX1_CR - IOMUX5_CR, five 32-bit registers, with four bits four bits + * for each I/O determine what is connected to each pad + * + * All internal peripherals are also connected to the fabric (apart from + * MMC/SDIO/GPIO/USB). The IOMUX0 register configures whether the IO + * function is connected to the fabric or the IOMUX. + * + * IOMUX6_CR Sets whether the MMC/SD Voltage select lines are inverted on + * entry to the IOMUX structure + * + * */ + + config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), + &(iomux_alt_config_values), + sizeof(IOMUX_CONFIG)); + + /* + * Configure MSS IO banks + * sets pcode and ncode using (mssio_bank2_cfg_cr/mssio_bank4_cfg_cr) + * + * The MSS IO pad configuration is provided by nineteen system registers + * each configuring two IO's using 15-bits per IO + * - (mssio_bank*_io_cfg_*_*_cr). + + | mssio_bank*_io_cfg_*_*_cr | offset | info | + | field | offset | info | + |:-------------------------:|:-------------:|:-----| + | io_cfg_ibufmd_0 |0 | | + | io_cfg_ibufmd_1 |1 | | + | io_cfg_ibufmd_2 |2 | | + | io_cfg_drv_0 |3 | | + | Io_cfg_drv_1 |4 | | + | Io_cfg_drv_2 |5 | | + | io_cfg_drv_3 |6 | | + | io_cfg_clamp |7 | | + | io_cfg_enhyst |8 | | + | io_cfg_lockdn_en |9 | | + | io_cfg_wpd |10 | | + | io_cfg_wpu |11 | | + | io_cfg_atp_en |12 | | + | io_cfg_lp_persist_en |13 | | + | io_cfg_lp_bypass_en |14 | | + * */ + + config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), + &(mssio_alt_bank4_io_config), + sizeof(MSSIO_BANK4_CONFIG)); + + config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), + &(mssio_alt_bank2_io_config), + sizeof(MSSIO_BANK2_CONFIG)); + + set_bank2_and_bank4_volts(DEFAULT_MSSIO_CONFIGURATION); return(0L); } +#endif +#endif /** * set_bank2_and_bank4_volts(void) @@ -208,17 +353,277 @@ static uint8_t io_mux_and_bank_config(void) * vs * @return */ -void set_bank2_and_bank4_volts(void) +void set_bank2_and_bank4_volts(MSSIO_CONFIG_OPTION config) { - SCB_REGS->MSSIO_BANK2_CFG_CR.MSSIO_BANK2_CFG_CR =\ - (uint32_t)LIBERO_SETTING_MSSIO_BANK2_CFG_CR; - SCB_REGS->MSSIO_BANK4_CFG_CR.MSSIO_BANK4_CFG_CR =\ - (uint32_t)LIBERO_SETTING_MSSIO_BANK4_CFG_CR; + switch(config) + { + default: + SCB_REGS->MSSIO_BANK2_CFG_CR.MSSIO_BANK2_CFG_CR =\ + (uint32_t)LIBERO_SETTING_MSSIO_BANK2_CFG_CR; + SCB_REGS->MSSIO_BANK4_CFG_CR.MSSIO_BANK4_CFG_CR =\ + (uint32_t)LIBERO_SETTING_MSSIO_BANK4_CFG_CR; + break; + +#ifdef LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS + case ALT_MSSIO_CONFIGURATION: + break; +#endif + } return; } +/***************************************************************************//** + * alternate_io_configured() + * Answers question is alternate I/O configuration present + * @return true/false + */ +uint8_t mss_is_alternate_io_configured(void) +{ + uint8_t result = false; +#ifdef LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS + if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) == (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) + { + result = true; + } +#endif + return result; +} + +/***************************************************************************//** + * alternate_io_setting_sd() + * Answers question is alternate setting SD? + * @return returns true if sd is alternate setting + */ +uint8_t mss_is_alternate_io_setting_sd(void) +{ + uint8_t result = false; +#ifdef LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS + if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) == (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) + { + if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & DEFAULT_ON_START_MASK)!=DEFAULT_ON_START_MASK) + { + result = true; + } + } +#endif + return result; +} + +/***************************************************************************//** + * alternate_io_setting_sd() + * Answers question is alternate setting emmc? + * @return returns true if sd is alternate setting + */ +uint8_t mss_is_alternate_io_setting_emmc(void) +{ + uint8_t result = false; +#ifdef LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS + if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) == (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) + { + if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & DEFAULT_ON_START_MASK)==DEFAULT_ON_START_MASK) + { + result = true; + } + } +#endif + return result; +} + +/** + * Determines if MSSIO alt switch support in MSS configurator version + * Does not indicate if alternate has been configured. + * Indicates you can use the following to determine setup + * mss_io_defaut_setting(void) + * mss_is_alternate_io_configured(void) + * mss_is_alternate_io_setting_emmc(void) + * mss_is_alternate_io_setting_sd(void) + * + * @return return true/false + */ +uint8_t mss_does_xml_ver_support_switch(void) +{ + uint8_t result = false; +#ifdef LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR + uint32_t header_ver = (LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR*100) + (LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR*10) + LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH; + uint32_t xml_ver = (LIBERO_SETTING_XML_VERSION_MAJOR*100) + (LIBERO_SETTING_XML_VERSION_MINOR*10) + LIBERO_SETTING_XML_VERSION_PATCH; + + if ((header_ver >= 64U) && (xml_ver >= 56U)) + { + result = true; + } +#else + (void)result; +#endif + return result; +} + + +/** + * mss_io_default_setting(void) + * @return returns what is configured on default if mss configurator version supports this. + */ +#ifdef LIBERO_SETTING_ALT_IOMUX1_CR +uint8_t mss_io_default_setting(void) +{ + uint8_t result; + + if ( mss_does_xml_ver_support_switch() == false ) + { + result = NO_SUPPORT_MSSIO_CONFIGURATION; + } + else + { +#ifdef LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS +#if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (SD_CONFIGURED_MASK | DEFAULT_ON_START_MASK)) == (SD_CONFIGURED_MASK | DEFAULT_ON_START_MASK)) + + result = SD_MSSIO_CONFIGURATION; + +#elif ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | DEFAULT_ON_START_MASK)) == (EMMC_CONFIGURED_MASK)) + + result = SD_MSSIO_CONFIGURATION; +#else + result = NOT_SETUP_MSSIO_CONFIGURATION; +#endif +#endif + } + + return(result); +} +#endif + +/** + * Set the MSSIO to a desired config + * @param option SD or eMMC + * @return + */ +uint8_t switch_mssio_config(MSS_IO_OPTIONS option) +{ + uint8_t result = false; +#ifdef LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS +#if ((LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS & (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) == (EMMC_CONFIGURED_MASK | SD_CONFIGURED_MASK)) + switch(option) + { + case SD_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_sd() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); + break; + + case EMMC_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_emmc() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); + break; + + case NO_SUPPORT_MSSIO_CONFIGURATION: + break; + + case NOT_SETUP_MSSIO_CONFIGURATION: + break; + } + result = true; +#else + (void)option; + result = false; +#endif +#endif + return result; +} + +/** + * Is there a mux present, define is true by default + * @return true/false + */ +__attribute__((weak)) uint8_t fabric_sd_emmc_demux_present(void) +{ + return (uint8_t) FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT; +} + +/** + * Returns the fabric mux address + * @return address of the mux in fabric + */ +__attribute__((weak)) uint32_t * fabric_sd_emmc_demux_address(void) +{ + return (uint32_t *)FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS; +} + +/** + * switch_demux_using_fabric_ip() + * Requires fpga switch hdl. This comes with the reference icicle kit design. + * You will need to create your own or copy when creating your own fpga design + * along with an external mux in your board design if you wish to use SD/eMMC + * muxing in your hardware design. + * Please note this function will cause a hang if you do not have support + * for switching in your fpga design. Only use if you have this support if your + * fabric design. + * @param option SD_MSSIO_CONFIGURATION/EMMC_MSSIO_CONFIGURATION + * @return + */ +__attribute__((weak)) uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option) +{ + uint8_t result = false; + + if (fabric_sd_emmc_demux_present() == true) + { + volatile uint32_t *reg_pt = fabric_sd_emmc_demux_address(); + switch(option) + { + case SD_MSSIO_CONFIGURATION: + *reg_pt = CMD_SD_EMMC_DEMUX_SD_ON; + break; + + case EMMC_MSSIO_CONFIGURATION: + *reg_pt = CMD_SD_EMMC_DEMUX_EMMC_ON; + break; + + case NO_SUPPORT_MSSIO_CONFIGURATION: + break; + + case NOT_SETUP_MSSIO_CONFIGURATION: + break; + } + result = true; + } + else + { + result = false; + } + return result; +} + + +/***************************************************************************//** + * See mss_io_config.h for details of how to use this function. + */ +__attribute__((weak)) void mss_set_gpio_interrupt_fab_cr(uint32_t reg_value) +{ + SYSREG->GPIO_INTERRUPT_FAB_CR = reg_value; +} + +/***************************************************************************//** + * See mss_peripherals.h for details of how to use this function. + */ +__attribute__((weak)) uint32_t mss_get_gpio_interrupt_fab_cr(void) +{ + return (SYSREG->GPIO_INTERRUPT_FAB_CR); +} + + #ifdef EXAMPLE_MSSIO_APP_CODE #include "drivers/mss_gpio/mss_gpio.h" /** diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_io_config.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_io_config.h index 0feebdfc..79a60e05 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_io_config.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_io_config.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -22,6 +22,88 @@ extern "C" { #endif +#define CMD_SD_EMMC_DEMUX_EMMC_ON 0U +#define CMD_SD_EMMC_DEMUX_SD_ON 1U + +/* + * fields of LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS + * */ +#define EMMC_CONFIGURED_MASK (0x01U<<0U) /*!< set => eMMC is configured */ +#define SD_CONFIGURED_MASK (0x01U<<1U) /*!< set => SD is configured */ +#define DEFAULT_ON_START_MASK (0x01U<<2U) /*!< set => default is SD config, + not set default is eMMC config */ +/* + * Please note in Icicle kit reference design pre 2022.09, the address below + * was 0x4F000000UL + */ +#ifndef FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS +#define FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS 0x4FFFFF00UL /*!< This is design + dependent */ +#endif +#ifndef FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT +#define FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT true /*!< true/false This is design + dependent */ +#endif + +#if !defined (LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR) +/*To limit the number of interrupts fed to the PLINT, the seventy GPIO +interrupts (GPIO0=14, GPIO1=24, GPIO2=32) are reduced down to 41 +interrupts by OR'ing some together. There is some flexibility regarding which +interrupts are OR'd or are direct. This selection is controlled by a 32-bit +system register(GPIO_INTERRUPT_FAB_CR). For example, if bit 0 of the register is +set to 1, gpio2_0 is chosen as a direct interrupt on the PLIC and gpio0_0 will +be OR'd with any other non-direct gpio0 interrupts. Please see the GPIO driver +for more details on using GPIO interrupts. */ +#define LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR 0x00000000UL + /* GPIO0_0_OR_GPIO2_0 [0:1] RW value= 0x0 */ + /* GPIO0_1_OR_GPIO2_1 [1:1] RW value= 0x0 */ + /* GPIO0_2_OR_GPIO2_2 [2:1] RW value= 0x0 */ + /* GPIO0_3_OR_GPIO2_3 [3:1] RW value= 0x0 */ + /* GPIO0_4_OR_GPIO2_4 [4:1] RW value= 0x0 */ + /* GPIO0_5_OR_GPIO2_5 [5:1] RW value= 0x0 */ + /* GPIO0_6_OR_GPIO2_6 [6:1] RW value= 0x0 */ + /* GPIO0_7_OR_GPIO2_7 [7:1] RW value= 0x0 */ + /* GPIO0_8_OR_GPIO2_8 [8:1] RW value= 0x0 */ + /* GPIO0_9_OR_GPIO2_9 [9:1] RW value= 0x0 */ + /* GPIO0_10_OR_GPIO2_10 [10:1] RW value= 0x0 */ + /* GPIO0_11_OR_GPIO2_11 [11:1] RW value= 0x0 */ + /* GPIO0_12_OR_GPIO2_12 [12:1] RW value= 0x0 */ + /* GPIO0_13_OR_GPIO2_13 [13:1] RW value= 0x0 */ + /* GPIO1_0_OR_GPIO2_14 [14:1] RW value= 0x0 */ + /* GPIO1_1_OR_GPIO2_15 [15:1] RW value= 0x0 */ + /* GPIO1_2_OR_GPIO2_16 [16:1] RW value= 0x0 */ + /* GPIO1_3_OR_GPIO2_17 [17:1] RW value= 0x0 */ + /* GPIO1_4_OR_GPIO2_18 [18:1] RW value= 0x0 */ + /* GPIO1_5_OR_GPIO2_19 [19:1] RW value= 0x0 */ + /* GPIO1_6_OR_GPIO2_20 [20:1] RW value= 0x0 */ + /* GPIO1_7_OR_GPIO2_21 [21:1] RW value= 0x0 */ + /* GPIO1_8_OR_GPIO2_22 [22:1] RW value= 0x0 */ + /* GPIO1_9_OR_GPIO2_23 [23:1] RW value= 0x0 */ + /* GPIO1_10_OR_GPIO2_24 [24:1] RW value= 0x0 */ + /* GPIO1_11_OR_GPIO2_25 [25:1] RW value= 0x0 */ + /* GPIO1_12_OR_GPIO2_26 [26:1] RW value= 0x0 */ + /* GPIO1_13_OR_GPIO2_27 [27:1] RW value= 0x0 */ + /* GPIO1_14_OR_GPIO2_28 [28:1] RW value= 0x0 */ + /* GPIO1_15_OR_GPIO2_29 [29:1] RW value= 0x0 */ + /* GPIO1_16_OR_GPIO2_30 [30:1] RW value= 0x0 */ + /* GPIO1_17_OR_GPIO2_31 [31:1] RW value= 0x0 */ +#endif + + +typedef enum MSSIO_CONFIG_OPTION_ +{ + DEFAULT_MSSIO_CONFIGURATION = 0x00, /*!< 0 default behavior */ + ALT_MSSIO_CONFIGURATION = 0x01, /*!< 1 alternate config */ +} MSSIO_CONFIG_OPTION; + +typedef enum MSS_IO_OPTIONS_ +{ + NO_SUPPORT_MSSIO_CONFIGURATION = 0x00, /*!< 0 MSS Configurator version too early */ + NOT_SETUP_MSSIO_CONFIGURATION = 0x01, /*!< 0 none configured */ + SD_MSSIO_CONFIGURATION = 0x02, /*!< 0 SD config */ + EMMC_MSSIO_CONFIGURATION = 0x03, /*!< 1 eMMC config */ +} MSS_IO_OPTIONS; + /* * There are 38 general purpose IO pads, referred to as MSSIO, to support * peripheral devices. System registers will select which signals are connected @@ -231,10 +313,261 @@ gpio_toggle_test void set_bank2_and_bank4_volts ( - void + MSSIO_CONFIG_OPTION config ); +/***************************************************************************//** + switch_mssio_config() + switches as instructed SD/eMMC + + Example: + + @code + + ASSERT(mss_does_xml_ver_support_switch() == true) + + if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) + { + // print warning message + return; + } + g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; + g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; + g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; + g_mmc.data_bus_width = MSS_MMC_DATA_WIDTH_4BIT; + g_mmc.bus_voltage = MSS_MMC_1_8V_BUS_VOLTAGE; + + @endcode + + * + */ +uint8_t +switch_mssio_config +( + MSS_IO_OPTIONS option +) +; + +/***************************************************************************//** + mss_does_xml_ver_support_switch() + Sets bank 2 and 4 voltages, with Values coming from Libero + + Example: + + @code + + ASSERT(mss_does_xml_ver_support_switch() == true); + + @endcode + + * + */ +uint8_t mss_does_xml_ver_support_switch(void); + +/***************************************************************************//** + mss_is_alternate_io_configured() + + Example: + + @code + + // e.g. first try SD, and fail, then try alt config + + if ( mss_is_alternate_io_configured() == true ) + { + if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) + { + // print warning message + return + } + g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; + g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; + g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; + g_mmc.data_bus_width = MSS_MMC_DATA_WIDTH_4BIT; + g_mmc.bus_voltage = MSS_MMC_1_8V_BUS_VOLTAGE; + + // ... + } + + @endcode + + * + */ +uint8_t mss_is_alternate_io_configured(void); + +/***************************************************************************//** + mss_is_alternate_io_setting_emmc() + + + Example: + + @code + + if ( mss_is_alternate_io_setting_emmc() == true ) + { + ... + } + + @endcode + + * + */ +uint8_t mss_is_alternate_io_setting_emmc(void); + +/***************************************************************************//** + mss_is_alternate_io_setting_sd() + + Example: + + @code + + if ( mss_is_alternate_io_setting_sd() == true ) + { + ... + } + + @endcode + + * + */ +uint8_t mss_is_alternate_io_setting_sd(void); + +/***************************************************************************//** + switch_demux_using_fabric_ip() + This is a function used to switch external mux. + It requires fpga switch IP in the fabric. This comes with reference icicle + kit design. + You will need to create your own or copy when creating your own fpga design + along with an external mux in your board design if you wish to use SD/eMMC + muxing in your hardware design. + + Example: + + @code + + case SD_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_sd() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(SD_MSSIO_CONFIGURATION); + break; + + case EMMC_MSSIO_CONFIGURATION: + if (mss_is_alternate_io_setting_emmc() == true) + { + io_mux_and_bank_config_alt(); + } + else + { + io_mux_and_bank_config(); + } + switch_demux_using_fabric_ip(EMMC_MSSIO_CONFIGURATION); + break; + + + @endcode + + */ +uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option); + +/***************************************************************************//** + mss_io_default_setting() + This helper function may be useful, e.g. print a message on start-up + explaining configuration. + + Example: + + @code + + if ( mss_io_default_setting() == SD_MSSIO_CONFIGURATION ) + { + // ... + } + + @endcode + + */ +uint8_t mss_io_default_setting(void); + +/***************************************************************************//** + fabric_sd_emmc_demux_present() + + Is there sd_emmc_demux IP present in the fabric. + + @return true/false + + Example: + + @code + + if ( fabric_sd_emmc_demux_present() == true ) + { + // ... + } + + @endcode + + */ +uint8_t fabric_sd_emmc_demux_present(void); + +/***************************************************************************//** + fabric_sd_emmc_demux_address() + + This function is used by the routine switch_demux_using_fabric_ip() + The address returned is a default address, used by the Icicle kit design + post v2022.09. + If another address is used in your Libero design, instantiate this function + in your application, and return the address that matches your Libero design. + + @return returns the address of the sd_emmc_demux in fabric + + Example: + + @code + + volatile uint32_t *reg_pt = fabric_sd_emmc_demux_address(); + + *reg_pt = CMD_SD_EMMC_DEMUX_SD_ON; + + @endcode + + */ +uint32_t * fabric_sd_emmc_demux_address(void); + +/***************************************************************************//** + This function is used to set the apb_bus_cr register value + + @param reg_value value of the register you want to set. + This value is available from the MSS configurator + LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR + + Example: + @code + (void)mss_set_gpio_interrupt_fab_cr((uint32_t)LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR); + @endcode + */ +void mss_set_gpio_interrupt_fab_cr(uint32_t reg_value); + +/***************************************************************************//** + This function is used to get the gpio_interrupt_fab_cr register value + + @return Return the gpio_interrupt_fab_cr reg value + + Example: + @code + uint32_t cr_reg; + cr_reg = mss_get_gpio_interrupt_fab_cr(); + @endcode + */ +uint32_t mss_get_gpio_interrupt_fab_cr(void); + + #ifdef __cplusplus } #endif diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c index 698cceff..27bde361 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -23,7 +23,6 @@ #ifdef DEBUG_DDR_INIT #include "drivers/mss/mss_mmuart/mss_uart.h" extern mss_uart_instance_t *g_debug_uart ; -uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); #endif /******************************************************************************* @@ -37,46 +36,30 @@ g5_mss_top_scb_regs_TypeDef * const SCB_REGS = (g5_mss_top_scb_re /******************************************************************************* * Local functions */ -void delay(uint32_t n); +static uint64_t report_status_functions(MSS_REPORT_STATUS report_status, uint64_t next_time); /******************************************************************************* * extern defined functions */ -#ifdef DEBUG_DDR_INIT -uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); -#endif /****************************************************************************** * Public Functions - API ******************************************************************************/ /** - * MSS_DDR_init_simulation(void) - * Flow when running through full chip simulation - * + * mss_nwc_init(void) + * Init of MSS called after hard and soft boot + * Settings informed by MSS Configurator config. + * - some registers set to required values + * - PLL + * - SGMII + * - MSS IO * @return */ uint8_t mss_nwc_init(void) { uint8_t error = 0U; -#ifndef SIFIVE_HIFIVE_UNLEASHED - -#ifdef SIMULATION_TEST_FEEDBACK - /* - * set the test version- this is read in Simulation environment - * x.y.z - * byte[0] = z - * byte[1] = y - * byte[2] = x - */ - SIM_FEEDBACK0(0x33333333); - SYSREG->TEMP0 = (0U << 16U) | (3U << 8U) | 3U; - SYSREG->TEMP0 = 0x44444444U; - SIM_FEEDBACK0(1); - SIM_FEEDBACK0(0x55555555); - SIM_FEEDBACK0(1); -#endif /* * Assumptions: * 1. We enter here shortly after start-up of E51 code by the system @@ -107,10 +90,6 @@ uint8_t mss_nwc_init(void) /* * SCB access settings - * Bits 15:8 Sets how long SCB request is held active after SCB bus granted. - * Allows SCB bus master-ship to maintained across multiple SCB access - * cycles - * Bits 7:0 Set the timeout for an SCB access in CPU cycles. */ SCBCFG_REGS->TIMER.TIMER = MSS_SCB_ACCESS_CONFIG; @@ -303,15 +282,15 @@ uint8_t mss_nwc_init(void) /* DCE:111, CORE_UP:1, FLASH_VALID:0, mss_io_en:0 */ SCB_REGS->MSSIO_CONTROL_CR.MSSIO_CONTROL_CR =\ (0x07U<<8U)|(0x01U<<11U)|(0x00U<<12U)|(0x00U<<13U); - delay((uint32_t) 10U); + delay(DELAY_CYCLES_500_NS); /* DCE:000, CORE_UP:1, FLASH_VALID:0, mss_io_en:0 */ SCB_REGS->MSSIO_CONTROL_CR.MSSIO_CONTROL_CR =\ (0x00U<<8U)|(0x01U<<11U)|(0x00U<<12U)|(0x00U<<13U); - delay((uint32_t) 10U); + delay(DELAY_CYCLES_500_NS); /* DCE:000, CORE_UP:1, FLASH_VALID:1, mss_io_en:0 */ SCB_REGS->MSSIO_CONTROL_CR.MSSIO_CONTROL_CR =\ (0x00U<<8U)|(0x01U<<11U)|(0x01U<<12U)|(0x00U<<13U); - delay((uint32_t) 10U); + delay(DELAY_CYCLES_500_NS); /* DCE:000, CORE_UP:1, FLASH_VALID:1, mss_io_en:1 */ SCB_REGS->MSSIO_CONTROL_CR.MSSIO_CONTROL_CR =\ (0x00U<<8U)|(0x01U<<11U)|(0x01U<<12U)|(0x01U<<13U); @@ -330,49 +309,76 @@ uint8_t mss_nwc_init(void) SIM_FEEDBACK0(3); mss_pll_config(); - { + return error; +} + +/** + * mss_nwc_init_ddr(void) + * Init the DDR + * + * @return error status, 0U => OK + */ +uint8_t mss_nwc_init_ddr(void) +{ + uint8_t error = 0U; #ifdef DDR_SUPPORT + uint64_t next_time; #ifdef DEBUG_DDR_INIT - { - (void)setup_ddr_debug_port(g_debug_uart); - } + if (g_debug_uart == NULL) + { + /* + * Defaults to UART0 if none selected by user boot code + */ + g_debug_uart = &g_mss_uart0_lo; + } + (void)setup_ddr_debug_port(g_debug_uart); #endif - uint32_t ddr_status; - ddr_status = ddr_state_machine(DDR_SS__INIT); - - while((ddr_status & DDR_SETUP_DONE) != DDR_SETUP_DONE) - { - ddr_status = ddr_state_machine(DDR_SS_MONITOR); - } - if ((ddr_status & DDR_SETUP_FAIL) == DDR_SETUP_FAIL) - { - error |= (0x1U << 2U); - } - //todo: remove, just for sim test ddr_recalib_io_test(); -#endif + uint32_t ddr_status; + ddr_status = ddr_state_machine(DDR_SS__INIT); + next_time = rdcycle() + DELAY_CYCLES_100MS; + while((ddr_status & DDR_SETUP_DONE) != DDR_SETUP_DONE) + { + ddr_status = ddr_state_machine(DDR_SS_MONITOR); + next_time = report_status_functions(DDR_BOOT_PROGRESS, next_time); + } + if ((ddr_status & DDR_SETUP_FAIL) == DDR_SETUP_FAIL) + { + error |= (0x1U << 2U); } +#endif -#endif /* end of !define SIFIVE_HIFIVE_UNLEASHED */ - SIM_FEEDBACK0(0x12345678U); - SIM_FEEDBACK0(error); - SIM_FEEDBACK0(0x87654321U); return error; } - -/*-------------------------------------------------------------------------*//** - * delay() - * Not absolute. Dependency on current clk rate - * @param n Number of iterations to wait. +/** + * report_status_functions() + * Used to call user boot functions for feedback during boot + * @param report_status */ -void delay(uint32_t n) +static uint64_t report_status_functions(MSS_REPORT_STATUS report_status, uint64_t next_time) { - volatile uint32_t count = n; - while(count!=0U) + if (next_time <= rdcycle()) { - count--; + switch(report_status) + { + case DDR_BOOT_PROGRESS: + ddr_report_progress(); + break; + default: + break; + } + next_time = rdcycle() + DELAY_CYCLES_100MS; } + return next_time; +} + +/** + * Application can create own function to show progress + */ +__attribute__((weak)) void ddr_report_progress(void) +{ + return; } /*-------------------------------------------------------------------------*//** diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h index b759b82c..59b0445c 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -88,31 +88,76 @@ #include #include - +#include "../encoding.h" #ifdef __cplusplus extern "C" { #endif +#define DELAY_CYCLES_500_NS ((uint32_t)(0.0000005 * LIBERO_SETTING_MSS_COREPLEX_CPU_CLK)) +#define DELAY_CYCLES_1_MICRO ((uint32_t)(DELAY_CYCLES_500_NS * 2U)) +#define DELAY_CYCLES_5_MICRO ((uint32_t)(DELAY_CYCLES_500_NS * 10U)) +#define DELAY_CYCLES_50_MICRO ((uint32_t)(DELAY_CYCLES_500_NS * 100U)) +#define DELAY_CYCLES_150_MICRO ((uint32_t)(DELAY_CYCLES_500_NS * 300U)) +#define DELAY_CYCLES_250_MICRO ((uint32_t)(DELAY_CYCLES_500_NS * 500U)) +#define DELAY_CYCLES_500_MICRO ((uint32_t)(DELAY_CYCLES_500_NS * 1000U)) +#define DELAY_CYCLES_2MS ((uint32_t)(DELAY_CYCLES_500_NS * 4000U)) +#define DELAY_CYCLES_100MS ((uint32_t)(DELAY_CYCLES_2MS * 50U)) + +/***************************************************************************//** + + */ +typedef enum { + DDR_BOOT_PROGRESS = 0x00 //!< DDR_BOOT_PROGRESS +} MSS_REPORT_STATUS; + +/*-------------------------------------------------------------------------*//** + * delay() + * Simple wait delay based on mcycles count + * @param n Number of mcycles to wait. + */ +static inline void delay(uint32_t n) +{ + volatile uint64_t cycles_end = rdcycle() + n ; + while (rdcycle() < cycles_end) + { + + } +} /***************************************************************************//** MSS_SCB_ACCESS_CONFIG_ON_RESET SCB access settings on reset. + + Bits 23:16 Sets the number of cycles that the bus is held mastered by the MSS + after grant removal. During this period the MSS must not start any new SCB + cycles. This allows for any active SCB cycles to complete. + This must be four greater than the number of pipelines (4) in the SCB ring from + the MSS to G5C + Bits 15:8 Sets how long SCB request is held active after SCB bus granted. Allows SCB bus master-ship to maintained across multiple SCB access cycles Bits 7:0 Set the timeout for an SCB access in CPU cycles. Note: These settings are used even after we change the MSS clock from SCB - 80MHz default setting. todo: This needs to be confirmed as OK, there will be - no potential timing issues: + 80MHz default setting. Min 143 Hclk cycles for simulation set-up, making 160 - todo: review setting */ +#ifndef MSS_SCB_ACCESS_CONFIG_TIMEOUT +#define MSS_SCB_ACCESS_CONFIG_TIMEOUT ((0x80U)&(0xFFU)) +#endif +#ifndef MSS_SCB_ACCESS_CONFIG_REQUST_TIME +#define MSS_SCB_ACCESS_CONFIG_REQUST_TIME ((160UL<<8U)&(0xFFU<<8U)) +#endif +#ifndef MSS_SCB_ACCESS_CONFIG_BUSHOLD +#define MSS_SCB_ACCESS_CONFIG_BUSHOLD ((8UL<<16U)&(0xFFU<<16U)) +#endif -#define MSS_SCB_ACCESS_CONFIG ((160UL<<8U)|(0x80U)) - +#ifndef MSS_SCB_ACCESS_CONFIG +#define MSS_SCB_ACCESS_CONFIG (MSS_SCB_ACCESS_CONFIG_BUSHOLD|MSS_SCB_ACCESS_CONFIG_REQUST_TIME|MSS_SCB_ACCESS_CONFIG_TIMEOUT) +#endif /***************************************************************************//** mss_nwc_init() @@ -124,6 +169,16 @@ mss_nwc_init void ); +/***************************************************************************//** + mss_nwc_init_ddr() + Called on start-up, initializes ddr + */ +uint8_t +mss_nwc_init_ddr +( + void +); + /***************************************************************************//** mtime_delay(x) delay function, passes microseconds @@ -146,6 +201,29 @@ mtime_delay uint32_t microseconds ); +/***************************************************************************//** + ddr_status() + + Application can create own function to show progress + + Example: + @code + + ddr_status(void){ + static uint32_ count = 0U; + count++; + display_progress_banner(count); + } + + @endcode + + */ +void +ddr_report_progress +( + void +); + #ifdef __cplusplus } diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c index df1ecc6f..761ef34c 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -16,7 +16,6 @@ #include "mpfs_hal/mss_hal.h" #include "mss_pll.h" -#ifndef SIFIVE_HIFIVE_UNLEASHED /** * We do it this way to avoid multiple LDRA warnings @@ -196,9 +195,9 @@ static void mss_mux_pre_mss_pll_config(void) * */ volatile uint32_t i; - for(i = 0U; i < 400U; i++) + for(i = 0U; i < 200U; i++) { - i++; + ; //i++; } } @@ -468,7 +467,7 @@ void mss_pll_config(void) * Wait for LOCK * todo: make wait clock based */ - volatile uint32_t timer_out=0x000000FFU; + volatile uint32_t timer_out=0x00FFFFFFU; while((MSS_SCB_MSS_PLL->PLL_CTRL & PLL_CTRL_LOCK_BIT) == 0U) { #ifdef RENODE_DEBUG @@ -480,7 +479,8 @@ void mss_pll_config(void) } else { - //todo: add failure mode + timer_out=0x00FFFFFFU; + flag_mss_pll_lock_error(); } } @@ -492,6 +492,17 @@ void mss_pll_config(void) mss_mux_post_mss_pll_config(); } +/** + * flag_mss_pll_lock_error(void) + * + * Implement platform specific function for lock failure feedback + * + */ +__attribute__((weak)) void flag_mss_pll_lock_error(void) +{ + ASSERT(0U); +} + /** * * @param option choose between SCB or RPC and soft reset update method. @@ -719,6 +730,3 @@ __attribute__((weak)) void copy_switch_code(void) } #endif /* MPFS_HAL_HW_CONFIG */ -#endif - - diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.h index 3581e6a8..a18e3b5a 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -339,11 +339,31 @@ void sgmii_mux_config_via_scb(uint8_t option); */ void pre_configure_sgmii_and_ddr_pll_via_scb(uint8_t option); -/****************************************************************************** - * Public Functions - API * - ******************************************************************************/ +/***************************************************************************//** + mss_pll_config() + + Setup the MSS PLL + feeds in ref clock, set freq based on MSS Configurator settings and once + lock achieved, feeds out to the MSS. + + Example: + @code + + mss_pll_config(); + + @endcode + + */ void mss_pll_config(void); +/***************************************************************************//** + flag_mss_pll_lock_error() + + Instantiate platform specific function to give error feedback on your platform + + */ +void flag_mss_pll_lock_error(void); + #ifdef __cplusplus } #endif diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h index 8b908397..15f50f2c 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c index a84396be..fb3f7b7d 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -640,15 +640,15 @@ static void set_early_late_thresholds(uint8_t n_late_threshold, uint8_t p_early_ * Set the N eye width value * bits 31:29 for CH1, bits 28:26 for CH0 in spare control (N eye width value) */ - n_eye_values = (n_late_threshold << SHIFT_TO_CH0_N_EYE_VALUE); - n_eye_values |= (n_late_threshold << SHIFT_TO_CH1_N_EYE_VALUE); + n_eye_values = (uint32_t)(n_late_threshold << SHIFT_TO_CH0_N_EYE_VALUE); + n_eye_values |= (uint32_t)(n_late_threshold << SHIFT_TO_CH1_N_EYE_VALUE); CFG_DDR_SGMII_PHY->SPARE_CNTL.SPARE_CNTL = (LIBERO_SETTING_SPARE_CNTL & N_EYE_MASK) | n_eye_values; /* * Set P values */ - p_eye_value = (p_early_threshold << SHIFT_TO_REG_RX0_EYEWIDTH); + p_eye_value = (uint32_t)(p_early_threshold << SHIFT_TO_REG_RX0_EYEWIDTH); CFG_DDR_SGMII_PHY->CH0_CNTL.CH0_CNTL = ((LIBERO_SETTING_CH0_CNTL & REG_RX0_EYEWIDTH_P_MASK) | p_eye_value) | REG_RX0_EN_FLAG_N; CFG_DDR_SGMII_PHY->CH1_CNTL.CH1_CNTL = ((LIBERO_SETTING_CH1_CNTL & REG_RX0_EYEWIDTH_P_MASK) | p_eye_value) | REG_RX1_EN_FLAG_N; diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.h index 75b3f80f..522c8a49 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/simulation.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/simulation.h index 2dcb3141..a6bdf766 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/simulation.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/common/nwc/simulation.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h index 81ab4259..72208576 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h @@ -2,7 +2,7 @@ #define MPFS_HAL_VERSION_H /******************************************************************************* - * Copyright 2019-2021 Microchip Corporation. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -39,9 +39,9 @@ extern "C" { #endif -#define MPFS_HAL_VERSION_MAJOR 1 -#define MPFS_HAL_VERSION_MINOR 8 -#define MPFS_HAL_VERSION_PATCH 125 +#define MPFS_HAL_VERSION_MAJOR 2 +#define MPFS_HAL_VERSION_MINOR 1 +#define MPFS_HAL_VERSION_PATCH 103 #ifdef __cplusplus } diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mss_hal.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mss_hal.h index 86a3f9c5..3261f105 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mss_hal.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/mss_hal.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -28,6 +28,8 @@ typedef long ssize_t; #endif #include "common/mss_assert.h" +#include "common/mss_legacy_defines.h" +#include "common/mss_beu_def.h" #include "common/nwc/mss_ddr_defs.h" #include "common/nwc/mss_ddr_sgmii_regs.h" #include "common/nwc/mss_io_config.h" @@ -39,19 +41,20 @@ typedef long ssize_t; * mpfs_hal folder */ #include "mpfs_hal_config/mss_sw_config.h" +#include "common/atomic.h" +#include "common/bits.h" +#include "common/encoding.h" /* - * The hw_platform.h is included here only. It must be included after + * The fpga_design_config.h is included here only. It must be included after * mss_sw_config.h. This allows defines in hw_platform.h be overload from * mss_sw_config.h if necessary. * */ -#include "common/atomic.h" -#include "common/bits.h" -#include "common/encoding.h" #include "fpga_design_config/fpga_design_config.h" #include "common/nwc/mss_ddr.h" #include "common/mss_clint.h" #include "common/mss_h2f.h" #include "common/mss_hart_ints.h" +#include "common/mss_beu.h" #include "common/mss_mpu.h" #include "common/mss_pmp.h" #include "common/mss_plic.h" diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S index 62caf72a..b1c94aba 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip Corporation. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -273,67 +273,46 @@ _start: nop j .LoopForeverOther -#else /* IMAGE_LOADED_BY_BOOTLOADER == 1 */ - -/*********************************************************************************** +#else /* IMAGE_LOADED_BY_BOOTLOADER == 1 */ +/******************************************************************************* *The program has been loaded by a bootloader * a0 - contains the hart ID * a1 - contains pointer to bootloader -Hart Local Storage, for this hart. */ -_start_non_bootloader_image: - /* ebreak called at the start of the program if required when debuging. */ - /* DEBUG_EBREAK_AT_START is set to one in the debug build, 0 in the */ - /* release build */ - /* uncomment the 3 lines below if you want to use this method to for */ - /* debugging */ - /* li a2, DEBUG_EBREAK_AT_START - beq x0, a2, 1f - ebreak */ -1: - /* store the value here received from boot-loader */ - /* a0 will always contain the hart ID */ - /* If a1 is null, boot-loader is not passing pointer to the HLS */ - /* If this is the case, point HLS to out own and fill with hart ID */ +_start_non_bootloader_amp_image: /* Setup trap handler */ - /* we are currently only supporting mmode */ - /* m-mode/s-mode set-up option will be added here */ la a4, trap_vector csrw mtvec, a4 # initalise machine trap vector address /* Make sure that mtvec is updated before continuing */ -2: + 1: csrr a5, mtvec - bne a4, a5, 2b - /* Disable and clear all interrupts */ - /* assumption is this has been done by the Boot-loader */ - # Init delegation registers, mideleg, medeleg, if a U54 - # These are not initialised by the hardware and come up in a random state - # mhartid is in a0 - beqz a0, 3f - csrw mideleg, 0 - csrw medeleg, 0 -3: - # mscratch must be init to zero- we are not using scratch memory - csrw mscratch, zero - csrw mcause, zero - csrw mepc, zero + bne a4, a5, 1b + /* assume ints in init state */ + /* assume PMP's set as required */ + # enable FPU and accelerator if present, setting ignored on E51 + li t0, MSTATUS_FS | MSTATUS_XS + csrs mstatus, t0 # Init floating point control register to zero # skip if e51 - # mhartid is in a0 - beqz a0, 1f + csrr a0, mhartid + beqz a0, .no_float #ifdef __riscv_flen fscsr x0 #endif -1: # no float - # make sure XLEN agrees with compilation choice, if not will loop here +.no_float: + + # make sure XLEN agrees with compilation choice, if not will loop here +.LxlenCheck: csrr t0, misa #if __riscv_xlen == 64 - bltz t0, 2f + bltz t0, .LxlenPass #else - bgez t0, 2f + bgez t0, .LxlenPass #endif - j 1b -2: + j .LxlenCheck +.LxlenPass: + # initialize global pointer, global data # The __global_pointer is allocated in the linker script. It points to a # location 2k after sdata start as the offsets used in the gp are +/- 2k @@ -344,44 +323,178 @@ _start_non_bootloader_image: la gp, __global_pointer$ .option pop - la a4, __app_stack_bottom # keep bottom of stack in a5 so we can init later - la a5, __app_stack_top - la sp, __app_stack_top -1: + # get core id + csrr a0, mhartid + li a1, 0 + beq a0, a1, .hart0 + li a1, 1 + beq a0, a1, .hart1 + li a1, 2 + beq a0, a1, .hart2 + li a1, 3 + beq a0, a1, .hart3 + li a1, 4 + beq a0, a1, .hart4 + +.hart0: + la a4, __stack_bottom_h0$ # keep bottom of stack in a5 so we can init later + la sp, __stack_top_h0$ + j .continue +.hart1: + la a4, __stack_bottom_h1$ # keep bottom of stack in a5 so we can init later + la sp, __stack_top_h1$ + j .continue +.hart2: + la a4, __stack_bottom_h2$ # keep bottom of stack in a5 so we can init later + la sp, __stack_top_h2$ + j .continue +.hart3: + la a4, __stack_bottom_h3$ # keep bottom of stack in a5 so we can init later + la sp, __stack_top_h3$ + j .continue +.hart4: + la a4, __stack_bottom_h4$ # keep bottom of stack in a5 so we can init later + la sp, __stack_top_h4$ + +.continue: + # clear HLS and stack + mv a5, sp +.init_stack: + #csrw mepc, zero STORE x0, 0(a4) add a4, a4, __SIZEOF_POINTER__ - blt a4, a5, 1b + blt a4, a5, .init_stack + # Allocate some space at top of stack for the HLS + addi sp, sp, -HLS_DEBUG_AREA_SIZE + # HLS grows up from new top of stack + mv tp, sp + # get core id + csrr a0, mhartid + li a1, MPFS_HAL_FIRST_HART + bne a0, a1, .LOtherHartstoWFI # clear the common heap la a4, __heap_start la a5, __heap_end -2: +.init_heap: + #csrw mepc, zero STORE x0, 0(a4) add a4, a4, __SIZEOF_POINTER__ - blt a4, a5, 2b - # check if HLS passed by BL, if not allocate one here - bnez a1, 1f - # Allocate some space at top of stack for the HLS, as HLS mem not passed - addi sp, sp, -HLS_DEBUG_AREA_SIZE - # HLS grows up from new top of stack - mv tp, sp - mv a0, tp - j u54_single_hart + blt a4, a5, .init_heap + # now core MPFS_HAL_FIRST_HART jumps to main_first_hart +.main_hart: + # pass HLS address + mv a0, tp + j main_first_hart_app +.LoopForeverMain: + #in case of return, loop forever. nop's added so can be seen in debugger + nop + nop + j .LoopForeverMain + +.LOtherHartstoWFI: + li a2, MSTATUS_MIE + csrc mstatus, a2 # clear interrupt enable bit + csrw mie, zero + csrw mip, zero + li a2, MIP_MSIP + csrw mie, a2 # Set MSIE bit to receive IPI. This needs to be + # enabled- otherwise stays in wfi. + # Other interrupts appera to bring out of wfi,even if + # not enabled. + # + # Wait here until main hart is up and running + # + # get core id + la a2, MPFS_HAL_FIRST_HART + li a3, 0 + beq a3, a2, .main_hart0 + li a3, 1 + beq a3, a2, .main_hart1 + li a3, 2 + beq a3, a2, .main_hart2 + li a3, 3 + beq a3, a2, .main_hart3 + li a3, 4 + beq a3, a2, .main_hart4 + +.main_hart0: + la a4, (__stack_top_h0$ - HLS_DEBUG_AREA_SIZE) + j 1f +.main_hart1: + la a4, (__stack_top_h1$ - HLS_DEBUG_AREA_SIZE) + j 1f +.main_hart2: + la a4, (__stack_top_h2$ - HLS_DEBUG_AREA_SIZE) + j 1f +.main_hart3: + la a4, (__stack_top_h3$ - HLS_DEBUG_AREA_SIZE) + j 1f +.main_hart4: + la a4, (__stack_top_h4$ - HLS_DEBUG_AREA_SIZE) 1: - # pass HLS address from the boot-loader - mv a0, a1 - j u54_single_hart -2: - # in case of return, loop forever. nop's added so can be seen in debugger + li a3, HLS_MAIN_HART_STARTED +.wait_main_hart: + LWU a2, 0(a4) + bne a3, a2, .wait_main_hart + # Flag we are here to the main hart + li a1, HLS_OTHER_HART_IN_WFI + sw a1, 0(tp) + /* flush the instruction cache */ + fence.i +.LwaitOtherHart: + # We assume wfi instruction will be run before main hart attampts to take + # out of wfi + wfi + # Only start if MIP_MSIP is set - the wfi will ensure this, but adding + # breakpoints in the debugger (halt) + # will wakeup wfi, so the following code will make sure we remain here until + # we get a software interrupt + csrr a2, mip + andi a2, a2, MIP_MSIP + beqz a2, .LwaitOtherHart + /* Disable and clear all interrupts- should be only a sw interrupt */ + li a2, MSTATUS_MIE + csrc mstatus, a2 # clear interrupt enable bit + csrw mie, zero + csrw mip, zero + # set marker as to where we are + li a1, HLS_OTHER_HART_PASSED_WFI + sw a1, 0(tp) + # pass HLS address + mv a0, tp + j main_other_hart +.LoopForeverOther: + #in case of return, loop forever. nop's added so can be seen in debugger nop nop - j 2b -#endif /* IMAGE_LOADED_BY_BOOTLOADER */ + j .LoopForeverOther + +#endif /* IMAGE_LOADED_BY_BOOTLOADER == 0 */ /******************************************************************************/ /******************************interrupt handeling below here******************/ /******************************************************************************/ trap_vector: +#if defined USING_FREERTOS + addi sp, sp, -REGBYTES /* Save t0 for now */ + STORE t0, 0x0(sp) + csrr t0, mcause + bge t0,x0,.Le51_other /* Not an interrupt... */ + slli t0,t0,1 + srli t0,t0,1 + addi t0,t0,-7 + bne t0,x0,.Le51_other /* Not Timer interrupt... */ + /* Interrupt is timer interrupt so let FreeRTOS handle it */ + LOAD t0, 0x0(sp) # Restore t0 for proper context save by FreeRTOS + addi sp, sp, REGBYTES + j TIMER_CMP_INT + mret + +.Le51_other: # Re-enter mainline here if not timer interrupt + LOAD t0, 0x0(sp) # Restore t0 for proper context save by HAL + addi sp, sp, REGBYTES +#endif # The mscratch register is an XLEN-bit read/write register dedicated for use by machine mode. # Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped # with a user register upon entry to an M-mode trap handler. @@ -539,7 +652,7 @@ copy_section: ret -/*********************************************************************************** +/******************************************************************************* * * The following copy_switch_code() symbol overrides the weak symbol in the HAL and does * a safe copy of HW config data diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_utils.S b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_utils.S index 482d4b61..846b79f2 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_utils.S +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/mss_utils.S @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2021 Microchip Corporation. + * Copyright 2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c index 0ed8513d..422b201d 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -21,50 +21,45 @@ #include "../mss_hal.h" /*============================================================================== - * Redirection of standard output to a SmartFusion2 MSS UART. + * Redirection of standard output to an MSS UART. *------------------------------------------------------------------------------ * A default implementation for the redirection of the output of printf() to a * UART is provided at the bottom of this file. This redirection is enabled by - * adding the symbol/define MICROCHIP_STDIO_THRU_MMUART0 or - * MICROCHIP_STDIO_THRU_MMUART0 to your project settings and specifying the baud - * rate using the MICROCHIP_STDIO_BAUD_RATE define. - */ -#ifdef MICROCHIP_STDIO_THRU_MMUART0 -#ifndef MICROCHIP_STDIO_THRU_UART -#define MICROCHIP_STDIO_THRU_UART -#endif -#endif /* MICROCHIP_STDIO_THRU_MMUART0 */ - -#ifdef MICROCHIP_STDIO_THRU_MMUART1 -#ifndef MICROCHIP_STDIO_THRU_UART -#define MICROCHIP_STDIO_THRU_UART -#endif -#endif /* MICROCHIP_STDIO_THRU_MMUART1 */ - -/* - * Select which MMUART will be used for stdio and what baud rate will be used. - * Default to 57600 baud if no baud rate is specified using the + * adding one of the following defines to your project in the project file + * boards/your-board/mpfs_hal_config/mss_sw_config.h + * + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart0_lo + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart1_lo + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart2_lo + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart3_lo + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart4_lo + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart0_hi + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart1_hi + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart2_hi + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart3_hi + * #define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart4_hi + * The baud rate using the MICROCHIP_STDIO_BAUD_RATE define. + * + * Note: you must have mss_mmuart driver source code included in the project. + * + * Also note defaults to 115200 baud if no baud rate is specified using the * MICROCHIP_STDIO_BAUD_RATE #define. */ -#ifdef MICROCHIP_STDIO_THRU_UART +#ifdef MICROCHIP_STDIO_THRU_MMUARTX #include "drivers/mss/mss_mmuart/mss_uart.h" #ifndef MICROCHIP_STDIO_BAUD_RATE #define MICROCHIP_STDIO_BAUD_RATE MSS_UART_115200_BAUD #endif -#ifdef MICROCHIP_STDIO_THRU_MMUART0 -static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0; -#else -static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1; -#endif +static mss_uart_instance_t * const gp_my_uart = MICROCHIP_STDIO_THRU_MMUARTX; /*------------------------------------------------------------------------------ * Global flag used to indicate if the UART driver needs to be initialized. */ static int g_stdio_uart_init_done = 0; -#endif /* MICROCHIP_STDIO_THRU_UART */ +#endif /* MICROCHIP_STDIO_THRU_MMUARTX */ /*============================================================================== * Environment variables. @@ -224,7 +219,7 @@ int _write_r( void * reent, int file, char * ptr, int len ) (void)file; (void)ptr; (void)len; -#ifdef MICROCHIP_STDIO_THRU_UART +#ifdef MICROCHIP_STDIO_THRU_MMUARTX /*-------------------------------------------------------------------------- * Initialize the UART driver if it is the first time this function is * called. @@ -244,9 +239,9 @@ int _write_r( void * reent, int file, char * ptr, int len ) MSS_UART_polled_tx(gp_my_uart, (uint8_t *)ptr, len); return len; -#else /* MICROCHIP_STDIO_THRU_UART */ +#else /* MICROCHIP_STDIO_THRU_MMUARTX */ return (0); -#endif /* MICROCHIP_STDIO_THRU_UART */ +#endif /* MICROCHIP_STDIO_THRU_MMUARTX */ } /*============================================================================== diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c index 7656c489..d3839d90 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c @@ -1,5 +1,5 @@ /****************************************************************************************** - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -32,13 +32,14 @@ #include "mpfs_hal/mss_hal.h" #ifdef MPFS_HAL_HW_CONFIG #include "../common/nwc/mss_nwc_init.h" -#include "system_startup_defs.h" #endif +#include "system_startup_defs.h" /*============================================================================== * This function is called by the lowest enabled hart (MPFS_HAL_FIRST_HART) in - * the configuration file (platform/config/software/mpfs_hal/mss_sw_config.h ) + * the configuration file : + * (src/boards/my_hart_id = MPFS_HAL_FIRST_HART; -#ifdef MPFS_HAL_SHARED_MEM_ENABLED - /* if shared memory enabled, pointer from Boot-loader in the HLS should be - * non-zero */ - ASSERT(hls->shared_mem != NULL); -#endif - switch(hls->my_hart_id) + uint64_t hartid = read_csr(mhartid); + + if(hartid == MPFS_HAL_FIRST_HART) { - case 0U: - e51(); - break; + uint8_t hart_id; + ptrdiff_t stack_top; + + init_memory(); + + hls->my_hart_id = MPFS_HAL_FIRST_HART; + hls->in_wfi_indicator = HLS_MAIN_HART_STARTED; + WFI_SM sm_check_thread = INIT_THREAD_PR; + hart_id = MPFS_HAL_FIRST_HART + 1U; + while( hart_id <= MPFS_HAL_LAST_HART) + { + uint32_t wait_count = 0U; - case 1U: - u54_1(); - break; + switch(sm_check_thread) + { + default: + case INIT_THREAD_PR: - case 2U: - u54_2(); - break; + switch (hart_id) + { + case 1: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h1$); + break; + case 2: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h2$); + break; + case 3: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h3$); + break; + case 4: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h4$); + break; + } + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); + sm_check_thread = CHECK_WFI; + wait_count = 0U; + break; - case 3U: - u54_3(); - break; + case CHECK_WFI: + if( hls->in_wfi_indicator == HLS_OTHER_HART_IN_WFI ) + { + /* Separate state- to add a little delay */ + sm_check_thread = SEND_WFI; + } + break; - case 4U: - u54_4(); - break; + case SEND_WFI: + hls->my_hart_id = hart_id; /* record hartid locally */ + raise_soft_interrupt(hart_id); + sm_check_thread = CHECK_WAKE; + wait_count = 0UL; + break; - default: - /* no more harts */ - break; + case CHECK_WAKE: + if( hls->in_wfi_indicator == HLS_OTHER_HART_PASSED_WFI ) + { + sm_check_thread = INIT_THREAD_PR; + hart_id++; + wait_count = 0UL; + } + else + { + wait_count++; + if(wait_count > 0x10U) + { + if( hls->in_wfi_indicator == HLS_OTHER_HART_IN_WFI ) + { + hls->my_hart_id = hart_id; /* record hartid locally */ + raise_soft_interrupt(hart_id); + wait_count = 0UL; + } + } + } + break; + } + } + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h1$); + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); + hls->in_wfi_indicator = HLS_MAIN_HART_FIN_INIT; + (void)main_other_hart(hls); } + __builtin_unreachable(); /* should never get here */ while(true) { @@ -264,6 +316,7 @@ __attribute__((weak)) int u54_single_hart(HLS_DATA* hls) return (0); } +#endif /*============================================================================== * U54s startup. @@ -280,7 +333,7 @@ __attribute__((weak)) int u54_single_hart(HLS_DATA* hls) */ __attribute__((weak)) int main_other_hart(HLS_DATA* hls) { -#ifdef MPFS_HAL_HW_CONFIG +#if (IMAGE_LOADED_BY_BOOTLOADER == 0) // This also means no hardware init is required extern char __app_stack_top_h0; extern char __app_stack_top_h1; extern char __app_stack_top_h2; @@ -365,7 +418,40 @@ __attribute__((weak)) int main_other_hart(HLS_DATA* hls) /* Added some code as debugger hangs if in loop doing nothing */ counter = counter + 1U; } +#else /* (IMAGE_LOADED_BY_BOOTLOADER == 0) */ + + + uint64_t hartid = read_csr(mhartid); + + switch(hartid) + { + + case 0U: + e51(); + break; + + case 1U: + u54_1(); + break; + + case 2U: + u54_2(); + break; + + case 3U: + u54_3(); + break; + + case 4U: + u54_4(); + break; + + default: + /* no more harts */ + break; + } #endif + return (0); } @@ -515,30 +601,6 @@ __attribute__((weak)) void u54_4(void) } } - /** - * This function is configured by editing parameters in - * mss_sw_config.h as required. - * @return - */ - -__attribute__((weak)) uint8_t init_bus_error_unit(void) -{ -#ifndef SIFIVE_HIFIVE_UNLEASHED - uint8_t hart_id; - /* Init BEU in all harts - enable local interrupt */ - for(hart_id = MPFS_HAL_FIRST_HART; hart_id <= MPFS_HAL_LAST_HART; hart_id++) - { - BEU->regs[hart_id].ENABLE = (uint64_t)BEU_ENABLE; - BEU->regs[hart_id].PLIC_INT = (uint64_t)BEU_PLIC_INT; - BEU->regs[hart_id].LOCAL_INT = (uint64_t)BEU_LOCAL_INT; - BEU->regs[hart_id].CAUSE = 0ULL; - BEU->regs[hart_id].ACCRUED = 0ULL; - BEU->regs[hart_id].VALUE = 0ULL; - } -#endif - return (0U); -} - /** * init_mem_protection_unit(void) * add this function to you code and configure as required @@ -546,9 +608,7 @@ __attribute__((weak)) uint8_t init_bus_error_unit(void) */ __attribute__((weak)) uint8_t init_mem_protection_unit(void) { -#ifndef SIFIVE_HIFIVE_UNLEASHED mpu_configure(); -#endif return (0U); } @@ -563,23 +623,4 @@ __attribute__((weak)) uint8_t init_pmp(uint8_t hart_id) return (0U); } -/** - * set_apb_bus_cr(void) - * todo: add check to see if value valid re. mss configurator - * @return - */ -__attribute__((weak)) uint8_t mss_set_apb_bus_cr(uint32_t reg_value) -{ - SYSREG->APBBUS_CR = reg_value; - return (0U); -} - -/** - * get_apb_bus_cr(void) - * @return - */ -__attribute__((weak)) uint8_t mss_get_apb_bus_cr(void) -{ - return (SYSREG->APBBUS_CR); -} diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h index 3c962166..ff2b620c 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -89,6 +89,7 @@ extern unsigned long __text_load; extern unsigned long __text_start; extern unsigned long __text_end; +extern unsigned long __l2lim_start; extern unsigned long __l2lim_end; extern unsigned long __e51itim_start; @@ -115,7 +116,9 @@ extern unsigned long __uninit_top$; * Function Declarations */ int main_first_hart(HLS_DATA* hls); +int main_first_hart_app(HLS_DATA* hls); int main_other_hart(HLS_DATA* hls); +int u54_single_hart(HLS_DATA* hls); void e51(void); void u54_1(void); void u54_2(void); @@ -125,9 +128,6 @@ void init_memory( void); void init_ddr( void); uint8_t init_mem_protection_unit(void); uint8_t init_pmp(uint8_t hart_id); -uint8_t init_bus_error_unit( void); -uint8_t mss_set_apb_bus_cr(uint32_t reg_value); -uint8_t mss_get_apb_bus_cr(void); char * memfill(void *dest, const void * src, size_t len); char * config_copy(void *dest, const void * src, size_t len); char * config_16_copy(void *dest, const void * src, size_t len); diff --git a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h index 586c5b97..6d230661 100644 --- a/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h +++ b/mpfs-watchdog-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -14,7 +14,7 @@ */ #ifndef SYSTEM_STARTUP_DEFS_H -#define SYSTEM_STARTUP_DESF_H +#define SYSTEM_STARTUP_DEFS_H #ifdef __cplusplus extern "C" { @@ -43,4 +43,4 @@ extern "C" { } #endif -#endif /* SYSTEM_STARTUP_DESF_H */ +#endif /* SYSTEM_STARTUP_DEFS_H */ diff --git a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld index 45c143ed..88af43ea 100644 --- a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld +++ b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-loaded-by-boot-loader.ld @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -23,9 +23,9 @@ * allocated by the boot-loader if the MPFS_HAL_SHARED_MEM_ENABLED * is defined in the mss_sw_config.h file project configuration file. * Please see the project mpfs-hal-run-from-ddr-u54-1 located in the Bare Metal - * library under examples/mpfs-hal for an example of it use. + * examples under examples/mpfs-hal for an example of it use. * - * https://github.com/polarfire-soc/polarfire-soc-bare-metal-library + * https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples * * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md * which can be found under the link below: @@ -53,10 +53,10 @@ during the development process. MEMORY { - /* In this example, our reset vector is set to point to the */ - /* start at page 1 of the envm */ envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k + /* This 1K of DTIM is used to run code when switching the envm clock */ + switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k @@ -64,8 +64,6 @@ MEMORY u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1K of DTIM is used to run code when switching the envm clock */ - switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k /* DDR sections example */ ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M @@ -74,18 +72,38 @@ MEMORY ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k } -HEAP_SIZE = 0k; /* needs to be calculated for your application if using */ +HEAP_SIZE = 8k; /* needs to be calculated for your application */ /* - * Stack size for our single hart U54 application. + * There is common area for shared variables, accessed from a pointer in a harts HLS */ -STACK_SIZE_U54_APPLICATION = 8k; +SIZE_OF_COMMON_HART_MEM = 4k; +/* + * The stack size needs to be calculated for your application. It must be aligned. + * Also Thread local storage (AKA hart local storage) is allocated for each hart + * as part of the stack. + * So the memory map will look like once apportion in startup code: + * stack hart0 + * HLS hart 0 + * stack hart1 + * HLS hart 1 + * etc + * Actual Stack size per hart = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) + * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h + */ /* - * A small amount of unitialised memory used to store information - * obtained from the boot-loader on start-up + * Stack size for each hart's application. + * These are the stack sizes that will be allocated to each hart before starting + * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). */ -UNITITALISED_MEM = 16B; +STACK_SIZE_E51_APPLICATION = 0k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; + + /* reset address 0xC0000000 */ SECTION_START_ADDRESS = 0x80000000; @@ -148,8 +166,10 @@ SECTIONS { __sdata_load = LOADADDR(.sdata); __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ + /* offset used with gp(gloabl pointer) are +/- 12 bits, so set + point to middle of expected sdata range */ + /* If sdata more than 4K, linker used direct addressing. + Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); @@ -205,7 +225,37 @@ SECTIONS .stack : ALIGN(0x1000) { PROVIDE(__app_stack_bottom = .); - . += STACK_SIZE_U54_APPLICATION; + + PROVIDE(__stack_bottom_h0$ = .); + PROVIDE(__app_stack_bottom_h0 = .); + . += STACK_SIZE_E51_APPLICATION; + PROVIDE(__app_stack_top_h0 = .); + PROVIDE(__stack_top_h0$ = .); + + PROVIDE(__stack_bottom_h1$ = .); + PROVIDE(__app_stack_bottom_h1$ = .); + . += STACK_SIZE_U54_1_APPLICATION; + PROVIDE(__app_stack_top_h1 = .); + PROVIDE(__stack_top_h1$ = .); + + PROVIDE(__stack_bottom_h2$ = .); + PROVIDE(__app_stack_bottom_h2 = .); + . += STACK_SIZE_U54_2_APPLICATION; + PROVIDE(__app_stack_top_h2 = .); + PROVIDE(__stack_top_h2$ = .); + + PROVIDE(__stack_bottom_h3$ = .); + PROVIDE(__app_stack_bottom_h3 = .); + . += STACK_SIZE_U54_3_APPLICATION; + PROVIDE(__app_stack_top_h3 = .); + PROVIDE(__stack_top_h3$ = .); + + PROVIDE(__stack_bottom_h4$ = .); + PROVIDE(__app_stack_bottom_h4 = .); + . += STACK_SIZE_U54_4_APPLICATION; + PROVIDE(__app_stack_top_h4 = .); + PROVIDE(__stack_top_h4$ = .); + PROVIDE(__app_stack_top = .); } > ddr_cached_32bit @@ -217,10 +267,11 @@ SECTIONS * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the * mss_sw_config.h */ - .no_init : ALIGN(0x10) + .app_hart_common : /* ALIGN(0x1000) */ { - PROVIDE(__uninit_bottom$ = .); - . += UNITITALISED_MEM; - PROVIDE(__uninit_top_h$ = .); + PROVIDE(__app_hart_common_start = .); + . += SIZE_OF_COMMON_HART_MEM; + PROVIDE(__app_hart_common_end = .); } > ddr_cached_32bit } + diff --git a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm-lma-scratchpad-vma.ld b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm-lma-scratchpad-vma.ld index b98f7342..2a5f0a37 100644 --- a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm-lma-scratchpad-vma.ld +++ b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm-lma-scratchpad-vma.ld @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -45,10 +45,10 @@ See the mpfs-lim.ld example linker script when runing from LIM. MEMORY { - /* In this example, our reset vector is set to point to the */ - /* start at page 1 of the envm */ envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k + /* This 1K of DTIM is used to run code when switching the envm clock */ + switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k @@ -56,8 +56,6 @@ MEMORY u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1k of DTIM is used to run code when switching the envm clock */ - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k /* DDR sections example */ ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M @@ -67,7 +65,7 @@ MEMORY ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k } -HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ +HEAP_SIZE = 8k; /* needs to be calculated for your application */ /* * There is common area for shared variables, accessed from a pointer in a harts HLS @@ -75,16 +73,16 @@ HEAP_SIZE = 8k; /* needs to be calculated for your appli SIZE_OF_COMMON_HART_MEM = 4k; /* - * The stack size needs to be calculated for your - * application. It must be Must be aligned + * The stack size needs to be calculated for your application. It must be aligned. * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack + * as part of the stack. * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 + * stack hart0 + * HLS hart 0 * stack hart1 - * TLS hart 1 + * HLS hart 1 * etc + * Actual Stack size per hart = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ @@ -94,12 +92,6 @@ SIZE_OF_COMMON_HART_MEM = 4k; * Before copying itself to the scratchpad memory area and executing the code from there, the * startup code is executing from LIM. The scratchpad area is not configured yet. This per-hart * startup stack area is located in LIM and used during this phase of the startup code. - * STACK_SIZE_xxx_APPLICATION - * After the startup code executing from LIM configures the scratchpad memory, it configures - * the each hart's SP with this stack area for the respective hart's application function, - * (namely e51(), u54_1(), u54_2(), u54_3(), u54_4() ) to use it. - * This per-hart application stack area is located in scratchpad and used by application when - * it is executing from scratchpad. * */ STACK_SIZE_E51_STARTUP = 4k; @@ -108,6 +100,14 @@ STACK_SIZE_U54_2_STARTUP = 4k; STACK_SIZE_U54_3_STARTUP = 4k; STACK_SIZE_U54_4_STARTUP = 4k; +/* + * STACK_SIZE_xxx_APPLICATION + * After the startup code executing from LIM configures the scratchpad memory, it configures + * the each hart's SP with this stack area for the respective hart's application function, + * (namely e51(), u54_1(), u54_2(), u54_3(), u54_4() ) to use it. + * This per-hart application stack area is located in scratchpad and used by application when + * it is executing from scratchpad. + */ STACK_SIZE_E51_APPLICATION = 8k; STACK_SIZE_U54_1_APPLICATION = 8k; STACK_SIZE_U54_2_APPLICATION = 8k; @@ -211,8 +211,10 @@ SECTIONS { __sdata_load = LOADADDR(.sdata); __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ + /* offset used with gp(gloabl pointer) are +/- 12 bits, so set + point to middle of expected sdata range */ + /* If sdata more than 4K, linker used direct addressing. + Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); @@ -262,10 +264,8 @@ SECTIONS __heap_end = .; . = ALIGN(0x10); _heap_end = __heap_end; - __l2_scratchpad_vma_end = .; } > scratchpad - /* must be on 4k boundary- corresponds to page size */ .stack_e51 : /* ALIGN(0x1000) */ { @@ -346,6 +346,7 @@ SECTIONS . += STACK_SIZE_U54_4_APPLICATION; PROVIDE(__app_stack_top_h4 = .); } > scratchpad + /* * memory shared accross harts. @@ -381,7 +382,7 @@ SECTIONS __sc_end = .; /* place __start_of_free_lim$ after last allocation of l2lim */ PROVIDE(__start_of_free_lim$ = .); - } >switch_code AT> envm /* On the MPFS for startup code use, >switch_code AT>envm */ + } >switch_code_dtim AT> envm } diff --git a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld index 29817bd0..c4a16adb 100644 --- a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld +++ b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -50,6 +50,8 @@ MEMORY /* start at page 1 of the envm */ envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k + /* This 1K of DTIM is used to run code when switching the envm clock */ + switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k @@ -57,8 +59,6 @@ MEMORY u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1K of DTIM is used to run code when switching the envm clock */ - switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k /* DDR sections example */ ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M @@ -76,16 +76,16 @@ HEAP_SIZE = 8k; /* needs to be calculated for your application */ SIZE_OF_COMMON_HART_MEM = 4k; /* - * The stack size needs to be calculated for your - * application. It must be Must be aligned + * The stack size needs to be calculated for your application. It must be aligned. * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack + * as part of the stack. * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 + * stack hart0 + * HLS hart 0 * stack hart1 - * TLS hart 1 + * HLS hart 1 * etc + * Actual Stack size per hart = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ @@ -137,7 +137,6 @@ SECTIONS __text_load = LOADADDR(.text); __text_start = .; *(.text.init) - /* *entry.o(.text); */ . = ALIGN(0x10); *(.text .text.* .gnu.linkonce.t.*) *(.plt) @@ -287,11 +286,8 @@ SECTIONS _heap_end = __heap_end; } > l2lim - /* must be on 4k boundary (0x1000) - corresponds to page size, when using - memory mem */ - /* protection */ - /* .stack : ALIGN(0x1000) */ - .stack : ALIGN(0x10) + /* must be on 4k boundary- corresponds to page size */ + .stack : ALIGN(0x1000) { PROVIDE(__stack_bottom_h0$ = .); PROVIDE(__app_stack_bottom_h0 = .); @@ -323,9 +319,6 @@ SECTIONS PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); - /* place __start_of_free_lim$ after last allocation of l2_lim */ - . = ALIGN(0x10); - PROVIDE(__start_of_free_lim$ = .); } > l2lim /* diff --git a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld index 391c47bf..7e3980f0 100644 --- a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld +++ b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -41,6 +41,8 @@ MEMORY { envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k + /* This 1K of DTIM is used to run code when switching the envm clock */ + switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k @@ -48,8 +50,6 @@ MEMORY u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k - /* This 1k of DTIM is used to run code when switching the envm clock */ - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k /* DDR sections example */ ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M @@ -59,7 +59,7 @@ MEMORY ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k } -HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ +HEAP_SIZE = 8k; /* needs to be calculated for your application */ /* * There is common area for shared variables, accessed from a pointer in a harts HLS @@ -67,16 +67,16 @@ HEAP_SIZE = 8k; /* needs to be calculated for your application if SIZE_OF_COMMON_HART_MEM = 4k; /* - * The stack size needs to be calculated for your - * application. It must be Must be aligned + * The stack size needs to be calculated for your application. It must be aligned. * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack + * as part of the stack. * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 + * stack hart0 + * HLS hart 0 * stack hart1 - * TLS hart 1 + * HLS hart 1 * etc + * Actual Stack size per hart = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ @@ -86,13 +86,7 @@ SIZE_OF_COMMON_HART_MEM = 4k; * Before copying itself to the scratchpad memory area and executing the code from there, the * startup code is executing from LIM. The scratchpad area is not configured yet. This per-hart * startup stack area is located in LIM and used during this phase of the startup code. - * STACK_SIZE_xxx_APPLICATION - * After the startup code executing from LIM configures the scratchpad memory, it configures - * the each hart's SP with this stack area for the respective hart's application function, - * (namely e51(), u54_1(), u54_2(), u54_3(), u54_4() ) to use it. - * This per-hart application stack area is located in scratchpad and used by application when - * it is executing from scratchpad. - * + * */ STACK_SIZE_E51_STARTUP = 4k; STACK_SIZE_U54_1_STARTUP = 4k; @@ -100,12 +94,21 @@ STACK_SIZE_U54_2_STARTUP = 4k; STACK_SIZE_U54_3_STARTUP = 4k; STACK_SIZE_U54_4_STARTUP = 4k; +/* + * STACK_SIZE_xxx_APPLICATION + * After the startup code executing from LIM configures the scratchpad memory, it configures + * the each hart's SP with this stack area for the respective hart's application function, + * (namely e51(), u54_1(), u54_2(), u54_3(), u54_4() ) to use it. + * This per-hart application stack area is located in scratchpad and used by application when + * it is executing from scratchpad. + */ STACK_SIZE_E51_APPLICATION = 8k; STACK_SIZE_U54_1_APPLICATION = 8k; STACK_SIZE_U54_2_APPLICATION = 8k; STACK_SIZE_U54_3_APPLICATION = 8k; STACK_SIZE_U54_4_APPLICATION = 8k; + SECTIONS { PROVIDE(__envm_start = ORIGIN(envm)); @@ -370,6 +373,6 @@ SECTIONS __sc_end = .; /* place __start_of_free_lim$ after last allocation of l2lim */ PROVIDE(__start_of_free_lim$ = .); - } >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>envm */ + } >switch_code_dtim AT> l2lim /* On the MPFS for startup code use, >switch_code AT>envm */ } diff --git a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld index 908cf23e..8b40be2a 100644 --- a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld +++ b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -35,11 +35,13 @@ during the development process. ------------------------------------------------------------------------------*/ + MEMORY { envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k + /* This 1K of DTIM is used to run code when switching the envm clock */ + switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k @@ -56,7 +58,7 @@ MEMORY ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k } -HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ +HEAP_SIZE = 8k; /* needs to be calculated for your application */ /* * There is common area for shared variables, accessed from a pointer in a harts HLS @@ -64,16 +66,16 @@ HEAP_SIZE = 8k; /* needs to be calculated for your appli SIZE_OF_COMMON_HART_MEM = 4k; /* - * The stack size needs to be calculated for your - * application. It must be Must be aligned + * The stack size needs to be calculated for your application. It must be aligned. * Also Thread local storage (AKA hart local storage) is allocated for each hart - * as part of the stack + * as part of the stack. * So the memory map will look like once apportion in startup code: - * stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) - * TLS hart 0 + * stack hart0 + * HLS hart 0 * stack hart1 - * TLS hart 1 - * etc + * HLS hart 1 + * etc + * Actual Stack size per hart = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) * note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ @@ -166,12 +168,10 @@ SECTIONS . = ALIGN(0x10); __text_end = .; - . = ALIGN(0x10); } > l2lim .l2_scratchpad : ALIGN(0x10) { - . = ALIGN (0x10); __l2_scratchpad_load = LOADADDR(.l2_scratchpad); __l2_scratchpad_start = .; __l2_scratchpad_vma_start = .; @@ -198,15 +198,17 @@ SECTIONS *(.ram_coderodata*) . = ALIGN (4); __sc_end = .; - } >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>eNVM */ + } >switch_code_dtim AT> l2lim /* short/global data section */ .sdata : ALIGN(0x10) { __sdata_load = LOADADDR(.sdata); __sdata_start = .; - /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ - /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ + /* offset used with gp(gloabl pointer) are +/- 12 bits, so set + point to middle of expected sdata range */ + /* If sdata more than 4K, linker used direct addressing. + Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); diff --git a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h index 7b6e905d..5b50f65b 100644 --- a/mpfs-watchdog-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h +++ b/mpfs-watchdog-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -161,9 +161,16 @@ * The reason you may want to use below is to save code space. */ #define SGMII_SUPPORT -#define DDR_SUPPORT +//#define DDR_SUPPORT #define MSSIO_SUPPORT +/* + * Uncomment MICROCHIP_STDIO_THRU_MMUARTx to enable stdio port + * Note: you must have mss_mmuart driver source code included in the project. + */ +//#define MICROCHIP_STDIO_THRU_MMUARTX &g_mss_uart0_lo +//#define MICROCHIP_STDIO_BAUD_RATE MSS_UART_115200_BAUD + /* * DDR software options */