diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/.cproject b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/.cproject
index 2f3b2362..7269fa4e 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/.cproject
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/.cproject
@@ -281,7 +281,7 @@
-
+
@@ -437,7 +437,7 @@
-
+
@@ -757,7 +757,7 @@
-
+
@@ -765,7 +765,7 @@
-
+
@@ -905,7 +905,7 @@
@@ -1161,7 +1161,7 @@
@@ -1417,7 +1417,7 @@
@@ -1761,17 +1761,27 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/README.md b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/README.md
index 352e1484..69cd44d6 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/README.md
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/README.md
@@ -9,7 +9,11 @@ This example project runs the Cormark performace test.
To use this example you will need to obtain the coremark source files from the
Embedded Microprocessor Benchmark Consortium (EEMBC). These are placed in the
-coremark directory
+coremark directory.
+This will be done automatically using gitsubmodule, once you clone the repo using
+git and then run the git submodule command
+**git submodule update --init --recursive\n**
+
To use this project you will need a UART terminal configured as below:
- 115200 baud
@@ -430,8 +434,18 @@ Example 5
-## Loading the Payload binary
-
-When the project configuration is selected, the resulting binary requires loading using a boot-loader.
+## Loading the Payload binary when using DDR
+
+When using the folloing build configurations a boot-loader progam must be used to load the binary or elf:
+ - Icicle-kit-payload-u54-1
+ - Icicle-kit-payload-u54-2
+ - Icicle-kit-payload-u54-3
+ - Icicle-kit-payload-u54-4
+
The MPFS HAL DDR DEMO program bundled with this example can be used. Load the MPFS HAL DDR DEMO binary to envm and use the CLI menu to load the binary.
-
\ No newline at end of file
+For payload 2 to 4, the default load address of 0x80000000 will need to be changed to match the required load address 0x800A0000 for U54-2, 0x80140000 for U54-3 or 0x801E0000 for U54-4.
+
+The HSS can also be used. Please find the details here:
+[HSS payloads](https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/software-development/hss-payloads.md)
+The entry points for the yaml file need to match the entry point used in each elf. These are :
+{u54_1: '0x80000000', u54_2: '0x800A0000', u54_3: '0x80140000', u54_4: '0x801E0000'}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
index ffbcfdc2..b1cd84c5 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
@@ -35,10 +35,10 @@
#define LIBERO_SETTING_XML_VERSION_MAJOR 0
#define LIBERO_SETTING_XML_VERSION_MINOR 5
#define LIBERO_SETTING_XML_VERSION_PATCH 3
-#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.3"
+#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.4"
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR 0
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR 6
-#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 3
+#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 4
#include "memory_map/hw_memory.h"
#include "memory_map/hw_apb_split.h"
@@ -58,7 +58,9 @@
#include "memory_map/hw_mpu_mmc.h"
#include "memory_map/hw_mpu_scb.h"
#include "memory_map/hw_mpu_trace.h"
+#include "memory_map/hw_nvm_map.h"
#include "io/hw_mssio_mux.h"
+#include "io/hw_mssio_mux_alternate.h"
#include "io/hw_hsio_mux.h"
#include "sgmii/hw_sgmii_tip.h"
#include "ddr/hw_ddr_options.h"
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-2.ld b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-2.ld
new file mode 100644
index 00000000..17045784
--- /dev/null
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-2.ld
@@ -0,0 +1,226 @@
+/*******************************************************************************
+ * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * MPFS HAL Embedded Software
+ *
+ */
+/*******************************************************************************
+ *
+ * file name : mpfs-ddr-loaded-by-boot-loader.ld
+ * Use this linker script when the program is fully located in DDR. The
+ * assumption is DDR has already been initialized by another program.
+ *
+ * This linker script can be used with a debugger or when compiled and loaded
+ * by a boot-loader.
+ * The loading program passes two parameters in a0 and a1
+ * a0 - The hartid is passed here
+ * a1 - A pointer to Hart Local Storage (HLS) is passed here
+ * The HLS is a small amount of memory dedicated to each hart.
+ * The HLS also contains a pointer to shared memory.
+ * The shared memory is accessible by all harts if used. It is
+ * allocated by the boot-loader if the MPFS_HAL_SHARED_MEM_ENABLED
+ * is defined in the mss_sw_config.h file project configuration file.
+ * Please see the project mpfs-hal-run-from-ddr-u54-1 located in the Bare Metal
+ * library under examples/mpfs-hal for an example of it use.
+ *
+ * https://github.com/polarfire-soc/polarfire-soc-bare-metal-library
+ *
+ * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md
+ * which can be found under the link below:
+ * https://github.com/polarfire-soc/polarfire-soc-documentation
+ *
+ */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/*-----------------------------------------------------------------------------
+
+-- MSS hart Reset vector
+
+The MSS reset vector for each hart is stored securely in the MPFS.
+The most common usage will be where the reset vector for each hart will be set
+to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous
+non-volatile storage. Normally this is where the initial boot-loader will
+reside. (Note: The first 256B page of envm is used for metadata associated with
+secure boot. When not using secure boot (mode 0,1), this area is still reserved
+by convention. It allows easier transition from non-secure to secure boot flow
+during the development process.
+
+------------------------------------------------------------------------------*/
+
+MEMORY
+{
+ /* In this example, our reset vector is set to point to the */
+ /* start at page 1 of the envm */
+ envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
+ dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
+ e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
+ u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
+ u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
+ u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
+ u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
+ l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
+ scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
+ /* This 1K of DTIM is used to run code when switching the envm clock */
+ switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
+ /* DDR sections example */
+ ddr_cached_32bit (rwx) : ORIGIN = 0x800A0000, LENGTH = 10M
+ ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
+ ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
+ ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
+ ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
+ ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
+}
+HEAP_SIZE = 0k; /* needs to be calculated for your application if using */
+
+/*
+ * Stack size for our single hart U54 application.
+ */
+STACK_SIZE_U54_APPLICATION = 8k;
+
+/*
+ * A small amount of unitialised memory used to store information
+ * obtained from the boot-loader on start-up
+ */
+UNITITALISED_MEM = 16B;
+
+/* reset address 0xC0000000 */
+SECTION_START_ADDRESS = 0x80000000;
+
+
+SECTIONS
+{
+
+ /* text: test code section */
+ . = SECTION_START_ADDRESS;
+ .text : ALIGN(0x10)
+ {
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+ *(.text.init)
+ . = ALIGN(0x10);
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ . = ALIGN(0x10);
+
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+
+ . = ALIGN(0x10);
+ __text_end = .;
+ } > ddr_cached_32bit
+
+ /* short/global data section */
+ .sdata : ALIGN(0x10)
+ {
+ __sdata_load = LOADADDR(.sdata);
+ __sdata_start = .;
+ /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */
+ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */
+ __global_pointer$ = . + 0x800;
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ . = ALIGN(0x10);
+ __sdata_end = .;
+ } > ddr_cached_32bit
+
+ /* data section */
+ .data : ALIGN(0x10)
+ {
+ __data_load = LOADADDR(.data);
+ __data_start = .;
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN(0x10);
+ __data_end = .;
+ } > ddr_cached_32bit
+
+ /* sbss section */
+ .sbss : ALIGN(0x10)
+ {
+ __sbss_start = .;
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ . = ALIGN(0x10);
+ __sbss_end = .;
+ } > ddr_cached_32bit
+
+ /* sbss section */
+ .bss : ALIGN(0x10)
+ {
+ __bss_start = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(0x10);
+ __bss_end = .;
+ } > ddr_cached_32bit
+
+ /* End of uninitialized data segment */
+ _end = .;
+
+ .heap : ALIGN(0x10)
+ {
+ __heap_start = .;
+ . += HEAP_SIZE;
+ __heap_end = .;
+ . = ALIGN(0x10);
+ _heap_end = __heap_end;
+ } > ddr_cached_32bit
+
+ /* must be on 4k boundary- corresponds to page size */
+ .stack : ALIGN(0x1000)
+ {
+ PROVIDE(__app_stack_bottom = .);
+ . += STACK_SIZE_U54_APPLICATION;
+ PROVIDE(__app_stack_top = .);
+ } > ddr_cached_32bit
+
+ /*
+ * used by a program loaded by a bootloader to store information passed
+ * from boot-loader
+ * a0 holds the hart ID
+ * a1 hold pointer to device data, which includes pointer to shared memory
+ * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the
+ * mss_sw_config.h
+ */
+ .no_init : ALIGN(0x10)
+ {
+ PROVIDE(__uninit_bottom$ = .);
+ . += UNITITALISED_MEM;
+ PROVIDE(__uninit_top_h$ = .);
+ } > ddr_cached_32bit
+}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-3.ld b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-3.ld
new file mode 100644
index 00000000..14f8c1ed
--- /dev/null
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-3.ld
@@ -0,0 +1,226 @@
+/*******************************************************************************
+ * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * MPFS HAL Embedded Software
+ *
+ */
+/*******************************************************************************
+ *
+ * file name : mpfs-ddr-loaded-by-boot-loader.ld
+ * Use this linker script when the program is fully located in DDR. The
+ * assumption is DDR has already been initialized by another program.
+ *
+ * This linker script can be used with a debugger or when compiled and loaded
+ * by a boot-loader.
+ * The loading program passes two parameters in a0 and a1
+ * a0 - The hartid is passed here
+ * a1 - A pointer to Hart Local Storage (HLS) is passed here
+ * The HLS is a small amount of memory dedicated to each hart.
+ * The HLS also contains a pointer to shared memory.
+ * The shared memory is accessible by all harts if used. It is
+ * allocated by the boot-loader if the MPFS_HAL_SHARED_MEM_ENABLED
+ * is defined in the mss_sw_config.h file project configuration file.
+ * Please see the project mpfs-hal-run-from-ddr-u54-1 located in the Bare Metal
+ * library under examples/mpfs-hal for an example of it use.
+ *
+ * https://github.com/polarfire-soc/polarfire-soc-bare-metal-library
+ *
+ * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md
+ * which can be found under the link below:
+ * https://github.com/polarfire-soc/polarfire-soc-documentation
+ *
+ */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/*-----------------------------------------------------------------------------
+
+-- MSS hart Reset vector
+
+The MSS reset vector for each hart is stored securely in the MPFS.
+The most common usage will be where the reset vector for each hart will be set
+to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous
+non-volatile storage. Normally this is where the initial boot-loader will
+reside. (Note: The first 256B page of envm is used for metadata associated with
+secure boot. When not using secure boot (mode 0,1), this area is still reserved
+by convention. It allows easier transition from non-secure to secure boot flow
+during the development process.
+
+------------------------------------------------------------------------------*/
+
+MEMORY
+{
+ /* In this example, our reset vector is set to point to the */
+ /* start at page 1 of the envm */
+ envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
+ dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
+ e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
+ u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
+ u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
+ u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
+ u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
+ l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
+ scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
+ /* This 1K of DTIM is used to run code when switching the envm clock */
+ switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
+ /* DDR sections example */
+ ddr_cached_32bit (rwx) : ORIGIN = 0x80140000, LENGTH = 10M
+ ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
+ ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
+ ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
+ ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
+ ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
+}
+HEAP_SIZE = 0k; /* needs to be calculated for your application if using */
+
+/*
+ * Stack size for our single hart U54 application.
+ */
+STACK_SIZE_U54_APPLICATION = 8k;
+
+/*
+ * A small amount of unitialised memory used to store information
+ * obtained from the boot-loader on start-up
+ */
+UNITITALISED_MEM = 16B;
+
+/* reset address 0xC0000000 */
+SECTION_START_ADDRESS = 0x80000000;
+
+
+SECTIONS
+{
+
+ /* text: test code section */
+ . = SECTION_START_ADDRESS;
+ .text : ALIGN(0x10)
+ {
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+ *(.text.init)
+ . = ALIGN(0x10);
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ . = ALIGN(0x10);
+
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+
+ . = ALIGN(0x10);
+ __text_end = .;
+ } > ddr_cached_32bit
+
+ /* short/global data section */
+ .sdata : ALIGN(0x10)
+ {
+ __sdata_load = LOADADDR(.sdata);
+ __sdata_start = .;
+ /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */
+ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */
+ __global_pointer$ = . + 0x800;
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ . = ALIGN(0x10);
+ __sdata_end = .;
+ } > ddr_cached_32bit
+
+ /* data section */
+ .data : ALIGN(0x10)
+ {
+ __data_load = LOADADDR(.data);
+ __data_start = .;
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN(0x10);
+ __data_end = .;
+ } > ddr_cached_32bit
+
+ /* sbss section */
+ .sbss : ALIGN(0x10)
+ {
+ __sbss_start = .;
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ . = ALIGN(0x10);
+ __sbss_end = .;
+ } > ddr_cached_32bit
+
+ /* sbss section */
+ .bss : ALIGN(0x10)
+ {
+ __bss_start = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(0x10);
+ __bss_end = .;
+ } > ddr_cached_32bit
+
+ /* End of uninitialized data segment */
+ _end = .;
+
+ .heap : ALIGN(0x10)
+ {
+ __heap_start = .;
+ . += HEAP_SIZE;
+ __heap_end = .;
+ . = ALIGN(0x10);
+ _heap_end = __heap_end;
+ } > ddr_cached_32bit
+
+ /* must be on 4k boundary- corresponds to page size */
+ .stack : ALIGN(0x1000)
+ {
+ PROVIDE(__app_stack_bottom = .);
+ . += STACK_SIZE_U54_APPLICATION;
+ PROVIDE(__app_stack_top = .);
+ } > ddr_cached_32bit
+
+ /*
+ * used by a program loaded by a bootloader to store information passed
+ * from boot-loader
+ * a0 holds the hart ID
+ * a1 hold pointer to device data, which includes pointer to shared memory
+ * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the
+ * mss_sw_config.h
+ */
+ .no_init : ALIGN(0x10)
+ {
+ PROVIDE(__uninit_bottom$ = .);
+ . += UNITITALISED_MEM;
+ PROVIDE(__uninit_top_h$ = .);
+ } > ddr_cached_32bit
+}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-4.ld b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-4.ld
new file mode 100644
index 00000000..3577ab49
--- /dev/null
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/linker/mpfs-ddr-loaded-by-boot-loader-u54-4.ld
@@ -0,0 +1,226 @@
+/*******************************************************************************
+ * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * MPFS HAL Embedded Software
+ *
+ */
+/*******************************************************************************
+ *
+ * file name : mpfs-ddr-loaded-by-boot-loader.ld
+ * Use this linker script when the program is fully located in DDR. The
+ * assumption is DDR has already been initialized by another program.
+ *
+ * This linker script can be used with a debugger or when compiled and loaded
+ * by a boot-loader.
+ * The loading program passes two parameters in a0 and a1
+ * a0 - The hartid is passed here
+ * a1 - A pointer to Hart Local Storage (HLS) is passed here
+ * The HLS is a small amount of memory dedicated to each hart.
+ * The HLS also contains a pointer to shared memory.
+ * The shared memory is accessible by all harts if used. It is
+ * allocated by the boot-loader if the MPFS_HAL_SHARED_MEM_ENABLED
+ * is defined in the mss_sw_config.h file project configuration file.
+ * Please see the project mpfs-hal-run-from-ddr-u54-1 located in the Bare Metal
+ * library under examples/mpfs-hal for an example of it use.
+ *
+ * https://github.com/polarfire-soc/polarfire-soc-bare-metal-library
+ *
+ * You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md
+ * which can be found under the link below:
+ * https://github.com/polarfire-soc/polarfire-soc-documentation
+ *
+ */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/*-----------------------------------------------------------------------------
+
+-- MSS hart Reset vector
+
+The MSS reset vector for each hart is stored securely in the MPFS.
+The most common usage will be where the reset vector for each hart will be set
+to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous
+non-volatile storage. Normally this is where the initial boot-loader will
+reside. (Note: The first 256B page of envm is used for metadata associated with
+secure boot. When not using secure boot (mode 0,1), this area is still reserved
+by convention. It allows easier transition from non-secure to secure boot flow
+during the development process.
+
+------------------------------------------------------------------------------*/
+
+MEMORY
+{
+ /* In this example, our reset vector is set to point to the */
+ /* start at page 1 of the envm */
+ envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
+ dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
+ e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
+ u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
+ u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
+ u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
+ u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
+ l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
+ scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
+ /* This 1K of DTIM is used to run code when switching the envm clock */
+ switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
+ /* DDR sections example */
+ ddr_cached_32bit (rwx) : ORIGIN = 0x801E0000, LENGTH = 10M
+ ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
+ ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
+ ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
+ ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
+ ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
+}
+HEAP_SIZE = 0k; /* needs to be calculated for your application if using */
+
+/*
+ * Stack size for our single hart U54 application.
+ */
+STACK_SIZE_U54_APPLICATION = 8k;
+
+/*
+ * A small amount of unitialised memory used to store information
+ * obtained from the boot-loader on start-up
+ */
+UNITITALISED_MEM = 16B;
+
+/* reset address 0xC0000000 */
+SECTION_START_ADDRESS = 0x80000000;
+
+
+SECTIONS
+{
+
+ /* text: test code section */
+ . = SECTION_START_ADDRESS;
+ .text : ALIGN(0x10)
+ {
+ __text_load = LOADADDR(.text);
+ __text_start = .;
+ *(.text.init)
+ . = ALIGN(0x10);
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ . = ALIGN(0x10);
+
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+
+ . = ALIGN(0x10);
+ __text_end = .;
+ } > ddr_cached_32bit
+
+ /* short/global data section */
+ .sdata : ALIGN(0x10)
+ {
+ __sdata_load = LOADADDR(.sdata);
+ __sdata_start = .;
+ /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */
+ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */
+ __global_pointer$ = . + 0x800;
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ . = ALIGN(0x10);
+ __sdata_end = .;
+ } > ddr_cached_32bit
+
+ /* data section */
+ .data : ALIGN(0x10)
+ {
+ __data_load = LOADADDR(.data);
+ __data_start = .;
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN(0x10);
+ __data_end = .;
+ } > ddr_cached_32bit
+
+ /* sbss section */
+ .sbss : ALIGN(0x10)
+ {
+ __sbss_start = .;
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ . = ALIGN(0x10);
+ __sbss_end = .;
+ } > ddr_cached_32bit
+
+ /* sbss section */
+ .bss : ALIGN(0x10)
+ {
+ __bss_start = .;
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(0x10);
+ __bss_end = .;
+ } > ddr_cached_32bit
+
+ /* End of uninitialized data segment */
+ _end = .;
+
+ .heap : ALIGN(0x10)
+ {
+ __heap_start = .;
+ . += HEAP_SIZE;
+ __heap_end = .;
+ . = ALIGN(0x10);
+ _heap_end = __heap_end;
+ } > ddr_cached_32bit
+
+ /* must be on 4k boundary- corresponds to page size */
+ .stack : ALIGN(0x1000)
+ {
+ PROVIDE(__app_stack_bottom = .);
+ . += STACK_SIZE_U54_APPLICATION;
+ PROVIDE(__app_stack_top = .);
+ } > ddr_cached_32bit
+
+ /*
+ * used by a program loaded by a bootloader to store information passed
+ * from boot-loader
+ * a0 holds the hart ID
+ * a1 hold pointer to device data, which includes pointer to shared memory
+ * when enabled by setting MPFS_HAL_SHARED_MEM_ENABLED define in the
+ * mss_sw_config.h
+ */
+ .no_init : ALIGN(0x10)
+ {
+ PROVIDE(__uninit_bottom$ = .);
+ . += UNITITALISED_MEM;
+ PROVIDE(__uninit_top_h$ = .);
+ } > ddr_cached_32bit
+}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
index 5b82efa2..981a046a 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
@@ -184,7 +184,7 @@
* linker scripts.
*/
-#define MPFS_HAL_SHARED_MEM_ENABLED
+//#define MPFS_HAL_SHARED_MEM_ENABLED
/* define the required tick rate in Milliseconds */
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/middleware/config/coremark/port/core_portme.c b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/middleware/config/coremark/port/core_portme.c
index cd241e92..2176b325 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/middleware/config/coremark/port/core_portme.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/middleware/config/coremark/port/core_portme.c
@@ -118,6 +118,8 @@ void portable_init(core_portable *p, int *argc, char *argv[])
{
uint32_t hartid = read_csr(mhartid);
+#ifdef TEST_CORE_U54_1
+
SYSREG->SOFT_RESET_CR &= ~( SOFT_RESET_CR_ENVM_MASK | SOFT_RESET_CR_TIMER_MASK | SOFT_RESET_CR_MMUART0_MASK);
SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_ENVM_MASK | SUBBLK_CLOCK_CR_TIMER_MASK | SUBBLK_CLOCK_CR_MMUART0_MASK;
@@ -127,6 +129,44 @@ void portable_init(core_portable *p, int *argc, char *argv[])
MSS_UART_init( &g_mss_uart0_lo,
MSS_UART_115200_BAUD,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+#endif
+
+#ifdef TEST_CORE_U54_2
+ SYSREG->SOFT_RESET_CR &= ~( SOFT_RESET_CR_ENVM_MASK | SOFT_RESET_CR_TIMER_MASK | SOFT_RESET_CR_MMUART1_MASK);
+
+ SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_ENVM_MASK | SUBBLK_CLOCK_CR_TIMER_MASK | SUBBLK_CLOCK_CR_MMUART1_MASK;
+
+ gp_my_uart = &g_mss_uart1_lo;
+
+ MSS_UART_init( &g_mss_uart1_lo,
+ MSS_UART_115200_BAUD,
+ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+#endif
+
+#ifdef TEST_CORE_U54_3
+ SYSREG->SOFT_RESET_CR &= ~( SOFT_RESET_CR_ENVM_MASK | SOFT_RESET_CR_TIMER_MASK | SOFT_RESET_CR_MMUART2_MASK);
+
+ SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_ENVM_MASK | SUBBLK_CLOCK_CR_TIMER_MASK | SUBBLK_CLOCK_CR_MMUART2_MASK;
+
+ gp_my_uart = &g_mss_uart2_lo;
+
+ MSS_UART_init( &g_mss_uart2_lo,
+ MSS_UART_115200_BAUD,
+ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+#endif
+
+#ifdef TEST_CORE_U54_4
+ SYSREG->SOFT_RESET_CR &= ~( SOFT_RESET_CR_ENVM_MASK | SOFT_RESET_CR_TIMER_MASK | SOFT_RESET_CR_MMUART3_MASK);
+
+ SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_ENVM_MASK | SUBBLK_CLOCK_CR_TIMER_MASK | SUBBLK_CLOCK_CR_MMUART3_MASK;
+
+ gp_my_uart = &g_mss_uart3_lo;
+
+ MSS_UART_init( &g_mss_uart3_lo,
+ MSS_UART_115200_BAUD,
+ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+#endif
+
// #error "Call board initialization routines in portable init (if needed), in particular initialize UART!\n"
if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_hart_ints.h
index c559d193..a82490cc 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_hart_ints.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_hart_ints.h
@@ -107,6 +107,7 @@ typedef struct BEU_Types_
#define LOCAL_INT_MAX 47U /* Highest numbered */
#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */
+
/*
* Interrupts associated with
* MAINTENANCE_E51_INT
@@ -375,3 +376,4 @@ void fabric_f2h_31_u54_local_IRQHandler_47(void);
#endif
#endif /* MSS_HART_INTS_H */
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.c
index 78ff22bf..1d7c28eb 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.c
@@ -74,9 +74,36 @@ void __enable_irq(void)
*/
void __enable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
+ uint8_t mhart_id = read_csr(mhartid);
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+
+ set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
+
+ /* Enable F2H interrupts as local instead of PLIC interrupts */
+ if (local_interrupt >= LOCAL_INT_F2H_OFFSET)
+ {
+ if (mhart_id == 1)
+ {
+ SYSREG->FAB_INTEN_U54_1 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 2)
+ {
+ SYSREG->FAB_INTEN_U54_2 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 3)
+ {
+ SYSREG->FAB_INTEN_U54_3 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 4)
+ {
+ SYSREG->FAB_INTEN_U54_4 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ }
}
}
@@ -85,9 +112,12 @@ void __enable_local_irq(uint8_t local_interrupt)
*/
void __disable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+ clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
}
}
@@ -177,3 +207,4 @@ void display_address_of_interest(uint64_t * address_of_interest, int nb_location
#ifdef __cplusplus
}
#endif
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.h b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.h
index 0b242c47..018c9764 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_util.h
@@ -37,6 +37,12 @@ extern "C" {
#define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y))
#define READ_REG64(x) (*((volatile uint64_t *)(x)))
+/*
+ * Local defines
+ */
+#define LOCAL_INT_OFFSET_IN_MIE 16U /* Offset from start of MIE for local irq enables */
+#define LOCAL_INT_F2H_OFFSET 16U /* Offset from 0 for fabric to MSS local interrupts */
+
/*
* return mcycle
*/
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/mpfs_hal_version.h
index a3e0bad1..0c07ea7b 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/mpfs_hal_version.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/mpfs_hal_version.h
@@ -41,7 +41,7 @@ extern "C" {
#define MPFS_HAL_VERSION_MAJOR 1
#define MPFS_HAL_VERSION_MINOR 8
-#define MPFS_HAL_VERSION_PATCH 131
+#define MPFS_HAL_VERSION_PATCH 134
#ifdef __cplusplus
}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/startup_gcc/mss_entry.S
index 8650949c..5ff6d95c 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/startup_gcc/mss_entry.S
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/startup_gcc/mss_entry.S
@@ -322,6 +322,9 @@ _start_non_bootloader_image:
# mhartid is in a0
beqz a0, 1f
#ifdef __riscv_flen
+ # enable FPU and accelerator
+ li t0, MSTATUS_FS | MSTATUS_XS
+ csrs mstatus, t0
fscsr x0
#endif
1: # no float
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/tools/test-coremark.yaml b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/tools/test-coremark.yaml
new file mode 100644
index 00000000..7a01d785
--- /dev/null
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-coremark/tools/test-coremark.yaml
@@ -0,0 +1,33 @@
+#
+# HSS Payload Generator - sample configuration file
+# Use this yaml file to run coremark on the four U54's.
+#
+
+# First, we can optionally set a name for our image, otherwise one will be created dynamically
+set-name: 'PolarFire-SoC-HSS::TestCoremarkImages running on four U54 harts'
+
+#
+# Next, we'll define the entry point addresses for each hart, as follows:
+#
+hart-entry-points: {u54_1: '0x80000000', u54_2: '0x800A0000', u54_3: '0x80140000', u54_4: '0x801E0000'}
+
+#
+# Finally, we'll define some payloads (source ELF files) that will be placed at certain regions in memory
+# The payload section is defined with the keyword payloads, and then a number of individual
+# payload descriptors.
+#
+# Each payload has a name (path to its ELF file), an owner-hart, and optionally 1-3 secondary-harts.
+#
+# Additionally, it has a privilege mode in which it will start execution.
+# * Valid privilege modes are PRV_M, PRV_S and PRV_U.
+#
+#
+#
+# Case only matters for the ELF path names, not the keywords.
+#
+payloads:
+ test/mpfs-hal-coremark_u54_1.elf: {exec-addr: '0x80000000', owner-hart: u54_1, priv-mode: prv_m}
+ test/mpfs-hal-coremark_u54-2.elf: {exec-addr: '0x800A0000', owner-hart: u54_2, priv-mode: prv_m}
+ test/mpfs-hal-coremark-u54-3.elf: {exec-addr: '0x80140000', owner-hart: u54_3, priv-mode: prv_m}
+ test/mpfs-hal-coremark-u54-4.elf: {exec-addr: '0x801E0000', owner-hart: u54_4, priv-mode: prv_m}
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_hart_ints.h
index c559d193..a82490cc 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_hart_ints.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_hart_ints.h
@@ -107,6 +107,7 @@ typedef struct BEU_Types_
#define LOCAL_INT_MAX 47U /* Highest numbered */
#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */
+
/*
* Interrupts associated with
* MAINTENANCE_E51_INT
@@ -375,3 +376,4 @@ void fabric_f2h_31_u54_local_IRQHandler_47(void);
#endif
#endif /* MSS_HART_INTS_H */
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.c
index 78ff22bf..1d7c28eb 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.c
@@ -74,9 +74,36 @@ void __enable_irq(void)
*/
void __enable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
+ uint8_t mhart_id = read_csr(mhartid);
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+
+ set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
+
+ /* Enable F2H interrupts as local instead of PLIC interrupts */
+ if (local_interrupt >= LOCAL_INT_F2H_OFFSET)
+ {
+ if (mhart_id == 1)
+ {
+ SYSREG->FAB_INTEN_U54_1 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 2)
+ {
+ SYSREG->FAB_INTEN_U54_2 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 3)
+ {
+ SYSREG->FAB_INTEN_U54_3 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 4)
+ {
+ SYSREG->FAB_INTEN_U54_4 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ }
}
}
@@ -85,9 +112,12 @@ void __enable_local_irq(uint8_t local_interrupt)
*/
void __disable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+ clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
}
}
@@ -177,3 +207,4 @@ void display_address_of_interest(uint64_t * address_of_interest, int nb_location
#ifdef __cplusplus
}
#endif
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.h b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.h
index 0b242c47..018c9764 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_util.h
@@ -37,6 +37,12 @@ extern "C" {
#define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y))
#define READ_REG64(x) (*((volatile uint64_t *)(x)))
+/*
+ * Local defines
+ */
+#define LOCAL_INT_OFFSET_IN_MIE 16U /* Offset from start of MIE for local irq enables */
+#define LOCAL_INT_F2H_OFFSET 16U /* Offset from 0 for fabric to MSS local interrupts */
+
/*
* return mcycle
*/
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/mpfs_hal_version.h
index a3e0bad1..0c07ea7b 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/mpfs_hal_version.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/mpfs_hal_version.h
@@ -41,7 +41,7 @@ extern "C" {
#define MPFS_HAL_VERSION_MAJOR 1
#define MPFS_HAL_VERSION_MINOR 8
-#define MPFS_HAL_VERSION_PATCH 131
+#define MPFS_HAL_VERSION_PATCH 134
#ifdef __cplusplus
}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S
index 8650949c..5ff6d95c 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S
@@ -322,6 +322,9 @@ _start_non_bootloader_image:
# mhartid is in a0
beqz a0, 1f
#ifdef __riscv_flen
+ # enable FPU and accelerator
+ li t0, MSTATUS_FS | MSTATUS_XS
+ csrs mstatus, t0
fscsr x0
#endif
1: # no float
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/application/hart1/u54_1.c b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/application/hart1/u54_1.c
index 8930a1e2..5933a431 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/application/hart1/u54_1.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/application/hart1/u54_1.c
@@ -36,22 +36,10 @@ void u54_1(void)
uint8_t info_string[100];
uint64_t hartid = read_csr(mhartid);
volatile uint32_t icount = 0U;
- HLS_DATA* hls = (HLS_DATA*)(uintptr_t)get_tp_reg();
-#ifdef MPFS_HAL_SHARED_MEM_ENABLED
- HART_SHARED_DATA * hart_share = (HART_SHARED_DATA *)hls->shared_mem;
-#endif
/* The hart is out of WFI, clear the SW interrupt. Hear onwards Application
can enable and use any interrupts as required */
clear_soft_interrupt();
- //__enable_irq();
-
-#ifdef MPFS_HAL_SHARED_MEM_ENABLED
- spinlock(&hart_share->mutex_uart0);
- MSS_UART_polled_tx_string(hart_share->g_mss_uart1_lo,
- "Hello World from u54 core 1 - hart1 running from DDR\r\n");
- spinunlock(&hart_share->mutex_uart0);
-#endif
/* Turn on UART1 clock and take out of reset */
(void)mss_config_clk_rst(MSS_PERIPH_MMUART1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON);
@@ -60,9 +48,6 @@ void u54_1(void)
MSS_UART_115200_BAUD,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
- sprintf(info_string, "\r\nHart %u, HLS mem address 0x%lx, Shared mem 0x%lx\r\n",\
- hls->my_hart_id, (uint64_t)hls, (uint64_t)hls->shared_mem);
-
MSS_UART_polled_tx_string(&g_mss_uart1_lo, (const uint8_t*)info_string);
#ifdef TEST_DDR_ACCESS
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
index ffbcfdc2..b1cd84c5 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
@@ -35,10 +35,10 @@
#define LIBERO_SETTING_XML_VERSION_MAJOR 0
#define LIBERO_SETTING_XML_VERSION_MINOR 5
#define LIBERO_SETTING_XML_VERSION_PATCH 3
-#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.3"
+#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.4"
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR 0
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR 6
-#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 3
+#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 4
#include "memory_map/hw_memory.h"
#include "memory_map/hw_apb_split.h"
@@ -58,7 +58,9 @@
#include "memory_map/hw_mpu_mmc.h"
#include "memory_map/hw_mpu_scb.h"
#include "memory_map/hw_mpu_trace.h"
+#include "memory_map/hw_nvm_map.h"
#include "io/hw_mssio_mux.h"
+#include "io/hw_mssio_mux_alternate.h"
#include "io/hw_hsio_mux.h"
#include "sgmii/hw_sgmii_tip.h"
#include "ddr/hw_ddr_options.h"
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
index 9c7743f3..3895ac14 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
@@ -108,7 +108,7 @@
* linker scripts.
*/
-#define MPFS_HAL_SHARED_MEM_ENABLED
+//#define MPFS_HAL_SHARED_MEM_ENABLED
/* define the required tick rate in Milliseconds */
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_hart_ints.h
index c559d193..a82490cc 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_hart_ints.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_hart_ints.h
@@ -107,6 +107,7 @@ typedef struct BEU_Types_
#define LOCAL_INT_MAX 47U /* Highest numbered */
#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */
+
/*
* Interrupts associated with
* MAINTENANCE_E51_INT
@@ -375,3 +376,4 @@ void fabric_f2h_31_u54_local_IRQHandler_47(void);
#endif
#endif /* MSS_HART_INTS_H */
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.c
index 78ff22bf..1d7c28eb 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.c
@@ -74,9 +74,36 @@ void __enable_irq(void)
*/
void __enable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
+ uint8_t mhart_id = read_csr(mhartid);
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+
+ set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
+
+ /* Enable F2H interrupts as local instead of PLIC interrupts */
+ if (local_interrupt >= LOCAL_INT_F2H_OFFSET)
+ {
+ if (mhart_id == 1)
+ {
+ SYSREG->FAB_INTEN_U54_1 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 2)
+ {
+ SYSREG->FAB_INTEN_U54_2 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 3)
+ {
+ SYSREG->FAB_INTEN_U54_3 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 4)
+ {
+ SYSREG->FAB_INTEN_U54_4 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ }
}
}
@@ -85,9 +112,12 @@ void __enable_local_irq(uint8_t local_interrupt)
*/
void __disable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+ clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
}
}
@@ -177,3 +207,4 @@ void display_address_of_interest(uint64_t * address_of_interest, int nb_location
#ifdef __cplusplus
}
#endif
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.h
index 0b242c47..018c9764 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/common/mss_util.h
@@ -37,6 +37,12 @@ extern "C" {
#define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y))
#define READ_REG64(x) (*((volatile uint64_t *)(x)))
+/*
+ * Local defines
+ */
+#define LOCAL_INT_OFFSET_IN_MIE 16U /* Offset from start of MIE for local irq enables */
+#define LOCAL_INT_F2H_OFFSET 16U /* Offset from 0 for fabric to MSS local interrupts */
+
/*
* return mcycle
*/
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/mpfs_hal_version.h
index a3e0bad1..0c07ea7b 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/mpfs_hal_version.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/mpfs_hal_version.h
@@ -41,7 +41,7 @@ extern "C" {
#define MPFS_HAL_VERSION_MAJOR 1
#define MPFS_HAL_VERSION_MINOR 8
-#define MPFS_HAL_VERSION_PATCH 131
+#define MPFS_HAL_VERSION_PATCH 134
#ifdef __cplusplus
}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/startup_gcc/mss_entry.S
index 8650949c..5ff6d95c 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/startup_gcc/mss_entry.S
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/src/platform/mpfs_hal/startup_gcc/mss_entry.S
@@ -322,6 +322,9 @@ _start_non_bootloader_image:
# mhartid is in a0
beqz a0, 1f
#ifdef __riscv_flen
+ # enable FPU and accelerator
+ li t0, MSTATUS_FS | MSTATUS_XS
+ csrs mstatus, t0
fscsr x0
#endif
1: # no float
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/tools/hss-payload.yaml b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/tools/hss-payload.yaml
new file mode 100644
index 00000000..d7832e4a
--- /dev/null
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-1/tools/hss-payload.yaml
@@ -0,0 +1,30 @@
+#
+# HSS Payload Generator - buildroot configuration file
+#
+
+# First, we can optionally set a name for our image, otherwise one will be created dynamically
+set-name: 'MPFS example programs for DDR'
+
+#
+# Next, we'll define the entry point addresses for each hart, as follows:
+#
+hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80200000', u54_3: '0x00000000', u54_4: '0x00000000'}
+#
+# Finally, we'll define a payloads (source binary file) that will be placed at certain regions in memory
+# The payload section is defined with the keyword payloads, and then a number of individual
+# payload descriptors.
+#
+# Each payload has a name (path to its ELF/bin file), an owner-hart, and optionally 1-3 secondary-harts.
+#
+# Additionally, it has a privilege mode in which it will start execution.
+# * Valid privilege modes are PRV_M, PRV_S and PRV_U.
+#
+#
+# In this case, we have two payloads, one for Linux context one and another one for FreeRTOS context
+#
+# Case only matters for the ELF path names, not the keywords.
+#
+payloads:
+ mpfs-hal-run-from-ddr-u54-1.elf: {exec-addr: '0x80000000', owner-hart: u54_1, priv-mode: prv_m}
+ mpfs-hal-run-from-ddr-u54-2.elf: {exec-addr: '0x80200000', owner-hart: u54_2, priv-mode: prv_m}
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/application/hart2/u54_2.c b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/application/hart2/u54_2.c
index be16a475..f3e5e4a2 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/application/hart2/u54_2.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/application/hart2/u54_2.c
@@ -30,34 +30,19 @@ void u54_2(void)
uint8_t info_string[100];
uint64_t hartid = read_csr(mhartid);
volatile uint32_t icount = 0U;
- HLS_DATA* hls = (HLS_DATA*)(uintptr_t)get_tp_reg();
-#ifdef MPFS_HAL_SHARED_MEM_ENABLED
- HART_SHARED_DATA * hart_share = (HART_SHARED_DATA *)hls->shared_mem;
-#endif
/* The hart is out of WFI, clear the SW interrupt. Hear onwards Application
can enable and use any interrupts as required */
clear_soft_interrupt();
- //__enable_irq();
-
-#ifdef MPFS_HAL_SHARED_MEM_ENABLED
- spinlock(&hart_share->mutex_uart0);
- MSS_UART_polled_tx_string(hart_share->g_mss_uart1_lo,
- "Hello World from u54 core 2 - hart2 running from DDR\r\n");
- spinunlock(&hart_share->mutex_uart0);
-#endif
/* Turn on UART1 clock and take out of reset */
(void)mss_config_clk_rst(MSS_PERIPH_MMUART1, (uint8_t) MPFS_HAL_FIRST_HART, PERIPHERAL_ON);
- MSS_UART_init( &g_mss_uart1_lo,
+ MSS_UART_init( &g_mss_uart2_lo,
MSS_UART_115200_BAUD,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
- sprintf(info_string, "\r\nHart %u, HLS mem address 0x%lx, Shared mem 0x%lx\r\n",\
- hls->my_hart_id, (uint64_t)hls, (uint64_t)hls->shared_mem);
-
- MSS_UART_polled_tx_string(&g_mss_uart1_lo, (const uint8_t*)info_string);
+ MSS_UART_polled_tx_string(&g_mss_uart2_lo, (const uint8_t*)info_string);
while (1U)
{
@@ -66,7 +51,7 @@ void u54_2(void)
{
icount = 0U;
sprintf(info_string,"Hart %d\r\n", hartid);
- MSS_UART_polled_tx(&g_mss_uart1_lo, info_string, strlen(info_string));
+ MSS_UART_polled_tx(&g_mss_uart2_lo, info_string, strlen(info_string));
}
}
/* never return */
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
index ffbcfdc2..b1cd84c5 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/fpga_design_config/fpga_design_config.h
@@ -35,10 +35,10 @@
#define LIBERO_SETTING_XML_VERSION_MAJOR 0
#define LIBERO_SETTING_XML_VERSION_MINOR 5
#define LIBERO_SETTING_XML_VERSION_PATCH 3
-#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.3"
+#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.4"
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR 0
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR 6
-#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 3
+#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 4
#include "memory_map/hw_memory.h"
#include "memory_map/hw_apb_split.h"
@@ -58,7 +58,9 @@
#include "memory_map/hw_mpu_mmc.h"
#include "memory_map/hw_mpu_scb.h"
#include "memory_map/hw_mpu_trace.h"
+#include "memory_map/hw_nvm_map.h"
#include "io/hw_mssio_mux.h"
+#include "io/hw_mssio_mux_alternate.h"
#include "io/hw_hsio_mux.h"
#include "sgmii/hw_sgmii_tip.h"
#include "ddr/hw_ddr_options.h"
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
index 658299e3..40d8965f 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h
@@ -108,7 +108,7 @@
* linker scripts.
*/
-#define MPFS_HAL_SHARED_MEM_ENABLED
+//#define MPFS_HAL_SHARED_MEM_ENABLED
/* define the required tick rate in Milliseconds */
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_hart_ints.h
index c559d193..a82490cc 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_hart_ints.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_hart_ints.h
@@ -107,6 +107,7 @@ typedef struct BEU_Types_
#define LOCAL_INT_MAX 47U /* Highest numbered */
#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */
+
/*
* Interrupts associated with
* MAINTENANCE_E51_INT
@@ -375,3 +376,4 @@ void fabric_f2h_31_u54_local_IRQHandler_47(void);
#endif
#endif /* MSS_HART_INTS_H */
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.c
index 78ff22bf..1d7c28eb 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.c
@@ -74,9 +74,36 @@ void __enable_irq(void)
*/
void __enable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
+ uint8_t mhart_id = read_csr(mhartid);
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+
+ set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
+
+ /* Enable F2H interrupts as local instead of PLIC interrupts */
+ if (local_interrupt >= LOCAL_INT_F2H_OFFSET)
+ {
+ if (mhart_id == 1)
+ {
+ SYSREG->FAB_INTEN_U54_1 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 2)
+ {
+ SYSREG->FAB_INTEN_U54_2 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 3)
+ {
+ SYSREG->FAB_INTEN_U54_3 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 4)
+ {
+ SYSREG->FAB_INTEN_U54_4 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ }
}
}
@@ -85,9 +112,12 @@ void __enable_local_irq(uint8_t local_interrupt)
*/
void __disable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+ clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
}
}
@@ -177,3 +207,4 @@ void display_address_of_interest(uint64_t * address_of_interest, int nb_location
#ifdef __cplusplus
}
#endif
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.h
index 0b242c47..018c9764 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/common/mss_util.h
@@ -37,6 +37,12 @@ extern "C" {
#define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y))
#define READ_REG64(x) (*((volatile uint64_t *)(x)))
+/*
+ * Local defines
+ */
+#define LOCAL_INT_OFFSET_IN_MIE 16U /* Offset from start of MIE for local irq enables */
+#define LOCAL_INT_F2H_OFFSET 16U /* Offset from 0 for fabric to MSS local interrupts */
+
/*
* return mcycle
*/
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/mpfs_hal_version.h
index a3e0bad1..0c07ea7b 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/mpfs_hal_version.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/mpfs_hal_version.h
@@ -41,7 +41,7 @@ extern "C" {
#define MPFS_HAL_VERSION_MAJOR 1
#define MPFS_HAL_VERSION_MINOR 8
-#define MPFS_HAL_VERSION_PATCH 131
+#define MPFS_HAL_VERSION_PATCH 134
#ifdef __cplusplus
}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/startup_gcc/mss_entry.S
index 8650949c..5ff6d95c 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/startup_gcc/mss_entry.S
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/src/platform/mpfs_hal/startup_gcc/mss_entry.S
@@ -322,6 +322,9 @@ _start_non_bootloader_image:
# mhartid is in a0
beqz a0, 1f
#ifdef __riscv_flen
+ # enable FPU and accelerator
+ li t0, MSTATUS_FS | MSTATUS_XS
+ csrs mstatus, t0
fscsr x0
#endif
1: # no float
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/tools/hss-payload.yaml b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/tools/hss-payload.yaml
new file mode 100644
index 00000000..d7832e4a
--- /dev/null
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-run-from-ddr-u54-2/tools/hss-payload.yaml
@@ -0,0 +1,30 @@
+#
+# HSS Payload Generator - buildroot configuration file
+#
+
+# First, we can optionally set a name for our image, otherwise one will be created dynamically
+set-name: 'MPFS example programs for DDR'
+
+#
+# Next, we'll define the entry point addresses for each hart, as follows:
+#
+hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80200000', u54_3: '0x00000000', u54_4: '0x00000000'}
+#
+# Finally, we'll define a payloads (source binary file) that will be placed at certain regions in memory
+# The payload section is defined with the keyword payloads, and then a number of individual
+# payload descriptors.
+#
+# Each payload has a name (path to its ELF/bin file), an owner-hart, and optionally 1-3 secondary-harts.
+#
+# Additionally, it has a privilege mode in which it will start execution.
+# * Valid privilege modes are PRV_M, PRV_S and PRV_U.
+#
+#
+# In this case, we have two payloads, one for Linux context one and another one for FreeRTOS context
+#
+# Case only matters for the ELF path names, not the keywords.
+#
+payloads:
+ mpfs-hal-run-from-ddr-u54-1.elf: {exec-addr: '0x80000000', owner-hart: u54_1, priv-mode: prv_m}
+ mpfs-hal-run-from-ddr-u54-2.elf: {exec-addr: '0x80200000', owner-hart: u54_2, priv-mode: prv_m}
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_hart_ints.h b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_hart_ints.h
index c559d193..a82490cc 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_hart_ints.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_hart_ints.h
@@ -107,6 +107,7 @@ typedef struct BEU_Types_
#define LOCAL_INT_MAX 47U /* Highest numbered */
#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */
+
/*
* Interrupts associated with
* MAINTENANCE_E51_INT
@@ -375,3 +376,4 @@ void fabric_f2h_31_u54_local_IRQHandler_47(void);
#endif
#endif /* MSS_HART_INTS_H */
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.c b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.c
index 78ff22bf..1d7c28eb 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.c
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.c
@@ -74,9 +74,36 @@ void __enable_irq(void)
*/
void __enable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
+ uint8_t mhart_id = read_csr(mhartid);
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+
+ set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
+
+ /* Enable F2H interrupts as local instead of PLIC interrupts */
+ if (local_interrupt >= LOCAL_INT_F2H_OFFSET)
+ {
+ if (mhart_id == 1)
+ {
+ SYSREG->FAB_INTEN_U54_1 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 2)
+ {
+ SYSREG->FAB_INTEN_U54_2 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 3)
+ {
+ SYSREG->FAB_INTEN_U54_3 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ else if (mhart_id == 4)
+ {
+ SYSREG->FAB_INTEN_U54_4 |= (1u << (local_interrupt - LOCAL_INT_F2H_OFFSET));
+ }
+ }
}
}
@@ -85,9 +112,12 @@ void __enable_local_irq(uint8_t local_interrupt)
*/
void __disable_local_irq(uint8_t local_interrupt)
{
+ ASSERT(local_interrupt > (int8_t)0);
+ ASSERT( (local_interrupt <= LOCAL_INT_MAX));
+
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
- clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
+ clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + LOCAL_INT_OFFSET_IN_MIE))); /* mie Register- Machine Interrupt Enable Register */
}
}
@@ -177,3 +207,4 @@ void display_address_of_interest(uint64_t * address_of_interest, int nb_location
#ifdef __cplusplus
}
#endif
+
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.h b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.h
index 0b242c47..018c9764 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/common/mss_util.h
@@ -37,6 +37,12 @@ extern "C" {
#define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y))
#define READ_REG64(x) (*((volatile uint64_t *)(x)))
+/*
+ * Local defines
+ */
+#define LOCAL_INT_OFFSET_IN_MIE 16U /* Offset from start of MIE for local irq enables */
+#define LOCAL_INT_F2H_OFFSET 16U /* Offset from 0 for fabric to MSS local interrupts */
+
/*
* return mcycle
*/
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/mpfs_hal_version.h b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/mpfs_hal_version.h
index a3e0bad1..0c07ea7b 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/mpfs_hal_version.h
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/mpfs_hal_version.h
@@ -41,7 +41,7 @@ extern "C" {
#define MPFS_HAL_VERSION_MAJOR 1
#define MPFS_HAL_VERSION_MINOR 8
-#define MPFS_HAL_VERSION_PATCH 131
+#define MPFS_HAL_VERSION_PATCH 134
#ifdef __cplusplus
}
diff --git a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S
index 8650949c..5ff6d95c 100644
--- a/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S
+++ b/driver-examples/mss/mpfs-hal/mpfs-hal-simple-demo/src/platform/mpfs_hal/startup_gcc/mss_entry.S
@@ -322,6 +322,9 @@ _start_non_bootloader_image:
# mhartid is in a0
beqz a0, 1f
#ifdef __riscv_flen
+ # enable FPU and accelerator
+ li t0, MSTATUS_FS | MSTATUS_XS
+ csrs mstatus, t0
fscsr x0
#endif
1: # no float