From 4297b40ec840d55b0684db04313e6d7abd019879 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:42:20 +0200 Subject: [PATCH 01/34] hw(nw_join): Use axi configs for `nw_join` --- hw/floo_nw_join.sv | 96 +++++++++++++++++++++------------------------- hw/floo_pkg.sv | 18 +++++++++ 2 files changed, 61 insertions(+), 53 deletions(-) diff --git a/hw/floo_nw_join.sv b/hw/floo_nw_join.sv index 79881685..11620869 100644 --- a/hw/floo_nw_join.sv +++ b/hw/floo_nw_join.sv @@ -12,23 +12,21 @@ /// of an HBM controller to enable access from both the /// narrow and the wide AXI bus. module floo_nw_join #( + /// Narrow AXI bus configuration + parameter floo_pkg::axi_cfg_t AxiCfgN = '0, + /// Wide AXI bus configuration + parameter floo_pkg::axi_cfg_t AxiCfgW = '0, + /// Resulting AXI bus configuration + parameter floo_pkg::axi_cfg_t AxiCfgJoin = '0, /// Filter Atops on the Narrow AXI bus parameter bit FilterNarrowAtops = 1'b0, /// Filter Atops on the Wide AXI bus parameter bit FilterWideAtops = 1'b0, - /// ID width of the narrow AXI bus - parameter int unsigned AxiNarrowIdInWidth = 0, - /// ID width of the wide AXI bus - parameter int unsigned AxiWideIdInWidth = 0, - /// User width of the narrow AXI bus - parameter int unsigned AxiNarrowUserInWidth = 0, - /// User width of the wide AXI bus - parameter int unsigned AxiWideUserInWidth = 0, /// ID width of the resulting AXI bus /// To prevent the instantiation of any ID remappers, /// `AxiIdOutWidth` should be chosen, such that: /// max(`AxiNarrowIdWidth` and `AxiWideIdWidth`) == AxidOutWidth - 1 - parameter int unsigned AxiIdOutWidth = 0, + parameter int unsigned AxiIdOutWidth = AxiCfgJoin.InIdWidth, /// ID width of the busses before muxing them together. localparam int unsigned AxiIdConvWidth = AxiIdOutWidth - 1, /// Default parameter for number of inflight narrow transactions @@ -38,7 +36,7 @@ module floo_nw_join #( /// Maximum number of in-flight AXI narrow read transactions parameter int unsigned AxiNarrowMaxReadTxns = AxiNarrowMaxTxns, /// Number of unique IDs on the narrow AXI bus - parameter int unsigned AxiNarrowSlvPortMaxUniqIds = 2**AxiNarrowIdInWidth, + parameter int unsigned AxiNarrowSlvPortMaxUniqIds = 2**AxiCfgN.InIdWidth, /// Maximum number of in-flight AXI transactions on the narrow AXI bus parameter int unsigned AxiNarrowSlvPortMaxTxnsPerId = AxiNarrowMaxTxns, /// Maximum number of in-flight transactions at the narrow slave port @@ -52,7 +50,7 @@ module floo_nw_join #( /// Maximum number of in-flight AXI wide write transactions parameter int unsigned AxiWideMaxWriteTxns = AxiWideMaxTxns, /// Number of unique IDs on the wide AXI bus - parameter int unsigned AxiWideSlvPortMaxUniqIds = 2**AxiWideIdInWidth, + parameter int unsigned AxiWideSlvPortMaxUniqIds = 2**AxiCfgW.InIdWidth, /// Maximum number of in-flight AXI transactions on the wide AXI bus parameter int unsigned AxiWideSlvPortMaxTxnsPerId = AxiWideMaxTxns, /// Maximum number of in-flight transactions at the wide slave port @@ -61,18 +59,10 @@ module floo_nw_join #( parameter int unsigned AxiWideMstPortMaxUniqIds = 2**AxiIdConvWidth, /// Maximum number of in-flight transactions with the same ID at the wide master port. parameter int unsigned AxiWideMstPortMaxTxnsPerId = AxiWideMaxTxns, - /// Address width of both AXI4+ATOP ports - parameter int unsigned AxiAddrWidth = 32'd0, - /// Data width of narrow AXI4+ATOP ports - parameter int unsigned AxiNarrowDataWidth = 32'd0, - /// Data width of wide AXI4+ATOP ports - parameter int unsigned AxiWideDataWidth = 32'd0, - /// User signal width of both AXI4+ATOP ports - parameter int unsigned AxiUserWidth = 32'd0, /// Use user signals for the ATOP adapter parameter bit AtopUserAsId = 1'b1, /// MSB of the ID field of the ATOP adapter - parameter int unsigned AtopAxiUserIdMsb = AxiUserWidth-1, + parameter int unsigned AtopAxiUserIdMsb = AxiCfgJoin.UserWidth-1, /// LSB of the ID field of the ATOP adapter parameter int unsigned AtopAxiUserIdLsb = 0, /// AXI type of the narrow AXI bus @@ -98,14 +88,14 @@ module floo_nw_join #( typedef logic [AxiIdOutWidth-1:0] id_t; typedef logic [AxiIdConvWidth-1:0] id_conv_t; - typedef logic [AxiAddrWidth-1:0] addr_t; - typedef logic [AxiNarrowDataWidth-1:0] narrow_data_t; - typedef logic [AxiNarrowDataWidth/8-1:0] narrow_strb_t; - typedef logic [AxiWideDataWidth-1:0] wide_data_t; - typedef logic [AxiWideDataWidth/8-1:0] wide_strb_t; - typedef logic [AxiNarrowUserInWidth-1:0] narrow_user_t; - typedef logic [AxiWideUserInWidth-1:0] wide_user_t; - typedef logic [AxiUserWidth-1:0] user_t; + typedef logic [AxiCfgJoin.AddrWidth-1:0] addr_t; + typedef logic [AxiCfgN.DataWidth-1:0] narrow_data_t; + typedef logic [AxiCfgN.DataWidth/8-1:0] narrow_strb_t; + typedef logic [AxiCfgW.DataWidth-1:0] wide_data_t; + typedef logic [AxiCfgW.DataWidth/8-1:0] wide_strb_t; + typedef logic [AxiCfgN.UserWidth-1:0] narrow_user_t; + typedef logic [AxiCfgW.UserWidth-1:0] wide_user_t; + typedef logic [AxiCfgJoin.UserWidth-1:0] user_t; `AXI_TYPEDEF_ALL_CT(axi_narrow_iw_conv, axi_narrow_iw_conv_req_t, axi_narrow_iw_conv_rsp_t, addr_t, id_conv_t, narrow_data_t, narrow_strb_t, narrow_user_t) @@ -129,7 +119,7 @@ module floo_nw_join #( if (FilterNarrowAtops) begin : gen_narrow_atop_filter axi_atop_filter #( - .AxiIdWidth ( AxiNarrowIdInWidth ), + .AxiIdWidth ( AxiCfgN.InIdWidth ), .AxiMaxWriteTxns ( AxiNarrowMaxWriteTxns ), .axi_req_t ( axi_narrow_req_t ), .axi_resp_t ( axi_narrow_rsp_t ) @@ -148,7 +138,7 @@ module floo_nw_join #( if (FilterWideAtops) begin : gen_wide_atop_filter axi_atop_filter #( - .AxiIdWidth ( AxiWideIdInWidth ), + .AxiIdWidth ( AxiCfgW.InIdWidth ), .AxiMaxWriteTxns ( AxiWideMaxWriteTxns ), .axi_req_t ( axi_wide_req_t ), .axi_resp_t ( axi_wide_rsp_t ) @@ -175,16 +165,16 @@ module floo_nw_join #( axi_wide_iw_conv_rsp_t axi_wide_rsp_iw_conv; axi_iw_converter #( - .AxiSlvPortIdWidth ( AxiNarrowIdInWidth ), + .AxiSlvPortIdWidth ( AxiCfgN.InIdWidth ), .AxiMstPortIdWidth ( AxiIdConvWidth ), .AxiSlvPortMaxUniqIds ( AxiNarrowSlvPortMaxUniqIds ), .AxiSlvPortMaxTxnsPerId ( AxiNarrowSlvPortMaxTxnsPerId ), .AxiSlvPortMaxTxns ( AxiNarrowSlvPortMaxTxns ), .AxiMstPortMaxUniqIds ( AxiNarrowMstPortMaxUniqIds ), .AxiMstPortMaxTxnsPerId ( AxiNarrowMstPortMaxTxnsPerId ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiNarrowDataWidth ), - .AxiUserWidth ( AxiNarrowUserInWidth ), + .AxiAddrWidth ( AxiCfgJoin.AddrWidth ), + .AxiDataWidth ( AxiCfgN.DataWidth ), + .AxiUserWidth ( AxiCfgN.UserWidth ), .slv_req_t ( axi_narrow_req_t ), .slv_resp_t ( axi_narrow_rsp_t ), .mst_req_t ( axi_narrow_iw_conv_req_t ), @@ -199,16 +189,16 @@ module floo_nw_join #( ); axi_iw_converter #( - .AxiSlvPortIdWidth ( AxiWideIdInWidth ), + .AxiSlvPortIdWidth ( AxiCfgW.InIdWidth ), .AxiMstPortIdWidth ( AxiIdConvWidth ), .AxiSlvPortMaxUniqIds ( AxiWideSlvPortMaxUniqIds ), .AxiSlvPortMaxTxnsPerId ( AxiWideSlvPortMaxTxnsPerId ), .AxiSlvPortMaxTxns ( AxiWideSlvPortMaxTxns ), .AxiMstPortMaxUniqIds ( AxiWideMstPortMaxUniqIds ), .AxiMstPortMaxTxnsPerId ( AxiWideMstPortMaxTxnsPerId ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiWideDataWidth ), - .AxiUserWidth ( AxiWideUserInWidth ), + .AxiAddrWidth ( AxiCfgJoin.AddrWidth ), + .AxiDataWidth ( AxiCfgW.DataWidth ), + .AxiUserWidth ( AxiCfgW.UserWidth ), .slv_req_t ( axi_wide_req_t ), .slv_resp_t ( axi_wide_rsp_t ), .mst_req_t ( axi_wide_iw_conv_req_t ), @@ -231,9 +221,9 @@ module floo_nw_join #( axi_dw_converter #( .AxiMaxReads ( AxiNarrowMaxReadTxns ), - .AxiSlvPortDataWidth ( AxiNarrowDataWidth ), - .AxiMstPortDataWidth ( AxiWideDataWidth ), - .AxiAddrWidth ( AxiAddrWidth ), + .AxiSlvPortDataWidth ( AxiCfgN.DataWidth ), + .AxiMstPortDataWidth ( AxiCfgW.DataWidth ), + .AxiAddrWidth ( AxiCfgJoin.AddrWidth ), .AxiIdWidth ( AxiIdConvWidth ), .aw_chan_t ( axi_narrow_iw_conv_aw_chan_t ), .mst_w_chan_t ( axi_narrow_dw_conv_w_chan_t ), @@ -309,18 +299,18 @@ module floo_nw_join #( axi_out_rsp_t axi_out_rsp_atop; axi_riscv_atomics_structs #( - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiWideDataWidth ), - .AxiIdWidth ( AxiIdOutWidth ), - .AxiUserWidth ( AxiUserWidth ), - .AxiMaxReadTxns ( AxiWideMaxTxns ), - .AxiMaxWriteTxns ( AxiWideMaxWriteTxns ), - .AxiUserAsId ( int'(AtopUserAsId) ), - .AxiUserIdMsb ( AtopAxiUserIdMsb ), - .AxiUserIdLsb ( AtopAxiUserIdLsb ), - .RiscvWordWidth ( AxiNarrowDataWidth ), - .axi_req_t ( axi_out_req_t ), - .axi_rsp_t ( axi_out_rsp_t ) + .AxiAddrWidth ( AxiCfgJoin.AddrWidth ), + .AxiDataWidth ( AxiCfgJoin.DataWidth ), + .AxiIdWidth ( AxiIdOutWidth ), + .AxiUserWidth ( AxiCfgJoin.UserWidth ), + .AxiMaxReadTxns ( AxiWideMaxTxns ), + .AxiMaxWriteTxns ( AxiWideMaxWriteTxns ), + .AxiUserAsId ( int'(AtopUserAsId) ), + .AxiUserIdMsb ( AtopAxiUserIdMsb ), + .AxiUserIdLsb ( AtopAxiUserIdLsb ), + .RiscvWordWidth ( AxiCfgN.DataWidth ), + .axi_req_t ( axi_out_req_t ), + .axi_rsp_t ( axi_out_rsp_t ) ) i_axi_riscv_atomics_structs ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/hw/floo_pkg.sv b/hw/floo_pkg.sv index d9f151c2..dda520d8 100644 --- a/hw/floo_pkg.sv +++ b/hw/floo_pkg.sv @@ -249,6 +249,24 @@ package floo_pkg; return cfg; endfunction + /// Helper function to calculate the maximum of two unsigned integers + function automatic int unsigned max(int unsigned a, int unsigned b); + return (a > b) ? a : b; + endfunction + + /// Returns the AXI config the resulting AXI config when joining a narrow + /// and wide AXI subordinate interfaces. + function automatic axi_cfg_t axi_join_cfg(axi_cfg_t cfg_n, axi_cfg_t cfg_w); + assert (cfg_n.AddrWidth == cfg_w.AddrWidth); + return '{ + AddrWidth: cfg_n.AddrWidth, + DataWidth: max(cfg_n.DataWidth, cfg_w.DataWidth), + UserWidth: max(cfg_n.UserWidth, cfg_w.UserWidth), + InIdWidth: 0, // Not used in `nw_join` + OutIdWidth: max(cfg_n.OutIdWidth, cfg_w.OutIdWidth) + 1 // for the AXI mux + }; + endfunction + /// Returns the number of bits of an AXI channel for a single-AXI config function automatic int unsigned get_axi_chan_width(axi_cfg_t cfg, axi_ch_e ch); case (ch) From ac806e1a45cef9723dfdbe7e0fdebeb301dff63c Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:42:46 +0200 Subject: [PATCH 02/34] sim: Don't show loading messages in vsim --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index ffbd74dc..8d56997f 100644 --- a/Makefile +++ b/Makefile @@ -47,6 +47,7 @@ VSIM_TB_DUT ?= floo_noc_router_test VSIM_FLAGS += -64 VSIM_FLAGS += -t 1ps VSIM_FLAGS += -sv_seed 0 +VSIM_FLAGS += -quiet # Set the job name and directory if specified ifdef JOB_NAME From 4b69104416b1137b6b3401a8e1e6bc18f0897cdb Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:43:23 +0200 Subject: [PATCH 03/34] tb: Add `nw_mesh` testbench with generated NoC --- Bender.yml | 7 + floogen/examples/nw_mesh_xy.yml | 86 ++++++++++ hw/tb/tb_floo_nw_mesh.sv | 246 ++++++++++++++++++++++++++++ hw/tb/wave/tb_floo_nw_mesh.wave.tcl | 31 ++++ 4 files changed, 370 insertions(+) create mode 100644 floogen/examples/nw_mesh_xy.yml create mode 100644 hw/tb/tb_floo_nw_mesh.sv create mode 100644 hw/tb/wave/tb_floo_nw_mesh.wave.tcl diff --git a/Bender.yml b/Bender.yml index e2233570..6c8f04aa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -88,3 +88,10 @@ sources: files: - hw/tb/tb_floo_vc_router.sv - hw/tb/tb_floo_vc_dma_mesh.sv + + - target: all(test, nw_mesh) + include_dirs: + - hw/test/include + files: + - generated/floo_nw_mesh_noc.sv + - hw/tb/tb_floo_nw_mesh.sv diff --git a/floogen/examples/nw_mesh_xy.yml b/floogen/examples/nw_mesh_xy.yml new file mode 100644 index 00000000..2f391d1d --- /dev/null +++ b/floogen/examples/nw_mesh_xy.yml @@ -0,0 +1,86 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: nw_mesh +description: "NW mesh configuration with XY routing for FlooGen" +network_type: "narrow-wide" + +routing: + route_algo: "XY" + use_id_table: true + +protocols: + - name: "narrow_in" + type: "narrow" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 4 + user_width: 1 + - name: "narrow_out" + type: "narrow" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 2 + user_width: 1 + - name: "wide_in" + type: "wide" + protocol: "AXI4" + data_width: 512 + addr_width: 48 + id_width: 3 + user_width: 1 + - name: "wide_out" + type: "wide" + protocol: "AXI4" + data_width: 512 + addr_width: 48 + id_width: 1 + user_width: 1 + +endpoints: + - name: "cluster" + array: [4, 4] + addr_range: + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 + mgr_port_protocol: + - "narrow_in" + - "wide_in" + sbr_port_protocol: + - "narrow_out" + - "wide_out" + - name: "hbm" + array: [4] + addr_range: + base: 0x0000_8000_0000 + size: 0x0000_0001_0000 + sbr_port_protocol: + - "narrow_out" + - "wide_out" + +routers: + - name: "router" + array: [4, 4] + degree: 5 + +connections: + - src: "cluster" + dst: "router" + src_range: + - [0, 3] + - [0, 3] + dst_range: + - [0, 3] + - [0, 3] + dst_dir: "Eject" + - src: "hbm" + dst: "router" + src_range: + - [0, 3] + dst_range: + - [0, 0] + - [0, 3] + dst_dir: "West" diff --git a/hw/tb/tb_floo_nw_mesh.sv b/hw/tb/tb_floo_nw_mesh.sv new file mode 100644 index 00000000..a0d830e4 --- /dev/null +++ b/hw/tb/tb_floo_nw_mesh.sv @@ -0,0 +1,246 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Tim Fischer + +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" + +module tb_floo_nw_mesh; + + import floo_pkg::*; + import floo_nw_mesh_noc_pkg::*; + + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + localparam int unsigned NumX = 4; + localparam int unsigned NumY = 4; + localparam int unsigned NumHBMChannels = NumY; + localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY; + + typedef axi_narrow_in_addr_t addr_t; + localparam int unsigned HBMLatency = 100; + localparam addr_t HBMSize = 48'h10000; // 64KB + localparam addr_t MemSize = HBMSize; + + logic clk, rst_n; + logic [NumX-1:0][NumY-1:0][1:0] end_of_sim; + + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o ( clk ), + .rst_no ( rst_n ) + ); + + ///////////////////// + // Axi Signals // + ///////////////////// + + axi_narrow_in_req_t [NumX-1:0][NumY-1:0] cluster_narrow_in_req; + axi_narrow_in_rsp_t [NumX-1:0][NumY-1:0] cluster_narrow_in_rsp; + axi_narrow_out_req_t [NumX-1:0][NumY-1:0] cluster_narrow_out_req; + axi_narrow_out_rsp_t [NumX-1:0][NumY-1:0] cluster_narrow_out_rsp; + axi_wide_in_req_t [NumX-1:0][NumY-1:0] cluster_wide_in_req; + axi_wide_in_rsp_t [NumX-1:0][NumY-1:0] cluster_wide_in_rsp; + axi_wide_out_req_t [NumX-1:0][NumY-1:0] cluster_wide_out_req; + axi_wide_out_rsp_t [NumX-1:0][NumY-1:0] cluster_wide_out_rsp; + + axi_narrow_out_req_t [NumHBMChannels-1:0] hbm_narrow_req; + axi_narrow_out_rsp_t [NumHBMChannels-1:0] hbm_narrow_rsp; + axi_wide_out_req_t [NumHBMChannels-1:0] hbm_wide_req; + axi_wide_out_rsp_t [NumHBMChannels-1:0] hbm_wide_rsp; + + /////////////////// + // HBM Model // + /////////////////// + + localparam axi_cfg_t AxiCfgJoin = floo_pkg::axi_join_cfg(AxiCfgN, AxiCfgW); + typedef logic [AxiCfgJoin.OutIdWidth-1:0] hbm_id_t; + typedef logic [AxiCfgJoin.UserWidth-1:0] hbm_user_t; + + `AXI_TYPEDEF_ALL_CT(hbm_axi, hbm_axi_req_t, hbm_axi_rsp_t, axi_wide_out_addr_t, hbm_id_t, axi_wide_out_data_t, axi_wide_out_strb_t, hbm_user_t) + + hbm_axi_req_t [NumHBMChannels-1:0] hbm_req; + hbm_axi_rsp_t [NumHBMChannels-1:0] hbm_rsp; + + floo_nw_join #( + .AxiCfgN ( axi_cfg_swap_iw(AxiCfgN) ), + .AxiCfgW ( axi_cfg_swap_iw(AxiCfgW) ), + .AxiCfgJoin ( axi_cfg_swap_iw(AxiCfgJoin) ), + .axi_narrow_req_t ( axi_narrow_out_req_t ), + .axi_narrow_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_req_t ( axi_wide_out_req_t ), + .axi_wide_rsp_t ( axi_wide_out_rsp_t ), + .axi_req_t ( hbm_axi_req_t ), + .axi_rsp_t ( hbm_axi_rsp_t ) + ) i_floo_nw_join [NumHBMChannels-1:0] ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .axi_narrow_req_i ( hbm_narrow_req ), + .axi_narrow_rsp_o ( hbm_narrow_rsp ), + .axi_wide_req_i ( hbm_wide_req ), + .axi_wide_rsp_o ( hbm_wide_rsp ), + .axi_req_o ( hbm_req ), + .axi_rsp_i ( hbm_rsp ) + ); + + floo_hbm_model #( + .TA ( ApplTime ), + .TT ( TestTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .AddrWidth ( AxiCfgJoin.AddrWidth ), + .DataWidth ( AxiCfgJoin.DataWidth ), + .UserWidth ( AxiCfgJoin.UserWidth ), + .IdWidth ( AxiCfgJoin.OutIdWidth ), + .axi_req_t ( hbm_axi_req_t ), + .axi_rsp_t ( hbm_axi_rsp_t ), + .aw_chan_t ( hbm_axi_aw_chan_t ), + .w_chan_t ( hbm_axi_w_chan_t ), + .b_chan_t ( hbm_axi_b_chan_t ), + .ar_chan_t ( hbm_axi_ar_chan_t ), + .r_chan_t ( hbm_axi_r_chan_t ) + ) i_floo_hbm_model [NumHBMChannels-1:0] ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .hbm_req_i ( hbm_req ), + .hbm_rsp_o ( hbm_rsp ) + ); + + //////////////////////// + // DMA Model Mesh // + //////////////////////// + + function automatic addr_t get_base_addr(int unsigned x, int unsigned y); + foreach (Sam[i]) begin + if (Sam[i].idx.x == x && Sam[i].idx.y == y) begin + return Sam[i].start_addr; + end + $error("No base address found for x=%0d, y=%0d", x, y); + end + + endfunction + + for (genvar x = 0; x < NumX; x++) begin : gen_x + for (genvar y = 0; y < NumX; y++) begin : gen_y + localparam string NarrowDmaName = $sformatf("narrow_dma_%0d_%0d", x, y); + localparam string WideDmaName = $sformatf("wide_dma_%0d_%0d", x, y); + + localparam int unsigned Index = y * NumX + x; + localparam addr_t MemBaseAddr = get_base_addr(x+1, y); + + floo_dma_test_node #( + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(AxiCfgN) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 100 + Index ) + ) i_narrow_dma_node ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_in_req_i ( cluster_narrow_out_req[x][y] ), + .axi_in_rsp_o ( cluster_narrow_out_rsp[x][y] ), + .axi_out_req_o ( cluster_narrow_in_req[x][y] ), + .axi_out_rsp_i ( cluster_narrow_in_rsp[x][y] ), + .end_of_sim_o ( end_of_sim[x][y][0] ) + ); + + floo_dma_test_node #( + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(AxiCfgW) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( Index ) + ) i_wide_dma_node ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_in_req_i ( cluster_wide_out_req[x][y] ), + .axi_in_rsp_o ( cluster_wide_out_rsp[x][y] ), + .axi_out_req_o ( cluster_wide_in_req[x][y] ), + .axi_out_rsp_i ( cluster_wide_in_rsp[x][y] ), + .end_of_sim_o ( end_of_sim[x][y][1] ) + ); + + axi_bw_monitor #( + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( AxiCfgN.InIdWidth ), + .Name ( NarrowDmaName ) + ) i_axi_narrow_bw_monitor ( + .clk_i ( clk ), + .en_i ( rst_n ), + .end_of_sim_i ( end_of_sim[x][y][0] ), + .req_i ( cluster_narrow_in_req[x][y] ), + .rsp_i ( cluster_narrow_in_rsp[x][y] ), + .ar_in_flight_o ( ), + .aw_in_flight_o ( ) + ); + + axi_bw_monitor #( + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( AxiCfgW.InIdWidth ), + .Name ( WideDmaName ) + ) i_axi_wide_bw_monitor ( + .clk_i ( clk ), + .en_i ( rst_n ), + .end_of_sim_i ( end_of_sim[x][y][1] ), + .req_i ( cluster_wide_in_req[x][y] ), + .rsp_i ( cluster_wide_in_rsp[x][y] ), + .ar_in_flight_o ( ), + .aw_in_flight_o ( ) + ); + end + end + + + ///////////////////////// + // Network-on-Chip // + ///////////////////////// + + floo_nw_mesh_noc i_floo_nw_mesh_noc ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .cluster_narrow_in_req_i ( cluster_narrow_in_req ), + .cluster_narrow_in_rsp_o ( cluster_narrow_in_rsp ), + .cluster_narrow_out_req_o ( cluster_narrow_out_req ), + .cluster_narrow_out_rsp_i ( cluster_narrow_out_rsp ), + .cluster_wide_in_req_i ( cluster_wide_in_req ), + .cluster_wide_in_rsp_o ( cluster_wide_in_rsp ), + .cluster_wide_out_req_o ( cluster_wide_out_req ), + .cluster_wide_out_rsp_i ( cluster_wide_out_rsp ), + .hbm_narrow_out_req_o ( hbm_narrow_req ), + .hbm_narrow_out_rsp_i ( hbm_narrow_rsp ), + .hbm_wide_out_req_o ( hbm_wide_req ), + .hbm_wide_out_rsp_i ( hbm_wide_rsp ) + ); + + + initial begin + wait(&end_of_sim); + // Wait for some time + repeat (2) @(posedge clk); + // Stop the simulation + $stop; + end + +endmodule diff --git a/hw/tb/wave/tb_floo_nw_mesh.wave.tcl b/hw/tb/wave/tb_floo_nw_mesh.wave.tcl new file mode 100644 index 00000000..40ec0e17 --- /dev/null +++ b/hw/tb/wave/tb_floo_nw_mesh.wave.tcl @@ -0,0 +1,31 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +source hw/tb/wave/wave.tcl + +floo_wave_init + +set tb_name tb_floo_nw_mesh +set noc_name i_floo_nw_mesh_noc + +set routers [find instances -bydu floo_nw_router -nodu] +set num_y [regexp -all {router_0} $routers] +set num_x [expr {[llength $routers] / $num_y}] + +for {set y 0} {$y < $num_y} {incr y} { + for {set x 0} {$x < $num_x} {incr x} { + set groups [list Node X=${x} Y=${y}] + floo_narrow_wide_chimney_wave $tb_name/$noc_name/cluster_ni_${x}_${y} [concat $groups [list Chimney]] + floo_router_wave $tb_name/$noc_name/router_${x}_${y} [concat $groups [list Router]] + + floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_narrow_bw_monitor/*in_flight_o $groups 1 + floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_wide_bw_monitor/*in_flight_o $groups 1 + } +} + +for {set y 0} {$y < $num_y} {incr y} { + floo_narrow_wide_chimney_wave $tb_name/$noc_name/hbm_ni_${y} [list HBM West "Channel ${y}" Chimney] 1 +} + +floo_wave_style From b1584e4192707401bfb0563dc7d7bc9ac86a8f38 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:43:44 +0200 Subject: [PATCH 04/34] floogen(router): Add global id offset to router --- floogen/model/network.py | 2 +- floogen/model/router.py | 8 ++++---- floogen/templates/floo_nw_router.sv.mako | 3 ++- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/floogen/model/network.py b/floogen/model/network.py index f7ede414..e02212a0 100644 --- a/floogen/model/network.py +++ b/floogen/model/network.py @@ -707,7 +707,7 @@ def render_routers(self): """Render the routers in the generated code.""" string = "" for rt in self.graph.get_rt_nodes(): - string += rt.render() + string += rt.render(network=self) return string def render_ni_tables(self): diff --git a/floogen/model/router.py b/floogen/model/router.py index 72675eb0..da7901b8 100644 --- a/floogen/model/router.py +++ b/floogen/model/router.py @@ -81,9 +81,9 @@ class AxiRouter(Router): ) as _tpl_path: _tpl: ClassVar = Template(filename=str(_tpl_path)) - def render(self): + def render(self, **kwargs): """Declare the router in the generated code.""" - return self._tpl.render(router=self) + "\n" + return self._tpl.render(router=self, **kwargs) + "\n" class NarrowWideRouter(Router): """Router class to describe a narrow-wide router""" @@ -93,6 +93,6 @@ class NarrowWideRouter(Router): ) as _tpl_path: _tpl: ClassVar = Template(filename=str(_tpl_path)) - def render(self): + def render(self, **kwargs): """Declare the router in the generated code.""" - return self._tpl.render(router=self) + "\n" + return self._tpl.render(router=self, **kwargs) + "\n" diff --git a/floogen/templates/floo_nw_router.sv.mako b/floogen/templates/floo_nw_router.sv.mako index a274aca8..28f21d5f 100644 --- a/floogen/templates/floo_nw_router.sv.mako +++ b/floogen/templates/floo_nw_router.sv.mako @@ -4,6 +4,7 @@ <% def camelcase(s): return ''.join(x.capitalize() or '_' for x in s.split('_')) %>\ +<% offset_xy_id = router.id - network.routing.id_offset if network.routing.id_offset is not None else router.id %>\ <% req_type = next(d for d in router.incoming if d is not None).req_type %>\ <% rsp_type = next(d for d in router.incoming if d is not None).rsp_type %>\ <% wide_type = next(d for d in router.incoming if d is not None).wide_type %>\ @@ -83,7 +84,7 @@ floo_nw_router #( .rst_ni, .test_enable_i, % if router.route_algo == RouteAlgo.XY: - .id_i (${router.id.render()}), + .id_i (${offset_xy_id.render()}), % else: .id_i ('0), % endif From 44c33cad3cd55e937eccc91e4c5a5400144c6fb6 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:44:05 +0200 Subject: [PATCH 05/34] util(jobs): Start mesh index at (0,0) --- util/gen_jobs.py | 45 +++++++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/util/gen_jobs.py b/util/gen_jobs.py index 11567264..606d262b 100755 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -13,8 +13,7 @@ MEM_SIZE = 2**16 NUM_X = 4 NUM_Y = 4 -XY_ADDR_OFFSET_X = 16 -XY_ADDR_OFFSET_Y = 20 +HBM_BASE_ADDR = 0x80000000 data_widths = {"wide": 512, "narrow": 64} @@ -27,7 +26,12 @@ def clog2(x: int): def get_xy_base_addr(x: int, y: int): """Get the address of a tile in the mesh.""" assert x <= NUM_X+1 and y <= NUM_Y+1 - return (x << XY_ADDR_OFFSET_X) + (y << XY_ADDR_OFFSET_Y) + return (x * NUM_Y + y) * MEM_SIZE + +def get_hbm_base_addr(ch: int): + """Get the address of an HBM channel.""" + assert ch <= NUM_Y+1 + return HBM_BASE_ADDR + (ch << MEM_SIZE) def gen_job_str( @@ -129,8 +133,8 @@ def gen_mesh_traffic( ): # pylint: disable=too-many-arguments, too-many-locals, too-many-branches, too-many-statements """Generate Mesh traffic.""" - for x in range(1, NUM_X + 1): - for y in range(1, NUM_Y + 1): + for x in range(0, NUM_X): + for y in range(0, NUM_Y): wide_jobs = "" narrow_jobs = "" wide_length = wide_burst_length * data_widths["wide"] / 8 @@ -140,25 +144,26 @@ def gen_mesh_traffic( if traffic_type == "hbm": # Tile x=0 are the HBM channels # Each core read from the channel of its y coordinate - ext_addr = get_xy_base_addr(0, y) + ext_addr = get_hbm_base_addr(y) elif traffic_type == "random": ext_addr = local_addr while ext_addr == local_addr: - ext_addr = get_xy_base_addr(random.randint(1, NUM_X), random.randint(1, NUM_Y)) + ext_addr = get_xy_base_addr(random.randint(0, NUM_X+1), random.randint(0, NUM_Y+1)) elif traffic_type == "onehop": - if not (x == 1 and y == 1): + if not (x == 0 and y == 0): wide_length = 0 narrow_length = 0 local_addr = 0 ext_addr = 0 else: ext_addr = get_xy_base_addr(x, y + 1) + elif traffic_type == "bit_complement": - ext_addr = get_xy_base_addr(NUM_X - x + 1, NUM_Y - y + 1) + ext_addr = get_xy_base_addr(NUM_X - x - 1, NUM_Y - y - 1) elif traffic_type == "bit_reverse": # in order to achieve same result as garnet: # change to space where addresses start at 0 and return afterwards - straight = x-1 + (y-1) * NUM_X + straight = x + y * NUM_X num_destinations = NUM_X * NUM_Y reverse = straight & 1 # LSB num_bits = clog2(num_destinations) @@ -166,33 +171,33 @@ def gen_mesh_traffic( reverse <<= 1 straight >>= 1 reverse |= (straight & 1) # LSB - ext_addr = get_xy_base_addr(reverse % NUM_X + 1, reverse // NUM_X + 1) + ext_addr = get_xy_base_addr(reverse % NUM_X, reverse // NUM_X) elif traffic_type == "bit_rotation": - source = x-1 + (y-1) * NUM_X + source = x + y * NUM_X num_destinations = NUM_X * NUM_Y if source % 2 == 0: ext = source // 2 else: # (source % 2 == 1) ext = (source // 2) + (num_destinations // 2) - ext_addr = get_xy_base_addr(ext % NUM_X + 1, ext // NUM_X + 1) + ext_addr = get_xy_base_addr(ext % NUM_X, ext // NUM_X) elif traffic_type == "neighbor": - ext_addr = get_xy_base_addr(x % NUM_X + 1, y) + ext_addr = get_xy_base_addr((x + 1) % NUM_X, y) elif traffic_type == "shuffle": - source = x-1 + (y-1) * NUM_X + source = x + y * NUM_X num_destinations = NUM_X * NUM_Y if source < num_destinations // 2: ext = source * 2 else: ext = (source * 2) - num_destinations + 1 - ext_addr = get_xy_base_addr(ext % NUM_X + 1, ext // NUM_X + 1) + ext_addr = get_xy_base_addr(ext % NUM_X, ext // NUM_X) elif traffic_type == "transpose": dest_x = y dest_y = x ext_addr = get_xy_base_addr(dest_x, dest_y) elif traffic_type == "tornado": - dest_x = (x-1 + math.ceil(NUM_X / 2) - 1) % NUM_X + 1 + dest_x = (x + math.ceil(NUM_X / 2) - 1) % NUM_X ext_addr = get_xy_base_addr(dest_x, y) elif traffic_type == "single_dest_boundary": - ext_addr = get_xy_base_addr(0, NUM_Y//2) + ext_addr = get_hbm_base_addr(NUM_Y//2) elif traffic_type == "single_dest_center": ext_addr = get_xy_base_addr(NUM_X//2, NUM_Y//2) else: @@ -203,8 +208,8 @@ def gen_mesh_traffic( wide_jobs += gen_job_str(wide_length, src_addr, dst_addr) for _ in range(num_narrow_bursts): narrow_jobs += gen_job_str(narrow_length, src_addr, dst_addr) - emit_jobs(wide_jobs, out_dir, "mesh", x + (y - 1) * NUM_X) - emit_jobs(narrow_jobs, out_dir, "mesh", x + (y - 1) * NUM_X + 100) + emit_jobs(wide_jobs, out_dir, "mesh", x + y * NUM_X) + emit_jobs(narrow_jobs, out_dir, "mesh", x + y * NUM_X + 100) def main(): From a6c411df872efefb3594f47be803ada43e5b8ac5 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:44:46 +0200 Subject: [PATCH 06/34] ci: Try to generate with floogen and run traffic on `nw_mesh` --- .gitlab-ci.yml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c5c83ce8..02349acb 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -7,6 +7,7 @@ variables: VSIM: questa-2023.4 vsim BENDER: bender + PYTHON: /usr/local/anaconda3/bin/python stages: - init @@ -65,15 +66,19 @@ run-traffic: JOB_NAME: mesh parallel: matrix: - - VSIM_TB_DUT: [tb_floo_dma_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses + - DUT: [nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses + ROUTE_ALGO: [xy] TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] TRAFFIC_RW: [read, write] needs: - collect-bender-sources - - compile-vsim script: + # Install FlooGen + - $PYTHON -m pip install . + - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated + - make compile-sim BENDER_FLAGS="-t ${DUT}" - make jobs - - make run-sim-batch | tee vsim.log 2>&1 + - make run-sim-batch VSIM_TB_DUT=${tb_floo_${DUT}} | tee vsim.log 2>&1 - 'grep "Errors: 0," vsim.log' morty: From e7706369c8985370cdf2705cc6e8815bf7cc992e Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:48:40 +0200 Subject: [PATCH 07/34] ci: Try with venv --- .gitlab-ci.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 02349acb..b574ff81 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -73,8 +73,9 @@ run-traffic: needs: - collect-bender-sources script: - # Install FlooGen - - $PYTHON -m pip install . + - $PYTHON -m venv .venv + - source .venv/bin/activate + - pip install . - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated - make compile-sim BENDER_FLAGS="-t ${DUT}" - make jobs From 996f715831d9c347c019fa7d1345da7f94a6a9f9 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:51:57 +0200 Subject: [PATCH 08/34] ci: Don't format generated sources with verible --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b574ff81..9f1037ce 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -76,7 +76,7 @@ run-traffic: - $PYTHON -m venv .venv - source .venv/bin/activate - pip install . - - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated + - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format - make compile-sim BENDER_FLAGS="-t ${DUT}" - make jobs - make run-sim-batch VSIM_TB_DUT=${tb_floo_${DUT}} | tee vsim.log 2>&1 From 6af9e0d6475079655848235a02a772ee5fc41a54 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 10:54:49 +0200 Subject: [PATCH 09/34] ci: Small fix --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9f1037ce..13e19308 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -79,7 +79,7 @@ run-traffic: - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format - make compile-sim BENDER_FLAGS="-t ${DUT}" - make jobs - - make run-sim-batch VSIM_TB_DUT=${tb_floo_${DUT}} | tee vsim.log 2>&1 + - make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} | tee vsim.log 2>&1 - 'grep "Errors: 0," vsim.log' morty: From f08fbb10791d8319e00d6132e9bd61bd43e65fae Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 11:06:09 +0200 Subject: [PATCH 10/34] make: Use `EXTRA_BENDER_FLAGS` to add additional bender targets from outside --- .gitlab-ci.yml | 6 ++++-- Makefile | 4 +--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 13e19308..9ba05979 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,8 +25,10 @@ collect-bender-sources: compile-vsim: stage: build + variables: + EXTRA_BENDER_FLAGS: "-t vc_router" script: - - make compile-sim VC=true | tee compile.log 2>&1 + - make compile-sim | tee compile.log 2>&1 - '! grep "\*\* Error" compile.log' needs: - collect-bender-sources @@ -77,7 +79,7 @@ run-traffic: - source .venv/bin/activate - pip install . - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format - - make compile-sim BENDER_FLAGS="-t ${DUT}" + - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" - make jobs - make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} | tee vsim.log 2>&1 - 'grep "Errors: 0," vsim.log' diff --git a/Makefile b/Makefile index 8d56997f..c5116deb 100644 --- a/Makefile +++ b/Makefile @@ -33,9 +33,7 @@ BENDER_FLAGS += -t rtl BENDER_FLAGS += -t test BENDER_FLAGS += -t snitch_cluster BENDER_FLAGS += -t idma_test -ifdef VC - BENDER_FLAGS += -t vc_router -endif +BENDER_FLAGS := $(BENDER_FLAGS) $(EXTRA_BENDER_FLAGS) VLOG_ARGS += -suppress vlog-2583 VLOG_ARGS += -suppress vlog-13314 From 10f563622beac4dddec10ab196f63ca05536fcf1 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 11:22:23 +0200 Subject: [PATCH 11/34] util(jobs): Fix `random` coordinate range --- util/gen_jobs.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/gen_jobs.py b/util/gen_jobs.py index 606d262b..8ba7ff89 100755 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -148,7 +148,7 @@ def gen_mesh_traffic( elif traffic_type == "random": ext_addr = local_addr while ext_addr == local_addr: - ext_addr = get_xy_base_addr(random.randint(0, NUM_X+1), random.randint(0, NUM_Y+1)) + ext_addr = get_xy_base_addr(random.randint(0, NUM_X-1), random.randint(0, NUM_Y-1)) elif traffic_type == "onehop": if not (x == 0 and y == 0): wide_length = 0 From 40debc6d9acde4cf6bc849737510979c554b2f57 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 11:36:38 +0200 Subject: [PATCH 12/34] ci: Install FlooGen in earlier stage --- .gitlab-ci.yml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9ba05979..dd764c64 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -38,6 +38,16 @@ compile-vsim: - work/ - modelsim.ini +install-floogen: + stage: build + script: + - $PYTHON -m venv .venv + - source .venv/bin/activate + - pip install . + artifacts: + paths: + - .venv/ + run-vsim: stage: run script: @@ -74,10 +84,9 @@ run-traffic: TRAFFIC_RW: [read, write] needs: - collect-bender-sources + - install-floogen script: - - $PYTHON -m venv .venv - source .venv/bin/activate - - pip install . - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" - make jobs From 7a44afa2ae5a38860987cdf81cc48e163c5dd3ee Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 11:36:48 +0200 Subject: [PATCH 13/34] ci: Remove `noci` rule --- .gitlab-ci.yml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index dd764c64..e602d38d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -67,10 +67,6 @@ run-vsim: needs: - collect-bender-sources - compile-vsim - rules: - - if: '$CI_COMMIT_REF_NAME =~ /noci$/' - when: manual - - when: always run-traffic: stage: run From 9a90fa26d67d225ab97ddd28b81d017cbd85a750 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 11:40:41 +0200 Subject: [PATCH 14/34] ci: Debug --- .gitlab-ci.yml | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e602d38d..985737e8 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -38,16 +38,6 @@ compile-vsim: - work/ - modelsim.ini -install-floogen: - stage: build - script: - - $PYTHON -m venv .venv - - source .venv/bin/activate - - pip install . - artifacts: - paths: - - .venv/ - run-vsim: stage: run script: @@ -80,13 +70,18 @@ run-traffic: TRAFFIC_RW: [read, write] needs: - collect-bender-sources - - install-floogen script: + # Install `floogen` + - $PYTHON -m venv .venv - source .venv/bin/activate + - pip install . + # Generate sources - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format - - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" - make jobs + # Compile and run the simulation + - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" - make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} | tee vsim.log 2>&1 + # Check for errors - 'grep "Errors: 0," vsim.log' morty: From c558b2bba164149f02e6f1a5d05252d88de2849c Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:12:23 +0200 Subject: [PATCH 15/34] floogen(pkg): Also print endpoint enum for XY routing and sort system address map --- floogen/model/network.py | 8 ++++++-- floogen/templates/floo_top_noc.sv.mako | 2 -- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/floogen/model/network.py b/floogen/model/network.py index e02212a0..01eca474 100644 --- a/floogen/model/network.py +++ b/floogen/model/network.py @@ -642,7 +642,7 @@ def gen_sam(self): """Generate the system address map, which is used by the network interfaces to determine the destination of a packet based on the address.""" addr_table = [] - ni_sbr_nodes = [ni for ni in self.graph.get_ni_nodes() if ni.is_sbr()] + ni_sbr_nodes = reversed([ni for ni in self.graph.get_ni_nodes() if ni.is_sbr()]) for ni in ni_sbr_nodes: dest = ni.id if self.routing.id_offset is not None: @@ -735,7 +735,11 @@ def render_nis(self): def render_ep_enum(self): """Render the endpoint enum in the generated code.""" - fields_dict = {ep.name: ep.id.id for ep in self.graph.get_ni_nodes()} + match self.routing.route_algo: + case RouteAlgo.XY: + fields_dict = {ep.name: i for i, ep in enumerate(self.graph.get_ni_nodes())} + case RouteAlgo.ID | RouteAlgo.SRC: + fields_dict = {ep.name: ep.id.id for ep in self.graph.get_ni_nodes()} fields_dict = dict(sorted(fields_dict.items(), key=lambda item: item[1])) fields_dict["num_endpoints"] = len(fields_dict) return sv_enum_typedef(name="ep_id_e", fields_dict=fields_dict) diff --git a/floogen/templates/floo_top_noc.sv.mako b/floogen/templates/floo_top_noc.sv.mako index 053e06f5..31e68099 100644 --- a/floogen/templates/floo_top_noc.sv.mako +++ b/floogen/templates/floo_top_noc.sv.mako @@ -18,9 +18,7 @@ package floo_${noc.name}_noc_pkg; // Address Map // ///////////////////// -% if noc.routing.route_algo.value != "XYRouting": ${noc.render_ep_enum()} -% endif ${noc.routing.render_typedefs()} From 9f1a90ea1ad1e8adca4c7a91a29639b57205a852 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:13:03 +0200 Subject: [PATCH 16/34] test: Use correct x,y increments --- hw/tb/tb_floo_nw_mesh.sv | 2 +- util/gen_jobs.py | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/tb/tb_floo_nw_mesh.sv b/hw/tb/tb_floo_nw_mesh.sv index a0d830e4..1bb65e37 100644 --- a/hw/tb/tb_floo_nw_mesh.sv +++ b/hw/tb/tb_floo_nw_mesh.sv @@ -132,8 +132,8 @@ module tb_floo_nw_mesh; localparam string NarrowDmaName = $sformatf("narrow_dma_%0d_%0d", x, y); localparam string WideDmaName = $sformatf("wide_dma_%0d_%0d", x, y); - localparam int unsigned Index = y * NumX + x; localparam addr_t MemBaseAddr = get_base_addr(x+1, y); + localparam int unsigned Index = x * NumX + y; floo_dma_test_node #( .TA ( ApplTime ), diff --git a/util/gen_jobs.py b/util/gen_jobs.py index 8ba7ff89..f0491f19 100755 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -163,7 +163,7 @@ def gen_mesh_traffic( elif traffic_type == "bit_reverse": # in order to achieve same result as garnet: # change to space where addresses start at 0 and return afterwards - straight = x + y * NUM_X + straight = x * NUM_Y + y num_destinations = NUM_X * NUM_Y reverse = straight & 1 # LSB num_bits = clog2(num_destinations) @@ -173,7 +173,7 @@ def gen_mesh_traffic( reverse |= (straight & 1) # LSB ext_addr = get_xy_base_addr(reverse % NUM_X, reverse // NUM_X) elif traffic_type == "bit_rotation": - source = x + y * NUM_X + source = x * NUM_Y + y num_destinations = NUM_X * NUM_Y if source % 2 == 0: ext = source // 2 @@ -183,7 +183,7 @@ def gen_mesh_traffic( elif traffic_type == "neighbor": ext_addr = get_xy_base_addr((x + 1) % NUM_X, y) elif traffic_type == "shuffle": - source = x + y * NUM_X + source = x * NUM_Y + y num_destinations = NUM_X * NUM_Y if source < num_destinations // 2: ext = source * 2 @@ -208,8 +208,8 @@ def gen_mesh_traffic( wide_jobs += gen_job_str(wide_length, src_addr, dst_addr) for _ in range(num_narrow_bursts): narrow_jobs += gen_job_str(narrow_length, src_addr, dst_addr) - emit_jobs(wide_jobs, out_dir, "mesh", x + y * NUM_X) - emit_jobs(narrow_jobs, out_dir, "mesh", x + y * NUM_X + 100) + emit_jobs(wide_jobs, out_dir, "mesh", x * NUM_Y + y) + emit_jobs(narrow_jobs, out_dir, "mesh", x * NUM_Y + y + 100) def main(): From e7e5e08867d58c2d446e471a239fb01f2c361f41 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:13:36 +0200 Subject: [PATCH 17/34] tb: Index directly into system address map --- hw/tb/tb_floo_nw_mesh.sv | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/hw/tb/tb_floo_nw_mesh.sv b/hw/tb/tb_floo_nw_mesh.sv index 1bb65e37..00e7cb3d 100644 --- a/hw/tb/tb_floo_nw_mesh.sv +++ b/hw/tb/tb_floo_nw_mesh.sv @@ -117,23 +117,13 @@ module tb_floo_nw_mesh; // DMA Model Mesh // //////////////////////// - function automatic addr_t get_base_addr(int unsigned x, int unsigned y); - foreach (Sam[i]) begin - if (Sam[i].idx.x == x && Sam[i].idx.y == y) begin - return Sam[i].start_addr; - end - $error("No base address found for x=%0d, y=%0d", x, y); - end - - endfunction - for (genvar x = 0; x < NumX; x++) begin : gen_x for (genvar y = 0; y < NumX; y++) begin : gen_y localparam string NarrowDmaName = $sformatf("narrow_dma_%0d_%0d", x, y); localparam string WideDmaName = $sformatf("wide_dma_%0d_%0d", x, y); - localparam addr_t MemBaseAddr = get_base_addr(x+1, y); localparam int unsigned Index = x * NumX + y; + localparam addr_t MemBaseAddr = Sam[ClusterNi00+Index].start_addr; floo_dma_test_node #( .TA ( ApplTime ), From 9970724a52a2eae3555bb29b5f7022e9da6cb95f Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:20:50 +0200 Subject: [PATCH 18/34] ci: Add `src` and `id` test for `nw_mesh` --- .gitlab-ci.yml | 2 +- floogen/examples/nw_mesh_id.yml | 86 ++++++++++++++++++++++++++++++++ floogen/examples/nw_mesh_src.yml | 86 ++++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 floogen/examples/nw_mesh_id.yml create mode 100644 floogen/examples/nw_mesh_src.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 985737e8..faebe0c8 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -65,7 +65,7 @@ run-traffic: parallel: matrix: - DUT: [nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses - ROUTE_ALGO: [xy] + ROUTE_ALGO: [xy, src, id] TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] TRAFFIC_RW: [read, write] needs: diff --git a/floogen/examples/nw_mesh_id.yml b/floogen/examples/nw_mesh_id.yml new file mode 100644 index 00000000..209604c9 --- /dev/null +++ b/floogen/examples/nw_mesh_id.yml @@ -0,0 +1,86 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: nw_mesh +description: "NW mesh configuration with table-based routing for FlooGen" +network_type: "narrow-wide" + +routing: + route_algo: "ID" + use_id_table: true + +protocols: + - name: "narrow_in" + type: "narrow" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 4 + user_width: 1 + - name: "narrow_out" + type: "narrow" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 2 + user_width: 1 + - name: "wide_in" + type: "wide" + protocol: "AXI4" + data_width: 512 + addr_width: 48 + id_width: 3 + user_width: 1 + - name: "wide_out" + type: "wide" + protocol: "AXI4" + data_width: 512 + addr_width: 48 + id_width: 1 + user_width: 1 + +endpoints: + - name: "cluster" + array: [4, 4] + addr_range: + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 + mgr_port_protocol: + - "narrow_in" + - "wide_in" + sbr_port_protocol: + - "narrow_out" + - "wide_out" + - name: "hbm" + array: [4] + addr_range: + base: 0x0000_8000_0000 + size: 0x0000_0001_0000 + sbr_port_protocol: + - "narrow_out" + - "wide_out" + +routers: + - name: "router" + array: [4, 4] + degree: 5 + +connections: + - src: "cluster" + dst: "router" + src_range: + - [0, 3] + - [0, 3] + dst_range: + - [0, 3] + - [0, 3] + dst_dir: "Eject" + - src: "hbm" + dst: "router" + src_range: + - [0, 3] + dst_range: + - [0, 0] + - [0, 3] + dst_dir: "West" diff --git a/floogen/examples/nw_mesh_src.yml b/floogen/examples/nw_mesh_src.yml new file mode 100644 index 00000000..4d93ea51 --- /dev/null +++ b/floogen/examples/nw_mesh_src.yml @@ -0,0 +1,86 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: nw_mesh +description: "NW mesh configuration with source-based routing for FlooGen" +network_type: "narrow-wide" + +routing: + route_algo: "SRC" + use_id_table: true + +protocols: + - name: "narrow_in" + type: "narrow" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 4 + user_width: 1 + - name: "narrow_out" + type: "narrow" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 2 + user_width: 1 + - name: "wide_in" + type: "wide" + protocol: "AXI4" + data_width: 512 + addr_width: 48 + id_width: 3 + user_width: 1 + - name: "wide_out" + type: "wide" + protocol: "AXI4" + data_width: 512 + addr_width: 48 + id_width: 1 + user_width: 1 + +endpoints: + - name: "cluster" + array: [4, 4] + addr_range: + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 + mgr_port_protocol: + - "narrow_in" + - "wide_in" + sbr_port_protocol: + - "narrow_out" + - "wide_out" + - name: "hbm" + array: [4] + addr_range: + base: 0x0000_8000_0000 + size: 0x0000_0001_0000 + sbr_port_protocol: + - "narrow_out" + - "wide_out" + +routers: + - name: "router" + array: [4, 4] + degree: 5 + +connections: + - src: "cluster" + dst: "router" + src_range: + - [0, 3] + - [0, 3] + dst_range: + - [0, 3] + - [0, 3] + dst_dir: "Eject" + - src: "hbm" + dst: "router" + src_range: + - [0, 3] + dst_range: + - [0, 0] + - [0, 3] + dst_dir: "West" From 47aa75e092129df24c6021aa022acfef66bd1a60 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:30:14 +0200 Subject: [PATCH 19/34] floogen(examples): Align `axi_mesh` exampels --- floogen/examples/axi_mesh_id.yml | 20 ++++---------------- floogen/examples/axi_mesh_src.yml | 20 ++++---------------- floogen/examples/axi_mesh_xy.yml | 20 ++++---------------- 3 files changed, 12 insertions(+), 48 deletions(-) diff --git a/floogen/examples/axi_mesh_id.yml b/floogen/examples/axi_mesh_id.yml index 39c0b436..60afbffc 100644 --- a/floogen/examples/axi_mesh_id.yml +++ b/floogen/examples/axi_mesh_id.yml @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 name: axi_mesh -description: "AXI mesh configuration for FlooGen" +description: "AXI mesh configuration with table-based routing for FlooGen" network_type: "axi" routing: @@ -30,8 +30,8 @@ endpoints: - name: "cluster" array: [4, 4] addr_range: - base: 0x0000_1000_0000 - size: 0x0000_0004_0000 + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 mgr_port_protocol: - "axi_in" sbr_port_protocol: @@ -40,15 +40,7 @@ endpoints: array: [4] addr_range: base: 0x0000_8000_0000 - size: 0x0000_4000_0000 - sbr_port_protocol: - - "axi_out" - - name: "peripherals" - addr_range: - start: 0x0000_0000_0000 - end: 0x0000_0fff_ffff - mgr_port_protocol: - - "axi_in" + size: 0x0000_0001_0000 sbr_port_protocol: - "axi_out" @@ -75,7 +67,3 @@ connections: - [0, 0] - [0, 3] dst_dir: "West" - - src: "peripherals" - dst: "router" - dst_idx: [1, 3] - dst_dir: "North" diff --git a/floogen/examples/axi_mesh_src.yml b/floogen/examples/axi_mesh_src.yml index 5213032b..bf01610b 100644 --- a/floogen/examples/axi_mesh_src.yml +++ b/floogen/examples/axi_mesh_src.yml @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 name: axi_mesh -description: "AXI mesh configuration for FlooGen" +description: "AXI mesh configuration with source-based routing for FlooGen" network_type: "axi" routing: @@ -30,8 +30,8 @@ endpoints: - name: "cluster" array: [4, 4] addr_range: - base: 0x0000_1000_0000 - size: 0x0000_0004_0000 + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 mgr_port_protocol: - "axi_in" sbr_port_protocol: @@ -40,15 +40,7 @@ endpoints: array: [4] addr_range: base: 0x0000_8000_0000 - size: 0x0000_4000_0000 - sbr_port_protocol: - - "axi_out" - - name: "peripherals" - addr_range: - start: 0x0000_0000_0000 - end: 0x0000_0fff_ffff - mgr_port_protocol: - - "axi_in" + size: 0x0000_0001_0000 sbr_port_protocol: - "axi_out" @@ -75,7 +67,3 @@ connections: - [0, 0] - [0, 3] dst_dir: "West" - - src: "peripherals" - dst: "router" - dst_idx: [1, 3] - dst_dir: "North" diff --git a/floogen/examples/axi_mesh_xy.yml b/floogen/examples/axi_mesh_xy.yml index 7a8cd32c..f0bfb5d8 100644 --- a/floogen/examples/axi_mesh_xy.yml +++ b/floogen/examples/axi_mesh_xy.yml @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 name: axi_mesh -description: "AXI mesh configuration for FlooGen" +description: "AXI mesh configuration with XY routing for FlooGen" network_type: "axi" routing: @@ -30,8 +30,8 @@ endpoints: - name: "cluster" array: [4, 4] addr_range: - base: 0x0000_1000_0000 - size: 0x0000_0004_0000 + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 mgr_port_protocol: - "axi_in" sbr_port_protocol: @@ -40,15 +40,7 @@ endpoints: array: [4] addr_range: base: 0x0000_8000_0000 - size: 0x0000_4000_0000 - sbr_port_protocol: - - "axi_out" - - name: "peripherals" - addr_range: - start: 0x0000_0000_0000 - end: 0x0000_0fff_ffff - mgr_port_protocol: - - "axi_in" + size: 0x0000_0001_0000 sbr_port_protocol: - "axi_out" @@ -75,7 +67,3 @@ connections: - [0, 0] - [0, 3] dst_dir: "West" - - src: "peripherals" - dst: "router" - dst_idx: [1, 3] - dst_dir: "North" From 372f168f6ec98594014e35ab6fe3aa8015e8706d Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:52:05 +0200 Subject: [PATCH 20/34] floogen(routing): Use correct `axi_ch` type for single-AXI networks --- floogen/model/routing.py | 7 ++++--- floogen/templates/floo_top_noc.sv.mako | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/floogen/model/routing.py b/floogen/model/routing.py index ef717b49..a0370b0e 100644 --- a/floogen/model/routing.py +++ b/floogen/model/routing.py @@ -512,14 +512,15 @@ def render_typedefs(self) -> str: string += sv_typedef("vc_id_t", array_size=self.num_vc_id_bits) return string - def render_hdr_typedef(self) -> str: + def render_hdr_typedef(self, network_type) -> str: """Render the SystemVerilog flit header.""" dst_type = "route_t" if self.route_algo == RouteAlgo.SRC else "id_t" + ch_type = "axi_ch_e" if network_type == "axi" else "nw_ch_e" if self.num_vc_id_bits == 0: - return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, nw_ch_e, rob_idx_t)" - return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, vc_id_t, nw_ch_e, rob_idx_t, vc_id_t)" + return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t)" + return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, vc_id_t, {ch_type}, rob_idx_t, vc_id_t)" def render_route_cfg(self, name) -> str: """Render the SystemVerilog routing configuration.""" diff --git a/floogen/templates/floo_top_noc.sv.mako b/floogen/templates/floo_top_noc.sv.mako index 31e68099..15feb642 100644 --- a/floogen/templates/floo_top_noc.sv.mako +++ b/floogen/templates/floo_top_noc.sv.mako @@ -40,7 +40,7 @@ package floo_${noc.name}_noc_pkg; ${prot.render_typedefs()} % endfor - ${noc.routing.render_hdr_typedef()} + ${noc.routing.render_hdr_typedef(network_type=noc.network_type)} ${noc.render_link_typedefs()} endpackage From 00650ef72119fae52f3457c3bd9dea269078b3c1 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:52:37 +0200 Subject: [PATCH 21/34] floogen(tpl): Fix xy id offset in `axi_router` --- floogen/templates/floo_axi_router.sv.mako | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/floogen/templates/floo_axi_router.sv.mako b/floogen/templates/floo_axi_router.sv.mako index 4d46ef8e..be082255 100644 --- a/floogen/templates/floo_axi_router.sv.mako +++ b/floogen/templates/floo_axi_router.sv.mako @@ -4,6 +4,7 @@ <% def camelcase(s): return ''.join(x.capitalize() or '_' for x in s.split('_')) %>\ +<% offset_xy_id = router.id - network.routing.id_offset if network.routing.id_offset is not None else router.id %>\ <% req_type = next(d for d in router.incoming if d is not None).req_type %>\ <% rsp_type = next(d for d in router.incoming if d is not None).rsp_type %>\ % if router.route_algo == RouteAlgo.ID: @@ -64,7 +65,7 @@ floo_axi_router #( .rst_ni, .test_enable_i, % if router.route_algo == RouteAlgo.XY: - .id_i (${router.id.render()}), + .id_i (${offset_xy_id.render()}), % else: .id_i ('0), % endif From d7f8f4729e92f2a4f87b6217c122e14c6cb2a117 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:53:29 +0200 Subject: [PATCH 22/34] waves: Rename `narrow_wide` to `nw` in wave scripts --- hw/tb/wave/tb_floo_dma_mesh.wave.tcl | 10 +++++----- hw/tb/wave/tb_floo_nw_chimney.wave.tcl | 2 +- hw/tb/wave/tb_floo_nw_mesh.wave.tcl | 4 ++-- hw/tb/wave/wave.tcl | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/tb/wave/tb_floo_dma_mesh.wave.tcl b/hw/tb/wave/tb_floo_dma_mesh.wave.tcl index 6d57341d..ae48a561 100644 --- a/hw/tb/wave/tb_floo_dma_mesh.wave.tcl +++ b/hw/tb/wave/tb_floo_dma_mesh.wave.tcl @@ -15,7 +15,7 @@ set num_x [regexp -all {y\[0\]} $routers] for {set y 0} {$y < $num_y} {incr y} { for {set x 0} {$x < $num_x} {incr x} { set groups [list Node X=${x} Y=${y}] - floo_narrow_wide_chimney_wave $tb_name/gen_x[$x]/gen_y[$y]/i_dma_chimney [concat $groups [list Chimney]] + floo_nw_chimney_wave $tb_name/gen_x[$x]/gen_y[$y]/i_dma_chimney [concat $groups [list Chimney]] floo_router_wave $tb_name/gen_x[$x]/gen_y[$y]/i_router [concat $groups [list Router]] floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_narrow_bw_monitor/*in_flight_o $groups 1 @@ -25,17 +25,17 @@ for {set y 0} {$y < $num_y} {incr y} { for {set y 0} {$y < $num_y} {incr y} { # East - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] 1 + floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] 1 # West - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] 1 + floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] 1 } for {set x 0} {$x < $num_x} {incr x} { # North - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[0]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] 1 + floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[0]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] 1 # South - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] 1 + floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] 1 } floo_wave_style diff --git a/hw/tb/wave/tb_floo_nw_chimney.wave.tcl b/hw/tb/wave/tb_floo_nw_chimney.wave.tcl index 5f2f6294..e1abe9e5 100644 --- a/hw/tb/wave/tb_floo_nw_chimney.wave.tcl +++ b/hw/tb/wave/tb_floo_nw_chimney.wave.tcl @@ -8,7 +8,7 @@ floo_wave_init for {set i 0} {$i < 2} {incr i} { set name [list "Chimney $i"] - floo_narrow_wide_chimney_wave tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i} $name + floo_nw_chimney_wave tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i} $name } floo_wave_style diff --git a/hw/tb/wave/tb_floo_nw_mesh.wave.tcl b/hw/tb/wave/tb_floo_nw_mesh.wave.tcl index 40ec0e17..84dbe5a6 100644 --- a/hw/tb/wave/tb_floo_nw_mesh.wave.tcl +++ b/hw/tb/wave/tb_floo_nw_mesh.wave.tcl @@ -16,7 +16,7 @@ set num_x [expr {[llength $routers] / $num_y}] for {set y 0} {$y < $num_y} {incr y} { for {set x 0} {$x < $num_x} {incr x} { set groups [list Node X=${x} Y=${y}] - floo_narrow_wide_chimney_wave $tb_name/$noc_name/cluster_ni_${x}_${y} [concat $groups [list Chimney]] + floo_nw_chimney_wave $tb_name/$noc_name/cluster_ni_${x}_${y} [concat $groups [list Chimney]] floo_router_wave $tb_name/$noc_name/router_${x}_${y} [concat $groups [list Router]] floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_narrow_bw_monitor/*in_flight_o $groups 1 @@ -25,7 +25,7 @@ for {set y 0} {$y < $num_y} {incr y} { } for {set y 0} {$y < $num_y} {incr y} { - floo_narrow_wide_chimney_wave $tb_name/$noc_name/hbm_ni_${y} [list HBM West "Channel ${y}" Chimney] 1 + floo_nw_chimney_wave $tb_name/$noc_name/hbm_ni_${y} [list HBM West "Channel ${y}" Chimney] 1 } floo_wave_style diff --git a/hw/tb/wave/wave.tcl b/hw/tb/wave/wave.tcl index 96066db0..0ed53633 100644 --- a/hw/tb/wave/wave.tcl +++ b/hw/tb/wave/wave.tcl @@ -102,7 +102,7 @@ proc floo_axi_chimney_wave {dut groups {expand 1}} { } } -proc floo_narrow_wide_chimney_wave {dut groups {expand 1}} { +proc floo_nw_chimney_wave {dut groups {expand 1}} { floo_add_wave $dut/* $groups 1 $expand From 04bf7437d26de2e8d8b7055ebe2a6ba16928239e Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:53:50 +0200 Subject: [PATCH 23/34] test: Add `axi_mesh` testbench --- Bender.yml | 7 ++ hw/tb/tb_floo_axi_mesh.sv | 155 +++++++++++++++++++++++++++ hw/tb/wave/tb_floo_axi_mesh.wave.tcl | 30 ++++++ 3 files changed, 192 insertions(+) create mode 100644 hw/tb/tb_floo_axi_mesh.sv create mode 100644 hw/tb/wave/tb_floo_axi_mesh.wave.tcl diff --git a/Bender.yml b/Bender.yml index 6c8f04aa..63c1b539 100644 --- a/Bender.yml +++ b/Bender.yml @@ -89,6 +89,13 @@ sources: - hw/tb/tb_floo_vc_router.sv - hw/tb/tb_floo_vc_dma_mesh.sv + - target: all(test, axi_mesh) + include_dirs: + - hw/test/include + files: + - generated/floo_axi_mesh_noc.sv + - hw/tb/tb_floo_axi_mesh.sv + - target: all(test, nw_mesh) include_dirs: - hw/test/include diff --git a/hw/tb/tb_floo_axi_mesh.sv b/hw/tb/tb_floo_axi_mesh.sv new file mode 100644 index 00000000..d0705b39 --- /dev/null +++ b/hw/tb/tb_floo_axi_mesh.sv @@ -0,0 +1,155 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Tim Fischer + +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" + +module tb_floo_axi_mesh; + + import floo_pkg::*; + import floo_axi_mesh_noc_pkg::*; + + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + localparam int unsigned NumX = 4; + localparam int unsigned NumY = 4; + localparam int unsigned NumHBMChannels = NumY; + localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY; + + typedef axi_in_addr_t addr_t; + localparam int unsigned HBMLatency = 100; + localparam addr_t HBMSize = 48'h10000; // 64KB + localparam addr_t MemSize = HBMSize; + + logic clk, rst_n; + logic [NumX-1:0][NumY-1:0] end_of_sim; + + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o ( clk ), + .rst_no ( rst_n ) + ); + + ///////////////////// + // Axi Signals // + ///////////////////// + + axi_in_req_t [NumX-1:0][NumY-1:0] cluster_in_req; + axi_in_rsp_t [NumX-1:0][NumY-1:0] cluster_in_rsp; + axi_out_req_t [NumX-1:0][NumY-1:0] cluster_out_req; + axi_out_rsp_t [NumX-1:0][NumY-1:0] cluster_out_rsp; + + axi_out_req_t [NumHBMChannels-1:0] hbm_req; + axi_out_rsp_t [NumHBMChannels-1:0] hbm_rsp; + + /////////////////// + // HBM Model // + /////////////////// + + floo_hbm_model #( + .TA ( ApplTime ), + .TT ( TestTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .AddrWidth ( AxiCfg.AddrWidth ), + .DataWidth ( AxiCfg.DataWidth ), + .UserWidth ( AxiCfg.UserWidth ), + .IdWidth ( AxiCfg.OutIdWidth ), + .axi_req_t ( axi_out_req_t ), + .axi_rsp_t ( axi_out_rsp_t ), + .aw_chan_t ( axi_out_aw_chan_t ), + .w_chan_t ( axi_out_w_chan_t ), + .b_chan_t ( axi_out_b_chan_t ), + .ar_chan_t ( axi_out_ar_chan_t ), + .r_chan_t ( axi_out_r_chan_t ) + ) i_floo_hbm_model [NumHBMChannels-1:0] ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .hbm_req_i ( hbm_req ), + .hbm_rsp_o ( hbm_rsp ) + ); + + //////////////////////// + // DMA Model Mesh // + //////////////////////// + + for (genvar x = 0; x < NumX; x++) begin : gen_x + for (genvar y = 0; y < NumX; y++) begin : gen_y + localparam string DmaName = $sformatf("dma_%0d_%0d", x, y); + + localparam int unsigned Index = x * NumX + y; + localparam addr_t MemBaseAddr = Sam[ClusterNi00+Index].start_addr; + + floo_dma_test_node #( + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(AxiCfg) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_out_req_t ), + .axi_in_rsp_t ( axi_out_rsp_t ), + .axi_out_req_t ( axi_in_req_t ), + .axi_out_rsp_t ( axi_in_rsp_t ), + .JobId ( Index ) + ) i_dma_node ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_in_req_i ( cluster_out_req[x][y] ), + .axi_in_rsp_o ( cluster_out_rsp[x][y] ), + .axi_out_req_o ( cluster_in_req[x][y] ), + .axi_out_rsp_i ( cluster_in_rsp[x][y] ), + .end_of_sim_o ( end_of_sim[x][y] ) + ); + + axi_bw_monitor #( + .req_t ( axi_in_req_t ), + .rsp_t ( axi_in_rsp_t ), + .AxiIdWidth ( AxiCfg.InIdWidth ), + .Name ( DmaName ) + ) i_axi_bw_monitor ( + .clk_i ( clk ), + .en_i ( rst_n ), + .end_of_sim_i ( end_of_sim[x][y] ), + .req_i ( cluster_in_req[x][y] ), + .rsp_i ( cluster_in_rsp[x][y] ), + .ar_in_flight_o ( ), + .aw_in_flight_o ( ) + ); + end + end + + + ///////////////////////// + // Network-on-Chip // + ///////////////////////// + + floo_axi_mesh_noc i_floo_axi_mesh_noc ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .cluster_axi_in_req_i ( cluster_in_req ), + .cluster_axi_in_rsp_o ( cluster_in_rsp ), + .cluster_axi_out_req_o ( cluster_out_req ), + .cluster_axi_out_rsp_i ( cluster_out_rsp ), + .hbm_axi_out_req_o ( hbm_req ), + .hbm_axi_out_rsp_i ( hbm_rsp ) + ); + + + initial begin + wait(&end_of_sim); + // Wait for some time + repeat (2) @(posedge clk); + // Stop the simulation + $stop; + end + +endmodule diff --git a/hw/tb/wave/tb_floo_axi_mesh.wave.tcl b/hw/tb/wave/tb_floo_axi_mesh.wave.tcl new file mode 100644 index 00000000..efe33f1c --- /dev/null +++ b/hw/tb/wave/tb_floo_axi_mesh.wave.tcl @@ -0,0 +1,30 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +source hw/tb/wave/wave.tcl + +floo_wave_init + +set tb_name tb_floo_axi_mesh +set noc_name i_floo_axi_mesh_noc + +set routers [find instances -bydu floo_axi_router -nodu] +set num_y [regexp -all {router_0} $routers] +set num_x [expr {[llength $routers] / $num_y}] + +for {set y 0} {$y < $num_y} {incr y} { + for {set x 0} {$x < $num_x} {incr x} { + set groups [list Node X=${x} Y=${y}] + floo_axi_chimney_wave $tb_name/$noc_name/cluster_ni_${x}_${y} [concat $groups [list Chimney]] + floo_router_wave $tb_name/$noc_name/router_${x}_${y} [concat $groups [list Router]] + + floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_bw_monitor/*in_flight_o $groups 1 + } +} + +for {set y 0} {$y < $num_y} {incr y} { + floo_axi_chimney_wave $tb_name/$noc_name/hbm_ni_${y} [list HBM West "Channel ${y}" Chimney] 1 +} + +floo_wave_style From 7f43d43c96dc1301715c4cb51d96d8cc47d5e2d3 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 14:54:09 +0200 Subject: [PATCH 24/34] ci: Add `axi_mesh` to CI --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index faebe0c8..74e63d67 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -64,7 +64,7 @@ run-traffic: JOB_NAME: mesh parallel: matrix: - - DUT: [nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses + - DUT: [axi_mesh, nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses ROUTE_ALGO: [xy, src, id] TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] TRAFFIC_RW: [read, write] From bbd90259b254c11b77040f9898966b28ddb0aa39 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:09:55 +0200 Subject: [PATCH 25/34] make: Specify work folder --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index c5116deb..ff9f49bd 100644 --- a/Makefile +++ b/Makefile @@ -35,10 +35,13 @@ BENDER_FLAGS += -t snitch_cluster BENDER_FLAGS += -t idma_test BENDER_FLAGS := $(BENDER_FLAGS) $(EXTRA_BENDER_FLAGS) +WORK ?= work + VLOG_ARGS += -suppress vlog-2583 VLOG_ARGS += -suppress vlog-13314 VLOG_ARGS += -suppress vlog-13233 VLOG_ARGS += -timescale \"1 ns / 1 ps\" +VLOG_ARGS += -work $(WORK) VSIM_TB_DUT ?= floo_noc_router_test @@ -46,6 +49,7 @@ VSIM_FLAGS += -64 VSIM_FLAGS += -t 1ps VSIM_FLAGS += -sv_seed 0 VSIM_FLAGS += -quiet +VSIM_FLAGS += -work $(WORK) # Set the job name and directory if specified ifdef JOB_NAME From 94d3d77b6a119c2d3ecb32c0593d4d4e8d0234eb Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:10:03 +0200 Subject: [PATCH 26/34] ci: Improve stages in CI --- .gitlab-ci.yml | 62 +++++++++++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 24 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 74e63d67..763d21b2 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,27 +25,46 @@ collect-bender-sources: compile-vsim: stage: build + needs: + - collect-bender-sources variables: EXTRA_BENDER_FLAGS: "-t vc_router" script: - make compile-sim | tee compile.log 2>&1 - '! grep "\*\* Error" compile.log' - needs: - - collect-bender-sources artifacts: paths: - scripts/ - work/ - modelsim.ini -run-vsim: - stage: run +compile-meshes: + stage: build + needs: + - collect-bender-sources + parallel: + matrix: + - DUT: [axi_mesh, nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses + ROUTE_ALGO: [xy, src, id] script: - - make run-sim-batch | tee vsim.log 2>&1 - - 'grep "Errors: 0," vsim.log' + # Install `floogen` + - $PYTHON -m venv .venv + - source .venv/bin/activate + - pip install . + # Generate sources + - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format + # Compile the network + - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" WORK="work_${DUT}_${ROUTE_ALGO}" | tee compile.log 2>&1 + - '! grep "\*\* Error" compile.log' artifacts: paths: - - vsim.log + - work_*/ + +run-vsim: + stage: run + needs: + - collect-bender-sources + - compile-vsim parallel: matrix: - VSIM_TB_DUT: @@ -54,12 +73,18 @@ run-vsim: - tb_floo_axi_chimney - tb_floo_nw_chimney - tb_floo_rob - needs: - - collect-bender-sources - - compile-vsim + script: + - make run-sim-batch | tee vsim.log 2>&1 + - 'grep "Errors: 0," vsim.log' + artifacts: + paths: + - vsim.log run-traffic: stage: run + needs: + - collect-bender-sources + - compile-meshes variables: JOB_NAME: mesh parallel: @@ -68,26 +93,15 @@ run-traffic: ROUTE_ALGO: [xy, src, id] TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] TRAFFIC_RW: [read, write] - needs: - - collect-bender-sources script: - # Install `floogen` - - $PYTHON -m venv .venv - - source .venv/bin/activate - - pip install . - # Generate sources - - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format - make jobs - # Compile and run the simulation - - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" - - make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} | tee vsim.log 2>&1 - # Check for errors + - make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} WORK=work_${DUT}_${ROUTE_ALGO} | tee vsim.log 2>&1 - 'grep "Errors: 0," vsim.log' morty: stage: build + needs: + - collect-bender-sources script: - $BENDER sources -f > source_list.txt - morty -f source_list.txt - needs: - - collect-bender-sources From fefde2e446a360e99b6bac635113210a78fea35e Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:27:09 +0200 Subject: [PATCH 27/34] lint: SV sources --- hw/tb/tb_floo_nw_mesh.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/tb/tb_floo_nw_mesh.sv b/hw/tb/tb_floo_nw_mesh.sv index 00e7cb3d..c84c5890 100644 --- a/hw/tb/tb_floo_nw_mesh.sv +++ b/hw/tb/tb_floo_nw_mesh.sv @@ -63,7 +63,8 @@ module tb_floo_nw_mesh; typedef logic [AxiCfgJoin.OutIdWidth-1:0] hbm_id_t; typedef logic [AxiCfgJoin.UserWidth-1:0] hbm_user_t; - `AXI_TYPEDEF_ALL_CT(hbm_axi, hbm_axi_req_t, hbm_axi_rsp_t, axi_wide_out_addr_t, hbm_id_t, axi_wide_out_data_t, axi_wide_out_strb_t, hbm_user_t) + `AXI_TYPEDEF_ALL_CT(hbm_axi, hbm_axi_req_t, hbm_axi_rsp_t, axi_wide_out_addr_t, + hbm_id_t, axi_wide_out_data_t, axi_wide_out_strb_t, hbm_user_t) hbm_axi_req_t [NumHBMChannels-1:0] hbm_req; hbm_axi_rsp_t [NumHBMChannels-1:0] hbm_rsp; From 08d402cc9b300313d79686ad4c96e363f4e329ea Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:27:20 +0200 Subject: [PATCH 28/34] lint: python sources --- floogen/model/routing.py | 2 +- util/gen_jobs.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/floogen/model/routing.py b/floogen/model/routing.py index a0370b0e..f5ab33ba 100644 --- a/floogen/model/routing.py +++ b/floogen/model/routing.py @@ -520,7 +520,7 @@ def render_hdr_typedef(self, network_type) -> str: if self.num_vc_id_bits == 0: return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t)" - return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, vc_id_t, {ch_type}, rob_idx_t, vc_id_t)" + return f"`FLOO_TYPEDEF_VC_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t, vc_id_t)" def render_route_cfg(self, name) -> str: """Render the SystemVerilog routing configuration.""" diff --git a/util/gen_jobs.py b/util/gen_jobs.py index f0491f19..877638fb 100755 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -148,7 +148,8 @@ def gen_mesh_traffic( elif traffic_type == "random": ext_addr = local_addr while ext_addr == local_addr: - ext_addr = get_xy_base_addr(random.randint(0, NUM_X-1), random.randint(0, NUM_Y-1)) + ext_addr = get_xy_base_addr(random.randint(0, NUM_X-1), + random.randint(0, NUM_Y-1)) elif traffic_type == "onehop": if not (x == 0 and y == 0): wide_length = 0 From b65e5bdc72d24df1d0868e4ea9570c39b26f174c Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:30:44 +0200 Subject: [PATCH 29/34] ci: Remove FlooGen generation from GitHub CI --- .github/workflows/floogen.yml | 55 ----------------------------------- 1 file changed, 55 deletions(-) diff --git a/.github/workflows/floogen.yml b/.github/workflows/floogen.yml index 5eca7203..ab7b0bcf 100644 --- a/.github/workflows/floogen.yml +++ b/.github/workflows/floogen.yml @@ -29,58 +29,3 @@ jobs: - name: Run unit tests run: | python -m pytest -v - - ##################### - # Generate SV files # - ##################### - gen-nocs: - runs-on: ubuntu-latest - strategy: - matrix: - examples: ["single_cluster", "occamy_mesh_xy", "occamy_tree", "occamy_mesh_src", "terapool"] - steps: - - uses: actions/checkout@v4 - - name: Set up Python - uses: actions/setup-python@v5 - with: - python-version: '3.10' - - name: Install dependencies - run: | - python -m pip install --upgrade pip - - name: Install floogen - run: | - python -m pip install . - - name: Install Verible - uses: chipsalliance/verible-actions-common/install-verible@main - with: - github_token: ${{ secrets.GITHUB_TOKEN }} - - name: Generate NoCs - run: | - floogen -c floogen/examples/${{ matrix.examples }}.yml -o generated - - name: Upload artifact - uses: actions/upload-artifact@v4 - with: - name: ${{ matrix.examples }} - path: generated/floo_${{ matrix.examples }}_noc.sv - if-no-files-found: error - retention-days: 1 - - ################# - # Lint SV files # - ################# - lint-nocs: - runs-on: ubuntu-latest - needs: gen-nocs - steps: - - uses: actions/checkout@v4 - - name: Download artifact - uses: actions/download-artifact@v4 - with: - path: generated - - name: Lint SV files - uses: chipsalliance/verible-linter-action@main - with: - config_file: '' - paths: - ./generated - github_token: ${{ secrets.GITHUB_TOKEN }} From c8e3955abea448554da10968ccf5ba7058800d7f Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:37:30 +0200 Subject: [PATCH 30/34] tb: Remove deprecated `dma_mesh` and `dma_vc_mesh` --- .gitlab-ci.yml | 4 +- Bender.yml | 2 - hw/tb/tb_floo_dma_mesh.sv | 455 --------------------- hw/tb/tb_floo_vc_dma_mesh.sv | 510 ------------------------ hw/tb/wave/tb_floo_dma_mesh.wave.tcl | 41 -- hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl | 41 -- 6 files changed, 2 insertions(+), 1051 deletions(-) delete mode 100644 hw/tb/tb_floo_dma_mesh.sv delete mode 100644 hw/tb/tb_floo_vc_dma_mesh.sv delete mode 100644 hw/tb/wave/tb_floo_dma_mesh.wave.tcl delete mode 100644 hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 763d21b2..4b4138b4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -44,7 +44,7 @@ compile-meshes: - collect-bender-sources parallel: matrix: - - DUT: [axi_mesh, nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses + - DUT: [axi_mesh, nw_mesh] ROUTE_ALGO: [xy, src, id] script: # Install `floogen` @@ -89,7 +89,7 @@ run-traffic: JOB_NAME: mesh parallel: matrix: - - DUT: [axi_mesh, nw_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses + - DUT: [axi_mesh, nw_mesh] ROUTE_ALGO: [xy, src, id] TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] TRAFFIC_RW: [read, write] diff --git a/Bender.yml b/Bender.yml index 63c1b539..b4ab39d8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -80,14 +80,12 @@ sources: - hw/tb/tb_floo_nw_chimney.sv - hw/tb/tb_floo_router.sv - hw/tb/tb_floo_rob.sv - - hw/tb/tb_floo_dma_mesh.sv - target: all(test, vc_router) include_dirs: - hw/test/include files: - hw/tb/tb_floo_vc_router.sv - - hw/tb/tb_floo_vc_dma_mesh.sv - target: all(test, axi_mesh) include_dirs: diff --git a/hw/tb/tb_floo_dma_mesh.sv b/hw/tb/tb_floo_dma_mesh.sv deleted file mode 100644 index 19aa1f02..00000000 --- a/hw/tb/tb_floo_dma_mesh.sv +++ /dev/null @@ -1,455 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Author: Tim Fischer - -`include "axi/typedef.svh" -`include "floo_noc/typedef.svh" - -module tb_floo_dma_mesh; - - import floo_pkg::*; - - localparam time CyclTime = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - localparam int unsigned NumX = 4; - localparam int unsigned NumY = 4; - localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY; - - typedef logic[$clog2(NumX+2)-1:0] x_bits_t; - typedef logic[$clog2(NumY+2)-1:0] y_bits_t; - `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic) - `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN) - `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW) - `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in, - floo_test_pkg::AxiCfgN, floo_test_pkg::AxiCfgW, hdr_t) - `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) - - localparam int unsigned HBMLatency = 100; - localparam axi_narrow_addr_t HBMSize = 48'h10000; // 64KB - localparam axi_narrow_addr_t MemSize = HBMSize; - - localparam int unsigned InFifoDepth = 2; - localparam int unsigned OutFifoDepth = 2; - - logic clk, rst_n; - - ///////////////////// - // AXI Signals // - ///////////////////// - - axi_narrow_in_req_t [NumX-1:0][NumY-1:0] narrow_man_req; - axi_narrow_in_rsp_t [NumX-1:0][NumY-1:0] narrow_man_rsp; - axi_wide_in_req_t [NumX-1:0][NumY-1:0] wide_man_req; - axi_wide_in_rsp_t [NumX-1:0][NumY-1:0] wide_man_rsp; - - axi_narrow_out_req_t [NumX-1:0][NumY-1:0] narrow_sub_req; - axi_narrow_out_rsp_t [NumX-1:0][NumY-1:0] narrow_sub_rsp; - axi_wide_out_req_t [NumX-1:0][NumY-1:0] wide_sub_req; - axi_wide_out_rsp_t [NumX-1:0][NumY-1:0] wide_sub_rsp; - - axi_narrow_out_req_t [West:North][NumMax-1:0] narrow_hbm_req; - axi_narrow_out_rsp_t [West:North][NumMax-1:0] narrow_hbm_rsp; - axi_wide_out_req_t [West:North][NumMax-1:0] wide_hbm_req; - axi_wide_out_rsp_t [West:North][NumMax-1:0] wide_hbm_rsp; - - ///////////////////// - // NoC Signals // - ///////////////////// - - - floo_req_t [NumX-1:0][NumY-1:0] narrow_chimney_man_req, narrow_chimney_sub_req; - floo_rsp_t [NumX-1:0][NumY-1:0] narrow_chimney_man_rsp, narrow_chimney_sub_rsp; - floo_wide_t [NumX-1:0][NumY-1:0] wide_chimney_man, wide_chimney_sub; - - floo_req_t [NumX:0][NumY-1:0] req_hor_pos; - floo_req_t [NumX:0][NumY-1:0] req_hor_neg; - floo_req_t [NumY:0][NumX-1:0] req_ver_pos; - floo_req_t [NumY:0][NumX-1:0] req_ver_neg; - floo_rsp_t [NumX:0][NumY-1:0] rsp_hor_pos; - floo_rsp_t [NumX:0][NumY-1:0] rsp_hor_neg; - floo_rsp_t [NumY:0][NumX-1:0] rsp_ver_pos; - floo_rsp_t [NumY:0][NumX-1:0] rsp_ver_neg; - floo_wide_t [NumX:0][NumY-1:0] wide_hor_pos; - floo_wide_t [NumX:0][NumY-1:0] wide_hor_neg; - floo_wide_t [NumY:0][NumX-1:0] wide_ver_pos; - floo_wide_t [NumY:0][NumX-1:0] wide_ver_neg; - - - logic [NumX-1:0][NumY-1:0][1:0] end_of_sim; - - clk_rst_gen #( - .ClkPeriod ( CyclTime ), - .RstClkCycles ( 5 ) - ) i_clk_gen ( - .clk_o ( clk ), - .rst_no ( rst_n ) - ); - - //////////////////////////////// - // HBM Model on left side // - //////////////////////////////// - - floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( floo_test_pkg::AxiCfgW.AddrWidth ), - .DataWidth ( floo_test_pkg::AxiCfgW.DataWidth ), - .UserWidth ( floo_test_pkg::AxiCfgW.UserWidth ), - .IdWidth ( floo_test_pkg::AxiCfgW.OutIdWidth ), - .axi_req_t ( axi_wide_out_req_t ), - .axi_rsp_t ( axi_wide_out_rsp_t ), - .aw_chan_t ( axi_wide_out_aw_chan_t ), - .w_chan_t ( axi_wide_out_w_chan_t ), - .b_chan_t ( axi_wide_out_b_chan_t ), - .ar_chan_t ( axi_wide_out_ar_chan_t ), - .r_chan_t ( axi_wide_out_r_chan_t ) - ) i_floo_wide_hbm_model [West:North][NumMax-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .hbm_req_i ( wide_hbm_req ), - .hbm_rsp_o ( wide_hbm_rsp ) - ); - - floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( floo_test_pkg::AxiCfgN.AddrWidth ), - .DataWidth ( floo_test_pkg::AxiCfgN.DataWidth ), - .UserWidth ( floo_test_pkg::AxiCfgN.UserWidth ), - .IdWidth ( floo_test_pkg::AxiCfgN.OutIdWidth ), - .axi_req_t ( axi_narrow_out_req_t ), - .axi_rsp_t ( axi_narrow_out_rsp_t ), - .aw_chan_t ( axi_narrow_out_aw_chan_t ), - .w_chan_t ( axi_narrow_out_w_chan_t ), - .b_chan_t ( axi_narrow_out_b_chan_t ), - .ar_chan_t ( axi_narrow_out_ar_chan_t ), - .r_chan_t ( axi_narrow_out_r_chan_t ) - ) i_floo_narrow_hbm_model [West:North][NumMax-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .hbm_req_i ( narrow_hbm_req ), - .hbm_rsp_o ( narrow_hbm_rsp ) - ); - - for (genvar i = North; i <= West; i++) begin : gen_hbm_chimneys - - localparam int unsigned NumChimneys = (i == North || i == South) ? NumX : NumY; - - floo_req_t [NumChimneys-1:0] req_hbm_in, req_hbm_out; - floo_rsp_t [NumChimneys-1:0] rsp_hbm_in, rsp_hbm_out; - floo_wide_t [NumChimneys-1:0] wide_hbm_in, wide_hbm_out; - id_t [NumChimneys-1:0] xy_id_hbm; - - if (i == North) begin : gen_north_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: j+1, y: NumY+1, port_id: 0}; - end - assign req_hbm_in = req_ver_pos[NumY]; - assign rsp_hbm_in = rsp_ver_pos[NumY]; - assign wide_hbm_in = wide_ver_pos[NumY]; - assign req_ver_neg[NumY] = req_hbm_out; - assign rsp_ver_neg[NumY] = rsp_hbm_out; - assign wide_ver_neg[NumY] = wide_hbm_out; - end - else if (i == South) begin : gen_south_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: j+1, y: 0, port_id: 0}; - end - assign req_hbm_in = req_ver_neg[0]; - assign rsp_hbm_in = rsp_ver_neg[0]; - assign wide_hbm_in = wide_ver_neg[0]; - assign req_ver_pos[0] = req_hbm_out; - assign rsp_ver_pos[0] = rsp_hbm_out; - assign wide_ver_pos[0] = wide_hbm_out; - end - else if (i == East) begin : gen_east_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: NumX+1, y: j+1, port_id: 0}; - end - assign req_hbm_in = req_hor_pos[NumX]; - assign rsp_hbm_in = rsp_hor_pos[NumX]; - assign wide_hbm_in = wide_hor_pos[NumX]; - assign req_hor_neg[NumX] = req_hbm_out; - assign rsp_hor_neg[NumX] = rsp_hbm_out; - assign wide_hor_neg[NumX] = wide_hbm_out; - end - else if (i == West) begin : gen_west_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: 0, y: j+1, port_id: 0}; - end - assign req_hbm_in = req_hor_neg[0]; - assign rsp_hbm_in = rsp_hor_neg[0]; - assign wide_hbm_in = wide_hor_neg[0]; - assign req_hor_pos[0] = req_hbm_out; - assign rsp_hor_pos[0] = rsp_hbm_out; - assign wide_hor_pos[0] = wide_hbm_out; - end - - floo_nw_chimney #( - .AxiCfgN ( floo_test_pkg::AxiCfgN ), - .AxiCfgW ( floo_test_pkg::AxiCfgW ), - .ChimneyCfgN ( floo_test_pkg::ChimneyCfg ), - .ChimneyCfgW ( floo_test_pkg::ChimneyCfg ), - .RouteCfg ( floo_test_pkg::RouteCfg ), - .hdr_t ( hdr_t ), - .id_t ( id_t ), - .axi_narrow_in_req_t ( axi_narrow_in_req_t ), - .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_narrow_out_req_t ( axi_narrow_out_req_t ), - .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), - .axi_wide_in_req_t ( axi_wide_in_req_t ), - .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), - .axi_wide_out_req_t ( axi_wide_out_req_t ), - .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), - .floo_req_t ( floo_req_t ), - .floo_rsp_t ( floo_rsp_t ), - .floo_wide_t ( floo_wide_t ) - ) i_hbm_chimney [NumChimneys-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .id_i ( xy_id_hbm ), - .route_table_i ( '0 ), - .axi_narrow_in_req_i ( '0 ), - .axi_narrow_in_rsp_o ( ), - .axi_narrow_out_req_o ( narrow_hbm_req[i] ), - .axi_narrow_out_rsp_i ( narrow_hbm_rsp[i] ), - .axi_wide_in_req_i ( '0 ), - .axi_wide_in_rsp_o ( ), - .axi_wide_out_req_o ( wide_hbm_req[i] ), - .axi_wide_out_rsp_i ( wide_hbm_rsp[i] ), - .floo_req_i ( req_hbm_in ), - .floo_req_o ( req_hbm_out ), - .floo_rsp_i ( rsp_hbm_in ), - .floo_rsp_o ( rsp_hbm_out ), - .floo_wide_i ( wide_hbm_in ), - .floo_wide_o ( wide_hbm_out ) - ); - end - - - - ////////////////// - // NoC Mesh // - ////////////////// - - for (genvar x = 0; x < NumX; x++) begin : gen_x - for (genvar y = 0; y < NumX; y++) begin : gen_y - id_t current_id; - localparam string NarrowDmaName = $sformatf("narrow_dma_%0d_%0d", x, y); - localparam string WideDmaName = $sformatf("wide_dma_%0d_%0d", x, y); - floo_req_t [NumDirections-1:0] req_out, req_in; - floo_rsp_t [NumDirections-1:0] rsp_out, rsp_in; - floo_wide_t [NumDirections-1:0] wide_out, wide_in; - - localparam int unsigned Index = y * NumX + x+1; - localparam axi_narrow_addr_t MemBaseAddr = - (x+1) << floo_test_pkg::RouteCfg.XYAddrOffsetX | - (y+1) << floo_test_pkg::RouteCfg.XYAddrOffsetY; - assign current_id = '{x: x+1, y: y+1, port_id: 0}; - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgN) ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), - .axi_in_req_t ( axi_narrow_out_req_t ), - .axi_in_rsp_t ( axi_narrow_out_rsp_t ), - .axi_out_req_t ( axi_narrow_in_req_t ), - .axi_out_rsp_t ( axi_narrow_in_rsp_t ), - .JobId ( 100 + Index ) - ) i_narrow_dma_node ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( narrow_sub_req[x][y] ), - .axi_in_rsp_o ( narrow_sub_rsp[x][y] ), - .axi_out_req_o ( narrow_man_req[x][y] ), - .axi_out_rsp_i ( narrow_man_rsp[x][y] ), - .end_of_sim_o ( end_of_sim[x][y][0] ) - ); - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgW) ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), - .axi_in_req_t ( axi_wide_out_req_t ), - .axi_in_rsp_t ( axi_wide_out_rsp_t ), - .axi_out_req_t ( axi_wide_in_req_t ), - .axi_out_rsp_t ( axi_wide_in_rsp_t ), - .JobId ( Index ) - ) i_wide_dma_node ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( wide_sub_req[x][y] ), - .axi_in_rsp_o ( wide_sub_rsp[x][y] ), - .axi_out_req_o ( wide_man_req[x][y] ), - .axi_out_rsp_i ( wide_man_rsp[x][y] ), - .end_of_sim_o ( end_of_sim[x][y][1] ) - ); - - axi_bw_monitor #( - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ), - .AxiIdWidth ( floo_test_pkg::AxiCfgN.InIdWidth ), - .Name ( NarrowDmaName ) - ) i_axi_narrow_bw_monitor ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( end_of_sim[x][y][0] ), - .req_i ( narrow_man_req[x][y] ), - .rsp_i ( narrow_man_rsp[x][y] ), - .ar_in_flight_o( ), - .aw_in_flight_o( ) - ); - - axi_bw_monitor #( - .req_t ( axi_wide_in_req_t ), - .rsp_t ( axi_wide_in_rsp_t ), - .AxiIdWidth ( floo_test_pkg::AxiCfgW.InIdWidth ), - .Name ( WideDmaName ) - ) i_axi_wide_bw_monitor ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( end_of_sim[x][y][1] ), - .req_i ( wide_man_req[x][y] ), - .rsp_i ( wide_man_rsp[x][y] ), - .ar_in_flight_o( ), - .aw_in_flight_o( ) - ); - - floo_nw_chimney #( - .AxiCfgN ( floo_test_pkg::AxiCfgN ), - .AxiCfgW ( floo_test_pkg::AxiCfgW ), - .ChimneyCfgN ( floo_test_pkg::ChimneyCfg ), - .ChimneyCfgW ( floo_test_pkg::ChimneyCfg ), - .RouteCfg ( floo_test_pkg::RouteCfg ), - .hdr_t ( hdr_t ), - .id_t ( id_t ), - .axi_narrow_in_req_t ( axi_narrow_in_req_t ), - .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_narrow_out_req_t ( axi_narrow_out_req_t ), - .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), - .axi_wide_in_req_t ( axi_wide_in_req_t ), - .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), - .axi_wide_out_req_t ( axi_wide_out_req_t ), - .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), - .floo_req_t ( floo_req_t ), - .floo_rsp_t ( floo_rsp_t ), - .floo_wide_t ( floo_wide_t ) - ) i_dma_chimney ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .id_i ( current_id ), - .route_table_i ( '0 ), - .axi_narrow_in_req_i ( narrow_man_req[x][y] ), - .axi_narrow_in_rsp_o ( narrow_man_rsp[x][y] ), - .axi_narrow_out_req_o ( narrow_sub_req[x][y] ), - .axi_narrow_out_rsp_i ( narrow_sub_rsp[x][y] ), - .axi_wide_in_req_i ( wide_man_req[x][y] ), - .axi_wide_in_rsp_o ( wide_man_rsp[x][y] ), - .axi_wide_out_req_o ( wide_sub_req[x][y] ), - .axi_wide_out_rsp_i ( wide_sub_rsp[x][y] ), - .floo_req_i ( narrow_chimney_sub_req[x][y] ), - .floo_req_o ( narrow_chimney_man_req[x][y] ), - .floo_rsp_i ( narrow_chimney_man_rsp[x][y] ), - .floo_rsp_o ( narrow_chimney_sub_rsp[x][y] ), - .floo_wide_i ( wide_chimney_sub[x][y] ), - .floo_wide_o ( wide_chimney_man[x][y] ) - ); - - floo_nw_router #( - .AxiCfgN ( floo_test_pkg::AxiCfgN ), - .AxiCfgW ( floo_test_pkg::AxiCfgW ), - .NumRoutes ( NumDirections ), - .InFifoDepth ( InFifoDepth ), - .OutFifoDepth ( OutFifoDepth ), - .RouteAlgo ( floo_test_pkg::RouteCfg.RouteAlgo ), - .XYRouteOpt ( 1'b0 ), - .id_t ( id_t ), - .hdr_t ( hdr_t ), - .floo_req_t ( floo_req_t ), - .floo_rsp_t ( floo_rsp_t ), - .floo_wide_t ( floo_wide_t ) - ) i_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_enable_i ( 1'b0 ), - .id_i ( current_id ), - .id_route_map_i ( '0 ), - .floo_req_i ( req_in ), - .floo_req_o ( req_out ), - .floo_rsp_i ( rsp_in ), - .floo_rsp_o ( rsp_out ), - .floo_wide_i ( wide_in ), - .floo_wide_o ( wide_out ) - ); - - // Eject - assign req_in[Eject] = narrow_chimney_man_req[x][y]; - assign narrow_chimney_sub_req[x][y] = req_out[Eject]; - assign rsp_in[Eject] = narrow_chimney_sub_rsp[x][y]; - assign narrow_chimney_man_rsp[x][y] = rsp_out[Eject]; - assign wide_in[Eject] = wide_chimney_man[x][y]; - assign wide_chimney_sub[x][y] = wide_out[Eject]; - - // East - assign req_in[East] = req_hor_neg[x+1][y]; - assign req_hor_pos[x+1][y] = req_out[East]; - assign rsp_in[East] = rsp_hor_neg[x+1][y]; - assign rsp_hor_pos[x+1][y] = rsp_out[East]; - assign wide_in[East] = wide_hor_neg[x+1][y]; - assign wide_hor_pos[x+1][y] = wide_out[East]; - - // West - assign req_in[West] = req_hor_pos[x][y]; - assign req_hor_neg[x][y] = req_out[West]; - assign rsp_in[West] = rsp_hor_pos[x][y]; - assign rsp_hor_neg[x][y] = rsp_out[West]; - assign wide_in[West] = wide_hor_pos[x][y]; - assign wide_hor_neg[x][y] = wide_out[West]; - - // North - assign req_in[North] = req_ver_neg[y+1][x]; - assign req_ver_pos[y+1][x] = req_out[North]; - assign rsp_in[North] = rsp_ver_neg[y+1][x]; - assign rsp_ver_pos[y+1][x] = rsp_out[North]; - assign wide_in[North] = wide_ver_neg[y+1][x]; - assign wide_ver_pos[y+1][x] = wide_out[North]; - - // South - assign req_in[South] = req_ver_pos[y][x]; - assign req_ver_neg[y][x] = req_out[South]; - assign rsp_in[South] = rsp_ver_pos[y][x]; - assign rsp_ver_neg[y][x] = rsp_out[South]; - assign wide_in[South] = wide_ver_pos[y][x]; - assign wide_ver_neg[y][x] = wide_out[South]; - - end - end - - initial begin - wait(&end_of_sim); - // Wait for some time - repeat (2) @(posedge clk); - // Stop the simulation - $stop; - end - -endmodule diff --git a/hw/tb/tb_floo_vc_dma_mesh.sv b/hw/tb/tb_floo_vc_dma_mesh.sv deleted file mode 100644 index 8a4e6ad2..00000000 --- a/hw/tb/tb_floo_vc_dma_mesh.sv +++ /dev/null @@ -1,510 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Author: Tim Fischer - -`include "axi/typedef.svh" -`include "floo_noc/typedef.svh" - -module tb_floo_vc_dma_mesh; - - import floo_pkg::*; - - localparam time CyclTime = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - localparam int unsigned NumX = 4; - localparam int unsigned NumY = 4; - localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY; - - typedef logic[$clog2(NumX+2)-1:0] x_bits_t; - typedef logic[$clog2(NumY+2)-1:0] y_bits_t; - typedef logic [2:0] vc_id_t; - `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) - `FLOO_TYPEDEF_VC_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic, vc_id_t) - `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN) - `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW) - `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in, - floo_test_pkg::AxiCfgN, floo_test_pkg::AxiCfgW, hdr_t) - `FLOO_TYPEDEF_VC_NW_LINK_ALL(vc_req, vc_rsp, vc_wide, req, rsp, wide, vc_id_t) - - function automatic chimney_cfg_t gen_cut_rsp_cfg(); - chimney_cfg_t cfg = floo_pkg::ChimneyDefaultCfg; - cfg.CutRsp = 1'b1; - return cfg; - endfunction - - localparam chimney_cfg_t ChimneyCfg = gen_cut_rsp_cfg(); - - localparam int unsigned HBMLatency = 100; - localparam axi_narrow_addr_t HBMSize = 48'h10000; // 64KB - localparam axi_narrow_addr_t MemSize = HBMSize; - - localparam int unsigned ChannelFifoDepth = 2; - localparam int unsigned WormholeVCDepth = 3; // >= ChannelFifoDepth - localparam int unsigned FixedWormholeVC = 1; // send all Wormhole flits to same VC - localparam int unsigned AllowVCOverflow = 1; // 1: FVADA, 0: fixed VC, direction based - localparam int unsigned AllowOverflowFromDeeperVC = 1; // can be overwritten by AllowVCOverflow=0 - localparam int unsigned UpdateRRArbIfNotSent = 0; // does not work - localparam int unsigned CreditShortcut = 1; // 1: if receive free credit from correct vc, send - localparam int unsigned NumVCLocal = 1; // 4 would be 1 per direction - localparam int unsigned Only1VC = 0; // tiny standart router - localparam int unsigned SingleStage = 0; // 0: standard 2 stage router, 1: single stage - - logic clk, rst_n; - - ///////////////////// - // AXI Signals // - ///////////////////// - - axi_narrow_in_req_t [NumX-1:0][NumY-1:0] narrow_man_req; - axi_narrow_in_rsp_t [NumX-1:0][NumY-1:0] narrow_man_rsp; - axi_wide_in_req_t [NumX-1:0][NumY-1:0] wide_man_req; - axi_wide_in_rsp_t [NumX-1:0][NumY-1:0] wide_man_rsp; - - axi_narrow_out_req_t [NumX-1:0][NumY-1:0] narrow_sub_req; - axi_narrow_out_rsp_t [NumX-1:0][NumY-1:0] narrow_sub_rsp; - axi_wide_out_req_t [NumX-1:0][NumY-1:0] wide_sub_req; - axi_wide_out_rsp_t [NumX-1:0][NumY-1:0] wide_sub_rsp; - - axi_narrow_out_req_t [West:North][NumMax-1:0] narrow_hbm_req; - axi_narrow_out_rsp_t [West:North][NumMax-1:0] narrow_hbm_rsp; - axi_wide_out_req_t [West:North][NumMax-1:0] wide_hbm_req; - axi_wide_out_rsp_t [West:North][NumMax-1:0] wide_hbm_rsp; - - ///////////////////// - // NoC Signals // - ///////////////////// - - - floo_vc_req_t [NumX-1:0][NumY-1:0] narrow_chimney_man_req, narrow_chimney_sub_req; - floo_vc_rsp_t [NumX-1:0][NumY-1:0] narrow_chimney_man_rsp, narrow_chimney_sub_rsp; - floo_vc_wide_t [NumX-1:0][NumY-1:0] wide_chimney_man, wide_chimney_sub; - - floo_vc_req_t [NumX:0][NumY-1:0] req_hor_pos; - floo_vc_req_t [NumX:0][NumY-1:0] req_hor_neg; - floo_vc_req_t [NumY:0][NumX-1:0] req_ver_pos; - floo_vc_req_t [NumY:0][NumX-1:0] req_ver_neg; - floo_vc_rsp_t [NumX:0][NumY-1:0] rsp_hor_pos; - floo_vc_rsp_t [NumX:0][NumY-1:0] rsp_hor_neg; - floo_vc_rsp_t [NumY:0][NumX-1:0] rsp_ver_pos; - floo_vc_rsp_t [NumY:0][NumX-1:0] rsp_ver_neg; - floo_vc_wide_t [NumX:0][NumY-1:0] wide_hor_pos; - floo_vc_wide_t [NumX:0][NumY-1:0] wide_hor_neg; - floo_vc_wide_t [NumY:0][NumX-1:0] wide_ver_pos; - floo_vc_wide_t [NumY:0][NumX-1:0] wide_ver_neg; - - - logic [NumX-1:0][NumY-1:0][1:0] end_of_sim; - - clk_rst_gen #( - .ClkPeriod ( CyclTime ), - .RstClkCycles ( 5 ) - ) i_clk_gen ( - .clk_o ( clk ), - .rst_no ( rst_n ) - ); - - //////////////////////////////// - // HBM Model on left side // - //////////////////////////////// - - floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( floo_test_pkg::AxiCfgW.AddrWidth ), - .DataWidth ( floo_test_pkg::AxiCfgW.DataWidth ), - .UserWidth ( floo_test_pkg::AxiCfgW.UserWidth ), - .IdWidth ( floo_test_pkg::AxiCfgW.OutIdWidth ), - .axi_req_t ( axi_wide_out_req_t ), - .axi_rsp_t ( axi_wide_out_rsp_t ), - .aw_chan_t ( axi_wide_out_aw_chan_t ), - .w_chan_t ( axi_wide_out_w_chan_t ), - .b_chan_t ( axi_wide_out_b_chan_t ), - .ar_chan_t ( axi_wide_out_ar_chan_t ), - .r_chan_t ( axi_wide_out_r_chan_t ) - ) i_floo_wide_hbm_model [West:North][NumMax-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .hbm_req_i ( wide_hbm_req ), - .hbm_rsp_o ( wide_hbm_rsp ) - ); - - floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( floo_test_pkg::AxiCfgN.AddrWidth ), - .DataWidth ( floo_test_pkg::AxiCfgN.DataWidth ), - .UserWidth ( floo_test_pkg::AxiCfgN.UserWidth ), - .IdWidth ( floo_test_pkg::AxiCfgN.OutIdWidth ), - .axi_req_t ( axi_narrow_out_req_t ), - .axi_rsp_t ( axi_narrow_out_rsp_t ), - .aw_chan_t ( axi_narrow_out_aw_chan_t ), - .w_chan_t ( axi_narrow_out_w_chan_t ), - .b_chan_t ( axi_narrow_out_b_chan_t ), - .ar_chan_t ( axi_narrow_out_ar_chan_t ), - .r_chan_t ( axi_narrow_out_r_chan_t ) - ) i_floo_narrow_hbm_model [West:North][NumMax-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .hbm_req_i ( narrow_hbm_req ), - .hbm_rsp_o ( narrow_hbm_rsp ) - ); - - for (genvar i = North; i <= West; i++) begin : gen_hbm_chimneys - - localparam int unsigned NumChimneys = (i == North || i == South) ? NumX : NumY; - - floo_vc_req_t [NumChimneys-1:0] req_hbm_in, req_hbm_out; - floo_vc_rsp_t [NumChimneys-1:0] rsp_hbm_in, rsp_hbm_out; - floo_vc_wide_t [NumChimneys-1:0] wide_hbm_in, wide_hbm_out; - id_t [NumChimneys-1:0] xy_id_hbm; - - if (i == North) begin : gen_north_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: j+1, y: NumY+1, port_id: 0}; - end - assign req_hbm_in = req_ver_pos[NumY]; - assign rsp_hbm_in = rsp_ver_pos[NumY]; - assign wide_hbm_in = wide_ver_pos[NumY]; - assign req_ver_neg[NumY] = req_hbm_out; - assign rsp_ver_neg[NumY] = rsp_hbm_out; - assign wide_ver_neg[NumY] = wide_hbm_out; - end - else if (i == South) begin : gen_south_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: j+1, y: 0, port_id: 0}; - end - assign req_hbm_in = req_ver_neg[0]; - assign rsp_hbm_in = rsp_ver_neg[0]; - assign wide_hbm_in = wide_ver_neg[0]; - assign req_ver_pos[0] = req_hbm_out; - assign rsp_ver_pos[0] = rsp_hbm_out; - assign wide_ver_pos[0] = wide_hbm_out; - end - else if (i == East) begin : gen_east_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: NumX+1, y: j+1, port_id: 0}; - end - assign req_hbm_in = req_hor_pos[NumX]; - assign rsp_hbm_in = rsp_hor_pos[NumX]; - assign wide_hbm_in = wide_hor_pos[NumX]; - assign req_hor_neg[NumX] = req_hbm_out; - assign rsp_hor_neg[NumX] = rsp_hbm_out; - assign wide_hor_neg[NumX] = wide_hbm_out; - end - else if (i == West) begin : gen_west_hbm_chimneys - for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: 0, y: j+1, port_id: 0}; - end - assign req_hbm_in = req_hor_neg[0]; - assign rsp_hbm_in = rsp_hor_neg[0]; - assign wide_hbm_in = wide_hor_neg[0]; - assign req_hor_pos[0] = req_hbm_out; - assign rsp_hor_pos[0] = rsp_hbm_out; - assign wide_hor_pos[0] = wide_hbm_out; - end - - floo_vc_narrow_wide_chimney #( - .AxiCfgN ( floo_test_pkg::AxiCfgN ), - .AxiCfgW ( floo_test_pkg::AxiCfgW ), - .ChimneyCfgN ( ChimneyCfg ), - .ChimneyCfgW ( ChimneyCfg ), - .RouteCfg ( floo_test_pkg::RouteCfg ), - .OutputDir ( route_direction_e'(i) ), - .NumVC ( Only1VC? 1 : (i==North||i==South)? 2:4 ), - .InputFifoDepth ( WormholeVCDepth ), - .VCDepth ( ChannelFifoDepth ), - .CreditShortcut ( CreditShortcut ), - .AllowVCOverflow ( AllowVCOverflow ), - .FixedWormholeVC ( FixedWormholeVC ), - .WormholeVCId ( i==East? 2: i==West? 1: 0 ), - .WormholeVCDepth ( WormholeVCDepth ), - .hdr_t ( hdr_t ), - .id_t ( id_t ), - .vc_id_t ( vc_id_t ), - .axi_narrow_in_req_t ( axi_narrow_in_req_t ), - .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_narrow_out_req_t ( axi_narrow_out_req_t ), - .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), - .axi_wide_in_req_t ( axi_wide_in_req_t ), - .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), - .axi_wide_out_req_t ( axi_wide_out_req_t ), - .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), - .floo_vc_req_t ( floo_vc_req_t ), - .floo_vc_rsp_t ( floo_vc_rsp_t ), - .floo_vc_wide_t ( floo_vc_wide_t ) - ) i_hbm_chimney [NumChimneys-1:0] ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .id_i ( xy_id_hbm ), - .route_table_i ( '0 ), - .id_route_map_i ( '0 ), - .axi_narrow_in_req_i ( '0 ), - .axi_narrow_in_rsp_o ( ), - .axi_narrow_out_req_o ( narrow_hbm_req[i] ), - .axi_narrow_out_rsp_i ( narrow_hbm_rsp[i] ), - .axi_wide_in_req_i ( '0 ), - .axi_wide_in_rsp_o ( ), - .axi_wide_out_req_o ( wide_hbm_req[i] ), - .axi_wide_out_rsp_i ( wide_hbm_rsp[i] ), - .floo_req_i ( req_hbm_in ), - .floo_req_o ( req_hbm_out ), - .floo_rsp_i ( rsp_hbm_in ), - .floo_rsp_o ( rsp_hbm_out ), - .floo_wide_i ( wide_hbm_in ), - .floo_wide_o ( wide_hbm_out ) - ); - end - - - - ////////////////// - // NoC Mesh // - ////////////////// - - for (genvar x = 0; x < NumX; x++) begin : gen_x - for (genvar y = 0; y < NumY; y++) begin : gen_y - id_t current_id; - localparam string NarrowDmaName = $sformatf("narrow_dma_%0d_%0d", x, y); - localparam string WideDmaName = $sformatf("wide_dma_%0d_%0d", x, y); - floo_vc_req_t [NumDirections-1:0] req_out, req_in; - floo_vc_rsp_t [NumDirections-1:0] rsp_out, rsp_in; - floo_vc_wide_t [NumDirections-1:0] wide_out, wide_in; - - localparam int unsigned Index = y * NumX + x+1; - localparam axi_narrow_addr_t MemBaseAddr = - (x+1) << floo_test_pkg::RouteCfg.XYAddrOffsetX | - (y+1) << floo_test_pkg::RouteCfg.XYAddrOffsetY; - assign current_id = '{x: x+1, y: y+1, port_id: 0}; - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgN) ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), - .axi_in_req_t ( axi_narrow_out_req_t ), - .axi_in_rsp_t ( axi_narrow_out_rsp_t ), - .axi_out_req_t ( axi_narrow_in_req_t ), - .axi_out_rsp_t ( axi_narrow_in_rsp_t ), - .JobId ( 100 + Index ) - ) i_narrow_dma_node ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( narrow_sub_req[x][y] ), - .axi_in_rsp_o ( narrow_sub_rsp[x][y] ), - .axi_out_req_o ( narrow_man_req[x][y] ), - .axi_out_rsp_i ( narrow_man_rsp[x][y] ), - .end_of_sim_o ( end_of_sim[x][y][0] ) - ); - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgW) ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), - .axi_in_req_t ( axi_wide_out_req_t ), - .axi_in_rsp_t ( axi_wide_out_rsp_t ), - .axi_out_req_t ( axi_wide_in_req_t ), - .axi_out_rsp_t ( axi_wide_in_rsp_t ), - .JobId ( Index ) - ) i_wide_dma_node ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( wide_sub_req[x][y] ), - .axi_in_rsp_o ( wide_sub_rsp[x][y] ), - .axi_out_req_o ( wide_man_req[x][y] ), - .axi_out_rsp_i ( wide_man_rsp[x][y] ), - .end_of_sim_o ( end_of_sim[x][y][1] ) - ); - - axi_bw_monitor #( - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ), - .AxiIdWidth ( floo_test_pkg::AxiCfgN.InIdWidth ), - .Name ( NarrowDmaName ) - ) i_axi_narrow_bw_monitor ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( end_of_sim[x][y][0] ), - .req_i ( narrow_man_req[x][y] ), - .rsp_i ( narrow_man_rsp[x][y] ), - .ar_in_flight_o( ), - .aw_in_flight_o( ) - ); - - axi_bw_monitor #( - .req_t ( axi_wide_in_req_t ), - .rsp_t ( axi_wide_in_rsp_t ), - .AxiIdWidth ( floo_test_pkg::AxiCfgW.InIdWidth ), - .Name ( WideDmaName ) - ) i_axi_wide_bw_monitor ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( end_of_sim[x][y][1] ), - .req_i ( wide_man_req[x][y] ), - .rsp_i ( wide_man_rsp[x][y] ), - .ar_in_flight_o( ), - .aw_in_flight_o( ) - ); - - floo_vc_narrow_wide_chimney #( - .AxiCfgN ( floo_test_pkg::AxiCfgN ), - .AxiCfgW ( floo_test_pkg::AxiCfgW ), - .ChimneyCfgN ( ChimneyCfg ), - .ChimneyCfgW ( ChimneyCfg ), - .RouteCfg ( floo_test_pkg::RouteCfg ), - .OutputDir ( Eject ), - .InputFifoDepth ( WormholeVCDepth ), - .NumVC ( NumVCLocal ), - .VCDepth ( ChannelFifoDepth ), - .CreditShortcut ( CreditShortcut ), - .AllowVCOverflow ( AllowVCOverflow ), - .FixedWormholeVC ( FixedWormholeVC ), - .WormholeVCId ( 0 ), - .WormholeVCDepth ( WormholeVCDepth ), - .hdr_t ( hdr_t ), - .id_t ( id_t ), - .vc_id_t ( vc_id_t ), - .axi_narrow_in_req_t ( axi_narrow_in_req_t ), - .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_narrow_out_req_t ( axi_narrow_out_req_t ), - .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), - .axi_wide_in_req_t ( axi_wide_in_req_t ), - .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), - .axi_wide_out_req_t ( axi_wide_out_req_t ), - .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), - .floo_vc_req_t ( floo_vc_req_t ), - .floo_vc_rsp_t ( floo_vc_rsp_t ), - .floo_vc_wide_t ( floo_vc_wide_t ) - ) i_dma_chimney ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .id_i ( current_id ), - .route_table_i ( '0 ), - .id_route_map_i ( '0 ), - .axi_narrow_in_req_i ( narrow_man_req[x][y] ), - .axi_narrow_in_rsp_o ( narrow_man_rsp[x][y] ), - .axi_narrow_out_req_o ( narrow_sub_req[x][y] ), - .axi_narrow_out_rsp_i ( narrow_sub_rsp[x][y] ), - .axi_wide_in_req_i ( wide_man_req[x][y] ), - .axi_wide_in_rsp_o ( wide_man_rsp[x][y] ), - .axi_wide_out_req_o ( wide_sub_req[x][y] ), - .axi_wide_out_rsp_i ( wide_sub_rsp[x][y] ), - .floo_req_i ( narrow_chimney_sub_req[x][y] ), - .floo_req_o ( narrow_chimney_man_req[x][y] ), - .floo_rsp_i ( narrow_chimney_man_rsp[x][y] ), - .floo_rsp_o ( narrow_chimney_sub_rsp[x][y] ), - .floo_wide_i ( wide_chimney_sub[x][y] ), - .floo_wide_o ( wide_chimney_man[x][y] ) - ); - - floo_vc_narrow_wide_router #( - .AxiCfgN ( floo_test_pkg::AxiCfgN ), - .AxiCfgW ( floo_test_pkg::AxiCfgW ), - .NumPorts ( int'(NumDirections) ), - .NumVC ( Only1VC ? - {1, 1, 1, 1, NumVCLocal} : - {2, 4, 2, 4, NumVCLocal} ), - .RouteAlgo ( floo_test_pkg::RouteCfg.RouteAlgo ), - .id_t ( id_t ), - .hdr_t ( hdr_t ), - .vc_id_t ( vc_id_t ), - .NumVCToOut ( Only1VC ? {1, 1, 1, 1, 1} : - {y==NumY-1 ? 1 : 2, - x==NumX-1 ? 1 : 4, - y==0 ? 1 : 2, - x==0 ? 1 : 4, - 1}), // only 1 towards hbm - .VCDepth ( ChannelFifoDepth ), - .CreditShortcut ( CreditShortcut ), - .AllowVCOverflow ( AllowVCOverflow ), - .FixedWormholeVC ( FixedWormholeVC ), - .SingleStage ( SingleStage ), - .WormholeVCDepth ( WormholeVCDepth ), - .AllowOverflowFromDeeperVC (AllowOverflowFromDeeperVC), - .WormholeVCId ( Only1VC? - {0, 0, 0, 0, 0} : - {0, 1, 0, 2, 0} ), - .floo_vc_req_t ( floo_vc_req_t ), - .floo_vc_rsp_t ( floo_vc_rsp_t ), - .floo_vc_wide_t ( floo_vc_wide_t ) - ) i_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .id_i ( current_id ), - .id_route_map_i ( '0 ), - .floo_req_i ( req_in ), - .floo_req_o ( req_out ), - .floo_rsp_i ( rsp_in ), - .floo_rsp_o ( rsp_out ), - .floo_wide_i ( wide_in ), - .floo_wide_o ( wide_out ) - ); - - // Eject - assign req_in[Eject] = narrow_chimney_man_req[x][y]; - assign narrow_chimney_sub_req[x][y] = req_out[Eject]; - assign rsp_in[Eject] = narrow_chimney_sub_rsp[x][y]; - assign narrow_chimney_man_rsp[x][y] = rsp_out[Eject]; - assign wide_in[Eject] = wide_chimney_man[x][y]; - assign wide_chimney_sub[x][y] = wide_out[Eject]; - - // East - assign req_in[East] = req_hor_neg[x+1][y]; - assign req_hor_pos[x+1][y] = req_out[East]; - assign rsp_in[East] = rsp_hor_neg[x+1][y]; - assign rsp_hor_pos[x+1][y] = rsp_out[East]; - assign wide_in[East] = wide_hor_neg[x+1][y]; - assign wide_hor_pos[x+1][y] = wide_out[East]; - - // West - assign req_in[West] = req_hor_pos[x][y]; - assign req_hor_neg[x][y] = req_out[West]; - assign rsp_in[West] = rsp_hor_pos[x][y]; - assign rsp_hor_neg[x][y] = rsp_out[West]; - assign wide_in[West] = wide_hor_pos[x][y]; - assign wide_hor_neg[x][y] = wide_out[West]; - - // North - assign req_in[North] = req_ver_neg[y+1][x]; - assign req_ver_pos[y+1][x] = req_out[North]; - assign rsp_in[North] = rsp_ver_neg[y+1][x]; - assign rsp_ver_pos[y+1][x] = rsp_out[North]; - assign wide_in[North] = wide_ver_neg[y+1][x]; - assign wide_ver_pos[y+1][x] = wide_out[North]; - - // South - assign req_in[South] = req_ver_pos[y][x]; - assign req_ver_neg[y][x] = req_out[South]; - assign rsp_in[South] = rsp_ver_pos[y][x]; - assign rsp_ver_neg[y][x] = rsp_out[South]; - assign wide_in[South] = wide_ver_pos[y][x]; - assign wide_ver_neg[y][x] = wide_out[South]; - - end - end - - initial begin - wait(&end_of_sim); - // Wait for some time - repeat (2) @(posedge clk); - // Stop the simulation - $stop; - end - -endmodule diff --git a/hw/tb/wave/tb_floo_dma_mesh.wave.tcl b/hw/tb/wave/tb_floo_dma_mesh.wave.tcl deleted file mode 100644 index ae48a561..00000000 --- a/hw/tb/wave/tb_floo_dma_mesh.wave.tcl +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2023 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -source hw/tb/wave/wave.tcl - -floo_wave_init - -set tb_name tb_floo_dma_mesh - -set routers [find instances -bydu floo_nw_router -nodu] -set num_y [regexp -all {x\[0\]} $routers] -set num_x [regexp -all {y\[0\]} $routers] - -for {set y 0} {$y < $num_y} {incr y} { - for {set x 0} {$x < $num_x} {incr x} { - set groups [list Node X=${x} Y=${y}] - floo_nw_chimney_wave $tb_name/gen_x[$x]/gen_y[$y]/i_dma_chimney [concat $groups [list Chimney]] - floo_router_wave $tb_name/gen_x[$x]/gen_y[$y]/i_router [concat $groups [list Router]] - - floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_narrow_bw_monitor/*in_flight_o $groups 1 - floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_wide_bw_monitor/*in_flight_o $groups 1 - } -} - -for {set y 0} {$y < $num_y} {incr y} { - # East - floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] 1 - # West - floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] 1 - -} - -for {set x 0} {$x < $num_x} {incr x} { - # North - floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[0]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] 1 - # South - floo_nw_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] 1 -} - -floo_wave_style diff --git a/hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl b/hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl deleted file mode 100644 index 4ac58083..00000000 --- a/hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2023 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -source hw/tb/wave/wave.tcl - -floo_wave_init - -set tb_name tb_floo_vc_dma_mesh - -set routers [find instances -bydu floo_vc_narrow_wide_router -nodu] -set num_y [regexp -all {x\[0\]} $routers] -set num_x [regexp -all {y\[0\]} $routers] - -for {set y 0} {$y < $num_y} {incr y} { - for {set x 0} {$x < $num_x} {incr x} { - set groups [list Node X=${x} Y=${y}] - floo_vc_narrow_wide_chimney_wave $tb_name/gen_x[$x]/gen_y[$y]/i_dma_chimney [concat $groups [list Chimney]] - floo_router_wave $tb_name/gen_x[$x]/gen_y[$y]/i_router [concat $groups [list Router]] - - floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_narrow_bw_monitor/*in_flight_o $groups 1 - floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_wide_bw_monitor/*in_flight_o $groups 1 - } -} - -for {set y 0} {$y < $num_y} {incr y} { - # East - floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] - # West - floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] - -} - -for {set x 0} {$x < $num_x} {incr x} { - # North - floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[0]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] - # South - floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] -} - -floo_wave_style From 58c511bfa9367f0df06187a0d2168c3284ad1067 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:39:02 +0200 Subject: [PATCH 31/34] bender: Remove special target for `vc_router` --- .gitlab-ci.yml | 2 -- Bender.yml | 5 ----- 2 files changed, 7 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4b4138b4..2b3dc8f3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -27,8 +27,6 @@ compile-vsim: stage: build needs: - collect-bender-sources - variables: - EXTRA_BENDER_FLAGS: "-t vc_router" script: - make compile-sim | tee compile.log 2>&1 - '! grep "\*\* Error" compile.log' diff --git a/Bender.yml b/Bender.yml index b4ab39d8..b59cd970 100644 --- a/Bender.yml +++ b/Bender.yml @@ -80,11 +80,6 @@ sources: - hw/tb/tb_floo_nw_chimney.sv - hw/tb/tb_floo_router.sv - hw/tb/tb_floo_rob.sv - - - target: all(test, vc_router) - include_dirs: - - hw/test/include - files: - hw/tb/tb_floo_vc_router.sv - target: all(test, axi_mesh) From c1da366becd042b1d2f49faa49da6171c18ba0b8 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:41:11 +0200 Subject: [PATCH 32/34] docs: Update README --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 1ff6a238..898c9f97 100644 --- a/README.md +++ b/README.md @@ -104,13 +104,13 @@ This repository includes the following NoC IPs: | Name | Description | Doc | | --- | --- | --- | | [floo_router](hw/floo_router.sv) | A simple router with configurable number of ports, physical and virtual channels, and input/output buffers | | -| [floo_narrow_wide_router](hw/floo_narrow_wide_router.sv) | Wrapper of a multi-link router for narrow and wide links | | +| [floo_nw_router](hw/floo_nw_router.sv) | Wrapper of a multi-link router for narrow and wide links | | ### Network Interfaces | Name | Description | Doc | | --- | --- | --- | | [floo_axi_chimney](hw/floo_axi_chimney.sv) | A bidirectional network interface for connecting AXI4 Buses to the NoC | | -| [floo_narrow_wide_chimney](hw/floo_narrow_wide_chimney.sv) | A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC | | +| [floo_nw_chimney](hw/floo_nw_chimney.sv) | A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC | | ### Common IPs | Name | Description | Doc | @@ -124,7 +124,7 @@ This repository includes the following NoC IPs: | [floo_rob](hw/floo_rob.sv) | A table-based Reorder Buffer | | | [floo_simple_rob](hw/floo_simple_rob.sv) | A simplistic low-complexity Reorder Buffer | | | [floo_rob_wrapper](hw/floo_simple_rob.sv) | A wrapper of all available types of RoBs including RoB-less version | | -| [floo_narrow_wide_join](hw/floo_narrow_wide_join.sv) | A mux for joining a narrow and wide AXI bus a single wide bus | | +| [floo_nw_join](hw/floo_nw_join.sv) | A mux for joining a narrow and wide AXI bus a single wide bus | | ### Verification IPs | Name | Description | Doc | From 933aeb304cb5bd705fc76e49a8de28546318e08a Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:46:25 +0200 Subject: [PATCH 33/34] docs: Update CHANGELOG --- CHANGELOG.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index ffa32d0b..e9dddc2b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -45,10 +45,12 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - The `name` field must be unique now, since it is used by `mgr_port_protocol` and `sbr_port_protocol` to reference the exact protocol. - All examples were adapted to reflect those changes. - A FlooGen configuration file now requires a `network_type` field, to determine the type of network to generate. The options are `axi` for single-AXI networks and `narrow-wide` for the narrow-wide AXI configurations. +- The system address map `Sam` is now sorted correctly and can be indexed with `ep_id_e` values. ### Fixed - A bug in the calcuation of the RoB offset in `floo_rob` was fixed. Previously, the allocation and the write process used the same counter in bursts for offset calculation, which resulted in wrong offsets. +- Routers with `XYRouting` do now use the global `id_offset`, which was previously not accounted for (or had to be specified manually). ### Removed @@ -57,6 +59,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - As the flit type definitions were moved to `typedef.svh`, the auto-generated `floo_*_pkg` packages were removed from the repository. Furthermore, all the (global) imports of those packages in the modules were replaced by parameters. - The testbench `tb_floo_nw_chimney` was removed since it was neither used nor maintained anymore. - The `IdIsPort` routing algorithm was removed since it can only be used for routes over a single router. The same functionality can be achieved with the `SourceRouting` algorithm. +- The `dma_mesh` testbench was removed in favor of `nw_mesh` and `axi_mesh` which use generated networks with _FlooGen_. #### FlooGen - The package generation was removed from _FlooGen_ since it is now handled by the `typedef.svh` file. Further, the `--only-pkg` and `--pkg-outdir` flags were removed from the _FlooGen_ CLI. From f2a38887fb26e16567d67652e15a68042f7954f4 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 18 Sep 2024 15:51:30 +0200 Subject: [PATCH 34/34] bender: Remove `vc_router` target --- Bender.yml | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/Bender.yml b/Bender.yml index b59cd970..35281513 100644 --- a/Bender.yml +++ b/Bender.yml @@ -42,24 +42,22 @@ sources: - hw/floo_axi_router.sv - hw/floo_nw_router.sv - - target: vc_router - files: - # Level 1 - - hw/vc_router_util/floo_credit_counter.sv - - hw/vc_router_util/floo_input_fifo.sv - - hw/vc_router_util/floo_input_port.sv - - hw/vc_router_util/floo_look_ahead_routing.sv - - hw/vc_router_util/floo_mux.sv - - hw/vc_router_util/floo_rr_arbiter.sv - - hw/vc_router_util/floo_sa_global.sv - - hw/vc_router_util/floo_sa_local.sv - - hw/vc_router_util/floo_vc_assignment.sv - - hw/vc_router_util/floo_vc_router_switch.sv - - hw/vc_router_util/floo_vc_selection.sv - # Level 2 - - hw/floo_vc_router.sv - - hw/floo_nw_vc_chimney.sv - - hw/floo_nw_vc_router.sv + # VC Router (Level 1) + - hw/vc_router_util/floo_credit_counter.sv + - hw/vc_router_util/floo_input_fifo.sv + - hw/vc_router_util/floo_input_port.sv + - hw/vc_router_util/floo_look_ahead_routing.sv + - hw/vc_router_util/floo_mux.sv + - hw/vc_router_util/floo_rr_arbiter.sv + - hw/vc_router_util/floo_sa_global.sv + - hw/vc_router_util/floo_sa_local.sv + - hw/vc_router_util/floo_vc_assignment.sv + - hw/vc_router_util/floo_vc_router_switch.sv + - hw/vc_router_util/floo_vc_selection.sv + # Level 2 + - hw/floo_vc_router.sv + - hw/floo_nw_vc_chimney.sv + - hw/floo_nw_vc_router.sv - target: test include_dirs: