diff --git a/Bender.lock b/Bender.lock
index a36bf3b2..a6bee9bb 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -22,8 +22,8 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6
-    version: 0.39.3
+    revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
+    version: 0.39.4
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -396,7 +396,7 @@ packages:
     dependencies:
     - axi_slice
   pulp-ethernet:
-    revision: 1f8f1776ec494773f8e6c48e16685eb35d5f445e
+    revision: 6ff3ef63f9b1e564f965691056ca374b32996b44
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp-ethernet.git
diff --git a/Bender.yml b/Bender.yml
index 45f1bf75..79f81a39 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -26,7 +26,7 @@ dependencies:
   can_bus:            { git: https://github.com/AlSaqr-platform/can_bus.git,            rev: 0ec0bf8b7dab6d5e4b3f7ec58338a8efee066379 } # branch: pulp
   spatz:              { git: https://github.com/pulp-platform/spatz.git,                rev: 98de97f24fe42675c9b4a8cc08354a03af57400a } # branch: yt/astral
   common_cells:       { git: https://github.com/pulp-platform/common_cells.git,         version: 1.37.0                               } # branch: master        
-  pulp-ethernet:      { git: https://github.com/pulp-platform/pulp-ethernet.git,        rev: 1f8f1776ec494773f8e6c48e16685eb35d5f445e } # branch: handshake
+  pulp-ethernet:      { git: https://github.com/pulp-platform/pulp-ethernet.git,        rev: 6ff3ef63f9b1e564f965691056ca374b32996b44 } # branch: handshake
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg.git,            version: =0.8.0                               }
 
 workspace:
diff --git a/sw/tests/bare-metal/hostd/ethernet.c b/sw/tests/bare-metal/hostd/ethernet.c
index 58f27754..1a7350a3 100644
--- a/sw/tests/bare-metal/hostd/ethernet.c
+++ b/sw/tests/bare-metal/hostd/ethernet.c
@@ -31,6 +31,7 @@ static dif_rv_plic_t plic0;
 #define IDMA_REQ_READY_OFFSET        0x40
 #define IDMA_RSP_READY_OFFSET        0x44
 #define IDMA_RSP_VALID_OFFSET        0x48
+#define IDMA_RX_EN_OFFSET            0x50
 
 #define RV_PLIC_PRIO87_REG_OFFSET    0x15c
 #define RV_PLIC_IE0_2_REG_OFFSET     0x2008
@@ -68,7 +69,7 @@ int main(void) {
 
   volatile uint64_t data_to_write[DATA_CHUNK] = {
         0x1032207098001032,
-        0x3210E20020709800,
+        0x3210400020709800,
         0x1716151413121110,
         0x2726252423222120,
         0x3736353433323130,
@@ -84,7 +85,7 @@ int main(void) {
   }
 
   fencei();
-  //// TX test
+  // TX test
   // Low 32 bit MAC Address
   *reg32(CAR_ETHERNET_BASE_ADDR, MACLO_OFFSET)          = 0x98001032;
   // High 16 bit Mac Address
@@ -102,20 +103,19 @@ int main(void) {
 
   // Validate Request to DMA
   *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_REQ_VALID_OFFSET) = 0x1;
-  
-  wfi();  // rx irq
 
   // RX test
-   // Low 32 bit MAC Address
+  wfi();  // rx irq
+  // Low 32 bit MAC Address
   *reg32(CAR_ETHERNET_BASE_ADDR, MACLO_OFFSET)          = 0x98001032;
   // High 16 bit Mac Address
   *reg32(CAR_ETHERNET_BASE_ADDR, MACHI_OFFSET)          = 0x00002070;
+  // dma length ready, dma can be configured now
+  while (!(*reg32(CAR_ETHERNET_BASE_ADDR,IDMA_RX_EN_OFFSET)));
   // DMA Source Address
   *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_ADDR_OFFSET)  = 0x0;
   // DMA Destination Address
   *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_ADDR_OFFSET)  = L2_RX_BASE;
-  // Data length
-  *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_LENGTH_OFFSET)    = DATA_CHUNK*BYTE_SIZE;
   // Source Protocol
   *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_PROTO_OFFSET) = 0x5;
   // Destination Protocol
diff --git a/target/sim/src/vip_carfield_soc.sv b/target/sim/src/vip_carfield_soc.sv
index df8aaee8..9ef7613f 100644
--- a/target/sim/src/vip_carfield_soc.sv
+++ b/target/sim/src/vip_carfield_soc.sv
@@ -109,6 +109,7 @@ module vip_carfield_soc
 
     logic reg_error;
     logic [RegDw-1:0] rx_rsp_valid;
+    logic dma_rx_en;
 
     typedef reg_test::reg_driver #(
       .AW(RegAw),
@@ -207,6 +208,13 @@ module vip_carfield_soc
 
     reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge periph_clk);
+    
+    while(1) begin
+      reg_drv_rx.send_read( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DMA_RX_EN_OFFSET, dma_rx_en, reg_error);   // req ready 
+      if( dma_rx_en )
+        break;
+      @(posedge periph_clk);
+    end
 
     reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR
     @(posedge periph_clk);
@@ -214,9 +222,6 @@ module vip_carfield_soc
     reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_ADDR_OFFSET, 32'h0, 'hf, reg_error); // DST_ADDR
     @(posedge periph_clk);
 
-    reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LENGTH_OFFSET, 32'h40,'hf , reg_error); // Size in bytes
-    @(posedge periph_clk);
-
     reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_PROTOCOL_OFFSET, 32'h5, 'hf , reg_error); // src protocol
     @(posedge periph_clk);