From 110aaa4ab534406a082c50cde5e72c07d8155e79 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Fri, 5 May 2023 16:26:37 +0200 Subject: [PATCH] fpga: Added ddr4 and vcu128 flow, added draft of Vivado IP simulation flow fpga: Added VIOs Connect VIO-generated reset signal to dram wrapper fpga: Support of zcu102 fpga: zcu102.xdc constraint file added fpga: zcu102 changed phy and added firsts constraints fpga: Switching to clk_wiz and xilinx.mk fpga: Testing ddr4 fpga: Start working on SPI driver fpga: SD card test fpga: Rolled-back SD fpga: Add vcu128 ci Co-Authored-By: Yann Picod --- Bender.yml | 4 +- README.md | 41 + cheshire.mk | 18 +- sw/boot/{cheshire.dts => cheshire.dtsi} | 12 +- sw/boot/cheshire_genesys2.dts | 18 + sw/boot/cheshire_vcu128.dts | 27 + sw/sw.mk | 4 +- target/xilinx/Makefile | 71 - target/xilinx/constraints/cheshire.xdc | 120 +- target/xilinx/constraints/genesys2.xdc | 159 +- target/xilinx/constraints/vcu128.xdc | 1803 +++++++++++++++++ target/xilinx/constraints/zcu102.xdc | 1100 ++++++++++ target/xilinx/scripts/flash_spi.tcl | 48 + target/xilinx/scripts/program.tcl | 25 +- target/xilinx/scripts/prologue.tcl | 2 +- target/xilinx/scripts/run.tcl | 88 +- target/xilinx/sim/run_simulation.tcl | 48 + target/xilinx/sim/setup_simulation.tcl | 35 + target/xilinx/sim/simulate.mk | 58 + target/xilinx/src/cheshire_top_xilinx.sv | 487 +++-- target/xilinx/src/dram_wrapper.sv | 441 ++++ target/xilinx/src/phy_definitions.svh | 93 + target/xilinx/xilinx.mk | 115 ++ target/xilinx/xilinx/common.mk | 1 + .../Makefile | 2 +- target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl | 113 ++ .../xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj | 7 +- target/xilinx/xilinx/xlnx_mig_ddr4/Makefile | 6 + .../xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl | 62 + .../xilinx/xlnx_protocol_checker/tcl/run.tcl | 40 - target/xilinx/xilinx/xlnx_vio/Makefile | 6 + target/xilinx/xilinx/xlnx_vio/tcl/run.tcl | 41 + 32 files changed, 4586 insertions(+), 509 deletions(-) rename sw/boot/{cheshire.dts => cheshire.dtsi} (94%) create mode 100644 sw/boot/cheshire_genesys2.dts create mode 100644 sw/boot/cheshire_vcu128.dts delete mode 100644 target/xilinx/Makefile create mode 100644 target/xilinx/constraints/vcu128.xdc create mode 100644 target/xilinx/constraints/zcu102.xdc create mode 100644 target/xilinx/scripts/flash_spi.tcl create mode 100644 target/xilinx/sim/run_simulation.tcl create mode 100644 target/xilinx/sim/setup_simulation.tcl create mode 100644 target/xilinx/sim/simulate.mk create mode 100644 target/xilinx/src/dram_wrapper.sv create mode 100644 target/xilinx/src/phy_definitions.svh create mode 100644 target/xilinx/xilinx.mk rename target/xilinx/xilinx/{xlnx_protocol_checker => xlnx_clk_wiz}/Makefile (85%) create mode 100644 target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl create mode 100644 target/xilinx/xilinx/xlnx_mig_ddr4/Makefile create mode 100644 target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl delete mode 100644 target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl create mode 100644 target/xilinx/xilinx/xlnx_vio/Makefile create mode 100644 target/xilinx/xilinx/xlnx_vio/tcl/run.tcl diff --git a/Bender.yml b/Bender.yml index b13581ff5..09b95cef4 100644 --- a/Bender.yml +++ b/Bender.yml @@ -50,7 +50,9 @@ sources: - target/sim/src/fixture_cheshire_soc.sv - target/sim/src/tb_cheshire_soc.sv - - target: all(fpga, xilinx) + - target: any(fpga, xilinx) files: - target/xilinx/src/fan_ctrl.sv + - target/xilinx/src/dram_wrapper.sv + - target/xilinx/src/phy_definitions.svh - target/xilinx/src/cheshire_top_xilinx.sv diff --git a/README.md b/README.md index e2a1dfe6e..f770fdf7f 100644 --- a/README.md +++ b/README.md @@ -27,6 +27,47 @@ make all If you have access to our internal servers, you can run `make nonfree-init` to fetch additional resources we cannot make publically accessible. Note that these are *not required* to use anything provided in this repository. +## Linux image + +To build the Linux image for FPGA: +```bash +# Clone and build GCC, OpenSBI, U-Boot and Linux +git clone git@github.com:pulp-platform/cva6-sdk.git --branch fix/cheshire +cd cva6-sdk +git submodule update --init --recursive +make images +# Link the output in the sw dir +ln -s cva6-sdk/install64 sw/boot/install64 +# Build the image at sw/boot/linux-[genesys2,vcu128].gpt.bin +make BOARD=[genesys2,vcu128] chs-linux-img + +``` + +On Genesys2, you can now flash this image to your sd card (require sudo). + +```bash +# Replace sdX by your SD card device +dd if=sw/boot/cheshire-linux-genesys2.gpt.bin of=/dev/sdX +``` + +On VCU128, you can now flash this image to the SPI using Vivado: + +```bash +# Define XILINX_PORT, XILINX_HOST, FPGA_PATH to let Vivado find your FPGA +# See defaults in xilinx.mk +make chs-xil-flash BOARD=vcu128 MODE=batch +``` + +## FPGA + +To build the bitstream for FPGA, initialize the repository with `make all` then run `make chs-xil-all` followed by desired arguments: + +* `BOARD=[genesys2,vcu128]`: select supported evaluation board (note `zcu102` is also supported but do not boot Linux as it does not provide access to an SPI flash or an SD card). +* `INT-JTAG=[1,0]`: (only on vcu128) connect the debugger to the intenal JTAG chain (see BSCANE2 primitive) or to an external JTAG dongle (if 0). +* `MODE=[batch,gui]`: open Vivado GUI or execute in shell. + +You can flash the bitstream from the GUI with `make chs-xil-gui` or directly in shell using `make chs-xil-program MODE=batch BOARD=[genesys2,vcu128]`. Here again you will need to define `XILINX_PORT`, `XILINX_HOST`, `FPGA_PATH` for your setup. At IIS, find default values in `carfield.mk`. + ## License Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see `LICENSE`) with the exception of generated register file code (e.g. `hw/regs/*.sv`), which is generated by a fork of lowRISC's [`regtool`](https://github.com/lowRISC/opentitan/blob/master/util/regtool.py) and licensed under Apache 2.0. All software sources are licensed under Apache 2.0. diff --git a/cheshire.mk b/cheshire.mk index 4f3dffa73..8d5d2e893 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -11,6 +11,9 @@ BENDER ?= bender VLOG_ARGS ?= -suppress 2583 -suppress 13314 VSIM ?= vsim +# Define board for FPGA flow and/or device tree selection +BOARD ?= genesys2 + # Define used paths (prefixed to avoid name conflicts) CHS_ROOT ?= $(shell $(BENDER) path cheshire) CHS_REG_DIR := $(shell $(BENDER) path register_interface) @@ -51,7 +54,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= 1c70a67 +CHS_NONFREE_COMMIT ?= d96f3a2 chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -150,13 +153,13 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl ############# -# FPGA Flow # +# Emulation # ############# -$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml - $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@ - -CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl +include $(CHS_ROOT)/target/xilinx/xilinx.mk +include $(CHS_XIL_DIR)/sim/simulate.mk +CHS_XILINX_ALL += $(CHS_XIL_DIR)/scripts/add_sources.tcl +CHS_LINUX_IMG += $(CHS_SW_DIR)/boot/linux-${BOARD}.gpt.bin ################################# # Phonies (KEEP AT END OF FILE) # @@ -164,7 +167,7 @@ CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl .PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all -CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL) +CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) chs-all: $(CHS_ALL) chs-sw-all: $(CHS_SW_ALL) @@ -172,3 +175,4 @@ chs-hw-all: $(CHS_HW_ALL) chs-bootrom-all: $(CHS_BOOTROM_ALL) chs-sim-all: $(CHS_SIM_ALL) chs-xilinx-all: $(CHS_XILINX_ALL) +chs-linux-img: $(CHS_LINUX_IMG) diff --git a/sw/boot/cheshire.dts b/sw/boot/cheshire.dtsi similarity index 94% rename from sw/boot/cheshire.dts rename to sw/boot/cheshire.dtsi index dbef5e505..76decc852 100644 --- a/sw/boot/cheshire.dts +++ b/sw/boot/cheshire.dtsi @@ -7,11 +7,13 @@ // Axel Vanoni /dts-v1/; + / { #address-cells = <2>; #size-cells = <2>; compatible = "eth,cheshire-dev"; model = "eth,cheshire"; + chosen { stdout-path = "/soc/serial@3002000:115200"; }; @@ -74,22 +76,16 @@ interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; reg = <0x0 0x3003000 0x0 0x1000>; }; - spi@3004000 { + spi: spi@3004000 { compatible = "opentitan,spi-host", "lowrisc,spi"; interrupt-parent = <&PLIC0>; interrupts = <17 18>; reg = <0x0 0x3004000 0x0 0x1000>; + num-cs = <2>; clock-frequency = <50000000>; max-frequency = <25000000>; #address-cells = <1>; #size-cells = <0>; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <25000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; }; vga@3007000 { compatible = "eth,axi-vga"; diff --git a/sw/boot/cheshire_genesys2.dts b/sw/boot/cheshire_genesys2.dts new file mode 100644 index 000000000..e26aa6f98 --- /dev/null +++ b/sw/boot/cheshire_genesys2.dts @@ -0,0 +1,18 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; // CS + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; diff --git a/sw/boot/cheshire_vcu128.dts b/sw/boot/cheshire_vcu128.dts new file mode 100644 index 000000000..c2a3528d5 --- /dev/null +++ b/sw/boot/cheshire_vcu128.dts @@ -0,0 +1,27 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <1>; + nor@1 { + #address-cells = <0x1>; + #size-cells = <0x1>; + // Note : u-boot does not find mt25qu02g + compatible = "mt25qu02g", "jedec,spi-nor"; + reg = <0x1>; // CS + spi-max-frequency = <25000000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + disable-wp; + partition@0 { + label = "all"; + reg = <0x0 0x6000000>; // 96 MB + read-only; + }; + }; +}; diff --git a/sw/sw.mk b/sw/sw.mk index 7c98cfc09..45ea76d27 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -113,7 +113,7 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*. $(CHS_SW_OBJCOPY) -O binary $< $@ %.dtb: %.dts - $(CHS_SW_DTC) -I dts -O dtb -o $@ $< + $(CHS_SW_DTC) -I dts -O dtb -i $(CHS_SW_DIR)/boot -o $@ $< %.memh: %.elf $(CHS_SW_OBJCOPY) -O verilog $< $@ @@ -134,7 +134,7 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*. $(CHS_SW_OBJCOPY) -I binary -O verilog $< $@ # Create full Linux disk image -$(CHS_SW_DIR)/boot/linux.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire.dtb $(CHS_SW_DIR)/boot/install64/fw_payload.bin $(CHS_SW_DIR)/boot/install64/uImage +$(CHS_SW_DIR)/boot/linux-${BOARD}.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire_$(BOARD).dtb $(CHS_SW_DIR)/boot/install64/fw_payload.bin $(CHS_SW_DIR)/boot/install64/uImage truncate -s $(CHS_SW_DISK_SIZE) $@ sgdisk --clear -g --set-alignment=1 \ --new=1:64:96 --typecode=1:$(CHS_SW_ZSL_TGUID) \ diff --git a/target/xilinx/Makefile b/target/xilinx/Makefile deleted file mode 100644 index 2bc7d1358..000000000 --- a/target/xilinx/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Nicole Narr -# Christopher Reinwardt - -PROJECT ?= cheshire -BOARD ?= genesys2 -XILINX_PART ?= xc7k325tffg900-2 -XILINX_BOARD ?= digilentinc.com:genesys2:part0:1.1 -XILINX_PORT ?= 3332 -XILINX_HOST ?= bordcomputer -FPGA_PATH ?= xilinx_tcf/Digilent/200300A8C60DB - -out := out -bit := $(out)/cheshire_top_xilinx.bit -mcs := $(out)/cheshire_top_xilinx.mcs -BIT ?= $(bit) - - -VIVADOENV ?= PROJECT=$(PROJECT) \ - BOARD=$(BOARD) \ - XILINX_PART=$(XILINX_PART) \ - XILINX_BOARD=$(XILINX_BOARD) \ - PORT=$(XILINX_PORT) \ - HOST=$(XILINX_HOST) \ - FPGA_PATH=$(FPGA_PATH) \ - BIT=$(BIT) - -# select IIS-internal tool commands if we run on IIS machines -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2022.1 vivado -else - VIVADO ?= vivado -endif - -VIVADOFLAGS ?= -nojournal -mode batch - -ip-dir := xilinx -ips := xlnx_mig_7_ddr3.xci - -all: $(mcs) - -# Generate mcs from bitstream -$(mcs): $(bit) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ - -$(bit): $(ips) - @mkdir -p $(out) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/prologue.tcl -source scripts/run.tcl - cp $(PROJECT).runs/impl_1/$(PROJECT)* ./$(out) - -$(ips): - @echo "Generating IP $(basename $@)" - cd $(ip-dir)/$(basename $@) && $(MAKE) clean && $(VIVADOENV) VIVADO="$(VIVADO)" $(MAKE) - cp $(ip-dir)/$(basename $@)/$(basename $@).srcs/sources_1/ip/$(basename $@)/$@ $@ - -gui: - @echo "Starting $(vivado) GUI" - @$(VIVADOENV) $(VIVADO) -nojournal -mode gui $(PROJECT).xpr & - -program: - @echo "Programming board $(BOARD) ($(XILINX_PART))" - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl - -clean: - rm -rf *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim - -.PHONY: - clean diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc index 398a8166b..0da9c9e4e 100644 --- a/target/xilinx/constraints/cheshire.xdc +++ b/target/xilinx/constraints/cheshire.xdc @@ -4,36 +4,25 @@ # # Nicole Narr # Christopher Reinwardt +# Cyril Koenig ################### # Global Settings # ################### -# Testmode is set to 0 during normal use -set_case_analysis 0 [get_ports test_mode_i] - # Preserve the output mux of the clock divider set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux] -# The pin of which we get the 200 MHz single ended clock from the MIG -set MIG_CLK_SRC {i_dram/ui_clk} +# The net of which we get the 200 MHz single ended clock from the MIG +set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]] ##################### # Timing Parameters # ##################### -# 200 MHz FPGA diff clock -set FPGA_TCK 5.0 - -# 50 MHz SoC clock -set SOC_TCK 20.0 - -# 10 MHz JTAG clock +# 10 MHz (max) JTAG clock set JTAG_TCK 100.0 -# I2C High-speed mode is 3.2 Mb/s -set I2C_IO_SPEED 312.5 - # UART speed is at most 5 Mb/s set UART_IO_SPEED 200.0 @@ -41,26 +30,40 @@ set UART_IO_SPEED 200.0 # Clocks # ########## +# Clk_wiz clocks +create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10] +create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20] +create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50] +create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100] + # System Clock -create_generated_clock -name clk_soc -source [get_pins $MIG_CLK_SRC] -divide_by 4 [get_pins i_sys_clk_div/i_clk_bypass_mux/i_BUFGMUX/O] +# [see in board.xdc] # JTAG Clock create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] set_input_jitter clk_jtag 1.000 +########## +# BUFG # +########## + +# JTAG are on non clock capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] + +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + ################ # Clock Groups # ################ # JTAG Clock is asynchronous to all other clocks -set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag] - -####################### -# Placement Overrides # -####################### - -# Accept suboptimal BUFG-BUFG cascades -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i] +set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} ######## # JTAG # @@ -75,32 +78,6 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK set_false_path -hold -from [get_ports jtag_trst_ni] -####### -# MIG # -####### - -set_max_delay -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] $FPGA_TCK -set_false_path -hold -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] - -######## -# SPIM # -######## - -set_input_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_input_delay -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] -set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] - -####### -# I2C # -####### - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] - ######## # UART # ######## @@ -111,43 +88,16 @@ set_false_path -hold -from [get_ports uart_rx_i] set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] set_false_path -hold -to [get_ports uart_tx_o] -####### -# VGA # -####### - -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*] - -############ -# Switches # -############ - -set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* test_mode_i}] -set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* test_mode_i}] - -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm] - -set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* test_mode_i}] -set_false_path -hold -from [get_ports {boot_mode* fan_sw* test_mode_i}] - -set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] -set_false_path -hold -to [get_ports fan_pwm] - ######## # CDCs # ######## -# cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew -set_property KEEP_HIERARCHY SOFT [get_cells i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync] -set_false_path -hold -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK - -################### -# Reset Generator # -################### +# Disable hold checks +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] +# src false path +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] +# dst false path +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] -set_max_delay -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] $SOC_TCK -set_false_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] +# Limit datapath delay +# [see in board.xdc] diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 7142b1593..0c71ca6f0 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -1,11 +1,110 @@ -#### This file is a general .xdc for the Genesys 2 Rev. H -#### To use it in a project: -#### - uncomment the lines corresponding to used pins -#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +##################### +# Timing Parameters # +##################### + +# 50 MHz SoC clock +set soc_clk clk_50 +set SOC_TCK 20.0 + +# I2C High-speed mode is 3.2 Mb/s +set I2C_IO_SPEED 312.5 + +########## +# Basics # +########## + +# Testmode is set to 0 during normal use +set_case_analysis 0 [get_ports testmode_i] + +# Remove annoying clk_mux +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +############# +# Sys clock # +############# + +# 200 MHz ref clock +set SYS_TCK 5 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +# Dram axi clock : ??? +set MIG_TCK 5 +set MIG_RST [get_nets i_dram_wrapper/dram_rst_o] +create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk] +set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk} +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK +set_max_delay -datapath -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $MIG_TCK + +####### +# VGA # +####### + +# set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports vga*] +# set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*] + +############ +# Switches # +############ + +set_input_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}] +set_input_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}] + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports fan_pwm] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports fan_pwm] + +set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* testmode_i}] +set_false_path -hold -from [get_ports {boot_mode* fan_sw* testmode_i}] + +set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] +set_false_path -hold -to [get_ports fan_pwm] + +######## +# SPIM # +######## + +set_input_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_input_delay -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_output_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] +set_output_delay -max -clock $soc_clk [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] + +####### +# I2C # +####### + +# set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] +# set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] + +# set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] +# set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] + +################################################################################# + +############### +# ASSIGN PINS # +############### ## Clock Signal -set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n -set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p ## Buttons #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc @@ -33,7 +132,7 @@ set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] #set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { test_mode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { testmode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] ## USB HIDs For Both Mouse and Keyboard #set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0] @@ -84,27 +183,27 @@ set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_scl #set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en ## VGA Connector -set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] -set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] -set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] -set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] -set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] - -set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] -set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] -set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] -set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] -set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] - -set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] -set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] -set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] -set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] -set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] - -set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs -set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs +# set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] +# set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] +# set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] +# set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] +# set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] + +# set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] +# set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] +# set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] +# set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] +# set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] +# set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] + +# set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] +# set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] +# set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] +# set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] +# set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] + +# set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs +# set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs ## HDMI in #set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec @@ -402,8 +501,8 @@ set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { jtag_t #set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3] ## IIC Bus -set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl -set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda +# set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl +# set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda ## Display Port IN #set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc new file mode 100644 index 000000000..d675b720c --- /dev/null +++ b/target/xilinx/constraints/vcu128.xdc @@ -0,0 +1,1803 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +############# +# Sys clock # +############# + +# 100 MHz ref clock +set SYS_TCK 10 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +# Dram axi clock : 833ps * 4 +set MIG_TCK 3.332 +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk} +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK +set_max_delay -datapath -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $MIG_TCK + + +################################################################################# + +############### +# ASSIGN PINS # +############### + +# VCU128 Rev1.0 XDC +# Date: 01/24/2018 + +#### This file is a general .xdc for the VCU128 1 Rev. +#### To use it in a project: +#### - uncomment the lines corresponding to used pins +#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + + +#set_property PACKAGE_PIN BF21 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 +#set_property PACKAGE_PIN BF22 [get_ports "ENET_PDWN_B_I_INT_B_O"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_PDWN_B_I_INT_B_O"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 +#set_property PACKAGE_PIN BH22 [get_ports "ENET_SGMII_IN_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_IN_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 +#set_property PACKAGE_PIN BG22 [get_ports "ENET_SGMII_IN_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_IN_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 +#set_property PACKAGE_PIN BJ21 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property PACKAGE_PIN BH21 [get_ports "QSFP4_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property PACKAGE_PIN BK21 [get_ports "ENET_SGMII_OUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_OUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 +#set_property PACKAGE_PIN BJ22 [get_ports "ENET_SGMII_OUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_OUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 +#set_property PACKAGE_PIN BK23 [get_ports "QSFP4_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 +#set_property PACKAGE_PIN BK24 [get_ports "QSFP4_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 +#set_property PACKAGE_PIN BL22 [get_ports "QSFP4_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property PACKAGE_PIN BL23 [get_ports "DUMMY_NC"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "DUMMY_NC"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property PACKAGE_PIN BG23 [get_ports "ENET_MDIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_MDIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 +#set_property PACKAGE_PIN BF23 [get_ports "QSFP4_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 +#set_property PACKAGE_PIN BH24 [get_ports "GPIO_LED_0_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_0_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 +#set_property PACKAGE_PIN BG24 [get_ports "GPIO_LED_1_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_1_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 +#set_property PACKAGE_PIN BG25 [get_ports "GPIO_LED_2_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_2_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 +#set_property PACKAGE_PIN BF25 [get_ports "GPIO_LED_3_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_3_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 +#set_property PACKAGE_PIN BF26 [get_ports "GPIO_LED_4_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_4_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property PACKAGE_PIN BF27 [get_ports "GPIO_LED_5_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_5_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property PACKAGE_PIN BG27 [get_ports "GPIO_LED_6_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_6_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 +#set_property PACKAGE_PIN BG28 [get_ports "GPIO_LED_7_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_7_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 +#set_property PACKAGE_PIN BJ23 [get_ports "ENET_CLKOUT"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_CLKOUT"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 +#set_property PACKAGE_PIN BJ24 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 +#set_property PACKAGE_PIN BH25 [get_ports "QSFP1_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 +#set_property PACKAGE_PIN BH26 [get_ports "QSFP1_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +#set_property PACKAGE_PIN BJ27 [get_ports "ENET_SGMII_CLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_CLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 +#set_property PACKAGE_PIN BH27 [get_ports "ENET_SGMII_CLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_CLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 +#set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 +#set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 +#set_property PACKAGE_PIN BL25 [get_ports "SMA_CLK_OUTPUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property IOSTANDARD LVDS [get_ports "SMA_CLK_OUTPUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property PACKAGE_PIN BK26 [get_ports "SMA_CLK_OUTPUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property IOSTANDARD LVDS [get_ports "SMA_CLK_OUTPUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property PACKAGE_PIN BK28 [get_ports "UART1_RXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_RXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 +#set_property PACKAGE_PIN BJ28 [get_ports "UART1_TXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_TXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 +#set_property PACKAGE_PIN BL26 [get_ports "UART1_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 +#set_property PACKAGE_PIN BL27 [get_ports "UART1_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 +#set_property PACKAGE_PIN BM27 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property PACKAGE_PIN BL28 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property PACKAGE_PIN BN27 [get_ports "ENET_MDC"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_MDC"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 +#set_property PACKAGE_PIN BP27 [get_ports "ENET_COL_GPIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_COL_GPIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 +#set_property PACKAGE_PIN BN22 [get_ports "SYSCTLR_UCA1_TX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_UCA1_TX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 +#set_property PACKAGE_PIN BM22 [get_ports "SYSCTLR_UCA1_RX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_UCA1_RX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 +#set_property PACKAGE_PIN BM23 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 +#set_property PACKAGE_PIN BM24 [get_ports "QSFP1_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 +#set_property PACKAGE_PIN BN25 [get_ports "QSFP1_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property PACKAGE_PIN BM25 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property PACKAGE_PIN BP24 [get_ports "QSFP1_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 +#set_property PACKAGE_PIN BN24 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 +set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +#set_property PACKAGE_PIN BP22 [get_ports "UART0_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART0_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 +#set_property PACKAGE_PIN BP23 [get_ports "UART0_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART0_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 +#set_property PACKAGE_PIN BE51 [get_ports "PL_DDR4_A5"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A5"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_66 +#set_property PACKAGE_PIN BD51 [get_ports "PL_DDR4_A1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_66 +#set_property PACKAGE_PIN BE50 [get_ports "PL_DDR4_A3"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A3"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_66 +#set_property PACKAGE_PIN BE49 [get_ports "PL_DDR4_A4"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A4"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_66 +#set_property PACKAGE_PIN BF48 [get_ports "PL_DDR4_A12"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A12"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_66 +#set_property PACKAGE_PIN BF47 [get_ports "PL_DDR4_A10"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A10"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property PACKAGE_PIN BF52 [get_ports "PL_DDR4_A13"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A13"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_66 +#set_property PACKAGE_PIN BF51 [get_ports "PL_DDR4_A8"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A8"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_66 +#set_property PACKAGE_PIN BG50 [get_ports "PL_DDR4_A7"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A7"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_66 +#set_property PACKAGE_PIN BF50 [get_ports "PL_DDR4_A0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_66 +#set_property PACKAGE_PIN BG49 [get_ports "PL_DDR4_A11"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A11"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_66 +#set_property PACKAGE_PIN BG48 [get_ports "PL_DDR4_A2"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A2"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property PACKAGE_PIN BG47 [get_ports "PL_DDR4_A9"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A9"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_66 +#set_property PACKAGE_PIN BF53 [get_ports "PL_DDR4_A6"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A6"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_66 +#set_property PACKAGE_PIN BE54 [get_ports "PL_DDR4_BA0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BA0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_66 +#set_property PACKAGE_PIN BE53 [get_ports "PL_DDR4_BA1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BA1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_66 +#set_property PACKAGE_PIN BG54 [get_ports "PL_DDR4_BG0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BG0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_66 +#set_property PACKAGE_PIN BG53 [get_ports "PL_DDR4_WE_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_WE_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_66 +#set_property PACKAGE_PIN BJ54 [get_ports "PL_DDR4_RAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_RAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_66 +#set_property PACKAGE_PIN BH54 [get_ports "PL_DDR4_CAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_CAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_66 +#set_property PACKAGE_PIN BK54 [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_66 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_66 +#set_property PACKAGE_PIN BK53 [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_66 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_66 +#set_property PACKAGE_PIN BH52 [get_ports "PL_DDR4_CKE"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_CKE"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_66 +#set_property PACKAGE_PIN BG52 [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_66 +#set_property PACKAGE_PIN BJ53 [get_ports "PL_DDR4_TEN"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_TEN"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_66 +#set_property PACKAGE_PIN BJ52 [get_ports "PL_DDR4_ALERT_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_ALERT_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_66 +#set_property PACKAGE_PIN BH50 [get_ports "PL_DDR4_RE#set_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_66 +#set_property IOSTANDARD LVCMOS12 [get_ports "PL_DDR4_RE#set_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_66 +#set_property PACKAGE_PIN BH49 [get_ports "PL_DDR4_ODT"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_ODT"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_66 +#set_property PACKAGE_PIN BJ51 [get_ports "DDR4_CLK_100MHZ_N"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_66 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CLK_100MHZ_N"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_66 +#set_property PACKAGE_PIN BH51 [get_ports "DDR4_CLK_100MHZ_P"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_66 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CLK_100MHZ_P"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_66 +#set_property PACKAGE_PIN BJ47 [get_ports "SYSCTLR_GPIO_0_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_66 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSCTLR_GPIO_0_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_66 +#set_property PACKAGE_PIN BH47 [get_ports "SYSCTLR_GPIO_1_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_66 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSCTLR_GPIO_1_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_66 +#set_property PACKAGE_PIN BJ49 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_66 +#set_property PACKAGE_PIN BJ48 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_66 +#set_property PACKAGE_PIN BK51 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_66 +#set_property PACKAGE_PIN BK50 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_66 +#set_property PACKAGE_PIN BK49 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_66 +#set_property PACKAGE_PIN BK48 [get_ports "PL_DDR4_BOT_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BOT_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property PACKAGE_PIN BL48 [get_ports "PL_DDR4_PARITY"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_PARITY"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_66 +#set_property PACKAGE_PIN BL50 [get_ports "VRP_66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_66 +#set_property PACKAGE_PIN BL53 [get_ports "PL_DDR4_DQ69"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ69"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_66 +#set_property PACKAGE_PIN BL52 [get_ports "PL_DDR4_DQ67"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ67"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_66 +#set_property PACKAGE_PIN BM52 [get_ports "PL_DDR4_DQ65"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ65"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_66 +#set_property PACKAGE_PIN BL51 [get_ports "PL_DDR4_DQ71"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ71"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_66 +#set_property PACKAGE_PIN BM50 [get_ports "PL_DDR4_DQS8_C"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_66 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS8_C"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_66 +#set_property PACKAGE_PIN BM49 [get_ports "PL_DDR4_DQS8_T"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS8_T"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property PACKAGE_PIN BN49 [get_ports "PL_DDR4_DQ70"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ70"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_66 +#set_property PACKAGE_PIN BM48 [get_ports "PL_DDR4_DQ68"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ68"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_66 +#set_property PACKAGE_PIN BN51 [get_ports "PL_DDR4_DQ64"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ64"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_66 +#set_property PACKAGE_PIN BN50 [get_ports "PL_DDR4_DQ66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_66 +#set_property PACKAGE_PIN BP49 [get_ports "PL_DDR4_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_66 +#set_property IOSTANDARD SSTL12 [get_ports "PL_DDR4_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_66 +#set_property PACKAGE_PIN BP48 [get_ports "PL_DDR4_DM8_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM8_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_66 +#set_property PACKAGE_PIN BE44 [get_ports "PL_DDR4_DQ30"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_DOUT_CSO_B_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ30"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_DOUT_CSO_B_65 +#set_property PACKAGE_PIN BE43 [get_ports "PL_DDR4_DQ24"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_EMCCLK_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ24"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_EMCCLK_65 +#set_property PACKAGE_PIN BD42 [get_ports "PL_DDR4_DQ28"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ28"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property PACKAGE_PIN BC42 [get_ports "PL_DDR4_DQ26"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ26"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property PACKAGE_PIN BE46 [get_ports "PL_DDR4_DQS3_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS3_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property PACKAGE_PIN BE45 [get_ports "PL_DDR4_DQS3_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS3_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property PACKAGE_PIN BF43 [get_ports "PL_DDR4_DQ27"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_D07_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ27"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_D07_65 +#set_property PACKAGE_PIN BF42 [get_ports "PL_DDR4_DQ25"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ25"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property PACKAGE_PIN BF46 [get_ports "PL_DDR4_DQ31"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_D09_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ31"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_D09_65 +#set_property PACKAGE_PIN BF45 [get_ports "PL_DDR4_DQ29"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_D08_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ29"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_D08_65 +#set_property PACKAGE_PIN BE41 [get_ports "SYSMON_SDA_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSMON_SDA_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +#set_property PACKAGE_PIN BD41 [get_ports "PL_DDR4_DM3_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM3_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +#set_property PACKAGE_PIN BF41 [get_ports "PCIE_EP_PERST_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_PERSTN0_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "PCIE_EP_PERST_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_PERSTN0_65 +#set_property PACKAGE_PIN BH41 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_CSI_ADV_B_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_CSI_ADV_B_65 +#set_property PACKAGE_PIN BG45 [get_ports "PL_DDR4_DQ21"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_D13_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ21"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_D13_65 +#set_property PACKAGE_PIN BG44 [get_ports "PL_DDR4_DQ17"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_D12_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ17"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_D12_65 +#set_property PACKAGE_PIN BG43 [get_ports "PL_DDR4_DQ22"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_D15_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ22"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_D15_65 +#set_property PACKAGE_PIN BG42 [get_ports "PL_DDR4_DQ18"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_D14_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ18"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_D14_65 +#set_property PACKAGE_PIN BJ46 [get_ports "PL_DDR4_DQS2_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS2_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +#set_property PACKAGE_PIN BH46 [get_ports "PL_DDR4_DQS2_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS2_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property PACKAGE_PIN BK41 [get_ports "PL_DDR4_DQ16"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ16"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property PACKAGE_PIN BJ41 [get_ports "PL_DDR4_DQ23"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_A02_D18_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ23"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_A02_D18_65 +#set_property PACKAGE_PIN BH45 [get_ports "PL_DDR4_DQ20"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_A05_D21_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ20"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_A05_D21_65 +#set_property PACKAGE_PIN BH44 [get_ports "PL_DDR4_DQ19"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_A04_D20_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ19"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_A04_D20_65 +#set_property PACKAGE_PIN BJ42 [get_ports "PCIE_EP_WAKE_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "PCIE_EP_WAKE_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +#set_property PACKAGE_PIN BH42 [get_ports "PL_DDR4_DM2_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM2_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +#set_property PACKAGE_PIN BJ44 [get_ports "PL_DDR4_DQ13"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ13"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property PACKAGE_PIN BJ43 [get_ports "PL_DDR4_DQ15"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ15"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property PACKAGE_PIN BK44 [get_ports "PL_DDR4_DQ9"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_A11_D27_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ9"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_A11_D27_65 +#set_property PACKAGE_PIN BK43 [get_ports "PL_DDR4_DQ11"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_A10_D26_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ11"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_A10_D26_65 +#set_property PACKAGE_PIN BK46 [get_ports "PL_DDR4_DQS1_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS1_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +#set_property PACKAGE_PIN BK45 [get_ports "PL_DDR4_DQS1_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS1_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +#set_property PACKAGE_PIN BL43 [get_ports "PL_DDR4_DQ12"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_A15_D31_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ12"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_A15_D31_65 +#set_property PACKAGE_PIN BL42 [get_ports "PL_DDR4_DQ14"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_A14_D30_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ14"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_A14_D30_65 +#set_property PACKAGE_PIN BL46 [get_ports "PL_DDR4_DQ10"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_A17_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ10"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_A17_65 +#set_property PACKAGE_PIN BL45 [get_ports "PL_DDR4_DQ8"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_A16_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ8"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_A16_65 +#set_property PACKAGE_PIN BM47 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +#set_property PACKAGE_PIN BL47 [get_ports "PL_DDR4_DM1_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM1_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +#set_property PACKAGE_PIN BM42 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_SMBALERT_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_SMBALERT_65 +#set_property PACKAGE_PIN BM43 [get_ports "VRP_65"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_A28_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_A28_65 +#set_property PACKAGE_PIN BN45 [get_ports "PL_DDR4_DQ3"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_A21_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ3"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_A21_65 +#set_property PACKAGE_PIN BM45 [get_ports "PL_DDR4_DQ0"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_A20_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ0"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_A20_65 +#set_property PACKAGE_PIN BN44 [get_ports "PL_DDR4_DQ5"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_A23_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ5"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_A23_65 +#set_property PACKAGE_PIN BM44 [get_ports "PL_DDR4_DQ4"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_A22_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ4"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_A22_65 +#set_property PACKAGE_PIN BP46 [get_ports "PL_DDR4_DQS0_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS0_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +#set_property PACKAGE_PIN BN46 [get_ports "PL_DDR4_DQS0_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS0_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +#set_property PACKAGE_PIN BP44 [get_ports "PL_DDR4_DQ1"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_A27_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ1"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_A27_65 +#set_property PACKAGE_PIN BP43 [get_ports "PL_DDR4_DQ7"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_A26_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ7"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_A26_65 +#set_property PACKAGE_PIN BP47 [get_ports "PL_DDR4_DQ2"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_FWE_FCS2_B_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ2"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_FWE_FCS2_B_65 +#set_property PACKAGE_PIN BN47 [get_ports "PL_DDR4_DQ6"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_FOE_B_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ6"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_FOE_B_65 +#set_property PACKAGE_PIN BP42 [get_ports "SYSMON_SCL_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_RS1_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSMON_SCL_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_RS1_65 +#set_property PACKAGE_PIN BN42 [get_ports "PL_DDR4_DM0_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_RS0_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM0_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_RS0_65 +#set_property PACKAGE_PIN BJ31 [get_ports "PL_DDR4_DQ58"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ58"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_64 +#set_property PACKAGE_PIN BH31 [get_ports "PL_DDR4_DQ60"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ60"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_64 +#set_property PACKAGE_PIN BF33 [get_ports "PL_DDR4_DQ63"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ63"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_64 +#set_property PACKAGE_PIN BF32 [get_ports "PL_DDR4_DQ61"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ61"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_64 +#set_property PACKAGE_PIN BK30 [get_ports "PL_DDR4_DQS7_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS7_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 +#set_property PACKAGE_PIN BJ29 [get_ports "PL_DDR4_DQS7_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS7_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 +#set_property PACKAGE_PIN BG32 [get_ports "PL_DDR4_DQ59"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ59"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_64 +#set_property PACKAGE_PIN BF31 [get_ports "PL_DDR4_DQ56"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ56"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_64 +#set_property PACKAGE_PIN BH30 [get_ports "PL_DDR4_DQ57"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ57"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_64 +#set_property PACKAGE_PIN BH29 [get_ports "PL_DDR4_DQ62"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ62"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_64 +#set_property PACKAGE_PIN BG30 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 +#set_property PACKAGE_PIN BG29 [get_ports "PL_DDR4_DM7_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM7_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property PACKAGE_PIN BK29 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_64 +#set_property PACKAGE_PIN BG33 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_64 +#set_property PACKAGE_PIN BH35 [get_ports "PL_DDR4_DQ51"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ51"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_64 +#set_property PACKAGE_PIN BH34 [get_ports "PL_DDR4_DQ50"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ50"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_64 +#set_property PACKAGE_PIN BF36 [get_ports "PL_DDR4_DQ55"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ55"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_64 +#set_property PACKAGE_PIN BF35 [get_ports "PL_DDR4_DQ53"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ53"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_64 +#set_property PACKAGE_PIN BK35 [get_ports "PL_DDR4_DQS6_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS6_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 +#set_property PACKAGE_PIN BK34 [get_ports "PL_DDR4_DQS6_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS6_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 +#set_property PACKAGE_PIN BG35 [get_ports "PL_DDR4_DQ49"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ49"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_64 +#set_property PACKAGE_PIN BG34 [get_ports "PL_DDR4_DQ54"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ54"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_64 +#set_property PACKAGE_PIN BJ34 [get_ports "PL_DDR4_DQ48"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ48"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_64 +#set_property PACKAGE_PIN BJ33 [get_ports "PL_DDR4_DQ52"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ52"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_64 +#set_property PACKAGE_PIN BJ32 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_64 +#set_property PACKAGE_PIN BH32 [get_ports "PL_DDR4_DM6_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM6_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_64 +#set_property PACKAGE_PIN BL33 [get_ports "PL_DDR4_DQ45"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ45"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_64 +#set_property PACKAGE_PIN BK33 [get_ports "PL_DDR4_DQ43"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ43"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_64 +#set_property PACKAGE_PIN BL31 [get_ports "PL_DDR4_DQ44"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ44"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_64 +#set_property PACKAGE_PIN BK31 [get_ports "PL_DDR4_DQ47"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ47"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_64 +#set_property PACKAGE_PIN BM35 [get_ports "PL_DDR4_DQS5_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS5_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 +#set_property PACKAGE_PIN BL35 [get_ports "PL_DDR4_DQS5_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS5_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property PACKAGE_PIN BM33 [get_ports "PL_DDR4_DQ46"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ46"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_64 +#set_property PACKAGE_PIN BL32 [get_ports "PL_DDR4_DQ40"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ40"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_64 +#set_property PACKAGE_PIN BP34 [get_ports "PL_DDR4_DQ41"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ41"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_64 +#set_property PACKAGE_PIN BN34 [get_ports "PL_DDR4_DQ42"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ42"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_64 +#set_property PACKAGE_PIN BN35 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 +#set_property PACKAGE_PIN BM34 [get_ports "PL_DDR4_DM5_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM5_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property PACKAGE_PIN BP33 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_64 +#set_property PACKAGE_PIN BM32 [get_ports "VRP_64"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_64"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_64 +#set_property PACKAGE_PIN BP32 [get_ports "PL_DDR4_DQ32"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ32"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_64 +#set_property PACKAGE_PIN BN32 [get_ports "PL_DDR4_DQ36"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ36"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_64 +#set_property PACKAGE_PIN BM30 [get_ports "PL_DDR4_DQ37"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ37"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_64 +#set_property PACKAGE_PIN BL30 [get_ports "PL_DDR4_DQ39"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ39"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_64 +#set_property PACKAGE_PIN BN30 [get_ports "PL_DDR4_DQS4_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS4_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 +#set_property PACKAGE_PIN BN29 [get_ports "PL_DDR4_DQS4_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS4_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 +#set_property PACKAGE_PIN BP31 [get_ports "PL_DDR4_DQ34"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ34"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_64 +#set_property PACKAGE_PIN BN31 [get_ports "PL_DDR4_DQ38"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ38"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_64 +#set_property PACKAGE_PIN BP29 [get_ports "PL_DDR4_DQ33"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ33"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_64 +#set_property PACKAGE_PIN BP28 [get_ports "PL_DDR4_DQ35"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ35"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_64 +set_property PACKAGE_PIN BM29 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] +#set_property PACKAGE_PIN BM28 [get_ports "PL_DDR4_DM4_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM4_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_64 +#set_property PACKAGE_PIN A16 [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 +#set_property PACKAGE_PIN B16 [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 71 VCCO - VADJ - IO_L24P_T3U_N10_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 71 VCCO - VADJ - IO_L24P_T3U_N10_71 +#set_property PACKAGE_PIN A18 [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 71 VCCO - VADJ - IO_L23N_T3U_N9_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 71 VCCO - VADJ - IO_L23N_T3U_N9_71 +#set_property PACKAGE_PIN A19 [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 71 VCCO - VADJ - IO_L23P_T3U_N8_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 71 VCCO - VADJ - IO_L23P_T3U_N8_71 +#set_property PACKAGE_PIN A20 [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property PACKAGE_PIN A21 [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property PACKAGE_PIN B17 [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 71 VCCO - VADJ - IO_L21N_T3L_N5_AD8N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 71 VCCO - VADJ - IO_L21N_T3L_N5_AD8N_71 +#set_property PACKAGE_PIN B18 [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 71 VCCO - VADJ - IO_L21P_T3L_N4_AD8P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 71 VCCO - VADJ - IO_L21P_T3L_N4_AD8P_71 +#set_property PACKAGE_PIN B20 [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 71 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 71 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_71 +#set_property PACKAGE_PIN B21 [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 71 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 71 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_71 +#set_property PACKAGE_PIN C17 [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 71 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 71 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_71 +#set_property PACKAGE_PIN C18 [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 71 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 71 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_71 +#set_property PACKAGE_PIN C19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T3U_N12_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T3U_N12_71 +#set_property PACKAGE_PIN C20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T2U_N12_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T2U_N12_71 +#set_property PACKAGE_PIN D19 [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 71 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 71 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_71 +#set_property PACKAGE_PIN D20 [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 +#set_property PACKAGE_PIN D16 [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 71 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 71 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_71 +#set_property PACKAGE_PIN D17 [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 71 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 71 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_71 +#set_property PACKAGE_PIN D21 [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 71 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 71 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_71 +#set_property PACKAGE_PIN E21 [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 71 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 71 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_71 +#set_property PACKAGE_PIN E16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_71 +#set_property PACKAGE_PIN F16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_71 +#set_property PACKAGE_PIN E18 [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L14N_T2L_N3_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L14N_T2L_N3_GC_71 +#set_property PACKAGE_PIN E19 [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L14P_T2L_N2_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L14P_T2L_N2_GC_71 +#set_property PACKAGE_PIN E17 [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_71 +#set_property PACKAGE_PIN F18 [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_71 +#set_property PACKAGE_PIN F19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12N_T1U_N11_GC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12N_T1U_N11_GC_71 +#set_property PACKAGE_PIN F20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12P_T1U_N10_GC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12P_T1U_N10_GC_71 +#set_property PACKAGE_PIN G17 [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 71 VCCO - VADJ - IO_L11N_T1U_N9_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 71 VCCO - VADJ - IO_L11N_T1U_N9_GC_71 +#set_property PACKAGE_PIN G18 [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 71 VCCO - VADJ - IO_L11P_T1U_N8_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 71 VCCO - VADJ - IO_L11P_T1U_N8_GC_71 +#set_property PACKAGE_PIN F21 [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 71 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 71 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_71 +#set_property PACKAGE_PIN G21 [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 71 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 71 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_71 +#set_property PACKAGE_PIN H18 [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 71 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 71 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_71 +#set_property PACKAGE_PIN H19 [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 71 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 71 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_71 +#set_property PACKAGE_PIN G20 [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 71 VCCO - VADJ - IO_L8N_T1L_N3_AD5N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 71 VCCO - VADJ - IO_L8N_T1L_N3_AD5N_71 +#set_property PACKAGE_PIN H20 [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 71 VCCO - VADJ - IO_L8P_T1L_N2_AD5P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 71 VCCO - VADJ - IO_L8P_T1L_N2_AD5P_71 +#set_property PACKAGE_PIN G16 [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 71 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 71 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_71 +#set_property PACKAGE_PIN H17 [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 71 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 71 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_71 +#set_property PACKAGE_PIN J16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T1U_N12_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T1U_N12_71 +#set_property PACKAGE_PIN J17 [get_ports "VRP_71"] ;# Bank 71 VCCO - VADJ - IO_T0U_N12_VRP_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_71"] ;# Bank 71 VCCO - VADJ - IO_T0U_N12_VRP_71 +#set_property PACKAGE_PIN J19 [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 71 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 71 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_71 +#set_property PACKAGE_PIN J20 [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 71 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 71 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_71 +#set_property PACKAGE_PIN J21 [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 71 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 71 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_71 +#set_property PACKAGE_PIN K21 [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 71 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 71 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_71 +#set_property PACKAGE_PIN K18 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_71 +#set_property PACKAGE_PIN K19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_71 +#set_property PACKAGE_PIN L20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_71 +#set_property PACKAGE_PIN L21 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_71 +#set_property PACKAGE_PIN L18 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2N_T0L_N3_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2N_T0L_N3_71 +#set_property PACKAGE_PIN L19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2P_T0L_N2_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2P_T0L_N2_71 +#set_property PACKAGE_PIN K16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1N_T0L_N1_DBC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1N_T0L_N1_DBC_71 +#set_property PACKAGE_PIN K17 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1P_T0L_N0_DBC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1P_T0L_N0_DBC_71 +#set_property PACKAGE_PIN A8 [get_ports "QDR4_DQB31"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB31"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_70 +#set_property PACKAGE_PIN A9 [get_ports "QDR4_DQB32"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB32"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_70 +#set_property PACKAGE_PIN A10 [get_ports "QDR4_DQB35"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB35"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_70 +#set_property PACKAGE_PIN A11 [get_ports "QDR4_DQB28"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB28"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_70 +#set_property PACKAGE_PIN A13 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_70 +#set_property PACKAGE_PIN B13 [get_ports "QDR4_DQB29"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB29"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_70 +#set_property PACKAGE_PIN B12 [get_ports "QDR4_DQB30"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB30"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_70 +#set_property PACKAGE_PIN C12 [get_ports "QDR4_DQB27"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB27"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_70 +#set_property PACKAGE_PIN B10 [get_ports "QDR4_DQB34"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB34"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_70 +#set_property PACKAGE_PIN B11 [get_ports "QDR4_DQB33"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB33"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_70 +#set_property PACKAGE_PIN C9 [get_ports "QDR4_DKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_70 +#set_property PACKAGE_PIN C10 [get_ports "QDR4_DKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_70 +#set_property PACKAGE_PIN C13 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_70 +#set_property PACKAGE_PIN C14 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_70 +#set_property PACKAGE_PIN A14 [get_ports "QDR4_DQB19"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB19"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_70 +#set_property PACKAGE_PIN A15 [get_ports "QDR4_DQB25"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB25"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_70 +#set_property PACKAGE_PIN B15 [get_ports "QDR4_DQB21"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB21"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_70 +#set_property PACKAGE_PIN C15 [get_ports "QDR4_DQB23"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB23"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_70 +#set_property PACKAGE_PIN D14 [get_ports "QDR4_QVLDB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_70 +#set_property PACKAGE_PIN D15 [get_ports "QDR4_DQB20"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB20"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_70 +#set_property PACKAGE_PIN E14 [get_ports "QDR4_DQB18"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB18"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_70 +#set_property PACKAGE_PIN F15 [get_ports "QDR4_DQB24"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB24"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_70 +#set_property PACKAGE_PIN F13 [get_ports "QDR4_DQB22"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB22"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_70 +#set_property PACKAGE_PIN F14 [get_ports "QDR4_DQB26"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB26"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_70 +#set_property PACKAGE_PIN D12 [get_ports "QDR4_QKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_70 +#set_property PACKAGE_PIN E13 [get_ports "QDR4_QKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_70 +#set_property PACKAGE_PIN E11 [get_ports "QDR4_DQB12"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB12"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_70 +#set_property PACKAGE_PIN F11 [get_ports "QDR4_DQB16"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB16"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_70 +#set_property PACKAGE_PIN D11 [get_ports "QDR4_DQB17"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB17"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_70 +#set_property PACKAGE_PIN E12 [get_ports "QDR4_DQB10"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB10"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_70 +#set_property PACKAGE_PIN D9 [get_ports "QDR4_QVLDB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_70 +#set_property PACKAGE_PIN D10 [get_ports "QDR4_DQB13"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB13"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_70 +#set_property PACKAGE_PIN E9 [get_ports "QDR4_DQB14"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB14"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_70 +#set_property PACKAGE_PIN F9 [get_ports "QDR4_DQB15"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB15"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_70 +#set_property PACKAGE_PIN F10 [get_ports "QDR4_DQB11"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB11"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_70 +#set_property PACKAGE_PIN G11 [get_ports "QDR4_DQB9"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB9"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_70 +#set_property PACKAGE_PIN G10 [get_ports "QDR4_QKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_70 +#set_property PACKAGE_PIN H10 [get_ports "QDR4_QKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_70 +#set_property PACKAGE_PIN H9 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_70 +#set_property PACKAGE_PIN G12 [get_ports "VRP_70"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_70"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_70 +#set_property PACKAGE_PIN G13 [get_ports "QDR4_DQB5"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB5"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_70 +#set_property PACKAGE_PIN H14 [get_ports "QDR4_DQB4"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB4"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_70 +#set_property PACKAGE_PIN H12 [get_ports "QDR4_DQB7"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB7"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_70 +#set_property PACKAGE_PIN H13 [get_ports "QDR4_DQB8"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB8"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_70 +#set_property PACKAGE_PIN G15 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_70 +#set_property PACKAGE_PIN H15 [get_ports "QDR4_DQB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_70 +#set_property PACKAGE_PIN J11 [get_ports "QDR4_DQB3"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB3"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_70 +#set_property PACKAGE_PIN J12 [get_ports "QDR4_DQB2"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB2"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_70 +#set_property PACKAGE_PIN J14 [get_ports "QDR4_DQB6"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB6"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_70 +#set_property PACKAGE_PIN J15 [get_ports "QDR4_DQB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_70 +#set_property PACKAGE_PIN K13 [get_ports "QDR4_DKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_70 +#set_property PACKAGE_PIN K14 [get_ports "QDR4_DKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_70 +#set_property PACKAGE_PIN BF1 [get_ports "QDR4_A1"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A1"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_69 +#set_property PACKAGE_PIN BE1 [get_ports "QDR4_A2"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A2"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_69 +#set_property PACKAGE_PIN BE3 [get_ports "QDR4_A3"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A3"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_69 +#set_property PACKAGE_PIN BE4 [get_ports "QDR4_A4"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A4"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_69 +#set_property PACKAGE_PIN BE5 [get_ports "QDR4_A5"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A5"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_69 +#set_property PACKAGE_PIN BE6 [get_ports "QDR4_A6"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A6"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_69 +#set_property PACKAGE_PIN BF2 [get_ports "QDR4_A7"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A7"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_69 +#set_property PACKAGE_PIN BF3 [get_ports "QDR4_A8"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A8"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_69 +#set_property PACKAGE_PIN BG2 [get_ports "QDR4_A9"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A9"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_69 +#set_property PACKAGE_PIN BG3 [get_ports "QDR4_A10"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A10"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_69 +#set_property PACKAGE_PIN BG4 [get_ports "QDR4_A11"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A11"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_69 +#set_property PACKAGE_PIN BG5 [get_ports "QDR4_A12"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A12"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_69 +#set_property PACKAGE_PIN BF5 [get_ports "QDR4_A0"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A0"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_69 +#set_property PACKAGE_PIN BF6 [get_ports "No Connect"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_69 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_69 +#set_property PACKAGE_PIN BF7 [get_ports "QDR4_A13"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A13"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_69 +#set_property PACKAGE_PIN BF8 [get_ports "QDR4_A14"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A14"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_69 +#set_property PACKAGE_PIN BG7 [get_ports "QDR4_A15"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A15"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_69 +#set_property PACKAGE_PIN BG8 [get_ports "QDR4_A16"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A16"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_69 +#set_property PACKAGE_PIN BJ7 [get_ports "QDR4_A17"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A17"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_69 +#set_property PACKAGE_PIN BH7 [get_ports "QDR4_A18"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A18"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_69 +#set_property PACKAGE_PIN BK8 [get_ports "QDR4_A19"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A19"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_69 +#set_property PACKAGE_PIN BJ8 [get_ports "QDR4_A20"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A20"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_69 +#set_property PACKAGE_PIN BH4 [get_ports "QDR4_CK_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_69 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_CK_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_69 +#set_property PACKAGE_PIN BH5 [get_ports "QDR4_CK_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_69 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_CK_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_69 +#set_property PACKAGE_PIN BJ6 [get_ports "QDR4_A21"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A21"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_69 +#set_property PACKAGE_PIN BH6 [get_ports "QDR4_A23"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A23"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_69 +#set_property PACKAGE_PIN BK4 [get_ports "QDR4_A24"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A24"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_69 +#set_property PACKAGE_PIN BK5 [get_ports "QDR4_A22"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A22"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_69 +#set_property PACKAGE_PIN BK3 [get_ports "QDR4_CLK_100MHZ_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_69 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_69 +#set_property PACKAGE_PIN BJ4 [get_ports "QDR4_CLK_100MHZ_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_69 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_69 +#set_property PACKAGE_PIN BJ2 [get_ports "QDR4_PE_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_PE_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_69 +#set_property PACKAGE_PIN BJ3 [get_ports "QDR4_LBK0_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LBK0_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_69 +#set_property PACKAGE_PIN BH1 [get_ports "QDR4_LBK1_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LBK1_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_69 +#set_property PACKAGE_PIN BH2 [get_ports "QDR4_CFG_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_CFG_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_69 +#set_property PACKAGE_PIN BK1 [get_ports "QDR4_RST_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QDR4_RST_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_69 +#set_property PACKAGE_PIN BJ1 [get_ports "QDR4_AINV"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_AINV"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_69 +#set_property PACKAGE_PIN BL2 [get_ports "QDR4_LDB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LDB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_69 +#set_property PACKAGE_PIN BL3 [get_ports "QDR4_RWB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_RWB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_69 +#set_property PACKAGE_PIN BK6 [get_ports "QDR4_AP"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_AP"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_69 +#set_property PACKAGE_PIN BL5 [get_ports "VRP_69"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_69 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_69"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_69 +#set_property PACKAGE_PIN BM3 [get_ports "QDR4_LDA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LDA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_69 +#set_property PACKAGE_PIN BM4 [get_ports "QDR4_RWA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_RWA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_69 +#set_property PACKAGE_PIN BM5 [get_ports "QSFP3_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_69 +#set_property PACKAGE_PIN BL6 [get_ports "QSFP3_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_69 +#set_property PACKAGE_PIN BM7 [get_ports "QSFP3_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_69 +#set_property PACKAGE_PIN BL7 [get_ports "QSFP3_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_69 +#set_property PACKAGE_PIN BN4 [get_ports "QSFP3_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_69 +#set_property PACKAGE_PIN BN5 [get_ports "QSFP2_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_69 +#set_property PACKAGE_PIN BN6 [get_ports "QSFP2_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_69 +#set_property PACKAGE_PIN BN7 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_69 +#set_property PACKAGE_PIN BP6 [get_ports "QSFP2_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_69 +#set_property PACKAGE_PIN BP7 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_69 +#set_property PACKAGE_PIN BE9 [get_ports "QDR4_DQA27"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA27"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_68 +#set_property PACKAGE_PIN BE10 [get_ports "QDR4_DQA28"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA28"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_68 +#set_property PACKAGE_PIN BF10 [get_ports "QDR4_DQA31"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA31"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_68 +#set_property PACKAGE_PIN BE11 [get_ports "QDR4_DQA30"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA30"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_68 +#set_property PACKAGE_PIN BF11 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_68 +#set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_68 +#set_property PACKAGE_PIN BF12 [get_ports "QDR4_DQA35"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA35"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_68 +#set_property PACKAGE_PIN BG9 [get_ports "QDR4_DQA33"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA33"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_68 +#set_property PACKAGE_PIN BG10 [get_ports "QDR4_DQA34"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA34"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_68 +#set_property PACKAGE_PIN BG12 [get_ports "QDR4_DQA32"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA32"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_68 +#set_property PACKAGE_PIN BG13 [get_ports "QDR4_DQA29"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA29"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_68 +#set_property PACKAGE_PIN BH9 [get_ports "QDR4_DKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_68 +#set_property PACKAGE_PIN BH10 [get_ports "QDR4_DKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_68 +#set_property PACKAGE_PIN BH11 [get_ports "PMBUS_ALERT_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_68 +#set_property IOSTANDARD LVCMOS12 [get_ports "PMBUS_ALERT_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_68 +#set_property PACKAGE_PIN BH12 [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_68 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_68 +#set_property PACKAGE_PIN BH14 [get_ports "QDR4_DQA23"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA23"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_68 +#set_property PACKAGE_PIN BH15 [get_ports "QDR4_DQA24"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA24"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_68 +#set_property PACKAGE_PIN BJ12 [get_ports "QDR4_DQA20"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA20"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_68 +#set_property PACKAGE_PIN BJ13 [get_ports "QDR4_DQA26"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA26"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_68 +#set_property PACKAGE_PIN BK13 [get_ports "QDR4_QVLDA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_68 +#set_property PACKAGE_PIN BJ14 [get_ports "QDR4_DQA25"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA25"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_68 +#set_property PACKAGE_PIN BK14 [get_ports "QDR4_DQA19"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA19"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_68 +#set_property PACKAGE_PIN BK15 [get_ports "QDR4_DQA21"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA21"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_68 +#set_property PACKAGE_PIN BL12 [get_ports "QDR4_DQA18"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA18"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_68 +#set_property PACKAGE_PIN BL13 [get_ports "QDR4_DQA22"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA22"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_68 +#set_property PACKAGE_PIN BK11 [get_ports "QDR4_QKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_68 +#set_property PACKAGE_PIN BJ11 [get_ports "QDR4_QKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_68 +#set_property PACKAGE_PIN BK9 [get_ports "QDR4_DQA10"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA10"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_68 +#set_property PACKAGE_PIN BJ9 [get_ports "QDR4_DQA17"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA17"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_68 +#set_property PACKAGE_PIN BL10 [get_ports "QDR4_DQA11"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA11"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_68 +#set_property PACKAGE_PIN BK10 [get_ports "QDR4_DQA12"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA12"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_68 +#set_property PACKAGE_PIN BM8 [get_ports "QDR4_QVLDA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_68 +#set_property PACKAGE_PIN BL8 [get_ports "QDR4_DQA13"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA13"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_68 +#set_property PACKAGE_PIN BN9 [get_ports "QDR4_DQA16"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA16"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_68 +#set_property PACKAGE_PIN BM9 [get_ports "QDR4_DQA9"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA9"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_68 +#set_property PACKAGE_PIN BN10 [get_ports "QDR4_DQA14"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA14"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_68 +#set_property PACKAGE_PIN BM10 [get_ports "QDR4_DQA15"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA15"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_68 +#set_property PACKAGE_PIN BP8 [get_ports "QDR4_QKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_68 +#set_property PACKAGE_PIN BP9 [get_ports "QDR4_QKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_68 +#set_property PACKAGE_PIN BL11 [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_68 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_68 +#set_property PACKAGE_PIN BN11 [get_ports "VRP_68"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_68 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_68"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_68 +#set_property PACKAGE_PIN BM15 [get_ports "QDR4_DQA4"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA4"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_68 +#set_property PACKAGE_PIN BL15 [get_ports "QDR4_DQA8"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA8"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_68 +#set_property PACKAGE_PIN BM13 [get_ports "QDR4_DQA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_68 +#set_property PACKAGE_PIN BM14 [get_ports "QDR4_DQA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_68 +#set_property PACKAGE_PIN BN14 [get_ports "SI5328_RST_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_68 +#set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_RST_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_68 +#set_property PACKAGE_PIN BN15 [get_ports "QDR4_DQA2"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA2"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_68 +#set_property PACKAGE_PIN BN12 [get_ports "QDR4_DQA3"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA3"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_68 +#set_property PACKAGE_PIN BM12 [get_ports "QDR4_DQA7"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA7"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_68 +#set_property PACKAGE_PIN BP13 [get_ports "QDR4_DQA5"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA5"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_68 +#set_property PACKAGE_PIN BP14 [get_ports "QDR4_DQA6"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA6"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_68 +#set_property PACKAGE_PIN BP11 [get_ports "QDR4_DKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_68 +#set_property PACKAGE_PIN BP12 [get_ports "QDR4_DKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_68 +#set_property PACKAGE_PIN A28 [get_ports "RLD3_72B_DM1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_75 +#set_property PACKAGE_PIN B28 [get_ports "RLD3_72B_DQ35"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ35"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_75 +#set_property PACKAGE_PIN A30 [get_ports "RLD3_72B_DQ31"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ31"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_75 +#set_property PACKAGE_PIN A29 [get_ports "RLD3_72B_DQ34"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ34"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_75 +#set_property PACKAGE_PIN A31 [get_ports "RLD3_72B_DQ27"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ27"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_75 +#set_property PACKAGE_PIN B30 [get_ports "RLD3_72B_DQ30"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ30"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_75 +#set_property PACKAGE_PIN A33 [get_ports "RLD3_72B_DQ29"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ29"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_75 +#set_property PACKAGE_PIN B32 [get_ports "RLD3_72B_DQ28"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ28"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_75 +#set_property PACKAGE_PIN C29 [get_ports "RLD3_72B_DQ33"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ33"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_75 +#set_property PACKAGE_PIN C28 [get_ports "RLD3_72B_DQ32"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ32"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_75 +#set_property PACKAGE_PIN B31 [get_ports "RLD3_72B_QK3_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK3_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_75 +#set_property PACKAGE_PIN C30 [get_ports "RLD3_72B_QK3_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK3_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_75 +#set_property PACKAGE_PIN B33 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_75 +#set_property PACKAGE_PIN C33 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_75 +#set_property PACKAGE_PIN D29 [get_ports "RLD3_72B_DQ25"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ25"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_75 +#set_property PACKAGE_PIN E28 [get_ports "RLD3_72B_QVLD1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_75 +#set_property PACKAGE_PIN C32 [get_ports "RLD3_72B_DQ21"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ21"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_75 +#set_property PACKAGE_PIN D32 [get_ports "RLD3_72B_DQ24"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ24"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_75 +#set_property PACKAGE_PIN D31 [get_ports "RLD3_72B_DQ26"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ26"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_75 +#set_property PACKAGE_PIN D30 [get_ports "RLD3_72B_DQ23"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ23"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_75 +#set_property PACKAGE_PIN E33 [get_ports "RLD3_72B_DQ18"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ18"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_75 +#set_property PACKAGE_PIN F33 [get_ports "RLD3_72B_DQ22"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ22"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_75 +#set_property PACKAGE_PIN E29 [get_ports "RLD3_72B_DQ20"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ20"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_75 +#set_property PACKAGE_PIN F29 [get_ports "RLD3_72B_DQ19"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ19"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_75 +#set_property PACKAGE_PIN E32 [get_ports "RLD3_72B_QK2_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QK2_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_75 +#set_property PACKAGE_PIN E31 [get_ports "RLD3_72B_QK2_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QK2_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_75 +#set_property PACKAGE_PIN F30 [get_ports "RLD3_72B_QVLD0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_75 +#set_property PACKAGE_PIN G30 [get_ports "RLD3_72B_DQ9"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ9"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_75 +#set_property PACKAGE_PIN F31 [get_ports "RLD3_72B_DQ11"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ11"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_75 +#set_property PACKAGE_PIN G31 [get_ports "RLD3_72B_DQ14"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ14"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_75 +#set_property PACKAGE_PIN F28 [get_ports "RLD3_72B_DQ17"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ17"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_75 +#set_property PACKAGE_PIN G28 [get_ports "RLD3_72B_DQ12"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ12"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_75 +#set_property PACKAGE_PIN G32 [get_ports "RLD3_72B_DQ15"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ15"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_75 +#set_property PACKAGE_PIN H32 [get_ports "RLD3_72B_DQ16"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ16"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_75 +#set_property PACKAGE_PIN H30 [get_ports "RLD3_72B_DQ10"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ10"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_75 +#set_property PACKAGE_PIN H29 [get_ports "RLD3_72B_DQ13"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ13"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_75 +#set_property PACKAGE_PIN G33 [get_ports "RLD3_72B_QK1_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK1_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_75 +#set_property PACKAGE_PIN H33 [get_ports "RLD3_72B_QK1_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK1_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_75 +#set_property PACKAGE_PIN H28 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_75 +#set_property PACKAGE_PIN K28 [get_ports "VRP_75"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_75"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_75 +#set_property PACKAGE_PIN J29 [get_ports "RLD3_72B_DM0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_75 +#set_property PACKAGE_PIN K29 [get_ports "RLD3_72B_DQ0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_75 +#set_property PACKAGE_PIN J31 [get_ports "RLD3_72B_DQ3"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ3"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_75 +#set_property PACKAGE_PIN J30 [get_ports "RLD3_72B_DQ1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_75 +#set_property PACKAGE_PIN J32 [get_ports "RLD3_72B_DQ7"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ7"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_75 +#set_property PACKAGE_PIN K32 [get_ports "RLD3_72B_DQ2"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ2"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_75 +#set_property PACKAGE_PIN K31 [get_ports "RLD3_72B_DQ8"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ8"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_75 +#set_property PACKAGE_PIN L31 [get_ports "RLD3_72B_DQ5"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ5"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_75 +#set_property PACKAGE_PIN L30 [get_ports "RLD3_72B_DQ6"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ6"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_75 +#set_property PACKAGE_PIN L29 [get_ports "RLD3_72B_DQ4"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ4"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_75 +#set_property PACKAGE_PIN K33 [get_ports "RLD3_72B_QK0_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK0_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_75 +#set_property PACKAGE_PIN L33 [get_ports "RLD3_72B_QK0_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK0_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_75 +#set_property PACKAGE_PIN A35 [get_ports "RLD3_72B_A12"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A12"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_74 +#set_property PACKAGE_PIN A34 [get_ports "RLD3_72B_CS_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_CS_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_74 +#set_property PACKAGE_PIN A36 [get_ports "RLD3_72B_BA2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_74 +#set_property PACKAGE_PIN B35 [get_ports "RLD3_72B_A8"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A8"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_74 +#set_property PACKAGE_PIN A38 [get_ports "RLD3_72B_A1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_74 +#set_property PACKAGE_PIN B37 [get_ports "RLD3_72B_BA1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_74 +#set_property PACKAGE_PIN B36 [get_ports "RLD3_72B_A17"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A17"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_74 +#set_property PACKAGE_PIN C35 [get_ports "RLD3_72B_A13"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A13"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_74 +#set_property PACKAGE_PIN B38 [get_ports "RLD3_72B_A2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_74 +#set_property PACKAGE_PIN C37 [get_ports "RLD3_72B_A16"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A16"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_74 +#set_property PACKAGE_PIN C34 [get_ports "RLD3_72B_BA0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_74 +#set_property PACKAGE_PIN D34 [get_ports "RLD3_72B_A10"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A10"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_74 +#set_property PACKAGE_PIN C38 [get_ports "RLD3_72B_A6"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A6"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_74 +#set_property PACKAGE_PIN C39 [get_ports "RLD3_72B_A20"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A20"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_74 +#set_property PACKAGE_PIN D37 [get_ports "RLD3_72B_WE_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_WE_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_74 +#set_property PACKAGE_PIN E36 [get_ports "RLD3_72B_A7"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A7"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_74 +#set_property PACKAGE_PIN E34 [get_ports "RLD3_72B_REF_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_REF_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_74 +#set_property PACKAGE_PIN F34 [get_ports "RLD3_72B_A18"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A18"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_74 +#set_property PACKAGE_PIN D39 [get_ports "RLD3_72B_A0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_74 +#set_property PACKAGE_PIN E39 [get_ports "RLD3_72B_A11"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A11"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_74 +#set_property PACKAGE_PIN D36 [get_ports "RLD3_72B_BA3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_74 +#set_property PACKAGE_PIN D35 [get_ports "RLD3_72B_RE#set_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_RE#set_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_74 +#set_property PACKAGE_PIN E38 [get_ports "RLD3_72B_A15"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A15"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_74 +#set_property PACKAGE_PIN E37 [get_ports "RLD3_72B_A14"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A14"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_74 +#set_property PACKAGE_PIN F36 [get_ports "RLD3_CLK_100MHZ_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_74 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_CLK_100MHZ_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_74 +#set_property PACKAGE_PIN F35 [get_ports "RLD3_CLK_100MHZ_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_74 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_CLK_100MHZ_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_74 +#set_property PACKAGE_PIN F38 [get_ports "RLD3_72B_CK_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_CK_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_74 +#set_property PACKAGE_PIN G37 [get_ports "RLD3_72B_CK_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_CK_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_74 +#set_property PACKAGE_PIN G36 [get_ports "RLD3_72B_DK3_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK3_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_74 +#set_property PACKAGE_PIN G35 [get_ports "RLD3_72B_DK3_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK3_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_74 +#set_property PACKAGE_PIN F39 [get_ports "RLD3_72B_DK2_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK2_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_74 +#set_property PACKAGE_PIN G38 [get_ports "RLD3_72B_DK2_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK2_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_74 +#set_property PACKAGE_PIN H35 [get_ports "RLD3_72B_DK1_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK1_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_74 +#set_property PACKAGE_PIN H34 [get_ports "RLD3_72B_DK1_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK1_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_74 +#set_property PACKAGE_PIN H38 [get_ports "RLD3_72B_DK0_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK0_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_74 +#set_property PACKAGE_PIN H37 [get_ports "RLD3_72B_DK0_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK0_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_74 +#set_property PACKAGE_PIN H39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_74 +#set_property PACKAGE_PIN J39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_74 +#set_property PACKAGE_PIN J34 [get_ports "RLD3_72B_A3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_74 +#set_property PACKAGE_PIN J35 [get_ports "VRP_74"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_74 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "VRP_74"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_74 +#set_property PACKAGE_PIN J37 [get_ports "RLD3_72B_A19"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A19"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_74 +#set_property PACKAGE_PIN K37 [get_ports "RLD3_72B_A5"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A5"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_74 +#set_property PACKAGE_PIN K34 [get_ports "RLD3_72B_A4"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A4"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_74 +#set_property PACKAGE_PIN L34 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_74 +#set_property PACKAGE_PIN K38 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_74 +#set_property PACKAGE_PIN L38 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_74 +#set_property PACKAGE_PIN J36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_74 +#set_property PACKAGE_PIN K36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_74 +#set_property PACKAGE_PIN K39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_74 +#set_property PACKAGE_PIN L39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_74 +#set_property PACKAGE_PIN L36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_74 +#set_property PACKAGE_PIN L35 [get_ports "RLD3_72B_A9"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A9"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_74 +#set_property PACKAGE_PIN A40 [get_ports "RLD3_72B_DM3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_73 +#set_property PACKAGE_PIN A39 [get_ports "RLD3_72B_DQ65"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ65"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_73 +#set_property PACKAGE_PIN B42 [get_ports "RLD3_72B_DQ70"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ70"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_73 +#set_property PACKAGE_PIN B41 [get_ports "RLD3_72B_DQ67"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ67"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_73 +#set_property PACKAGE_PIN A41 [get_ports "RLD3_72B_DQ66"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ66"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_73 +#set_property PACKAGE_PIN B40 [get_ports "RLD3_72B_DQ68"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ68"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_73 +#set_property PACKAGE_PIN D41 [get_ports "RLD3_72B_DQ69"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ69"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_73 +#set_property PACKAGE_PIN E41 [get_ports "RLD3_72B_DQ71"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ71"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_73 +#set_property PACKAGE_PIN C40 [get_ports "RLD3_72B_DQ64"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ64"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_73 +#set_property PACKAGE_PIN D40 [get_ports "RLD3_72B_DQ63"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ63"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_73 +#set_property PACKAGE_PIN F41 [get_ports "RLD3_72B_QK7_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK7_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_73 +#set_property PACKAGE_PIN F40 [get_ports "RLD3_72B_QK7_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK7_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_73 +#set_property PACKAGE_PIN C42 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_73 +#set_property PACKAGE_PIN B43 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_73 +#set_property PACKAGE_PIN A44 [get_ports "RLD3_72B_QVLD3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_73 +#set_property PACKAGE_PIN A43 [get_ports "RLD3_72B_DQ62"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ62"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_73 +#set_property PACKAGE_PIN B45 [get_ports "RLD3_72B_DQ57"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ57"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_73 +#set_property PACKAGE_PIN C44 [get_ports "RLD3_72B_DQ60"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ60"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_73 +#set_property PACKAGE_PIN A46 [get_ports "RLD3_72B_DQ55"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ55"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_73 +#set_property PACKAGE_PIN A45 [get_ports "RLD3_72B_DQ58"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ58"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_73 +#set_property PACKAGE_PIN B46 [get_ports "RLD3_72B_DQ54"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ54"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_73 +#set_property PACKAGE_PIN C45 [get_ports "RLD3_72B_DQ59"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ59"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_73 +#set_property PACKAGE_PIN C43 [get_ports "RLD3_72B_DQ56"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ56"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_73 +#set_property PACKAGE_PIN D42 [get_ports "RLD3_72B_DQ61"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ61"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_73 +#set_property PACKAGE_PIN E43 [get_ports "RLD3_72B_QK6_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK6_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_73 +#set_property PACKAGE_PIN E42 [get_ports "RLD3_72B_QK6_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK6_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_73 +#set_property PACKAGE_PIN D45 [get_ports "RLD3_72B_QVLD2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_73 +#set_property PACKAGE_PIN D44 [get_ports "RLD3_72B_DQ45"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ45"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_73 +#set_property PACKAGE_PIN E44 [get_ports "RLD3_72B_DQ50"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ50"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_73 +#set_property PACKAGE_PIN F44 [get_ports "RLD3_72B_DQ47"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ47"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_73 +#set_property PACKAGE_PIN D46 [get_ports "RLD3_72B_DQ48"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ48"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_73 +#set_property PACKAGE_PIN E46 [get_ports "RLD3_72B_DQ51"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ51"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_73 +#set_property PACKAGE_PIN G45 [get_ports "RLD3_72B_DQ52"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ52"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_73 +#set_property PACKAGE_PIN H45 [get_ports "RLD3_72B_DQ53"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ53"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_73 +#set_property PACKAGE_PIN F46 [get_ports "RLD3_72B_DQ49"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ49"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_73 +#set_property PACKAGE_PIN F45 [get_ports "RLD3_72B_DQ46"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ46"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_73 +#set_property PACKAGE_PIN H44 [get_ports "RLD3_72B_QK5_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK5_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_73 +#set_property PACKAGE_PIN J44 [get_ports "RLD3_72B_QK5_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK5_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_73 +#set_property PACKAGE_PIN G46 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_73 +#set_property PACKAGE_PIN F43 [get_ports "VRP_73"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_73"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_73 +#set_property PACKAGE_PIN G43 [get_ports "RLD3_72B_DM2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_73 +#set_property PACKAGE_PIN H43 [get_ports "RLD3_72B_DQ40"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ40"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_73 +#set_property PACKAGE_PIN G42 [get_ports "RLD3_72B_DQ36"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ36"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_73 +#set_property PACKAGE_PIN G41 [get_ports "RLD3_72B_DQ37"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ37"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_73 +#set_property PACKAGE_PIN G40 [get_ports "RLD3_72B_DQ39"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ39"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_73 +#set_property PACKAGE_PIN H40 [get_ports "RLD3_72B_DQ42"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ42"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_73 +#set_property PACKAGE_PIN J41 [get_ports "RLD3_72B_DQ44"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ44"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_73 +#set_property PACKAGE_PIN J40 [get_ports "RLD3_72B_DQ43"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ43"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_73 +#set_property PACKAGE_PIN H42 [get_ports "RLD3_72B_DQ38"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ38"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_73 +#set_property PACKAGE_PIN J42 [get_ports "RLD3_72B_DQ41"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ41"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_73 +#set_property PACKAGE_PIN K42 [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 +#set_property PACKAGE_PIN K41 [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 +#set_property PACKAGE_PIN A24 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 +#set_property PACKAGE_PIN A25 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 +#set_property PACKAGE_PIN A26 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 +#set_property PACKAGE_PIN B27 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 + +set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND +set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; + +set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD +set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; + +set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; + +#set_property PACKAGE_PIN C24 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 +#set_property PACKAGE_PIN C25 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 +#set_property PACKAGE_PIN B22 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 +#set_property PACKAGE_PIN C23 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +#set_property PACKAGE_PIN C22 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 +#set_property PACKAGE_PIN C27 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 +#set_property PACKAGE_PIN D27 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 +#set_property PACKAGE_PIN E27 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 +#set_property PACKAGE_PIN D26 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 +#set_property PACKAGE_PIN E26 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 +#set_property PACKAGE_PIN D24 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 +#set_property PACKAGE_PIN D25 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 +#set_property PACKAGE_PIN D22 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 +#set_property PACKAGE_PIN E22 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 +#set_property PACKAGE_PIN F25 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +#set_property PACKAGE_PIN F26 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +#set_property PACKAGE_PIN E23 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 +#set_property PACKAGE_PIN E24 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 +#set_property PACKAGE_PIN G25 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 +#set_property PACKAGE_PIN G26 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 +#set_property PACKAGE_PIN F23 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 +#set_property PACKAGE_PIN F24 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 +#set_property PACKAGE_PIN G22 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 +#set_property PACKAGE_PIN G23 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 +#set_property PACKAGE_PIN G27 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 +#set_property PACKAGE_PIN H27 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 + +set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; + +set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] + +#set_property PACKAGE_PIN H23 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 +#set_property PACKAGE_PIN H24 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 +#set_property PACKAGE_PIN H25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 +#set_property PACKAGE_PIN J24 [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 +#set_property PACKAGE_PIN J25 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 +#set_property PACKAGE_PIN J26 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 +#set_property PACKAGE_PIN J27 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 +#set_property PACKAGE_PIN K27 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 +#set_property PACKAGE_PIN K22 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 +#set_property PACKAGE_PIN L23 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property PACKAGE_PIN K23 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 +#set_property PACKAGE_PIN K24 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 +#set_property PACKAGE_PIN K26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 +#set_property PACKAGE_PIN L26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 +#set_property PACKAGE_PIN L24 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 +#set_property PACKAGE_PIN L25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 +#set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_GBTCLK0_M2C_N"] ;# Bank 124 - MGTREFCLK0N_124 +#set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_GBTCLK0_M2C_P"] ;# Bank 124 - MGTREFCLK0P_124 +#set_property PACKAGE_PIN AT43 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1N_124 +#set_property PACKAGE_PIN AT42 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1P_124 +#set_property PACKAGE_PIN BC54 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 124 - MGTYRXN0_124 +#set_property PACKAGE_PIN BB52 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 124 - MGTYRXN1_124 +#set_property PACKAGE_PIN BA54 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 124 - MGTYRXN2_124 +#set_property PACKAGE_PIN BA50 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 124 - MGTYRXN3_124 +#set_property PACKAGE_PIN BC53 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 124 - MGTYRXP0_124 +#set_property PACKAGE_PIN BB51 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 124 - MGTYRXP1_124 +#set_property PACKAGE_PIN BA53 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 124 - MGTYRXP2_124 +#set_property PACKAGE_PIN BA49 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 124 - MGTYRXP3_124 +#set_property PACKAGE_PIN BC49 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 124 - MGTYTXN0_124 +#set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 124 - MGTYTXN1_124 +#set_property PACKAGE_PIN BB47 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 124 - MGTYTXN2_124 +#set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 124 - MGTYTXN3_124 +#set_property PACKAGE_PIN BC48 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 124 - MGTYTXP0_124 +#set_property PACKAGE_PIN BC44 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 124 - MGTYTXP1_124 +#set_property PACKAGE_PIN BB46 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 124 - MGTYTXP2_124 +#set_property PACKAGE_PIN BA44 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 124 - MGTYTXP3_124 +#set_property PACKAGE_PIN AR41 [get_ports "FMCP_HSPC_GBTCLK1_M2C_N"] ;# Bank 125 - MGTREFCLK0N_125 +#set_property PACKAGE_PIN AR40 [get_ports "FMCP_HSPC_GBTCLK1_M2C_P"] ;# Bank 125 - MGTREFCLK0P_125 +#set_property PACKAGE_PIN AP43 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1N_125 +#set_property PACKAGE_PIN AP42 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1P_125 +#set_property PACKAGE_PIN AU41 [get_ports "N22117206"] ;# Bank 125 - MGTRREF_LS +#set_property PACKAGE_PIN AY52 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 125 - MGTYRXN0_125 +#set_property PACKAGE_PIN AW54 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 125 - MGTYRXN1_125 +#set_property PACKAGE_PIN AW50 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 125 - MGTYRXN2_125 +#set_property PACKAGE_PIN AV52 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 125 - MGTYRXN3_125 +#set_property PACKAGE_PIN AY51 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 125 - MGTYRXP0_125 +#set_property PACKAGE_PIN AW53 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 125 - MGTYRXP1_125 +#set_property PACKAGE_PIN AW49 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 125 - MGTYRXP2_125 +#set_property PACKAGE_PIN AV51 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 125 - MGTYRXP3_125 +#set_property PACKAGE_PIN AY47 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 125 - MGTYTXN0_125 +#set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 125 - MGTYTXN1_125 +#set_property PACKAGE_PIN AV47 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 125 - MGTYTXN2_125 +#set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 125 - MGTYTXN3_125 +#set_property PACKAGE_PIN AY46 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 125 - MGTYTXP0_125 +#set_property PACKAGE_PIN AW44 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 125 - MGTYTXP1_125 +#set_property PACKAGE_PIN AV46 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 125 - MGTYTXP2_125 +#set_property PACKAGE_PIN AU44 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 125 - MGTYTXP3_125 +#set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK2_M2C_N"] ;# Bank 126 - MGTREFCLK0N_126 +#set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK2_M2C_P"] ;# Bank 126 - MGTREFCLK0P_126 +#set_property PACKAGE_PIN AM43 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1N_126 +#set_property PACKAGE_PIN AM42 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1P_126 +#set_property PACKAGE_PIN AU54 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 126 - MGTYRXN0_126 +#set_property PACKAGE_PIN AT52 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 126 - MGTYRXN1_126 +#set_property PACKAGE_PIN AR54 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 126 - MGTYRXN2_126 +#set_property PACKAGE_PIN AP52 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 126 - MGTYRXN3_126 +#set_property PACKAGE_PIN AU53 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 126 - MGTYRXP0_126 +#set_property PACKAGE_PIN AT51 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 126 - MGTYRXP1_126 +#set_property PACKAGE_PIN AR53 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 126 - MGTYRXP2_126 +#set_property PACKAGE_PIN AP51 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 126 - MGTYRXP3_126 +#set_property PACKAGE_PIN AU49 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 126 - MGTYTXN0_126 +#set_property PACKAGE_PIN AT47 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 126 - MGTYTXN1_126 +#set_property PACKAGE_PIN AR49 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 126 - MGTYTXN2_126 +#set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 126 - MGTYTXN3_126 +#set_property PACKAGE_PIN AU48 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 126 - MGTYTXP0_126 +#set_property PACKAGE_PIN AT46 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 126 - MGTYTXP1_126 +#set_property PACKAGE_PIN AR48 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 126 - MGTYTXP2_126 +#set_property PACKAGE_PIN AR44 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 126 - MGTYTXP3_126 +#set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_GBTCLK3_M2C_N"] ;# Bank 127 - MGTREFCLK0N_127 +#set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_GBTCLK3_M2C_P"] ;# Bank 127 - MGTREFCLK0P_127 +#set_property PACKAGE_PIN AK43 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1N_127 +#set_property PACKAGE_PIN AK42 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1P_127 +#set_property PACKAGE_PIN AN54 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 127 - MGTYRXN0_127 +#set_property PACKAGE_PIN AN50 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 127 - MGTYRXN1_127 +#set_property PACKAGE_PIN AM52 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 127 - MGTYRXN2_127 +#set_property PACKAGE_PIN AL54 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 127 - MGTYRXN3_127 +#set_property PACKAGE_PIN AN53 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 127 - MGTYRXP0_127 +#set_property PACKAGE_PIN AN49 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 127 - MGTYRXP1_127 +#set_property PACKAGE_PIN AM51 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 127 - MGTYRXP2_127 +#set_property PACKAGE_PIN AL53 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 127 - MGTYRXP3_127 +#set_property PACKAGE_PIN AP47 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 127 - MGTYTXN0_127 +#set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 127 - MGTYTXN1_127 +#set_property PACKAGE_PIN AM47 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 127 - MGTYTXN2_127 +#set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 127 - MGTYTXN3_127 +#set_property PACKAGE_PIN AP46 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 127 - MGTYTXP0_127 +#set_property PACKAGE_PIN AN44 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 127 - MGTYTXP1_127 +#set_property PACKAGE_PIN AM46 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 127 - MGTYTXP2_127 +#set_property PACKAGE_PIN AL44 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 127 - MGTYTXP3_127 +#set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_N"] ;# Bank 128 - MGTREFCLK0N_128 +#set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_P"] ;# Bank 128 - MGTREFCLK0P_128 +#set_property PACKAGE_PIN AH43 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1N_128 +#set_property PACKAGE_PIN AH42 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1P_128 +#set_property PACKAGE_PIN AL50 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 128 - MGTYRXN0_128 +#set_property PACKAGE_PIN AK52 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 128 - MGTYRXN1_128 +#set_property PACKAGE_PIN AJ54 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 128 - MGTYRXN2_128 +#set_property PACKAGE_PIN AH52 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 128 - MGTYRXN3_128 +#set_property PACKAGE_PIN AL49 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 128 - MGTYRXP0_128 +#set_property PACKAGE_PIN AK51 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 128 - MGTYRXP1_128 +#set_property PACKAGE_PIN AJ53 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 128 - MGTYRXP2_128 +#set_property PACKAGE_PIN AH51 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 128 - MGTYRXP3_128 +#set_property PACKAGE_PIN AK47 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 128 - MGTYTXN0_128 +#set_property PACKAGE_PIN AJ49 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 128 - MGTYTXN1_128 +#set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 128 - MGTYTXN2_128 +#set_property PACKAGE_PIN AH47 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 128 - MGTYTXN3_128 +#set_property PACKAGE_PIN AK46 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 128 - MGTYTXP0_128 +#set_property PACKAGE_PIN AJ48 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 128 - MGTYTXP1_128 +#set_property PACKAGE_PIN AJ44 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 128 - MGTYTXP2_128 +#set_property PACKAGE_PIN AH46 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 128 - MGTYTXP3_128 +#set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_N"] ;# Bank 129 - MGTREFCLK0N_129 +#set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_P"] ;# Bank 129 - MGTREFCLK0P_129 +#set_property PACKAGE_PIN AF43 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1N_129 +#set_property PACKAGE_PIN AF42 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1P_129 +#set_property PACKAGE_PIN AE41 [get_ports "N21075880"] ;# Bank 129 - MGTRREF_LC +#set_property PACKAGE_PIN AG54 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 129 - MGTYRXN0_129 +#set_property PACKAGE_PIN AF52 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 129 - MGTYRXN1_129 +#set_property PACKAGE_PIN AE54 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 129 - MGTYRXN2_129 +#set_property PACKAGE_PIN AE50 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 129 - MGTYRXN3_129 +#set_property PACKAGE_PIN AG53 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 129 - MGTYRXP0_129 +#set_property PACKAGE_PIN AF51 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 129 - MGTYRXP1_129 +#set_property PACKAGE_PIN AE53 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 129 - MGTYRXP2_129 +#set_property PACKAGE_PIN AE49 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 129 - MGTYRXP3_129 +#set_property PACKAGE_PIN AG49 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 129 - MGTYTXN0_129 +#set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 129 - MGTYTXN1_129 +#set_property PACKAGE_PIN AF47 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 129 - MGTYTXN2_129 +#set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 129 - MGTYTXN3_129 +#set_property PACKAGE_PIN AG48 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 129 - MGTYTXP0_129 +#set_property PACKAGE_PIN AG44 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 129 - MGTYTXP1_129 +#set_property PACKAGE_PIN AF46 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 129 - MGTYTXP2_129 +#set_property PACKAGE_PIN AE44 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 129 - MGTYTXP3_129 +#set_property PACKAGE_PIN AD43 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0N_130 +#set_property PACKAGE_PIN AD42 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0P_130 +#set_property PACKAGE_PIN AC41 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1N_130 +#set_property PACKAGE_PIN AC40 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1P_130 +#set_property PACKAGE_PIN AD52 [get_ports "GND"] ;# Bank 130 - MGTYRXN0_130 +#set_property PACKAGE_PIN AC54 [get_ports "GND"] ;# Bank 130 - MGTYRXN1_130 +#set_property PACKAGE_PIN AC50 [get_ports "GND"] ;# Bank 130 - MGTYRXN2_130 +#set_property PACKAGE_PIN AB52 [get_ports "GND"] ;# Bank 130 - MGTYRXN3_130 +#set_property PACKAGE_PIN AD51 [get_ports "GND"] ;# Bank 130 - MGTYRXP0_130 +#set_property PACKAGE_PIN AC53 [get_ports "GND"] ;# Bank 130 - MGTYRXP1_130 +#set_property PACKAGE_PIN AC49 [get_ports "GND"] ;# Bank 130 - MGTYRXP2_130 +#set_property PACKAGE_PIN AB51 [get_ports "GND"] ;# Bank 130 - MGTYRXP3_130 +#set_property PACKAGE_PIN AD47 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN0_130 +#set_property PACKAGE_PIN AC45 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN1_130 +#set_property PACKAGE_PIN AB47 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN2_130 +#set_property PACKAGE_PIN AA49 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN3_130 +#set_property PACKAGE_PIN AD46 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP0_130 +#set_property PACKAGE_PIN AC44 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP1_130 +#set_property PACKAGE_PIN AB46 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP2_130 +#set_property PACKAGE_PIN AA48 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP3_130 +#set_property PACKAGE_PIN AB43 [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131 +#set_property PACKAGE_PIN AB42 [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131 +#set_property PACKAGE_PIN AA41 [get_ports "SMA_REFCLK_INPUT_N"] ;# Bank 131 - MGTREFCLK1N_131 +#set_property PACKAGE_PIN AA40 [get_ports "SMA_REFCLK_INPUT_P"] ;# Bank 131 - MGTREFCLK1P_131 +#set_property PACKAGE_PIN AA54 [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131 +#set_property PACKAGE_PIN Y52 [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131 +#set_property PACKAGE_PIN W54 [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131 +#set_property PACKAGE_PIN V52 [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131 +#set_property PACKAGE_PIN AA53 [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131 +#set_property PACKAGE_PIN Y51 [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131 +#set_property PACKAGE_PIN W53 [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131 +#set_property PACKAGE_PIN V51 [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131 +#set_property PACKAGE_PIN AA45 [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131 +#set_property PACKAGE_PIN Y47 [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131 +#set_property PACKAGE_PIN W49 [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131 +#set_property PACKAGE_PIN W45 [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131 +#set_property PACKAGE_PIN AA44 [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131 +#set_property PACKAGE_PIN Y46 [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131 +#set_property PACKAGE_PIN W48 [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131 +#set_property PACKAGE_PIN W44 [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131 +#set_property PACKAGE_PIN Y43 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 132 - MGTREFCLK0N_132 +#set_property PACKAGE_PIN Y42 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 132 - MGTREFCLK0P_132 +#set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 132 - MGTREFCLK1N_132 +#set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 132 - MGTREFCLK1P_132 +#set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 132 - MGTYRXN0_132 +#set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 132 - MGTYRXN1_132 +#set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 132 - MGTYRXN2_132 +#set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 132 - MGTYRXN3_132 +#set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 132 - MGTYRXP0_132 +#set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 132 - MGTYRXP1_132 +#set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 132 - MGTYRXP2_132 +#set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 132 - MGTYRXP3_132 +#set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 132 - MGTYTXN0_132 +#set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 132 - MGTYTXN1_132 +#set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 132 - MGTYTXN2_132 +#set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 132 - MGTYTXN3_132 +#set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 132 - MGTYTXP0_132 +#set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 132 - MGTYTXP1_132 +#set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 132 - MGTYTXP2_132 +#set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 132 - MGTYTXP3_132 +#set_property PACKAGE_PIN V43 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK0N_133 +#set_property PACKAGE_PIN V42 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK0P_133 +#set_property PACKAGE_PIN U41 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK1N_133 +#set_property PACKAGE_PIN U40 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK1P_133 +#set_property PACKAGE_PIN N41 [get_ports "N22119065"] ;# Bank 133 - MGTRREF_LN +#set_property PACKAGE_PIN R50 [get_ports "GND"] ;# Bank 133 - MGTYRXN0_133 +#set_property PACKAGE_PIN P52 [get_ports "GND"] ;# Bank 133 - MGTYRXN1_133 +#set_property PACKAGE_PIN N54 [get_ports "GND"] ;# Bank 133 - MGTYRXN2_133 +#set_property PACKAGE_PIN M52 [get_ports "GND"] ;# Bank 133 - MGTYRXN3_133 +#set_property PACKAGE_PIN R49 [get_ports "GND"] ;# Bank 133 - MGTYRXP0_133 +#set_property PACKAGE_PIN P51 [get_ports "GND"] ;# Bank 133 - MGTYRXP1_133 +#set_property PACKAGE_PIN N53 [get_ports "GND"] ;# Bank 133 - MGTYRXP2_133 +#set_property PACKAGE_PIN M51 [get_ports "GND"] ;# Bank 133 - MGTYRXP3_133 +#set_property PACKAGE_PIN P47 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN0_133 +#set_property PACKAGE_PIN N49 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN1_133 +#set_property PACKAGE_PIN N45 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN2_133 +#set_property PACKAGE_PIN M47 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN3_133 +#set_property PACKAGE_PIN P46 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP0_133 +#set_property PACKAGE_PIN N48 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP1_133 +#set_property PACKAGE_PIN N44 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP2_133 +#set_property PACKAGE_PIN M46 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP3_133 +#set_property PACKAGE_PIN T43 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 134 - MGTREFCLK0N_134 +#set_property PACKAGE_PIN T42 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 134 - MGTREFCLK0P_134 +#set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 134 - MGTREFCLK1N_134 +#set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 134 - MGTREFCLK1P_134 +#set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 134 - MGTYRXN0_134 +#set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 134 - MGTYRXN1_134 +#set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 134 - MGTYRXN2_134 +#set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 134 - MGTYRXN3_134 +#set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 134 - MGTYRXP0_134 +#set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 134 - MGTYRXP1_134 +#set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 134 - MGTYRXP2_134 +#set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 134 - MGTYRXP3_134 +#set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 134 - MGTYTXN0_134 +#set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 134 - MGTYTXN1_134 +#set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 134 - MGTYTXN2_134 +#set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 134 - MGTYTXN3_134 +#set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 134 - MGTYTXP0_134 +#set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 134 - MGTYTXP1_134 +#set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 134 - MGTYTXP2_134 +#set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 134 - MGTYTXP3_134 +#set_property PACKAGE_PIN P43 [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 135 - MGTREFCLK0N_135 +#set_property PACKAGE_PIN P42 [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 135 - MGTREFCLK0P_135 +#set_property PACKAGE_PIN M43 [get_ports "No Connect"] ;# Bank 135 - MGTREFCLK1N_135 +#set_property PACKAGE_PIN M42 [get_ports "No Connect"] ;# Bank 135 - MGTREFCLK1P_135 +#set_property PACKAGE_PIN G54 [get_ports "QSFP1_RX1_N"] ;# Bank 135 - MGTYRXN0_135 +#set_property PACKAGE_PIN F52 [get_ports "QSFP1_RX2_N"] ;# Bank 135 - MGTYRXN1_135 +#set_property PACKAGE_PIN E54 [get_ports "QSFP1_RX3_N"] ;# Bank 135 - MGTYRXN2_135 +#set_property PACKAGE_PIN D52 [get_ports "QSFP1_RX4_N"] ;# Bank 135 - MGTYRXN3_135 +#set_property PACKAGE_PIN G53 [get_ports "QSFP1_RX1_P"] ;# Bank 135 - MGTYRXP0_135 +#set_property PACKAGE_PIN F51 [get_ports "QSFP1_RX2_P"] ;# Bank 135 - MGTYRXP1_135 +#set_property PACKAGE_PIN E53 [get_ports "QSFP1_RX3_P"] ;# Bank 135 - MGTYRXP2_135 +#set_property PACKAGE_PIN D51 [get_ports "QSFP1_RX4_P"] ;# Bank 135 - MGTYRXP3_135 +#set_property PACKAGE_PIN G49 [get_ports "QSFP1_TX1_N"] ;# Bank 135 - MGTYTXN0_135 +#set_property PACKAGE_PIN E49 [get_ports "QSFP1_TX2_N"] ;# Bank 135 - MGTYTXN1_135 +#set_property PACKAGE_PIN C49 [get_ports "QSFP1_TX3_N"] ;# Bank 135 - MGTYTXN2_135 +#set_property PACKAGE_PIN A50 [get_ports "QSFP1_TX4_N"] ;# Bank 135 - MGTYTXN3_135 +#set_property PACKAGE_PIN G48 [get_ports "QSFP1_TX1_P"] ;# Bank 135 - MGTYTXP0_135 +#set_property PACKAGE_PIN E48 [get_ports "QSFP1_TX2_P"] ;# Bank 135 - MGTYTXP1_135 +#set_property PACKAGE_PIN C48 [get_ports "QSFP1_TX3_P"] ;# Bank 135 - MGTYTXP2_135 +#set_property PACKAGE_PIN A49 [get_ports "QSFP1_TX4_P"] ;# Bank 135 - MGTYTXP3_135 +#set_property PACKAGE_PIN AV12 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK0N_224 +#set_property PACKAGE_PIN AV13 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK0P_224 +#set_property PACKAGE_PIN AT12 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK1N_224 +#set_property PACKAGE_PIN AT13 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK1P_224 +#set_property PACKAGE_PIN BC1 [get_ports "PCIE_EP_RX15_N"] ;# Bank 224 - MGTYRXN0_224 +#set_property PACKAGE_PIN BB3 [get_ports "PCIE_EP_RX14_N"] ;# Bank 224 - MGTYRXN1_224 +#set_property PACKAGE_PIN BA1 [get_ports "PCIE_EP_RX13_N"] ;# Bank 224 - MGTYRXN2_224 +#set_property PACKAGE_PIN BA5 [get_ports "PCIE_EP_RX12_N"] ;# Bank 224 - MGTYRXN3_224 +#set_property PACKAGE_PIN BC2 [get_ports "PCIE_EP_RX15_P"] ;# Bank 224 - MGTYRXP0_224 +#set_property PACKAGE_PIN BB4 [get_ports "PCIE_EP_RX14_P"] ;# Bank 224 - MGTYRXP1_224 +#set_property PACKAGE_PIN BA2 [get_ports "PCIE_EP_RX13_P"] ;# Bank 224 - MGTYRXP2_224 +#set_property PACKAGE_PIN BA6 [get_ports "PCIE_EP_RX12_P"] ;# Bank 224 - MGTYRXP3_224 +#set_property PACKAGE_PIN BC6 [get_ports "PCIE_EP_TX15_N"] ;# Bank 224 - MGTYTXN0_224 +#set_property PACKAGE_PIN BC10 [get_ports "PCIE_EP_TX14_N"] ;# Bank 224 - MGTYTXN1_224 +#set_property PACKAGE_PIN BB8 [get_ports "PCIE_EP_TX13_N"] ;# Bank 224 - MGTYTXN2_224 +#set_property PACKAGE_PIN BA10 [get_ports "PCIE_EP_TX12_N"] ;# Bank 224 - MGTYTXN3_224 +#set_property PACKAGE_PIN BC7 [get_ports "PCIE_EP_TX15_P"] ;# Bank 224 - MGTYTXP0_224 +#set_property PACKAGE_PIN BC11 [get_ports "PCIE_EP_TX14_P"] ;# Bank 224 - MGTYTXP1_224 +#set_property PACKAGE_PIN BB9 [get_ports "PCIE_EP_TX13_P"] ;# Bank 224 - MGTYTXP2_224 +#set_property PACKAGE_PIN BA11 [get_ports "PCIE_EP_TX12_P"] ;# Bank 224 - MGTYTXP3_224 +#set_property PACKAGE_PIN AR14 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225 +#set_property PACKAGE_PIN AR15 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225 +#set_property PACKAGE_PIN AP12 [get_ports "No Connect"] ;# Bank 225 - MGTREFCLK1N_225 +#set_property PACKAGE_PIN AP13 [get_ports "No Connect"] ;# Bank 225 - MGTREFCLK1P_225 +#set_property PACKAGE_PIN AU14 [get_ports "N22119509"] ;# Bank 225 - MGTRREF_RS +#set_property PACKAGE_PIN AY3 [get_ports "PCIE_EP_RX11_N"] ;# Bank 225 - MGTYRXN0_225 +#set_property PACKAGE_PIN AW1 [get_ports "PCIE_EP_RX10_N"] ;# Bank 225 - MGTYRXN1_225 +#set_property PACKAGE_PIN AW5 [get_ports "PCIE_EP_RX9_N"] ;# Bank 225 - MGTYRXN2_225 +#set_property PACKAGE_PIN AV3 [get_ports "PCIE_EP_RX8_N"] ;# Bank 225 - MGTYRXN3_225 +#set_property PACKAGE_PIN AY4 [get_ports "PCIE_EP_RX11_P"] ;# Bank 225 - MGTYRXP0_225 +#set_property PACKAGE_PIN AW2 [get_ports "PCIE_EP_RX10_P"] ;# Bank 225 - MGTYRXP1_225 +#set_property PACKAGE_PIN AW6 [get_ports "PCIE_EP_RX9_P"] ;# Bank 225 - MGTYRXP2_225 +#set_property PACKAGE_PIN AV4 [get_ports "PCIE_EP_RX8_P"] ;# Bank 225 - MGTYRXP3_225 +#set_property PACKAGE_PIN AY8 [get_ports "PCIE_EP_TX11_N"] ;# Bank 225 - MGTYTXN0_225 +#set_property PACKAGE_PIN AW10 [get_ports "PCIE_EP_TX10_N"] ;# Bank 225 - MGTYTXN1_225 +#set_property PACKAGE_PIN AV8 [get_ports "PCIE_EP_TX9_N"] ;# Bank 225 - MGTYTXN2_225 +#set_property PACKAGE_PIN AU6 [get_ports "PCIE_EP_TX8_N"] ;# Bank 225 - MGTYTXN3_225 +#set_property PACKAGE_PIN AY9 [get_ports "PCIE_EP_TX11_P"] ;# Bank 225 - MGTYTXP0_225 +#set_property PACKAGE_PIN AW11 [get_ports "PCIE_EP_TX10_P"] ;# Bank 225 - MGTYTXP1_225 +#set_property PACKAGE_PIN AV9 [get_ports "PCIE_EP_TX9_P"] ;# Bank 225 - MGTYTXP2_225 +#set_property PACKAGE_PIN AU7 [get_ports "PCIE_EP_TX8_P"] ;# Bank 225 - MGTYTXP3_225 +#set_property PACKAGE_PIN AN14 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK0N_226 +#set_property PACKAGE_PIN AN15 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK0P_226 +#set_property PACKAGE_PIN AM12 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK1N_226 +#set_property PACKAGE_PIN AM13 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK1P_226 +#set_property PACKAGE_PIN AU1 [get_ports "PCIE_EP_RX7_N"] ;# Bank 226 - MGTYRXN0_226 +#set_property PACKAGE_PIN AT3 [get_ports "PCIE_EP_RX6_N"] ;# Bank 226 - MGTYRXN1_226 +#set_property PACKAGE_PIN AR1 [get_ports "PCIE_EP_RX5_N"] ;# Bank 226 - MGTYRXN2_226 +#set_property PACKAGE_PIN AP3 [get_ports "PCIE_EP_RX4_N"] ;# Bank 226 - MGTYRXN3_226 +#set_property PACKAGE_PIN AU2 [get_ports "PCIE_EP_RX7_P"] ;# Bank 226 - MGTYRXP0_226 +#set_property PACKAGE_PIN AT4 [get_ports "PCIE_EP_RX6_P"] ;# Bank 226 - MGTYRXP1_226 +#set_property PACKAGE_PIN AR2 [get_ports "PCIE_EP_RX5_P"] ;# Bank 226 - MGTYRXP2_226 +#set_property PACKAGE_PIN AP4 [get_ports "PCIE_EP_RX4_P"] ;# Bank 226 - MGTYRXP3_226 +#set_property PACKAGE_PIN AU10 [get_ports "PCIE_EP_TX7_N"] ;# Bank 226 - MGTYTXN0_226 +#set_property PACKAGE_PIN AT8 [get_ports "PCIE_EP_TX6_N"] ;# Bank 226 - MGTYTXN1_226 +#set_property PACKAGE_PIN AR6 [get_ports "PCIE_EP_TX5_N"] ;# Bank 226 - MGTYTXN2_226 +#set_property PACKAGE_PIN AR10 [get_ports "PCIE_EP_TX4_N"] ;# Bank 226 - MGTYTXN3_226 +#set_property PACKAGE_PIN AU11 [get_ports "PCIE_EP_TX7_P"] ;# Bank 226 - MGTYTXP0_226 +#set_property PACKAGE_PIN AT9 [get_ports "PCIE_EP_TX6_P"] ;# Bank 226 - MGTYTXP1_226 +#set_property PACKAGE_PIN AR7 [get_ports "PCIE_EP_TX5_P"] ;# Bank 226 - MGTYTXP2_226 +#set_property PACKAGE_PIN AR11 [get_ports "PCIE_EP_TX4_P"] ;# Bank 226 - MGTYTXP3_226 +#set_property PACKAGE_PIN AL14 [get_ports "PCIE_CLK2_N"] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports "PCIE_CLK2_P"] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports "No Connect"] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports "No Connect"] ;# Bank 227 - MGTREFCLK1P_227 +#set_property PACKAGE_PIN AN1 [get_ports "PCIE_EP_RX3_N"] ;# Bank 227 - MGTYRXN0_227 +#set_property PACKAGE_PIN AN5 [get_ports "PCIE_EP_RX2_N"] ;# Bank 227 - MGTYRXN1_227 +#set_property PACKAGE_PIN AM3 [get_ports "PCIE_EP_RX1_N"] ;# Bank 227 - MGTYRXN2_227 +#set_property PACKAGE_PIN AL1 [get_ports "PCIE_EP_RX0_N"] ;# Bank 227 - MGTYRXN3_227 +#set_property PACKAGE_PIN AN2 [get_ports "PCIE_EP_RX3_P"] ;# Bank 227 - MGTYRXP0_227 +#set_property PACKAGE_PIN AN6 [get_ports "PCIE_EP_RX2_P"] ;# Bank 227 - MGTYRXP1_227 +#set_property PACKAGE_PIN AM4 [get_ports "PCIE_EP_RX1_P"] ;# Bank 227 - MGTYRXP2_227 +#set_property PACKAGE_PIN AL2 [get_ports "PCIE_EP_RX0_P"] ;# Bank 227 - MGTYRXP3_227 +#set_property PACKAGE_PIN AP8 [get_ports "PCIE_EP_TX3_N"] ;# Bank 227 - MGTYTXN0_227 +#set_property PACKAGE_PIN AN10 [get_ports "PCIE_EP_TX2_N"] ;# Bank 227 - MGTYTXN1_227 +#set_property PACKAGE_PIN AM8 [get_ports "PCIE_EP_TX1_N"] ;# Bank 227 - MGTYTXN2_227 +#set_property PACKAGE_PIN AL10 [get_ports "PCIE_EP_TX0_N"] ;# Bank 227 - MGTYTXN3_227 +#set_property PACKAGE_PIN AP9 [get_ports "PCIE_EP_TX3_P"] ;# Bank 227 - MGTYTXP0_227 +#set_property PACKAGE_PIN AN11 [get_ports "PCIE_EP_TX2_P"] ;# Bank 227 - MGTYTXP1_227 +#set_property PACKAGE_PIN AM9 [get_ports "PCIE_EP_TX1_P"] ;# Bank 227 - MGTYTXP2_227 +#set_property PACKAGE_PIN AL11 [get_ports "PCIE_EP_TX0_P"] ;# Bank 227 - MGTYTXP3_227 +#set_property PACKAGE_PIN AJ14 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK0N_228 +#set_property PACKAGE_PIN AJ15 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK0P_228 +#set_property PACKAGE_PIN AH12 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK1N_228 +#set_property PACKAGE_PIN AH13 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK1P_228 +#set_property PACKAGE_PIN AL5 [get_ports "GND"] ;# Bank 228 - MGTYRXN0_228 +#set_property PACKAGE_PIN AK3 [get_ports "GND"] ;# Bank 228 - MGTYRXN1_228 +#set_property PACKAGE_PIN AJ1 [get_ports "GND"] ;# Bank 228 - MGTYRXN2_228 +#set_property PACKAGE_PIN AH3 [get_ports "GND"] ;# Bank 228 - MGTYRXN3_228 +#set_property PACKAGE_PIN AL6 [get_ports "GND"] ;# Bank 228 - MGTYRXP0_228 +#set_property PACKAGE_PIN AK4 [get_ports "GND"] ;# Bank 228 - MGTYRXP1_228 +#set_property PACKAGE_PIN AJ2 [get_ports "GND"] ;# Bank 228 - MGTYRXP2_228 +#set_property PACKAGE_PIN AH4 [get_ports "GND"] ;# Bank 228 - MGTYRXP3_228 +#set_property PACKAGE_PIN AK8 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN0_228 +#set_property PACKAGE_PIN AJ6 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN1_228 +#set_property PACKAGE_PIN AJ10 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN2_228 +#set_property PACKAGE_PIN AH8 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN3_228 +#set_property PACKAGE_PIN AK9 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP0_228 +#set_property PACKAGE_PIN AJ7 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP1_228 +#set_property PACKAGE_PIN AJ11 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP2_228 +#set_property PACKAGE_PIN AH9 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP3_228 +#set_property PACKAGE_PIN AG14 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK0N_229 +#set_property PACKAGE_PIN AG15 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK0P_229 +#set_property PACKAGE_PIN AF12 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK1N_229 +#set_property PACKAGE_PIN AF13 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK1P_229 +#set_property PACKAGE_PIN AE14 [get_ports "N22480070"] ;# Bank 229 - MGTRREF_RC +#set_property PACKAGE_PIN AG1 [get_ports "GND"] ;# Bank 229 - MGTYRXN0_229 +#set_property PACKAGE_PIN AF3 [get_ports "GND"] ;# Bank 229 - MGTYRXN1_229 +#set_property PACKAGE_PIN AE1 [get_ports "GND"] ;# Bank 229 - MGTYRXN2_229 +#set_property PACKAGE_PIN AE5 [get_ports "GND"] ;# Bank 229 - MGTYRXN3_229 +#set_property PACKAGE_PIN AG2 [get_ports "GND"] ;# Bank 229 - MGTYRXP0_229 +#set_property PACKAGE_PIN AF4 [get_ports "GND"] ;# Bank 229 - MGTYRXP1_229 +#set_property PACKAGE_PIN AE2 [get_ports "GND"] ;# Bank 229 - MGTYRXP2_229 +#set_property PACKAGE_PIN AE6 [get_ports "GND"] ;# Bank 229 - MGTYRXP3_229 +#set_property PACKAGE_PIN AG6 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN0_229 +#set_property PACKAGE_PIN AG10 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN1_229 +#set_property PACKAGE_PIN AF8 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN2_229 +#set_property PACKAGE_PIN AE10 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN3_229 +#set_property PACKAGE_PIN AG7 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP0_229 +#set_property PACKAGE_PIN AG11 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP1_229 +#set_property PACKAGE_PIN AF9 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP2_229 +#set_property PACKAGE_PIN AE11 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP3_229 +#set_property PACKAGE_PIN AD12 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK0N_230 +#set_property PACKAGE_PIN AD13 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK0P_230 +#set_property PACKAGE_PIN AC14 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK1N_230 +#set_property PACKAGE_PIN AC15 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK1P_230 +#set_property PACKAGE_PIN AD3 [get_ports "GND"] ;# Bank 230 - MGTYRXN0_230 +#set_property PACKAGE_PIN AC1 [get_ports "GND"] ;# Bank 230 - MGTYRXN1_230 +#set_property PACKAGE_PIN AC5 [get_ports "GND"] ;# Bank 230 - MGTYRXN2_230 +#set_property PACKAGE_PIN AB3 [get_ports "GND"] ;# Bank 230 - MGTYRXN3_230 +#set_property PACKAGE_PIN AD4 [get_ports "GND"] ;# Bank 230 - MGTYRXP0_230 +#set_property PACKAGE_PIN AC2 [get_ports "GND"] ;# Bank 230 - MGTYRXP1_230 +#set_property PACKAGE_PIN AC6 [get_ports "GND"] ;# Bank 230 - MGTYRXP2_230 +#set_property PACKAGE_PIN AB4 [get_ports "GND"] ;# Bank 230 - MGTYRXP3_230 +#set_property PACKAGE_PIN AD8 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN0_230 +#set_property PACKAGE_PIN AC10 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN1_230 +#set_property PACKAGE_PIN AB8 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN2_230 +#set_property PACKAGE_PIN AA6 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN3_230 +#set_property PACKAGE_PIN AD9 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP0_230 +#set_property PACKAGE_PIN AC11 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP1_230 +#set_property PACKAGE_PIN AB9 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP2_230 +#set_property PACKAGE_PIN AA7 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP3_230 +#set_property PACKAGE_PIN AB12 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK0N_231 +#set_property PACKAGE_PIN AB13 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK0P_231 +#set_property PACKAGE_PIN AA14 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK1N_231 +#set_property PACKAGE_PIN AA15 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK1P_231 +#set_property PACKAGE_PIN AA1 [get_ports "GND"] ;# Bank 231 - MGTYRXN0_231 +#set_property PACKAGE_PIN Y3 [get_ports "GND"] ;# Bank 231 - MGTYRXN1_231 +#set_property PACKAGE_PIN W1 [get_ports "GND"] ;# Bank 231 - MGTYRXN2_231 +#set_property PACKAGE_PIN V3 [get_ports "GND"] ;# Bank 231 - MGTYRXN3_231 +#set_property PACKAGE_PIN AA2 [get_ports "GND"] ;# Bank 231 - MGTYRXP0_231 +#set_property PACKAGE_PIN Y4 [get_ports "GND"] ;# Bank 231 - MGTYRXP1_231 +#set_property PACKAGE_PIN W2 [get_ports "GND"] ;# Bank 231 - MGTYRXP2_231 +#set_property PACKAGE_PIN V4 [get_ports "GND"] ;# Bank 231 - MGTYRXP3_231 +#set_property PACKAGE_PIN AA10 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN0_231 +#set_property PACKAGE_PIN Y8 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN1_231 +#set_property PACKAGE_PIN W6 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN2_231 +#set_property PACKAGE_PIN W10 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN3_231 +#set_property PACKAGE_PIN AA11 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP0_231 +#set_property PACKAGE_PIN Y9 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP1_231 +#set_property PACKAGE_PIN W7 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP2_231 +#set_property PACKAGE_PIN W11 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP3_231 +#set_property PACKAGE_PIN Y12 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK0N_232 +#set_property PACKAGE_PIN Y13 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK0P_232 +#set_property PACKAGE_PIN W14 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK1N_232 +#set_property PACKAGE_PIN W15 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK1P_232 +#set_property PACKAGE_PIN U1 [get_ports "GND"] ;# Bank 232 - MGTYRXN0_232 +#set_property PACKAGE_PIN U5 [get_ports "GND"] ;# Bank 232 - MGTYRXN1_232 +#set_property PACKAGE_PIN T3 [get_ports "GND"] ;# Bank 232 - MGTYRXN2_232 +#set_property PACKAGE_PIN R1 [get_ports "GND"] ;# Bank 232 - MGTYRXN3_232 +#set_property PACKAGE_PIN U2 [get_ports "GND"] ;# Bank 232 - MGTYRXP0_232 +#set_property PACKAGE_PIN U6 [get_ports "GND"] ;# Bank 232 - MGTYRXP1_232 +#set_property PACKAGE_PIN T4 [get_ports "GND"] ;# Bank 232 - MGTYRXP2_232 +#set_property PACKAGE_PIN R2 [get_ports "GND"] ;# Bank 232 - MGTYRXP3_232 +#set_property PACKAGE_PIN V8 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN0_232 +#set_property PACKAGE_PIN U10 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN1_232 +#set_property PACKAGE_PIN T8 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN2_232 +#set_property PACKAGE_PIN R10 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN3_232 +#set_property PACKAGE_PIN V9 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP0_232 +#set_property PACKAGE_PIN U11 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP1_232 +#set_property PACKAGE_PIN T9 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP2_232 +#set_property PACKAGE_PIN R11 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP3_232 +#set_property PACKAGE_PIN V12 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK0N_233 +#set_property PACKAGE_PIN V13 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK0P_233 +#set_property PACKAGE_PIN U14 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK1N_233 +#set_property PACKAGE_PIN U15 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK1P_233 +#set_property PACKAGE_PIN N14 [get_ports "N22119643"] ;# Bank 233 - MGTRREF_RN +#set_property PACKAGE_PIN R5 [get_ports "GND"] ;# Bank 233 - MGTYRXN0_233 +#set_property PACKAGE_PIN P3 [get_ports "GND"] ;# Bank 233 - MGTYRXN1_233 +#set_property PACKAGE_PIN N1 [get_ports "GND"] ;# Bank 233 - MGTYRXN2_233 +#set_property PACKAGE_PIN M3 [get_ports "GND"] ;# Bank 233 - MGTYRXN3_233 +#set_property PACKAGE_PIN R6 [get_ports "GND"] ;# Bank 233 - MGTYRXP0_233 +#set_property PACKAGE_PIN P4 [get_ports "GND"] ;# Bank 233 - MGTYRXP1_233 +#set_property PACKAGE_PIN N2 [get_ports "GND"] ;# Bank 233 - MGTYRXP2_233 +#set_property PACKAGE_PIN M4 [get_ports "GND"] ;# Bank 233 - MGTYRXP3_233 +#set_property PACKAGE_PIN P8 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN0_233 +#set_property PACKAGE_PIN N6 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN1_233 +#set_property PACKAGE_PIN N10 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN2_233 +#set_property PACKAGE_PIN M8 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN3_233 +#set_property PACKAGE_PIN P9 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP0_233 +#set_property PACKAGE_PIN N7 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP1_233 +#set_property PACKAGE_PIN N11 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP2_233 +#set_property PACKAGE_PIN M9 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP3_233 +#set_property PACKAGE_PIN T12 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK0N_234 +#set_property PACKAGE_PIN T13 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK0P_234 +#set_property PACKAGE_PIN R14 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK1N_234 +#set_property PACKAGE_PIN R15 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK1P_234 +#set_property PACKAGE_PIN L1 [get_ports "GND"] ;# Bank 234 - MGTYRXN0_234 +#set_property PACKAGE_PIN K3 [get_ports "GND"] ;# Bank 234 - MGTYRXN1_234 +#set_property PACKAGE_PIN J1 [get_ports "GND"] ;# Bank 234 - MGTYRXN2_234 +#set_property PACKAGE_PIN H3 [get_ports "GND"] ;# Bank 234 - MGTYRXN3_234 +#set_property PACKAGE_PIN L2 [get_ports "GND"] ;# Bank 234 - MGTYRXP0_234 +#set_property PACKAGE_PIN K4 [get_ports "GND"] ;# Bank 234 - MGTYRXP1_234 +#set_property PACKAGE_PIN J2 [get_ports "GND"] ;# Bank 234 - MGTYRXP2_234 +#set_property PACKAGE_PIN H4 [get_ports "GND"] ;# Bank 234 - MGTYRXP3_234 +#set_property PACKAGE_PIN L6 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN0_234 +#set_property PACKAGE_PIN L10 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN1_234 +#set_property PACKAGE_PIN K8 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN2_234 +#set_property PACKAGE_PIN J6 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN3_234 +#set_property PACKAGE_PIN L7 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP0_234 +#set_property PACKAGE_PIN L11 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP1_234 +#set_property PACKAGE_PIN K9 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP2_234 +#set_property PACKAGE_PIN J7 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP3_234 +#set_property PACKAGE_PIN P12 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK0N_235 +#set_property PACKAGE_PIN P13 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK0P_235 +#set_property PACKAGE_PIN M12 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK1N_235 +#set_property PACKAGE_PIN M13 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK1P_235 +#set_property PACKAGE_PIN G1 [get_ports "GND"] ;# Bank 235 - MGTYRXN0_235 +#set_property PACKAGE_PIN F3 [get_ports "GND"] ;# Bank 235 - MGTYRXN1_235 +#set_property PACKAGE_PIN E1 [get_ports "GND"] ;# Bank 235 - MGTYRXN2_235 +#set_property PACKAGE_PIN D3 [get_ports "GND"] ;# Bank 235 - MGTYRXN3_235 +#set_property PACKAGE_PIN G2 [get_ports "GND"] ;# Bank 235 - MGTYRXP0_235 +#set_property PACKAGE_PIN F4 [get_ports "GND"] ;# Bank 235 - MGTYRXP1_235 +#set_property PACKAGE_PIN E2 [get_ports "GND"] ;# Bank 235 - MGTYRXP2_235 +#set_property PACKAGE_PIN D4 [get_ports "GND"] ;# Bank 235 - MGTYRXP3_235 +#set_property PACKAGE_PIN G6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN0_235 +#set_property PACKAGE_PIN E6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN1_235 +#set_property PACKAGE_PIN C6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN2_235 +#set_property PACKAGE_PIN A5 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN3_235 +#set_property PACKAGE_PIN G7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP0_235 +#set_property PACKAGE_PIN E7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP1_235 +#set_property PACKAGE_PIN C7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP2_235 +#set_property PACKAGE_PIN A6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP3_235 + +set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] +set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] +set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] +set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] + +#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +#connect_debug_port dbg_hub/clk [get_nets clk] diff --git a/target/xilinx/constraints/zcu102.xdc b/target/xilinx/constraints/zcu102.xdc new file mode 100644 index 000000000..c60b72cd4 --- /dev/null +++ b/target/xilinx/constraints/zcu102.xdc @@ -0,0 +1,1100 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +############# +# Sys clock # +############# + +# 300 MHz ref clock +set SYS_TCK 3.332 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +# Dram axi clock : 833ps * 4 +set MIG_TCK 3.332 +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk} +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK +set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK + + + +################################################################################# + +############### +# ASSIGN PINS # +############### + +################################################# +### ZCU102 Rev1.0 Master XDC file 09-15-2016 #### +################################################# +#Other net PACKAGE_PIN W17 - SYSMON_DXN Bank 0 - DXN +#Other net PACKAGE_PIN T18 - FPGA_SYSMON_AVCC Bank 0 - VCCADC +#Other net PACKAGE_PIN T17 - SYSMON_AGND Bank 0 - GNDADC +#Other net PACKAGE_PIN W18 - SYSMON_DXP Bank 0 - DXP +#Other net PACKAGE_PIN V18 - SYSMON_VREFP Bank 0 - VREFP +#Other net PACKAGE_PIN U17 - SYSMON_AGND Bank 0 - VREFN +#Other net PACKAGE_PIN U18 - SYSMON_VP_R Bank 0 - VP +#Other net PACKAGE_PIN V17 - SYSMON_VN_R Bank 0 - VN +#Other net PACKAGE_PIN AD15 - 3N5822 Bank 0 - PUDC_B_0 +#Other net PACKAGE_PIN AD14 - 3N5824 Bank 0 - POR_OVERRIDE +#set_property PACKAGE_PIN J15 [get_ports "L12N_AD8N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L12N_AD8N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50 +#set_property PACKAGE_PIN J16 [get_ports "L12P_AD8P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L12P_AD8P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50 +#set_property PACKAGE_PIN G16 [get_ports "L11N_AD9N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L11N_AD9N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L11N_AD9N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L11N_AD9N_50 +#set_property PACKAGE_PIN H16 [get_ports "L11P_AD9P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L11P_AD9P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L11P_AD9P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L11P_AD9P_50 +#set_property PACKAGE_PIN H14 [get_ports "L10N_AD10N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L10N_AD10N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L10N_AD10N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L10N_AD10N_50 +#set_property PACKAGE_PIN J14 [get_ports "L10P_AD10P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L10P_AD10P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L10P_AD10P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L10P_AD10P_50 +#set_property PACKAGE_PIN G14 [get_ports "L9N_AD11N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L9N_AD11N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L9N_AD11N_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L9N_AD11N_50 +#set_property PACKAGE_PIN G15 [get_ports "L9P_AD11P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L9P_AD11P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L9P_AD11P_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L9P_AD11P_50 +#set_property PACKAGE_PIN G13 [get_ports "L8N_HDGC_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L8N_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L8N_HDGC_50_N"] ;# Bank 50 VCCO - VCC3V3 - IO_L8N_HDGC_50 +#set_property PACKAGE_PIN H13 [get_ports "L8P_HDGC_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L8P_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "L8P_HDGC_50_P"] ;# Bank 50 VCCO - VCC3V3 - IO_L8P_HDGC_50 +#set_property PACKAGE_PIN H12 [get_ports "HDMI_SI5324_LOL"] ;# Bank 50 VCCO - VCC3V3 - IO_L7N_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_LOL"] ;# Bank 50 VCCO - VCC3V3 - IO_L7N_HDGC_50 +#set_property PACKAGE_PIN J12 [get_ports "HDMI_SI5324_RST"] ;# Bank 50 VCCO - VCC3V3 - IO_L7P_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_RST"] ;# Bank 50 VCCO - VCC3V3 - IO_L7P_HDGC_50 +#set_property PACKAGE_PIN F11 [get_ports "HDMI_SI5324_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L6N_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_SI5324_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L6N_HDGC_50 +#set_property PACKAGE_PIN F12 [get_ports "34N8121"] ;# Bank 50 VCCO - VCC3V3 - IO_L6P_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "34N8121"] ;# Bank 50 VCCO - VCC3V3 - IO_L6P_HDGC_50 +#set_property PACKAGE_PIN G11 [get_ports "34N8125"] ;# Bank 50 VCCO - VCC3V3 - IO_L5N_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "34N8125"] ;# Bank 50 VCCO - VCC3V3 - IO_L5N_HDGC_50 +#set_property PACKAGE_PIN H11 [get_ports "34N8129"] ;# Bank 50 VCCO - VCC3V3 - IO_L5P_HDGC_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "34N8129"] ;# Bank 50 VCCO - VCC3V3 - IO_L5P_HDGC_50 +#set_property PACKAGE_PIN D10 [get_ports "34N8133"] ;# Bank 50 VCCO - VCC3V3 - IO_L4N_AD12N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "34N8133"] ;# Bank 50 VCCO - VCC3V3 - IO_L4N_AD12N_50 +#set_property PACKAGE_PIN D11 [get_ports "MSP430_GPIO_PL_0"] ;# Bank 50 VCCO - VCC3V3 - IO_L4P_AD12P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_0"] ;# Bank 50 VCCO - VCC3V3 - IO_L4P_AD12P_50 +#set_property PACKAGE_PIN E10 [get_ports "MSP430_GPIO_PL_1"] ;# Bank 50 VCCO - VCC3V3 - IO_L3N_AD13N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_1"] ;# Bank 50 VCCO - VCC3V3 - IO_L3N_AD13N_50 +#set_property PACKAGE_PIN F10 [get_ports "MSP430_GPIO_PL_2"] ;# Bank 50 VCCO - VCC3V3 - IO_L3P_AD13P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_2"] ;# Bank 50 VCCO - VCC3V3 - IO_L3P_AD13P_50 +#set_property PACKAGE_PIN G10 [get_ports "MSP430_GPIO_PL_3"] ;# Bank 50 VCCO - VCC3V3 - IO_L2N_AD14N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_3"] ;# Bank 50 VCCO - VCC3V3 - IO_L2N_AD14N_50 +#set_property PACKAGE_PIN H10 [get_ports "SFP_SI5328_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L2P_AD14P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "SFP_SI5328_INT_ALM"] ;# Bank 50 VCCO - VCC3V3 - IO_L2P_AD14P_50 +#set_property PACKAGE_PIN J10 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 +#set_property PACKAGE_PIN J11 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 +#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 +set_property PACKAGE_PIN E13 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property IOSTANDARD LVCMOS33 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property PACKAGE_PIN F13 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +#set_property PACKAGE_PIN D12 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 +#set_property PACKAGE_PIN E12 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 +#set_property PACKAGE_PIN B12 [get_ports "MSP430_UCA1_TXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10N_AD10N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_TXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10N_AD10N_49 +#set_property PACKAGE_PIN C12 [get_ports "MSP430_UCA1_RXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10P_AD10P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_UCA1_RXD"] ;# Bank 49 VCCO - VCC3V3 - IO_L10P_AD10P_49 +#set_property PACKAGE_PIN A12 [get_ports "SFP0_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9N_AD11N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "SFP0_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9N_AD11N_49 +#set_property PACKAGE_PIN A13 [get_ports "SFP1_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9P_AD11P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "SFP1_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L9P_AD11P_49 +#set_property PACKAGE_PIN B13 [get_ports "SFP2_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8N_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "SFP2_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8N_HDGC_49 +#set_property PACKAGE_PIN C13 [get_ports "SFP3_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8P_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "SFP3_TX_DISABLE"] ;# Bank 49 VCCO - VCC3V3 - IO_L8P_HDGC_49 +#set_property PACKAGE_PIN B14 [get_ports "SYSMON_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L7N_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L7N_HDGC_49 +#set_property PACKAGE_PIN C14 [get_ports "SYSMON_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L7P_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "SYSMON_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L7P_HDGC_49 +#set_property PACKAGE_PIN D14 [get_ports "HDMI_RX_PWR_DET"] ;# Bank 49 VCCO - VCC3V3 - IO_L6N_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_PWR_DET"] ;# Bank 49 VCCO - VCC3V3 - IO_L6N_HDGC_49 +#set_property PACKAGE_PIN E14 [get_ports "HDMI_RX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L6P_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L6P_HDGC_49 +#set_property PACKAGE_PIN D15 [get_ports "HDMI_RX_CEC_SINK"] ;# Bank 49 VCCO - VCC3V3 - IO_L5N_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_CEC_SINK"] ;# Bank 49 VCCO - VCC3V3 - IO_L5N_HDGC_49 +#set_property PACKAGE_PIN E15 [get_ports "HDMI_RX_SNK_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L5P_HDGC_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L5P_HDGC_49 +#set_property PACKAGE_PIN A15 [get_ports "HDMI_RX_SNK_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L4N_AD12N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_RX_SNK_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L4N_AD12N_49 +#set_property PACKAGE_PIN B15 [get_ports "HDMI_TX_EN"] ;# Bank 49 VCCO - VCC3V3 - IO_L4P_AD12P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_EN"] ;# Bank 49 VCCO - VCC3V3 - IO_L4P_AD12P_49 +#set_property PACKAGE_PIN A16 [get_ports "HDMI_TX_CEC"] ;# Bank 49 VCCO - VCC3V3 - IO_L3N_AD13N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_CEC"] ;# Bank 49 VCCO - VCC3V3 - IO_L3N_AD13N_49 +#set_property PACKAGE_PIN B16 [get_ports "HDMI_TX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L3P_AD13P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_HPD"] ;# Bank 49 VCCO - VCC3V3 - IO_L3P_AD13P_49 +#set_property PACKAGE_PIN C16 [get_ports "HDMI_TX_SRC_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L2N_AD14N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L2N_AD14N_49 +#set_property PACKAGE_PIN D16 [get_ports "HDMI_TX_SRC_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L2P_AD14P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_TX_SRC_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L2P_AD14P_49 +#set_property PACKAGE_PIN F15 [get_ports "HDMI_CTL_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L1N_AD15N_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SCL"] ;# Bank 49 VCCO - VCC3V3 - IO_L1N_AD15N_49 +#set_property PACKAGE_PIN F16 [get_ports "HDMI_CTL_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L1P_AD15P_49 +#set_property IOSTANDARD LVCMOS33 [get_ports "HDMI_CTL_SDA"] ;# Bank 49 VCCO - VCC3V3 - IO_L1P_AD15P_49 +#set_property PACKAGE_PIN A18 [get_ports "TRACEDBGRQ"] ;# Bank 48 VCCO - VCC3V3 - IO_L12N_AD8N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGRQ"] ;# Bank 48 VCCO - VCC3V3 - IO_L12N_AD8N_48 +#set_property PACKAGE_PIN A17 [get_ports "TRACESRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L12P_AD8P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACESRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L12P_AD8P_48 +#set_property PACKAGE_PIN C19 [get_ports "TRACETDO"] ;# Bank 48 VCCO - VCC3V3 - IO_L11N_AD9N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDO"] ;# Bank 48 VCCO - VCC3V3 - IO_L11N_AD9N_48 +#set_property PACKAGE_PIN C18 [get_ports "TRACERTCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L11P_AD9P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACERTCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L11P_AD9P_48 +#set_property PACKAGE_PIN B19 [get_ports "TRACETCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L10N_AD10N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETCK"] ;# Bank 48 VCCO - VCC3V3 - IO_L10N_AD10N_48 +#set_property PACKAGE_PIN B18 [get_ports "TRACETMS"] ;# Bank 48 VCCO - VCC3V3 - IO_L10P_AD10P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETMS"] ;# Bank 48 VCCO - VCC3V3 - IO_L10P_AD10P_48 +#set_property PACKAGE_PIN C17 [get_ports "TRACETDI"] ;# Bank 48 VCCO - VCC3V3 - IO_L9N_AD11N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETDI"] ;# Bank 48 VCCO - VCC3V3 - IO_L9N_AD11N_48 +#set_property PACKAGE_PIN D17 [get_ports "TRACETRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L9P_AD11P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACETRST_B"] ;# Bank 48 VCCO - VCC3V3 - IO_L9P_AD11P_48 +#set_property PACKAGE_PIN E18 [get_ports "TRACEDATA15"] ;# Bank 48 VCCO - VCC3V3 - IO_L8N_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA15"] ;# Bank 48 VCCO - VCC3V3 - IO_L8N_HDGC_48 +#set_property PACKAGE_PIN E17 [get_ports "TRACEDATA14"] ;# Bank 48 VCCO - VCC3V3 - IO_L8P_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA14"] ;# Bank 48 VCCO - VCC3V3 - IO_L8P_HDGC_48 +#set_property PACKAGE_PIN D19 [get_ports "TRACEDATA13"] ;# Bank 48 VCCO - VCC3V3 - IO_L7N_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA13"] ;# Bank 48 VCCO - VCC3V3 - IO_L7N_HDGC_48 +#set_property PACKAGE_PIN E19 [get_ports "TRACEDATA12"] ;# Bank 48 VCCO - VCC3V3 - IO_L7P_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA12"] ;# Bank 48 VCCO - VCC3V3 - IO_L7P_HDGC_48 +#set_property PACKAGE_PIN F18 [get_ports "TRACEDATA11"] ;# Bank 48 VCCO - VCC3V3 - IO_L6N_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA11"] ;# Bank 48 VCCO - VCC3V3 - IO_L6N_HDGC_48 +#set_property PACKAGE_PIN F17 [get_ports "TRACEDATA10"] ;# Bank 48 VCCO - VCC3V3 - IO_L6P_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA10"] ;# Bank 48 VCCO - VCC3V3 - IO_L6P_HDGC_48 +#set_property PACKAGE_PIN G19 [get_ports "TRACEDATA9"] ;# Bank 48 VCCO - VCC3V3 - IO_L5N_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA9"] ;# Bank 48 VCCO - VCC3V3 - IO_L5N_HDGC_48 +#set_property PACKAGE_PIN G18 [get_ports "TRACEDATA8"] ;# Bank 48 VCCO - VCC3V3 - IO_L5P_HDGC_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA8"] ;# Bank 48 VCCO - VCC3V3 - IO_L5P_HDGC_48 +#set_property PACKAGE_PIN K17 [get_ports "TRACECLKA"] ;# Bank 48 VCCO - VCC3V3 - IO_L4N_AD12N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACECLKA"] ;# Bank 48 VCCO - VCC3V3 - IO_L4N_AD12N_48 +#set_property PACKAGE_PIN L17 [get_ports "TRACEDBGACK"] ;# Bank 48 VCCO - VCC3V3 - IO_L4P_AD12P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDBGACK"] ;# Bank 48 VCCO - VCC3V3 - IO_L4P_AD12P_48 +#set_property PACKAGE_PIN K18 [get_ports "TRACEEXTTRIG"] ;# Bank 48 VCCO - VCC3V3 - IO_L3N_AD13N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEEXTTRIG"] ;# Bank 48 VCCO - VCC3V3 - IO_L3N_AD13N_48 +#set_property PACKAGE_PIN L18 [get_ports "TRACEDATA7"] ;# Bank 48 VCCO - VCC3V3 - IO_L3P_AD13P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA7"] ;# Bank 48 VCCO - VCC3V3 - IO_L3P_AD13P_48 +#set_property PACKAGE_PIN H17 [get_ports "TRACEDATA6"] ;# Bank 48 VCCO - VCC3V3 - IO_L2N_AD14N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA6"] ;# Bank 48 VCCO - VCC3V3 - IO_L2N_AD14N_48 +#set_property PACKAGE_PIN J17 [get_ports "TRACEDATA5"] ;# Bank 48 VCCO - VCC3V3 - IO_L2P_AD14P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA5"] ;# Bank 48 VCCO - VCC3V3 - IO_L2P_AD14P_48 +#set_property PACKAGE_PIN H19 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 +#set_property PACKAGE_PIN H18 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 +set_property PACKAGE_PIN A20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property PACKAGE_PIN B20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +set_property PACKAGE_PIN A22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +set_property PACKAGE_PIN A21 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +#set_property PACKAGE_PIN B21 [get_ports "jtag_trst_ni"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_trst_ni"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 +#set_property PACKAGE_PIN C21 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 +#set_property PACKAGE_PIN C22 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 +#set_property PACKAGE_PIN D21 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 +#set_property PACKAGE_PIN D20 [get_ports "PMOD1_0"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_0"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +#set_property PACKAGE_PIN E20 [get_ports "PMOD1_1"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_1"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +#set_property PACKAGE_PIN D22 [get_ports "PMOD1_2"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_2"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 +#set_property PACKAGE_PIN E22 [get_ports "PMOD1_3"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_3"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 +#set_property PACKAGE_PIN F20 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 +#set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 +#set_property PACKAGE_PIN F21 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -> CLK_125_N +#set_property IOSTANDARD LVDS_25 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -> CLK_125_N +#set_property PACKAGE_PIN G21 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -> CLK_125_P +#set_property IOSTANDARD LVDS_25 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -> CLK_125_P +#set_property PACKAGE_PIN J20 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 +#set_property PACKAGE_PIN J19 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 +#set_property PACKAGE_PIN H21 [get_ports "TRACEDATA2"] ;# Bank 47 VCCO - VCC3V3 - IO_L3N_AD9N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA2"] ;# Bank 47 VCCO - VCC3V3 - IO_L3N_AD9N_47 +#set_property PACKAGE_PIN J21 [get_ports "TRACEDATA1"] ;# Bank 47 VCCO - VCC3V3 - IO_L3P_AD9P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA1"] ;# Bank 47 VCCO - VCC3V3 - IO_L3P_AD9P_47 +#set_property PACKAGE_PIN K19 [get_ports "TRACECTL"] ;# Bank 47 VCCO - VCC3V3 - IO_L2N_AD10N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACECTL"] ;# Bank 47 VCCO - VCC3V3 - IO_L2N_AD10N_47 +#set_property PACKAGE_PIN L19 [get_ports "TRACEDATA0"] ;# Bank 47 VCCO - VCC3V3 - IO_L2P_AD10P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA0"] ;# Bank 47 VCCO - VCC3V3 - IO_L2P_AD10P_47 +#set_property PACKAGE_PIN K20 [get_ports "PL_I2C1_SCL_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1N_AD11N_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SCL_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1N_AD11N_47 +#set_property PACKAGE_PIN L20 [get_ports "PL_I2C1_SDA_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1P_AD11P_47 +#set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C1_SDA_LS"] ;# Bank 47 VCCO - VCC3V3 - IO_L1P_AD11P_47 +#set_property PACKAGE_PIN AE14 [get_ports "GPIO_SW_E"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_E"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44 +#set_property PACKAGE_PIN AE15 [get_ports "GPIO_SW_S"] ;# Bank 44 VCCO - VCC3V3 - IO_L12P_AD0P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_S"] ;# Bank 44 VCCO - VCC3V3 - IO_L12P_AD0P_44 +#set_property PACKAGE_PIN AG15 [get_ports "GPIO_SW_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L11N_AD1N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L11N_AD1N_44 +#set_property PACKAGE_PIN AF15 [get_ports "GPIO_SW_W"] ;# Bank 44 VCCO - VCC3V3 - IO_L11P_AD1P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_W"] ;# Bank 44 VCCO - VCC3V3 - IO_L11P_AD1P_44 +#set_property PACKAGE_PIN AG13 [get_ports "GPIO_SW_C"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_SW_C"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 +#set_property PACKAGE_PIN AG14 [get_ports "GPIO_LED_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 +#set_property PACKAGE_PIN AF13 [get_ports "GPIO_LED_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 +#set_property PACKAGE_PIN AE13 [get_ports "GPIO_LED_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 +#set_property PACKAGE_PIN AJ14 [get_ports "GPIO_LED_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 +#set_property PACKAGE_PIN AJ15 [get_ports "GPIO_LED_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 +#set_property PACKAGE_PIN AH13 [get_ports "GPIO_LED_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 +#set_property PACKAGE_PIN AH14 [get_ports "GPIO_LED_6"] ;# Bank 44 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_6"] ;# Bank 44 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_44 +#set_property PACKAGE_PIN AL12 [get_ports "GPIO_LED_7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_LED_7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_44 +#set_property PACKAGE_PIN AK13 [get_ports "GPIO_DIP_SW7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW7"] ;# Bank 44 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_44 +#set_property PACKAGE_PIN AK14 [get_ports "CLK_74_25_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_44 +#set_property IOSTANDARD LVDS_25 [get_ports "CLK_74_25_N"] ;# Bank 44 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_44 +#set_property PACKAGE_PIN AK15 [get_ports "CLK_74_25_P"] ;# Bank 44 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_44 +#set_property IOSTANDARD LVDS_25 [get_ports "CLK_74_25_P"] ;# Bank 44 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_44 +set_property PACKAGE_PIN AM13 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44 +#set_property PACKAGE_PIN AL13 [get_ports "GPIO_DIP_SW6"] ;# Bank 44 VCCO - VCC3V3 - IO_L4P_AD8P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW6"] ;# Bank 44 VCCO - VCC3V3 - IO_L4P_AD8P_44 +#set_property PACKAGE_PIN AP12 [get_ports "GPIO_DIP_SW5"] ;# Bank 44 VCCO - VCC3V3 - IO_L3N_AD9N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW5"] ;# Bank 44 VCCO - VCC3V3 - IO_L3N_AD9N_44 +#set_property PACKAGE_PIN AN12 [get_ports "GPIO_DIP_SW4"] ;# Bank 44 VCCO - VCC3V3 - IO_L3P_AD9P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW4"] ;# Bank 44 VCCO - VCC3V3 - IO_L3P_AD9P_44 +#set_property PACKAGE_PIN AN13 [get_ports "GPIO_DIP_SW3"] ;# Bank 44 VCCO - VCC3V3 - IO_L2N_AD10N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW3"] ;# Bank 44 VCCO - VCC3V3 - IO_L2N_AD10N_44 +#set_property PACKAGE_PIN AM14 [get_ports "GPIO_DIP_SW2"] ;# Bank 44 VCCO - VCC3V3 - IO_L2P_AD10P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW2"] ;# Bank 44 VCCO - VCC3V3 - IO_L2P_AD10P_44 +#set_property PACKAGE_PIN AP14 [get_ports "GPIO_DIP_SW1"] ;# Bank 44 VCCO - VCC3V3 - IO_L1N_AD11N_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW1"] ;# Bank 44 VCCO - VCC3V3 - IO_L1N_AD11N_44 +#set_property PACKAGE_PIN AN14 [get_ports "GPIO_DIP_SW0"] ;# Bank 44 VCCO - VCC3V3 - IO_L1P_AD11P_44 +#set_property IOSTANDARD LVCMOS33 [get_ports "GPIO_DIP_SW0"] ;# Bank 44 VCCO - VCC3V3 - IO_L1P_AD11P_44 +#set_property PACKAGE_PIN K15 [get_ports "FMC_HPC0_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24N_T3U_N11_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24N_T3U_N11_67 +#set_property PACKAGE_PIN L15 [get_ports "FMC_HPC0_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24P_T3U_N10_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L24P_T3U_N10_67 +#set_property PACKAGE_PIN K13 [get_ports "FMC_HPC0_LA19_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23N_T3U_N9_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA19_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23N_T3U_N9_67 +#set_property PACKAGE_PIN L13 [get_ports "FMC_HPC0_LA19_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23P_T3U_N8_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA19_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L23P_T3U_N8_67 +#set_property PACKAGE_PIN M13 [get_ports "FMC_HPC0_LA20_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA20_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property PACKAGE_PIN N13 [get_ports "FMC_HPC0_LA20_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA20_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property PACKAGE_PIN N12 [get_ports "FMC_HPC0_LA21_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA21_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_67 +#set_property PACKAGE_PIN P12 [get_ports "FMC_HPC0_LA21_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA21_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_67 +#set_property PACKAGE_PIN M14 [get_ports "FMC_HPC0_LA22_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA22_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_67 +#set_property PACKAGE_PIN M15 [get_ports "FMC_HPC0_LA22_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA22_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_67 +#set_property PACKAGE_PIN K16 [get_ports "FMC_HPC0_LA23_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA23_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property PACKAGE_PIN L16 [get_ports "FMC_HPC0_LA23_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA23_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property PACKAGE_PIN K14 [get_ports "7N8557"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8557"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67 +#set_property PACKAGE_PIN K10 [get_ports "7N8560"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8560"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67 +#set_property PACKAGE_PIN K12 [get_ports "FMC_HPC0_LA24_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA24_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67 +#set_property PACKAGE_PIN L12 [get_ports "FMC_HPC0_LA24_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA24_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_67 +#set_property PACKAGE_PIN L11 [get_ports "FMC_HPC0_LA25_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA25_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_67 +#set_property PACKAGE_PIN M11 [get_ports "FMC_HPC0_LA25_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA25_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_67 +#set_property PACKAGE_PIN N8 [get_ports "FMC_HPC0_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property PACKAGE_PIN N9 [get_ports "FMC_HPC0_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property PACKAGE_PIN L10 [get_ports "FMC_HPC0_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_67 +#set_property PACKAGE_PIN M10 [get_ports "FMC_HPC0_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_67 +#set_property PACKAGE_PIN P9 [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_67 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_67 +#set_property PACKAGE_PIN P10 [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_67 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_67 +#set_property PACKAGE_PIN N11 [get_ports "FMC_HPC0_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_67 +#set_property PACKAGE_PIN P11 [get_ports "FMC_HPC0_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_67 +#set_property PACKAGE_PIN R8 [get_ports "FMC_HPC0_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_67 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_67 +#set_property PACKAGE_PIN T8 [get_ports "FMC_HPC0_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_67 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_67 +#set_property PACKAGE_PIN R9 [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67 +#set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67 +#set_property PACKAGE_PIN R10 [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67 +#set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67 +#set_property PACKAGE_PIN T6 [get_ports "FMC_HPC0_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property PACKAGE_PIN T7 [get_ports "FMC_HPC0_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property PACKAGE_PIN U8 [get_ports "FMC_HPC0_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_67 +#set_property PACKAGE_PIN U9 [get_ports "FMC_HPC0_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_67 +#set_property PACKAGE_PIN U6 [get_ports "FMC_HPC0_LA30_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_67 +#set_property PACKAGE_PIN V6 [get_ports "FMC_HPC0_LA30_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_67 +#set_property PACKAGE_PIN V7 [get_ports "FMC_HPC0_LA31_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property PACKAGE_PIN V8 [get_ports "FMC_HPC0_LA31_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property PACKAGE_PIN V9 [get_ports "7N8563"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8563"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67 +#set_property PACKAGE_PIN W10 [get_ports "7N8566"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8566"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67 +#set_property PACKAGE_PIN T11 [get_ports "FMC_HPC0_LA32_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67 +#set_property PACKAGE_PIN U11 [get_ports "FMC_HPC0_LA32_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_67 +#set_property PACKAGE_PIN V11 [get_ports "FMC_HPC0_LA33_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_67 +#set_property PACKAGE_PIN V12 [get_ports "FMC_HPC0_LA33_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_67 +#set_property PACKAGE_PIN R12 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property PACKAGE_PIN T12 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property PACKAGE_PIN T10 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 +#set_property PACKAGE_PIN U10 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 +#set_property PACKAGE_PIN R13 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67 +#set_property PACKAGE_PIN T13 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67 +#set_property PACKAGE_PIN W11 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67 +#set_property PACKAGE_PIN W12 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67 +#Other net PACKAGE_PIN N14 - 7N8332 Bank 67 - VREF_67 +#set_property PACKAGE_PIN W1 [get_ports "FMC_HPC0_LA09_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24N_T3U_N11_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA09_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24N_T3U_N11_66 +#set_property PACKAGE_PIN W2 [get_ports "FMC_HPC0_LA09_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24P_T3U_N10_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA09_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L24P_T3U_N10_66 +#set_property PACKAGE_PIN V1 [get_ports "FMC_HPC0_LA02_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23N_T3U_N9_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA02_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23N_T3U_N9_66 +#set_property PACKAGE_PIN V2 [get_ports "FMC_HPC0_LA02_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23P_T3U_N8_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA02_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L23P_T3U_N8_66 +#set_property PACKAGE_PIN Y1 [get_ports "FMC_HPC0_LA03_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA03_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_66 +#set_property PACKAGE_PIN Y2 [get_ports "FMC_HPC0_LA03_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA03_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property PACKAGE_PIN AA1 [get_ports "FMC_HPC0_LA04_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA04_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_66 +#set_property PACKAGE_PIN AA2 [get_ports "FMC_HPC0_LA04_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA04_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_66 +#set_property PACKAGE_PIN AC3 [get_ports "FMC_HPC0_LA05_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA05_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_66 +#set_property PACKAGE_PIN AB3 [get_ports "FMC_HPC0_LA05_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA05_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_66 +#set_property PACKAGE_PIN AC1 [get_ports "FMC_HPC0_LA06_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA06_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_66 +#set_property PACKAGE_PIN AC2 [get_ports "FMC_HPC0_LA06_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA06_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property PACKAGE_PIN AB1 [get_ports "7N8545"] ;# Bank 66 VCCO - VADJ_FMC - IO_T3U_N12_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8545"] ;# Bank 66 VCCO - VADJ_FMC - IO_T3U_N12_66 +#set_property PACKAGE_PIN AA3 [get_ports "7N8548"] ;# Bank 66 VCCO - VADJ_FMC - IO_T2U_N12_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8548"] ;# Bank 66 VCCO - VADJ_FMC - IO_T2U_N12_66 +#set_property PACKAGE_PIN U4 [get_ports "FMC_HPC0_LA07_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA07_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_66 +#set_property PACKAGE_PIN U5 [get_ports "FMC_HPC0_LA07_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA07_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_66 +#set_property PACKAGE_PIN V3 [get_ports "FMC_HPC0_LA08_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA08_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_66 +#set_property PACKAGE_PIN V4 [get_ports "FMC_HPC0_LA08_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA08_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_66 +#set_property PACKAGE_PIN AC4 [get_ports "FMC_HPC0_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_66 +#set_property PACKAGE_PIN AB4 [get_ports "FMC_HPC0_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_66 +#set_property PACKAGE_PIN W4 [get_ports "FMC_HPC0_LA10_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA10_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_66 +#set_property PACKAGE_PIN W5 [get_ports "FMC_HPC0_LA10_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA10_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_66 +#set_property PACKAGE_PIN AA5 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_66 +#set_property PACKAGE_PIN Y5 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_66 +#set_property PACKAGE_PIN Y3 [get_ports "FMC_HPC0_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_66 +#set_property PACKAGE_PIN Y4 [get_ports "FMC_HPC0_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_66 +#set_property PACKAGE_PIN AA6 [get_ports "FMC_HPC0_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_66 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_66 +#set_property PACKAGE_PIN AA7 [get_ports "FMC_HPC0_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_66 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_66 +#set_property PACKAGE_PIN Y7 [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_66 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_66 +#set_property PACKAGE_PIN Y8 [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_66 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_66 +#set_property PACKAGE_PIN AB5 [get_ports "FMC_HPC0_LA11_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA11_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_66 +#set_property PACKAGE_PIN AB6 [get_ports "FMC_HPC0_LA11_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA11_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_66 +#set_property PACKAGE_PIN W6 [get_ports "FMC_HPC0_LA12_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA12_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_66 +#set_property PACKAGE_PIN W7 [get_ports "FMC_HPC0_LA12_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA12_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_66 +#set_property PACKAGE_PIN AC8 [get_ports "FMC_HPC0_LA13_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA13_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_66 +#set_property PACKAGE_PIN AB8 [get_ports "FMC_HPC0_LA13_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA13_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_66 +#set_property PACKAGE_PIN AC6 [get_ports "FMC_HPC0_LA14_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA14_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_66 +#set_property PACKAGE_PIN AC7 [get_ports "FMC_HPC0_LA14_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA14_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property PACKAGE_PIN AA8 [get_ports "7N8551"] ;# Bank 66 VCCO - VADJ_FMC - IO_T1U_N12_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8551"] ;# Bank 66 VCCO - VADJ_FMC - IO_T1U_N12_66 +#set_property PACKAGE_PIN W9 [get_ports "7N8554"] ;# Bank 66 VCCO - VADJ_FMC - IO_T0U_N12_VRP_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "7N8554"] ;# Bank 66 VCCO - VADJ_FMC - IO_T0U_N12_VRP_66 +#set_property PACKAGE_PIN Y9 [get_ports "FMC_HPC0_LA15_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA15_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_66 +#set_property PACKAGE_PIN Y10 [get_ports "FMC_HPC0_LA15_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA15_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_66 +#set_property PACKAGE_PIN AA12 [get_ports "FMC_HPC0_LA16_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA16_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_66 +#set_property PACKAGE_PIN Y12 [get_ports "FMC_HPC0_LA16_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA16_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_66 +#set_property PACKAGE_PIN AC9 [get_ports "7N8645"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "7N8645"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_66 +#set_property PACKAGE_PIN AB9 [get_ports "7N8643"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "7N8643"] ;# Bank 66 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property PACKAGE_PIN AA10 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_66 +#set_property PACKAGE_PIN AA11 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_66 +#set_property PACKAGE_PIN AB10 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2N_T0L_N3_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2N_T0L_N3_66 +#set_property PACKAGE_PIN AB11 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2P_T0L_N2_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L2P_T0L_N2_66 +#set_property PACKAGE_PIN AC11 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_66 +#set_property PACKAGE_PIN AC12 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_66 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 66 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_66 +#Other net PACKAGE_PIN AD12 - 7N8282 Bank 66 - VREF_66 +#set_property PACKAGE_PIN AE1 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24N_T3U_N11_PERSTN0_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24N_T3U_N11_PERSTN0_65 +#set_property PACKAGE_PIN AE2 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 +#set_property PACKAGE_PIN AD1 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23N_T3U_N9_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23N_T3U_N9_65 +#set_property PACKAGE_PIN AD2 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property PACKAGE_PIN AJ1 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22N_T3U_N7_DBC_AD0N_65 +#set_property PACKAGE_PIN AH1 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L22P_T3U_N6_DBC_AD0P_65 +#set_property PACKAGE_PIN AF1 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21N_T3L_N5_AD8N_65 +#set_property PACKAGE_PIN AF2 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 +#set_property PACKAGE_PIN AH3 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20N_T3L_N3_AD1N_65 +#set_property PACKAGE_PIN AG3 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L20P_T3L_N2_AD1P_65 +#set_property PACKAGE_PIN AJ2 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19N_T3L_N1_DBC_AD9N_65 +#set_property PACKAGE_PIN AH2 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L19P_T3L_N0_DBC_AD9P_65 +#set_property PACKAGE_PIN AG1 [get_ports "6N9904"] ;# Bank 65 VCCO - VADJ_FMC - IO_T3U_N12_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "6N9904"] ;# Bank 65 VCCO - VADJ_FMC - IO_T3U_N12_65 +#set_property PACKAGE_PIN AD5 [get_ports "6N9901"] ;# Bank 65 VCCO - VADJ_FMC - IO_T2U_N12_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "6N9901"] ;# Bank 65 VCCO - VADJ_FMC - IO_T2U_N12_65 +#set_property PACKAGE_PIN AE4 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_65 +#set_property PACKAGE_PIN AD4 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L18P_T2U_N10_AD2P_65 +#set_property PACKAGE_PIN AF3 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17N_T2U_N9_AD10N_65 +#set_property PACKAGE_PIN AE3 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L17P_T2U_N8_AD10P_65 +#set_property PACKAGE_PIN AJ5 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16N_T2U_N7_QBC_AD3N_65 +#set_property PACKAGE_PIN AJ6 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L16P_T2U_N6_QBC_AD3P_65 +#set_property PACKAGE_PIN AJ4 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15N_T2L_N5_AD11N_65 +#set_property PACKAGE_PIN AH4 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L15P_T2L_N4_AD11P_65 +#set_property PACKAGE_PIN AG4 [get_ports "HDMI_REC_CLOCK_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "HDMI_REC_CLOCK_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 +#set_property PACKAGE_PIN AG5 [get_ports "HDMI_REC_CLOCK_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "HDMI_REC_CLOCK_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 +#set_property PACKAGE_PIN AF5 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65 +#set_property PACKAGE_PIN AE5 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 +#set_property PACKAGE_PIN AF7 [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_65 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12N_T1U_N11_GC_65 +#set_property PACKAGE_PIN AE7 [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_65 +#set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L12P_T1U_N10_GC_65 +#set_property PACKAGE_PIN AG6 [get_ports "HDMI_TX_LVDS_OUT_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_65 +#set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_65 +#set_property PACKAGE_PIN AF6 [get_ports "HDMI_TX_LVDS_OUT_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_65 +#set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_65 +#set_property PACKAGE_PIN AF8 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_65 +#set_property PACKAGE_PIN AE8 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_65 +#set_property PACKAGE_PIN AD6 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9N_T1L_N5_AD12N_65 +#set_property PACKAGE_PIN AD7 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L9P_T1L_N4_AD12P_65 +#set_property PACKAGE_PIN AH8 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8N_T1L_N3_AD5N_65 +#set_property PACKAGE_PIN AG8 [get_ports "FMC_HPC1_LA13_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA13_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L8P_T1L_N2_AD5P_65 +#set_property PACKAGE_PIN AH6 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7N_T1L_N1_QBC_AD13N_65 +#set_property PACKAGE_PIN AH7 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L7P_T1L_N0_QBC_AD13P_65 +#set_property PACKAGE_PIN AH9 [get_ports "DDR4_RESET_B_LS"] ;# Bank 65 VCCO - VADJ_FMC - IO_T1U_N12_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "DDR4_RESET_B_LS"] ;# Bank 65 VCCO - VADJ_FMC - IO_T1U_N12_65 +#set_property PACKAGE_PIN AD9 [get_ports "VRP_65"] ;# Bank 65 VCCO - VADJ_FMC - IO_T0U_N12_VRP_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VADJ_FMC - IO_T0U_N12_VRP_65 +#set_property PACKAGE_PIN AE9 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_65 +#set_property PACKAGE_PIN AD10 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_65 +#set_property PACKAGE_PIN AG9 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_65 +#set_property PACKAGE_PIN AG10 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_65 +#set_property PACKAGE_PIN AG11 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_65 +#set_property PACKAGE_PIN AF11 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 +#set_property PACKAGE_PIN AF12 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_65 +#set_property PACKAGE_PIN AE12 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_65 +#set_property PACKAGE_PIN AH11 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2N_T0L_N3_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2N_T0L_N3_65 +#set_property PACKAGE_PIN AH12 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2P_T0L_N2_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L2P_T0L_N2_65 +#set_property PACKAGE_PIN AF10 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_65 +#set_property PACKAGE_PIN AE10 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_65 +#set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 65 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_65 +#Other net PACKAGE_PIN AD11 - 6N9689 Bank 65 - VREF_65 +#set_property PACKAGE_PIN AK2 [get_ports "DDR4_DQ8"] ;# Bank 64 VCCO - VCC1V2 - IO_L24N_T3U_N11_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"] ;# Bank 64 VCCO - VCC1V2 - IO_L24N_T3U_N11_64 +#set_property PACKAGE_PIN AK3 [get_ports "DDR4_DQ9"] ;# Bank 64 VCCO - VCC1V2 - IO_L24P_T3U_N10_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"] ;# Bank 64 VCCO - VCC1V2 - IO_L24P_T3U_N10_64 +#set_property PACKAGE_PIN AL1 [get_ports "DDR4_DQ10"] ;# Bank 64 VCCO - VCC1V2 - IO_L23N_T3U_N9_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"] ;# Bank 64 VCCO - VCC1V2 - IO_L23N_T3U_N9_64 +#set_property PACKAGE_PIN AK1 [get_ports "DDR4_DQ11"] ;# Bank 64 VCCO - VCC1V2 - IO_L23P_T3U_N8_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"] ;# Bank 64 VCCO - VCC1V2 - IO_L23P_T3U_N8_64 +#set_property PACKAGE_PIN AL2 [get_ports "DDR4_DQS1_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 +#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 +#set_property PACKAGE_PIN AL3 [get_ports "DDR4_DQS1_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 +#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 +#set_property PACKAGE_PIN AN1 [get_ports "DDR4_DQ12"] ;# Bank 64 VCCO - VCC1V2 - IO_L21N_T3L_N5_AD8N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"] ;# Bank 64 VCCO - VCC1V2 - IO_L21N_T3L_N5_AD8N_64 +#set_property PACKAGE_PIN AM1 [get_ports "DDR4_DQ13"] ;# Bank 64 VCCO - VCC1V2 - IO_L21P_T3L_N4_AD8P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"] ;# Bank 64 VCCO - VCC1V2 - IO_L21P_T3L_N4_AD8P_64 +#set_property PACKAGE_PIN AP3 [get_ports "DDR4_DQ14"] ;# Bank 64 VCCO - VCC1V2 - IO_L20N_T3L_N3_AD1N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"] ;# Bank 64 VCCO - VCC1V2 - IO_L20N_T3L_N3_AD1N_64 +#set_property PACKAGE_PIN AN3 [get_ports "DDR4_DQ15"] ;# Bank 64 VCCO - VCC1V2 - IO_L20P_T3L_N2_AD1P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"] ;# Bank 64 VCCO - VCC1V2 - IO_L20P_T3L_N2_AD1P_64 +#set_property PACKAGE_PIN AP2 [get_ports "DDR4_CS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 +#set_property PACKAGE_PIN AN2 [get_ports "DDR4_DM1"] ;# Bank 64 VCCO - VCC1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM1"] ;# Bank 64 VCCO - VCC1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property PACKAGE_PIN AP1 [get_ports "DDR4_PAR"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_PAR"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64 +#set_property PACKAGE_PIN AM3 [get_ports "DDR4_CKE"] ;# Bank 64 VCCO - VCC1V2 - IO_T2U_N12_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CKE"] ;# Bank 64 VCCO - VCC1V2 - IO_T2U_N12_64 +#set_property PACKAGE_PIN AK4 [get_ports "DDR4_DQ0"] ;# Bank 64 VCCO - VCC1V2 - IO_L18N_T2U_N11_AD2N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"] ;# Bank 64 VCCO - VCC1V2 - IO_L18N_T2U_N11_AD2N_64 +#set_property PACKAGE_PIN AK5 [get_ports "DDR4_DQ1"] ;# Bank 64 VCCO - VCC1V2 - IO_L18P_T2U_N10_AD2P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"] ;# Bank 64 VCCO - VCC1V2 - IO_L18P_T2U_N10_AD2P_64 +#set_property PACKAGE_PIN AN4 [get_ports "DDR4_DQ2"] ;# Bank 64 VCCO - VCC1V2 - IO_L17N_T2U_N9_AD10N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"] ;# Bank 64 VCCO - VCC1V2 - IO_L17N_T2U_N9_AD10N_64 +#set_property PACKAGE_PIN AM4 [get_ports "DDR4_DQ3"] ;# Bank 64 VCCO - VCC1V2 - IO_L17P_T2U_N8_AD10P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"] ;# Bank 64 VCCO - VCC1V2 - IO_L17P_T2U_N8_AD10P_64 +#set_property PACKAGE_PIN AP6 [get_ports "DDR4_DQS0_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 +#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 +#set_property PACKAGE_PIN AN6 [get_ports "DDR4_DQS0_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 +#set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 +#set_property PACKAGE_PIN AP4 [get_ports "DDR4_DQ4"] ;# Bank 64 VCCO - VCC1V2 - IO_L15N_T2L_N5_AD11N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"] ;# Bank 64 VCCO - VCC1V2 - IO_L15N_T2L_N5_AD11N_64 +#set_property PACKAGE_PIN AP5 [get_ports "DDR4_DQ5"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64 +#set_property PACKAGE_PIN AM5 [get_ports "DDR4_DQ6"] ;# Bank 64 VCCO - VCC1V2 - IO_L14N_T2L_N3_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"] ;# Bank 64 VCCO - VCC1V2 - IO_L14N_T2L_N3_GC_64 +#set_property PACKAGE_PIN AM6 [get_ports "DDR4_DQ7"] ;# Bank 64 VCCO - VCC1V2 - IO_L14P_T2L_N2_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"] ;# Bank 64 VCCO - VCC1V2 - IO_L14P_T2L_N2_GC_64 +#set_property PACKAGE_PIN AL5 [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 +#set_property PACKAGE_PIN AL6 [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 +set_property PACKAGE_PIN AL7 [get_ports "sys_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 => USER_SI570_N +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 => USER_SI570_N +set_property PACKAGE_PIN AL8 [get_ports "sys_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 => USER_SI570_P +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 => USER_SI570_P +#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 +#set_property PACKAGE_PIN AK8 [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 +#set_property PACKAGE_PIN AP7 [get_ports "DDR4_CK_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_C"] ;# Bank 64 VCCO - VCC1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 +#set_property PACKAGE_PIN AN7 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property PACKAGE_PIN AK9 [get_ports "DDR4_ODT"] ;# Bank 64 VCCO - VCC1V2 - IO_L9N_T1L_N5_AD12N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ODT"] ;# Bank 64 VCCO - VCC1V2 - IO_L9N_T1L_N5_AD12N_64 +#set_property PACKAGE_PIN AJ9 [get_ports "DDR4_A16_RAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L9P_T1L_N4_AD12P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A16_RAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L9P_T1L_N4_AD12P_64 +#set_property PACKAGE_PIN AM8 [get_ports "DDR4_A0"] ;# Bank 64 VCCO - VCC1V2 - IO_L8N_T1L_N3_AD5N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A0"] ;# Bank 64 VCCO - VCC1V2 - IO_L8N_T1L_N3_AD5N_64 +#set_property PACKAGE_PIN AM9 [get_ports "DDR4_A1"] ;# Bank 64 VCCO - VCC1V2 - IO_L8P_T1L_N2_AD5P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A1"] ;# Bank 64 VCCO - VCC1V2 - IO_L8P_T1L_N2_AD5P_64 +#set_property PACKAGE_PIN AP8 [get_ports "DDR4_A2"] ;# Bank 64 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A2"] ;# Bank 64 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 +#set_property PACKAGE_PIN AN8 [get_ports "DDR4_A3"] ;# Bank 64 VCCO - VCC1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A3"] ;# Bank 64 VCCO - VCC1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property PACKAGE_PIN AJ7 [get_ports "DDR4_A14_WE_B"] ;# Bank 64 VCCO - VCC1V2 - IO_T1U_N12_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A14_WE_B"] ;# Bank 64 VCCO - VCC1V2 - IO_T1U_N12_64 +#set_property PACKAGE_PIN AN11 [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64 +#set_property IOSTANDARD [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64 +#set_property PACKAGE_PIN AK10 [get_ports "DDR4_A4"] ;# Bank 64 VCCO - VCC1V2 - IO_L6N_T0U_N11_AD6N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A4"] ;# Bank 64 VCCO - VCC1V2 - IO_L6N_T0U_N11_AD6N_64 +#set_property PACKAGE_PIN AJ10 [get_ports "DDR4_A5"] ;# Bank 64 VCCO - VCC1V2 - IO_L6P_T0U_N10_AD6P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A5"] ;# Bank 64 VCCO - VCC1V2 - IO_L6P_T0U_N10_AD6P_64 +#set_property PACKAGE_PIN AP9 [get_ports "DDR4_A6"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A6"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64 +#set_property PACKAGE_PIN AN9 [get_ports "DDR4_A7"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A7"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64 +#set_property PACKAGE_PIN AP10 [get_ports "DDR4_A8"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A8"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 +#set_property PACKAGE_PIN AP11 [get_ports "DDR4_A9"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A9"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 +#set_property PACKAGE_PIN AM10 [get_ports "DDR4_A10"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A10"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64 +#set_property PACKAGE_PIN AL10 [get_ports "DDR4_A11"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A11"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64 +#set_property PACKAGE_PIN AM11 [get_ports "DDR4_A12"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A12"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64 +#set_property PACKAGE_PIN AL11 [get_ports "DDR4_A13"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A13"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64 +#set_property PACKAGE_PIN AK12 [get_ports "DDR4_BA0"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA0"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64 +#set_property PACKAGE_PIN AJ12 [get_ports "DDR4_BA1"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64 +#set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA1"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64 +#Other net PACKAGE_PIN AJ11 - 6N6772 Bank 64 - VREF_64 +#set_property PACKAGE_PIN T34 [get_ports "HDMI_RX0_C_N"] ;# Bank 128 - MGTHRXN0_128 +#set_property PACKAGE_PIN P34 [get_ports "HDMI_RX1_C_N"] ;# Bank 128 - MGTHRXN1_128 +#set_property PACKAGE_PIN N32 [get_ports "HDMI_RX2_C_N"] ;# Bank 128 - MGTHRXN2_128 +#set_property PACKAGE_PIN M34 [get_ports "SMA_MGT_RX_C_N"] ;# Bank 128 - MGTHRXN3_128 +#set_property PACKAGE_PIN T33 [get_ports "HDMI_RX0_C_P"] ;# Bank 128 - MGTHRXP0_128 +#set_property PACKAGE_PIN P33 [get_ports "HDMI_RX1_C_P"] ;# Bank 128 - MGTHRXP1_128 +#set_property PACKAGE_PIN N31 [get_ports "HDMI_RX2_C_P"] ;# Bank 128 - MGTHRXP2_128 +#set_property PACKAGE_PIN M33 [get_ports "SMA_MGT_RX_C_P"] ;# Bank 128 - MGTHRXP3_128 +#set_property PACKAGE_PIN T30 [get_ports "HDMI_TX0_N"] ;# Bank 128 - MGTHTXN0_128 +#set_property PACKAGE_PIN R32 [get_ports "HDMI_TX1_N"] ;# Bank 128 - MGTHTXN1_128 +#set_property PACKAGE_PIN P30 [get_ports "HDMI_TX2_N"] ;# Bank 128 - MGTHTXN2_128 +#set_property PACKAGE_PIN M30 [get_ports "SMA_MGT_TX_N"] ;# Bank 128 - MGTHTXN3_128 +#set_property PACKAGE_PIN T29 [get_ports "HDMI_TX0_P"] ;# Bank 128 - MGTHTXP0_128 +#set_property PACKAGE_PIN R31 [get_ports "HDMI_TX1_P"] ;# Bank 128 - MGTHTXP1_128 +#set_property PACKAGE_PIN P29 [get_ports "HDMI_TX2_P"] ;# Bank 128 - MGTHTXP2_128 +#set_property PACKAGE_PIN M29 [get_ports "SMA_MGT_TX_P"] ;# Bank 128 - MGTHTXP3_128 +#set_property PACKAGE_PIN N28 [get_ports "HDMI_RX_CLK_C_N"] ;# Bank 128 - MGTREFCLK1N_128 +#set_property PACKAGE_PIN N27 [get_ports "HDMI_RX_CLK_C_P"] ;# Bank 128 - MGTREFCLK1P_128 +#set_property PACKAGE_PIN R28 [get_ports "HDMI_SI5324_OUT_C_N"] ;# Bank 128 - MGTREFCLK0N_128 +#set_property PACKAGE_PIN R27 [get_ports "HDMI_SI5324_OUT_C_P"] ;# Bank 128 - MGTREFCLK0P_128 +#set_property PACKAGE_PIN A29 [get_ports "MGTRREF_128"] ;# Bank 128 - MGTRREF_L +#Other net PACKAGE_PIN A30 - MGTAVTT Bank 128 - MGTAVTTRCAL_L +#set_property PACKAGE_PIN L32 [get_ports "FMC_HPC1_DP4_M2C_N"] ;# Bank 129 - MGTHRXN0_129 +#set_property PACKAGE_PIN K34 [get_ports "FMC_HPC1_DP5_M2C_N"] ;# Bank 129 - MGTHRXN1_129 +#set_property PACKAGE_PIN H34 [get_ports "FMC_HPC1_DP6_M2C_N"] ;# Bank 129 - MGTHRXN2_129 +#set_property PACKAGE_PIN F34 [get_ports "FMC_HPC1_DP7_M2C_N"] ;# Bank 129 - MGTHRXN3_129 +#set_property PACKAGE_PIN L31 [get_ports "FMC_HPC1_DP4_M2C_P"] ;# Bank 129 - MGTHRXP0_129 +#set_property PACKAGE_PIN K33 [get_ports "FMC_HPC1_DP5_M2C_P"] ;# Bank 129 - MGTHRXP1_129 +#set_property PACKAGE_PIN H33 [get_ports "FMC_HPC1_DP6_M2C_P"] ;# Bank 129 - MGTHRXP2_129 +#set_property PACKAGE_PIN F33 [get_ports "FMC_HPC1_DP7_M2C_P"] ;# Bank 129 - MGTHRXP3_129 +#set_property PACKAGE_PIN K30 [get_ports "FMC_HPC1_DP4_C2M_N"] ;# Bank 129 - MGTHTXN0_129 +#set_property PACKAGE_PIN J32 [get_ports "FMC_HPC1_DP5_C2M_N"] ;# Bank 129 - MGTHTXN1_129 +#set_property PACKAGE_PIN H30 [get_ports "FMC_HPC1_DP6_C2M_N"] ;# Bank 129 - MGTHTXN2_129 +#set_property PACKAGE_PIN G32 [get_ports "FMC_HPC1_DP7_C2M_N"] ;# Bank 129 - MGTHTXN3_129 +#set_property PACKAGE_PIN K29 [get_ports "FMC_HPC1_DP4_C2M_P"] ;# Bank 129 - MGTHTXP0_129 +#set_property PACKAGE_PIN J31 [get_ports "FMC_HPC1_DP5_C2M_P"] ;# Bank 129 - MGTHTXP1_129 +#set_property PACKAGE_PIN H29 [get_ports "FMC_HPC1_DP6_C2M_P"] ;# Bank 129 - MGTHTXP2_129 +#set_property PACKAGE_PIN G31 [get_ports "FMC_HPC1_DP7_C2M_P"] ;# Bank 129 - MGTHTXP3_129 +#set_property PACKAGE_PIN J28 [get_ports "USER_SMA_MGT_CLOCK_C_N"] ;# Bank 129 - MGTREFCLK1N_129 +#set_property PACKAGE_PIN J27 [get_ports "USER_SMA_MGT_CLOCK_C_P"] ;# Bank 129 - MGTREFCLK1P_129 +#set_property PACKAGE_PIN L28 [get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK0N_129 +#set_property PACKAGE_PIN L27 [get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK0P_129 +#set_property PACKAGE_PIN E32 [get_ports "FMC_HPC1_DP0_M2C_N"] ;# Bank 130 - MGTHRXN0_130 +#set_property PACKAGE_PIN D34 [get_ports "FMC_HPC1_DP1_M2C_N"] ;# Bank 130 - MGTHRXN1_130 +#set_property PACKAGE_PIN C32 [get_ports "FMC_HPC1_DP2_M2C_N"] ;# Bank 130 - MGTHRXN2_130 +#set_property PACKAGE_PIN B34 [get_ports "FMC_HPC1_DP3_M2C_N"] ;# Bank 130 - MGTHRXN3_130 +#set_property PACKAGE_PIN E31 [get_ports "FMC_HPC1_DP0_M2C_P"] ;# Bank 130 - MGTHRXP0_130 +#set_property PACKAGE_PIN D33 [get_ports "FMC_HPC1_DP1_M2C_P"] ;# Bank 130 - MGTHRXP1_130 +#set_property PACKAGE_PIN C31 [get_ports "FMC_HPC1_DP2_M2C_P"] ;# Bank 130 - MGTHRXP2_130 +#set_property PACKAGE_PIN B33 [get_ports "FMC_HPC1_DP3_M2C_P"] ;# Bank 130 - MGTHRXP3_130 +#set_property PACKAGE_PIN F30 [get_ports "FMC_HPC1_DP0_C2M_N"] ;# Bank 130 - MGTHTXN0_130 +#set_property PACKAGE_PIN D30 [get_ports "FMC_HPC1_DP1_C2M_N"] ;# Bank 130 - MGTHTXN1_130 +#set_property PACKAGE_PIN B30 [get_ports "FMC_HPC1_DP2_C2M_N"] ;# Bank 130 - MGTHTXN2_130 +#set_property PACKAGE_PIN A32 [get_ports "FMC_HPC1_DP3_C2M_N"] ;# Bank 130 - MGTHTXN3_130 +#set_property PACKAGE_PIN F29 [get_ports "FMC_HPC1_DP0_C2M_P"] ;# Bank 130 - MGTHTXP0_130 +#set_property PACKAGE_PIN D29 [get_ports "FMC_HPC1_DP1_C2M_P"] ;# Bank 130 - MGTHTXP1_130 +#set_property PACKAGE_PIN B29 [get_ports "FMC_HPC1_DP2_C2M_P"] ;# Bank 130 - MGTHTXP2_130 +#set_property PACKAGE_PIN A31 [get_ports "FMC_HPC1_DP3_C2M_P"] ;# Bank 130 - MGTHTXP3_130 +#set_property PACKAGE_PIN G28 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"] ;# Bank 130 - MGTREFCLK0N_130 +#set_property PACKAGE_PIN G27 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"] ;# Bank 130 - MGTREFCLK0P_130 +#set_property PACKAGE_PIN E28 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_N"] ;# Bank 130 - MGTREFCLK1N_130 +#set_property PACKAGE_PIN E27 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_P"] ;# Bank 130 - MGTREFCLK1P_130 +#set_property PACKAGE_PIN T1 [get_ports "FMC_HPC0_DP6_M2C_N"] ;# Bank 228 - MGTHRXN0_228 +#set_property PACKAGE_PIN P1 [get_ports "FMC_HPC0_DP5_M2C_N"] ;# Bank 228 - MGTHRXN1_228 +#set_property PACKAGE_PIN M1 [get_ports "FMC_HPC0_DP7_M2C_N"] ;# Bank 228 - MGTHRXN2_228 +#set_property PACKAGE_PIN L3 [get_ports "FMC_HPC0_DP4_M2C_N"] ;# Bank 228 - MGTHRXN3_228 +#set_property PACKAGE_PIN T2 [get_ports "FMC_HPC0_DP6_M2C_P"] ;# Bank 228 - MGTHRXP0_228 +#set_property PACKAGE_PIN P2 [get_ports "FMC_HPC0_DP5_M2C_P"] ;# Bank 228 - MGTHRXP1_228 +#set_property PACKAGE_PIN M2 [get_ports "FMC_HPC0_DP7_M2C_P"] ;# Bank 228 - MGTHRXP2_228 +#set_property PACKAGE_PIN L4 [get_ports "FMC_HPC0_DP4_M2C_P"] ;# Bank 228 - MGTHRXP3_228 +#set_property PACKAGE_PIN R3 [get_ports "FMC_HPC0_DP6_C2M_N"] ;# Bank 228 - MGTHTXN0_228 +#set_property PACKAGE_PIN P5 [get_ports "FMC_HPC0_DP5_C2M_N"] ;# Bank 228 - MGTHTXN1_228 +#set_property PACKAGE_PIN N3 [get_ports "FMC_HPC0_DP7_C2M_N"] ;# Bank 228 - MGTHTXN2_228 +#set_property PACKAGE_PIN M5 [get_ports "FMC_HPC0_DP4_C2M_N"] ;# Bank 228 - MGTHTXN3_228 +#set_property PACKAGE_PIN R4 [get_ports "FMC_HPC0_DP6_C2M_P"] ;# Bank 228 - MGTHTXP0_228 +#set_property PACKAGE_PIN P6 [get_ports "FMC_HPC0_DP5_C2M_P"] ;# Bank 228 - MGTHTXP1_228 +#set_property PACKAGE_PIN N4 [get_ports "FMC_HPC0_DP7_C2M_P"] ;# Bank 228 - MGTHTXP2_228 +#set_property PACKAGE_PIN M6 [get_ports "FMC_HPC0_DP4_C2M_P"] ;# Bank 228 - MGTHTXP3_228 +#set_property PACKAGE_PIN J7 [get_ports "38N7145"] ;# Bank 228 - MGTREFCLK1N_228 +#set_property PACKAGE_PIN J8 [get_ports "38N7142"] ;# Bank 228 - MGTREFCLK1P_228 +#set_property PACKAGE_PIN L7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;# Bank 228 - MGTREFCLK0N_228 +#set_property PACKAGE_PIN L8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;# Bank 228 - MGTREFCLK0P_228 +#set_property PACKAGE_PIN A6 [get_ports "38N2099"] ;# Bank 228 - MGTRREF_R +#Other net PACKAGE_PIN A5 - MGTAVTT Bank 228 - MGTAVTTRCAL_R +#set_property PACKAGE_PIN K1 [get_ports "FMC_HPC0_DP3_M2C_N"] ;# Bank 229 - MGTHRXN0_229 +#set_property PACKAGE_PIN J3 [get_ports "FMC_HPC0_DP1_M2C_N"] ;# Bank 229 - MGTHRXN1_229 +#set_property PACKAGE_PIN H1 [get_ports "FMC_HPC0_DP0_M2C_N"] ;# Bank 229 - MGTHRXN2_229 +#set_property PACKAGE_PIN F1 [get_ports "FMC_HPC0_DP2_M2C_N"] ;# Bank 229 - MGTHRXN3_229 +#set_property PACKAGE_PIN K2 [get_ports "FMC_HPC0_DP3_M2C_P"] ;# Bank 229 - MGTHRXP0_229 +#set_property PACKAGE_PIN J4 [get_ports "FMC_HPC0_DP1_M2C_P"] ;# Bank 229 - MGTHRXP1_229 +#set_property PACKAGE_PIN H2 [get_ports "FMC_HPC0_DP0_M2C_P"] ;# Bank 229 - MGTHRXP2_229 +#set_property PACKAGE_PIN F2 [get_ports "FMC_HPC0_DP2_M2C_P"] ;# Bank 229 - MGTHRXP3_229 +#set_property PACKAGE_PIN K5 [get_ports "FMC_HPC0_DP3_C2M_N"] ;# Bank 229 - MGTHTXN0_229 +#set_property PACKAGE_PIN H5 [get_ports "FMC_HPC0_DP1_C2M_N"] ;# Bank 229 - MGTHTXN1_229 +#set_property PACKAGE_PIN G3 [get_ports "FMC_HPC0_DP0_C2M_N"] ;# Bank 229 - MGTHTXN2_229 +#set_property PACKAGE_PIN F5 [get_ports "FMC_HPC0_DP2_C2M_N"] ;# Bank 229 - MGTHTXN3_229 +#set_property PACKAGE_PIN K6 [get_ports "FMC_HPC0_DP3_C2M_P"] ;# Bank 229 - MGTHTXP0_229 +#set_property PACKAGE_PIN H6 [get_ports "FMC_HPC0_DP1_C2M_P"] ;# Bank 229 - MGTHTXP1_229 +#set_property PACKAGE_PIN G4 [get_ports "FMC_HPC0_DP0_C2M_P"] ;# Bank 229 - MGTHTXP2_229 +#set_property PACKAGE_PIN F6 [get_ports "FMC_HPC0_DP2_C2M_P"] ;# Bank 229 - MGTHTXP3_229 +#set_property PACKAGE_PIN E7 [get_ports "38N7165"] ;# Bank 229 - MGTREFCLK1N_229 +#set_property PACKAGE_PIN E8 [get_ports "38N7162"] ;# Bank 229 - MGTREFCLK1P_229 +#set_property PACKAGE_PIN G7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;# Bank 229 - MGTREFCLK0N_229 +#set_property PACKAGE_PIN G8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;# Bank 229 - MGTREFCLK0P_229 +#set_property PACKAGE_PIN D1 [get_ports "SFP0_RX_N"] ;# Bank 230 - MGTHRXN0_230 +#set_property PACKAGE_PIN C3 [get_ports "SFP1_RX_N"] ;# Bank 230 - MGTHRXN1_230 +#set_property PACKAGE_PIN B1 [get_ports "SFP2_RX_N"] ;# Bank 230 - MGTHRXN2_230 +#set_property PACKAGE_PIN A3 [get_ports "SFP3_RX_N"] ;# Bank 230 - MGTHRXN3_230 +#set_property PACKAGE_PIN D2 [get_ports "SFP0_RX_P"] ;# Bank 230 - MGTHRXP0_230 +#set_property PACKAGE_PIN C4 [get_ports "SFP1_RX_P"] ;# Bank 230 - MGTHRXP1_230 +#set_property PACKAGE_PIN B2 [get_ports "SFP2_RX_P"] ;# Bank 230 - MGTHRXP2_230 +#set_property PACKAGE_PIN A4 [get_ports "SFP3_RX_P"] ;# Bank 230 - MGTHRXP3_230 +#set_property PACKAGE_PIN E3 [get_ports "SFP0_TX_N"] ;# Bank 230 - MGTHTXN0_230 +#set_property PACKAGE_PIN D5 [get_ports "SFP1_TX_N"] ;# Bank 230 - MGTHTXN1_230 +#set_property PACKAGE_PIN B5 [get_ports "SFP2_TX_N"] ;# Bank 230 - MGTHTXN2_230 +#set_property PACKAGE_PIN A7 [get_ports "SFP3_TX_N"] ;# Bank 230 - MGTHTXN3_230 +#set_property PACKAGE_PIN E4 [get_ports "SFP0_TX_P"] ;# Bank 230 - MGTHTXP0_230 +#set_property PACKAGE_PIN D6 [get_ports "SFP1_TX_P"] ;# Bank 230 - MGTHTXP1_230 +#set_property PACKAGE_PIN B6 [get_ports "SFP2_TX_P"] ;# Bank 230 - MGTHTXP2_230 +#set_property PACKAGE_PIN A8 [get_ports "SFP3_TX_P"] ;# Bank 230 - MGTHTXP3_230 +#set_property PACKAGE_PIN C7 [get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;# Bank 230 - MGTREFCLK0N_230 +#set_property PACKAGE_PIN C8 [get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;# Bank 230 - MGTREFCLK0P_230 +#set_property PACKAGE_PIN B9 [get_ports "SFP_SI5328_OUT_C_N"] ;# Bank 230 - MGTREFCLK1N_230 +#set_property PACKAGE_PIN B10 [get_ports "SFP_SI5328_OUT_C_P"] ;# Bank 230 - MGTREFCLK1P_230 +################################################################################ +### PS Side +################################################################################ +#Other net PACKAGE_PIN AF16 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0 +#Other net PACKAGE_PIN AJ16 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1 +#Other net PACKAGE_PIN AD16 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2 +#Other net PACKAGE_PIN AG16 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3 +#Other net PACKAGE_PIN AH16 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4 +#Other net PACKAGE_PIN AM15 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5 +#Other net PACKAGE_PIN AL15 - 53N6816 Bank 500 - PS_MIO6 +#Other net PACKAGE_PIN AD17 - MIO7_QSPI_UPR_CS_B Bank 500 - PS_MIO7 +#Other net PACKAGE_PIN AE17 - MIO8_QSPI_UPR_DQ0 Bank 500 - PS_MIO8 +#Other net PACKAGE_PIN AP15 - MIO9_QSPI_UPR_DQ1 Bank 500 - PS_MIO9 +#Other net PACKAGE_PIN AH17 - MIO10_QSPI_UPR_DQ2 Bank 500 - PS_MIO10 +#Other net PACKAGE_PIN AF17 - MIO11_QSPI_UPR_DQ3 Bank 500 - PS_MIO11 +#Other net PACKAGE_PIN AJ17 - MIO12_QSPI_UPR_CLK Bank 500 - PS_MIO12 +#Other net PACKAGE_PIN AK17 - MIO13PS_GPIO2 Bank 500 - PS_MIO13 +#Other net PACKAGE_PIN AL16 - MIO14_I2C0_SCL Bank 500 - PS_MIO14 +#Other net PACKAGE_PIN AN16 - MIO15_I2C0_SDA Bank 500 - PS_MIO15 +#Other net PACKAGE_PIN AM16 - MIO16_I2C1_SCL Bank 500 - PS_MIO16 +#Other net PACKAGE_PIN AP16 - MIO17_I2C1_SDA Bank 500 - PS_MIO17 +#Other net PACKAGE_PIN AE18 - MIO18_UART0_RXD Bank 500 - PS_MIO18 +#Other net PACKAGE_PIN AL17 - MIO19_UART0_TXD Bank 500 - PS_MIO19 +#Other net PACKAGE_PIN AD18 - MIO20_UART1_TXD Bank 500 - PS_MIO20 +#Other net PACKAGE_PIN AF18 - MIO21_UART1_RXD Bank 500 - PS_MIO21 +#Other net PACKAGE_PIN AD20 - MIO22_BUTTON Bank 500 - PS_MIO22 +#Other net PACKAGE_PIN AD19 - MIO23_LED Bank 500 - PS_MIO23 +#Other net PACKAGE_PIN AE20 - MIO24_CAN_TX Bank 500 - PS_MIO24 +#Other net PACKAGE_PIN AE19 - MIO25_CAN_RX Bank 500 - PS_MIO25 +#Other net PACKAGE_PIN P21 - MIO26_PMU_INPUT Bank 501 - PS_MIO26 +#Other net PACKAGE_PIN M21 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27 +#Other net PACKAGE_PIN N21 - MIO28_DP_HPD Bank 501 - PS_MIO28 +#Other net PACKAGE_PIN K22 - MIO29_DP_OE Bank 501 - PS_MIO29 +#Other net PACKAGE_PIN L21 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30 +#Other net PACKAGE_PIN J22 - MIO31_PCIE_RESET_N Bank 501 - PS_MIO31 +#Other net PACKAGE_PIN H22 - MIO32_PMU_GPO0 Bank 501 - PS_MIO32 +#Other net PACKAGE_PIN H23 - MIO33_PMU_GPO1 Bank 501 - PS_MIO33 +#Other net PACKAGE_PIN L22 - MIO34_PMU_GPO2 Bank 501 - PS_MIO34 +#Other net PACKAGE_PIN P22 - MIO35_PMU_GPO3 Bank 501 - PS_MIO35 +#Other net PACKAGE_PIN K23 - MIO36_PMU_GPO4 Bank 501 - PS_MIO36 +#Other net PACKAGE_PIN N22 - MIO37_PMU_GPO5 Bank 501 - PS_MIO37 +#Other net PACKAGE_PIN L23 - MIO38_PS_GPIO1 Bank 501 - PS_MIO38 +#Other net PACKAGE_PIN N23 - MIO39_SDIO_SEL Bank 501 - PS_MIO39 +#Other net PACKAGE_PIN M23 - MIO40_SDIO_DIR_CMD Bank 501 - PS_MIO40 +#Other net PACKAGE_PIN J24 - MIO41_SDIO_DIR_DAT0 Bank 501 - PS_MIO41 +#Other net PACKAGE_PIN M24 - MIO42_SDIO_DIR_DAT1_3 Bank 501 - PS_MIO42 +#Other net PACKAGE_PIN K24 - 53N6798 Bank 501 - PS_MIO43 +#Other net PACKAGE_PIN N24 - MIO44_SDIO_PROTECT Bank 501 - PS_MIO44 +#Other net PACKAGE_PIN P24 - MIO45_SDIO_DETECT Bank 501 - PS_MIO45 +#Other net PACKAGE_PIN J25 - MIO46_SDIO_DAT0 Bank 501 - PS_MIO46 +#Other net PACKAGE_PIN L25 - MIO47_SDIO_DAT1 Bank 501 - PS_MIO47 +#Other net PACKAGE_PIN M25 - MIO48_SDIO_DAT2 Bank 501 - PS_MIO48 +#Other net PACKAGE_PIN K25 - MIO49_SDIO_DAT3 Bank 501 - PS_MIO49 +#Other net PACKAGE_PIN P25 - MIO50_SDIO_CMD Bank 501 - PS_MIO50 +#Other net PACKAGE_PIN N25 - MIO51_SDIO_CLK Bank 501 - PS_MIO51 +#Other net PACKAGE_PIN F22 - MIO52_USB_CLK Bank 502 - PS_MIO52 +#Other net PACKAGE_PIN E23 - MIO53_USB_DIR Bank 502 - PS_MIO53 +#Other net PACKAGE_PIN F23 - MIO54_USB_DATA2 Bank 502 - PS_MIO54 +#Other net PACKAGE_PIN B23 - MIO55_USB_NXT Bank 502 - PS_MIO55 +#Other net PACKAGE_PIN C23 - MIO56_USB_DATA0 Bank 502 - PS_MIO56 +#Other net PACKAGE_PIN A23 - MIO57_USB_DATA1 Bank 502 - PS_MIO57 +#Other net PACKAGE_PIN G23 - MIO58_USB_STP Bank 502 - PS_MIO58 +#Other net PACKAGE_PIN B24 - MIO59_USB_DATA3 Bank 502 - PS_MIO59 +#Other net PACKAGE_PIN E24 - MIO60_USB_DATA4 Bank 502 - PS_MIO60 +#Other net PACKAGE_PIN C24 - MIO61_USB_DATA5 Bank 502 - PS_MIO61 +#Other net PACKAGE_PIN G24 - MIO62_USB_DATA6 Bank 502 - PS_MIO62 +#Other net PACKAGE_PIN D24 - MIO63_USB_DATA7 Bank 502 - PS_MIO63 +#Other net PACKAGE_PIN A25 - MIO64_ENET_TX_CLK Bank 502 - PS_MIO64 +#Other net PACKAGE_PIN A26 - MIO65_ENET_TX_D0 Bank 502 - PS_MIO65 +#Other net PACKAGE_PIN A27 - MIO66_ENET_TX_D1 Bank 502 - PS_MIO66 +#Other net PACKAGE_PIN B25 - MIO67_ENET_TX_D2 Bank 502 - PS_MIO67 +#Other net PACKAGE_PIN B26 - MIO68_ENET_TX_D3 Bank 502 - PS_MIO68 +#Other net PACKAGE_PIN B27 - MIO69_ENET_TX_CTRL Bank 502 - PS_MIO69 +#Other net PACKAGE_PIN C26 - MIO70_ENET_RX_CLK Bank 502 - PS_MIO70 +#Other net PACKAGE_PIN C27 - MIO71_ENET_RX_D0 Bank 502 - PS_MIO71 +#Other net PACKAGE_PIN E25 - MIO72_ENET_RX_D1 Bank 502 - PS_MIO72 +#Other net PACKAGE_PIN H24 - MIO73_ENET_RX_D2 Bank 502 - PS_MIO73 +#Other net PACKAGE_PIN G25 - MIO74_ENET_RX_D3 Bank 502 - PS_MIO74 +#Other net PACKAGE_PIN D25 - MIO75_ENET_RX_CTRL Bank 502 - PS_MIO75 +#Other net PACKAGE_PIN H25 - MIO76_ENET_MDC Bank 502 - PS_MIO76 +#Other net PACKAGE_PIN F25 - MIO77_ENET_MDIO Bank 502 - PS_MIO77 +#Other net PACKAGE_PIN W21 - PS_DONE Bank 503 - PS_DONE +#Other net PACKAGE_PIN T21 - PS_ERR_OUT Bank 503 - PS_ERROR_OUT +#Other net PACKAGE_PIN R21 - PS_ERR_STATUS Bank 503 - PS_ERROR_STATUS +#Other net PACKAGE_PIN V24 - PS_INIT_B Bank 503 - PS_INIT_B +#Other net PACKAGE_PIN R25 - JTAG_TCK Bank 503 - PS_JTAG_TCK +#Other net PACKAGE_PIN U25 - JTAG_TDI Bank 503 - PS_JTAG_TDI +#Other net PACKAGE_PIN T25 - FPGA_TDO_FMC_TDI Bank 503 - PS_JTAG_TDO +#Other net PACKAGE_PIN R24 - JTAG_TMS Bank 503 - PS_JTAG_TMS +#Other net PACKAGE_PIN T22 - PS_MODE0 Bank 503 - PS_MODE0 +#Other net PACKAGE_PIN R22 - PS_MODE1 Bank 503 - PS_MODE1 +#Other net PACKAGE_PIN T23 - PS_MODE2 Bank 503 - PS_MODE2 +#Other net PACKAGE_PIN R23 - PS_MODE3 Bank 503 - PS_MODE3 +#Other net PACKAGE_PIN V21 - PS_PADI Bank 503 - PS_PADI +#Other net PACKAGE_PIN V22 - PS_PADO Bank 503 - PS_PADO +#Other net PACKAGE_PIN V23 - PS_POR_B Bank 503 - PS_POR_B +#Other net PACKAGE_PIN U21 - PS_PROG_B Bank 503 - PS_PROG_B +#Other net PACKAGE_PIN U24 - PS_REF_CLK Bank 503 - PS_REF_CLK +#Other net PACKAGE_PIN U23 - PS_SRST_B Bank 503 - PS_SRST_B +#Other net PACKAGE_PIN AP29 - DDR4_SODIMM_A0 Bank 504 - PS_DDR_A0 +#Other net PACKAGE_PIN AP30 - DDR4_SODIMM_A1 Bank 504 - PS_DDR_A1 +#Other net PACKAGE_PIN AL28 - DDR4_SODIMM_A10 Bank 504 - PS_DDR_A10 +#Other net PACKAGE_PIN AK27 - DDR4_SODIMM_A11 Bank 504 - PS_DDR_A11 +#Other net PACKAGE_PIN AJ25 - DDR4_SODIMM_A12 Bank 504 - PS_DDR_A12 +#Other net PACKAGE_PIN AL25 - DDR4_SODIMM_A13 Bank 504 - PS_DDR_A13 +#Other net PACKAGE_PIN AK25 - DDR4_SODIMM_WE_B Bank 504 - PS_DDR_A14 +#Other net PACKAGE_PIN AK24 - DDR4_SODIMM_CAS_B Bank 504 - PS_DDR_A15 +#Other net PACKAGE_PIN AM24 - DDR4_SODIMM_RAS_B Bank 504 - PS_DDR_A16 +#Other net PACKAGE_PIN AF25 - 68N6692 Bank 504 - PS_DDR_A17 +#Other net PACKAGE_PIN AP26 - DDR4_SODIMM_A2 Bank 504 - PS_DDR_A2 +#Other net PACKAGE_PIN AP27 - DDR4_SODIMM_A3 Bank 504 - PS_DDR_A3 +#Other net PACKAGE_PIN AP25 - DDR4_SODIMM_A4 Bank 504 - PS_DDR_A4 +#Other net PACKAGE_PIN AN24 - DDR4_SODIMM_A5 Bank 504 - PS_DDR_A5 +#Other net PACKAGE_PIN AM29 - DDR4_SODIMM_A6 Bank 504 - PS_DDR_A6 +#Other net PACKAGE_PIN AM28 - DDR4_SODIMM_A7 Bank 504 - PS_DDR_A7 +#Other net PACKAGE_PIN AM26 - DDR4_SODIMM_A8 Bank 504 - PS_DDR_A8 +#Other net PACKAGE_PIN AM25 - DDR4_SODIMM_A9 Bank 504 - PS_DDR_A9 +#Other net PACKAGE_PIN AG25 - DDR4_SODIMM_ACT_B Bank 504 - PS_DDR_ACT_N +#Other net PACKAGE_PIN AF22 - DDR4_SODIMM_ALERT_B Bank 504 - PS_DDR_ALERT_N +#Other net PACKAGE_PIN AH26 - DDR4_SODIMM_BA0 Bank 504 - PS_DDR_BA0 +#Other net PACKAGE_PIN AG26 - DDR4_SODIMM_BA1 Bank 504 - PS_DDR_BA1 +#Other net PACKAGE_PIN AK28 - DDR4_SODIMM_BG0 Bank 504 - PS_DDR_BG0 +#Other net PACKAGE_PIN AH27 - DDR4_SODIMM_BG1 Bank 504 - PS_DDR_BG1 +#Other net PACKAGE_PIN AN27 - DDR4_SODIMM_CK0_C Bank 504 - PS_DDR_CK_N0 +#Other net PACKAGE_PIN AL27 - DDR4_SODIMM_CK1_C Bank 504 - PS_DDR_CK_N1 +#Other net PACKAGE_PIN AN26 - DDR4_SODIMM_CK0_T Bank 504 - PS_DDR_CK0 +#Other net PACKAGE_PIN AL26 - DDR4_SODIMM_CK1_T Bank 504 - PS_DDR_CK1 +#Other net PACKAGE_PIN AN29 - DDR4_SODIMM_CKE0 Bank 504 - PS_DDR_CKE0 +#Other net PACKAGE_PIN AJ27 - DDR4_SODIMM_CKE1 Bank 504 - PS_DDR_CKE1 +#Other net PACKAGE_PIN AN28 - DDR4_SODIMM_CS0_B Bank 504 - PS_DDR_CS_N0 +#Other net PACKAGE_PIN AL30 - DDR4_SODIMM_CS1_B Bank 504 - PS_DDR_CS_N1 +#Other net PACKAGE_PIN AN17 - DDR4_SODIMM_DM0_B Bank 504 - PS_DDR_DM0 +#Other net PACKAGE_PIN AM21 - DDR4_SODIMM_DM1_B Bank 504 - PS_DDR_DM1 +#Other net PACKAGE_PIN AK19 - DDR4_SODIMM_DM2_B Bank 504 - PS_DDR_DM2 +#Other net PACKAGE_PIN AH24 - DDR4_SODIMM_DM3_B Bank 504 - PS_DDR_DM3 +#Other net PACKAGE_PIN AH31 - DDR4_SODIMM_DM4_B Bank 504 - PS_DDR_DM4 +#Other net PACKAGE_PIN AE30 - DDR4_SODIMM_DM5_B Bank 504 - PS_DDR_DM5 +#Other net PACKAGE_PIN AJ31 - DDR4_SODIMM_DM6_B Bank 504 - PS_DDR_DM6 +#Other net PACKAGE_PIN AE34 - DDR4_SODIMM_DM7_B Bank 504 - PS_DDR_DM7 +#Other net PACKAGE_PIN AN34 - DDR4_SODIMM_DM8_B Bank 504 - PS_DDR_DM8 +#Other net PACKAGE_PIN AP20 - DDR4_SODIMM_DQ0 Bank 504 - PS_DDR_DQ0 +#Other net PACKAGE_PIN AP18 - DDR4_SODIMM_DQ1 Bank 504 - PS_DDR_DQ1 +#Other net PACKAGE_PIN AP19 - DDR4_SODIMM_DQ2 Bank 504 - PS_DDR_DQ2 +#Other net PACKAGE_PIN AP17 - DDR4_SODIMM_DQ3 Bank 504 - PS_DDR_DQ3 +#Other net PACKAGE_PIN AM20 - DDR4_SODIMM_DQ4 Bank 504 - PS_DDR_DQ4 +#Other net PACKAGE_PIN AM19 - DDR4_SODIMM_DQ5 Bank 504 - PS_DDR_DQ5 +#Other net PACKAGE_PIN AM18 - DDR4_SODIMM_DQ6 Bank 504 - PS_DDR_DQ6 +#Other net PACKAGE_PIN AL18 - DDR4_SODIMM_DQ7 Bank 504 - PS_DDR_DQ7 +#Other net PACKAGE_PIN AP22 - DDR4_SODIMM_DQ8 Bank 504 - PS_DDR_DQ8 +#Other net PACKAGE_PIN AP21 - DDR4_SODIMM_DQ9 Bank 504 - PS_DDR_DQ9 +#Other net PACKAGE_PIN AP24 - DDR4_SODIMM_DQ10 Bank 504 - PS_DDR_DQ10 +#Other net PACKAGE_PIN AN23 - DDR4_SODIMM_DQ11 Bank 504 - PS_DDR_DQ11 +#Other net PACKAGE_PIN AL21 - DDR4_SODIMM_DQ12 Bank 504 - PS_DDR_DQ12 +#Other net PACKAGE_PIN AL22 - DDR4_SODIMM_DQ13 Bank 504 - PS_DDR_DQ13 +#Other net PACKAGE_PIN AM23 - DDR4_SODIMM_DQ14 Bank 504 - PS_DDR_DQ14 +#Other net PACKAGE_PIN AL23 - DDR4_SODIMM_DQ15 Bank 504 - PS_DDR_DQ15 +#Other net PACKAGE_PIN AL20 - DDR4_SODIMM_DQ16 Bank 504 - PS_DDR_DQ16 +#Other net PACKAGE_PIN AK20 - DDR4_SODIMM_DQ17 Bank 504 - PS_DDR_DQ17 +#Other net PACKAGE_PIN AJ20 - DDR4_SODIMM_DQ18 Bank 504 - PS_DDR_DQ18 +#Other net PACKAGE_PIN AK18 - DDR4_SODIMM_DQ19 Bank 504 - PS_DDR_DQ19 +#Other net PACKAGE_PIN AG20 - DDR4_SODIMM_DQ20 Bank 504 - PS_DDR_DQ20 +#Other net PACKAGE_PIN AH18 - DDR4_SODIMM_DQ21 Bank 504 - PS_DDR_DQ21 +#Other net PACKAGE_PIN AG19 - DDR4_SODIMM_DQ22 Bank 504 - PS_DDR_DQ22 +#Other net PACKAGE_PIN AG18 - DDR4_SODIMM_DQ23 Bank 504 - PS_DDR_DQ23 +#Other net PACKAGE_PIN AG21 - DDR4_SODIMM_DQ24 Bank 504 - PS_DDR_DQ24 +#Other net PACKAGE_PIN AH21 - DDR4_SODIMM_DQ25 Bank 504 - PS_DDR_DQ25 +#Other net PACKAGE_PIN AG24 - DDR4_SODIMM_DQ26 Bank 504 - PS_DDR_DQ26 +#Other net PACKAGE_PIN AG23 - DDR4_SODIMM_DQ27 Bank 504 - PS_DDR_DQ27 +#Other net PACKAGE_PIN AK22 - DDR4_SODIMM_DQ28 Bank 504 - PS_DDR_DQ28 +#Other net PACKAGE_PIN AJ21 - DDR4_SODIMM_DQ29 Bank 504 - PS_DDR_DQ29 +#Other net PACKAGE_PIN AJ22 - DDR4_SODIMM_DQ30 Bank 504 - PS_DDR_DQ30 +#Other net PACKAGE_PIN AK23 - DDR4_SODIMM_DQ31 Bank 504 - PS_DDR_DQ31 +#Other net PACKAGE_PIN AG31 - DDR4_SODIMM_DQ32 Bank 504 - PS_DDR_DQ32 +#Other net PACKAGE_PIN AG30 - DDR4_SODIMM_DQ33 Bank 504 - PS_DDR_DQ33 +#Other net PACKAGE_PIN AG29 - DDR4_SODIMM_DQ34 Bank 504 - PS_DDR_DQ34 +#Other net PACKAGE_PIN AG28 - DDR4_SODIMM_DQ35 Bank 504 - PS_DDR_DQ35 +#Other net PACKAGE_PIN AJ30 - DDR4_SODIMM_DQ36 Bank 504 - PS_DDR_DQ36 +#Other net PACKAGE_PIN AK29 - DDR4_SODIMM_DQ37 Bank 504 - PS_DDR_DQ37 +#Other net PACKAGE_PIN AK30 - DDR4_SODIMM_DQ38 Bank 504 - PS_DDR_DQ38 +#Other net PACKAGE_PIN AJ29 - DDR4_SODIMM_DQ39 Bank 504 - PS_DDR_DQ39 +#Other net PACKAGE_PIN AE27 - DDR4_SODIMM_DQ40 Bank 504 - PS_DDR_DQ40 +#Other net PACKAGE_PIN AF28 - DDR4_SODIMM_DQ41 Bank 504 - PS_DDR_DQ41 +#Other net PACKAGE_PIN AF30 - DDR4_SODIMM_DQ42 Bank 504 - PS_DDR_DQ42 +#Other net PACKAGE_PIN AF31 - DDR4_SODIMM_DQ43 Bank 504 - PS_DDR_DQ43 +#Other net PACKAGE_PIN AD28 - DDR4_SODIMM_DQ44 Bank 504 - PS_DDR_DQ44 +#Other net PACKAGE_PIN AD27 - DDR4_SODIMM_DQ45 Bank 504 - PS_DDR_DQ45 +#Other net PACKAGE_PIN AD29 - DDR4_SODIMM_DQ46 Bank 504 - PS_DDR_DQ46 +#Other net PACKAGE_PIN AD30 - DDR4_SODIMM_DQ47 Bank 504 - PS_DDR_DQ47 +#Other net PACKAGE_PIN AH33 - DDR4_SODIMM_DQ48 Bank 504 - PS_DDR_DQ48 +#Other net PACKAGE_PIN AJ34 - DDR4_SODIMM_DQ49 Bank 504 - PS_DDR_DQ49 +#Other net PACKAGE_PIN AH34 - DDR4_SODIMM_DQ50 Bank 504 - PS_DDR_DQ50 +#Other net PACKAGE_PIN AH32 - DDR4_SODIMM_DQ51 Bank 504 - PS_DDR_DQ51 +#Other net PACKAGE_PIN AK34 - DDR4_SODIMM_DQ52 Bank 504 - PS_DDR_DQ52 +#Other net PACKAGE_PIN AK33 - DDR4_SODIMM_DQ53 Bank 504 - PS_DDR_DQ53 +#Other net PACKAGE_PIN AL32 - DDR4_SODIMM_DQ54 Bank 504 - PS_DDR_DQ54 +#Other net PACKAGE_PIN AL31 - DDR4_SODIMM_DQ55 Bank 504 - PS_DDR_DQ55 +#Other net PACKAGE_PIN AG33 - DDR4_SODIMM_DQ56 Bank 504 - PS_DDR_DQ56 +#Other net PACKAGE_PIN AG34 - DDR4_SODIMM_DQ57 Bank 504 - PS_DDR_DQ57 +#Other net PACKAGE_PIN AF32 - DDR4_SODIMM_DQ58 Bank 504 - PS_DDR_DQ58 +#Other net PACKAGE_PIN AF33 - DDR4_SODIMM_DQ59 Bank 504 - PS_DDR_DQ59 +#Other net PACKAGE_PIN AD31 - DDR4_SODIMM_DQ60 Bank 504 - PS_DDR_DQ60 +#Other net PACKAGE_PIN AD32 - DDR4_SODIMM_DQ61 Bank 504 - PS_DDR_DQ61 +#Other net PACKAGE_PIN AD34 - DDR4_SODIMM_DQ62 Bank 504 - PS_DDR_DQ62 +#Other net PACKAGE_PIN AD33 - DDR4_SODIMM_DQ63 Bank 504 - PS_DDR_DQ63 +#Other net PACKAGE_PIN AN31 - DDR4_SODIMM_CB0 Bank 504 - PS_DDR_DQ64 +#Other net PACKAGE_PIN AP31 - DDR4_SODIMM_CB1 Bank 504 - PS_DDR_DQ65 +#Other net PACKAGE_PIN AP32 - DDR4_SODIMM_CB2 Bank 504 - PS_DDR_DQ66 +#Other net PACKAGE_PIN AP33 - DDR4_SODIMM_CB3 Bank 504 - PS_DDR_DQ67 +#Other net PACKAGE_PIN AM31 - DDR4_SODIMM_CB4 Bank 504 - PS_DDR_DQ68 +#Other net PACKAGE_PIN AM33 - DDR4_SODIMM_CB5 Bank 504 - PS_DDR_DQ69 +#Other net PACKAGE_PIN AM34 - DDR4_SODIMM_CB6 Bank 504 - PS_DDR_DQ70 +#Other net PACKAGE_PIN AL33 - DDR4_SODIMM_CB7 Bank 504 - PS_DDR_DQ71 +#Other net PACKAGE_PIN AN19 - DDR4_SODIMM_DQS0_C Bank 504 - PS_DDR_DQS_N0 +#Other net PACKAGE_PIN AN22 - DDR4_SODIMM_DQS1_C Bank 504 - PS_DDR_DQS_N1 +#Other net PACKAGE_PIN AJ19 - DDR4_SODIMM_DQS2_C Bank 504 - PS_DDR_DQS_N2 +#Other net PACKAGE_PIN AH23 - DDR4_SODIMM_DQS3_C Bank 504 - PS_DDR_DQS_N3 +#Other net PACKAGE_PIN AH29 - DDR4_SODIMM_DQS4_C Bank 504 - PS_DDR_DQS_N4 +#Other net PACKAGE_PIN AE29 - DDR4_SODIMM_DQS5_C Bank 504 - PS_DDR_DQS_N5 +#Other net PACKAGE_PIN AK32 - DDR4_SODIMM_DQS6_C Bank 504 - PS_DDR_DQS_N6 +#Other net PACKAGE_PIN AE33 - DDR4_SODIMM_DQS7_C Bank 504 - PS_DDR_DQS_N7 +#Other net PACKAGE_PIN AN33 - DDR4_SODIMM_DQS8_C Bank 504 - PS_DDR_DQS_N8 +#Other net PACKAGE_PIN AN18 - DDR4_SODIMM_DQS0_T Bank 504 - PS_DDR_DQS_P0 +#Other net PACKAGE_PIN AN21 - DDR4_SODIMM_DQS1_T Bank 504 - PS_DDR_DQS_P1 +#Other net PACKAGE_PIN AH19 - DDR4_SODIMM_DQS2_T Bank 504 - PS_DDR_DQS_P2 +#Other net PACKAGE_PIN AH22 - DDR4_SODIMM_DQS3_T Bank 504 - PS_DDR_DQS_P3 +#Other net PACKAGE_PIN AH28 - DDR4_SODIMM_DQS4_T Bank 504 - PS_DDR_DQS_P4 +#Other net PACKAGE_PIN AE28 - DDR4_SODIMM_DQS5_T Bank 504 - PS_DDR_DQS_P5 +#Other net PACKAGE_PIN AJ32 - DDR4_SODIMM_DQS6_T Bank 504 - PS_DDR_DQS_P6 +#Other net PACKAGE_PIN AE32 - DDR4_SODIMM_DQS7_T Bank 504 - PS_DDR_DQS_P7 +#Other net PACKAGE_PIN AN32 - DDR4_SODIMM_DQS8_T Bank 504 - PS_DDR_DQS_P8 +#Other net PACKAGE_PIN AM30 - DDR4_SODIMM_ODT0 Bank 504 - PS_DDR_ODT0 +#Other net PACKAGE_PIN AJ26 - DDR4_SODIMM_ODT1 Bank 504 - PS_DDR_ODT1 +#Other net PACKAGE_PIN AF20 - DDR4_SODIMM_PARITY Bank 504 - PS_DDR_PARITY +#Other net PACKAGE_PIN AF21 - ZYNQ_DDR4_SODIMM_RESET_B Bank 504 - PS_DDR_RAM_RST_N +#Other net PACKAGE_PIN AF23 - UDIMM_PS_ZQ Bank 504 - PS_DDR_ZQ +#Other net PACKAGE_PIN AF27 - 68N6670 Bank 504 - PS_SENSE_DDRPHY_VREF_N +#Other net PACKAGE_PIN AF26 - 68N6673 Bank 504 - PS_SENSE_DDRPHY_VREF_P +#Other net PACKAGE_PIN AB34 - GTR_LANE0_RX_N Bank 505 - PS_MGTRRXN0_505 +#Other net PACKAGE_PIN AA32 - GTR_LANE1_RX_N Bank 505 - PS_MGTRRXN1_505 +#Other net PACKAGE_PIN Y34 - GTR_LANE2_RX_N Bank 505 - PS_MGTRRXN2_505 +#Other net PACKAGE_PIN V34 - GTR_LANE3_RX_N Bank 505 - PS_MGTRRXN3_505 +#Other net PACKAGE_PIN AB33 - GTR_LANE0_RX_P Bank 505 - PS_MGTRRXP0_505 +#Other net PACKAGE_PIN AA31 - GTR_LANE1_RX_P Bank 505 - PS_MGTRRXP1_505 +#Other net PACKAGE_PIN Y33 - GTR_LANE2_RX_P Bank 505 - PS_MGTRRXP2_505 +#Other net PACKAGE_PIN V33 - GTR_LANE3_RX_P Bank 505 - PS_MGTRRXP3_505 +#Other net PACKAGE_PIN AB30 - GTR_LANE0_TX_N Bank 505 - PS_MGTRTXN0_505 +#Other net PACKAGE_PIN Y30 - GTR_LANE1_TX_N Bank 505 - PS_MGTRTXN1_505 +#Other net PACKAGE_PIN W32 - GTR_LANE2_TX_N Bank 505 - PS_MGTRTXN2_505 +#Other net PACKAGE_PIN V30 - GTR_LANE3_TX_N Bank 505 - PS_MGTRTXN3_505 +#Other net PACKAGE_PIN AB29 - GTR_LANE0_TX_P Bank 505 - PS_MGTRTXP0_505 +#Other net PACKAGE_PIN Y29 - GTR_LANE1_TX_P Bank 505 - PS_MGTRTXP1_505 +#Other net PACKAGE_PIN W31 - GTR_LANE2_TX_P Bank 505 - PS_MGTRTXP2_505 +#Other net PACKAGE_PIN V29 - GTR_LANE3_TX_P Bank 505 - PS_MGTRTXP3_505 +#Other net PACKAGE_PIN AA28 - GTR_REF_CLK_PCIE_C_N Bank 505 - PS_MGTREFCLK0N_505 +#Other net PACKAGE_PIN AA27 - GTR_REF_CLK_PCIE_C_P Bank 505 - PS_MGTREFCLK0P_505 +#Other net PACKAGE_PIN W28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505 +#Other net PACKAGE_PIN W27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505 +#Other net PACKAGE_PIN U28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505 +#Other net PACKAGE_PIN U27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505 +#Other net PACKAGE_PIN U32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505 +#Other net PACKAGE_PIN U31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505 +#Other net PACKAGE_PIN AB28 - 69N5804 Bank 505 - PS_MGTRREF_505 diff --git a/target/xilinx/scripts/flash_spi.tcl b/target/xilinx/scripts/flash_spi.tcl new file mode 100644 index 000000000..75eca913e --- /dev/null +++ b/target/xilinx/scripts/flash_spi.tcl @@ -0,0 +1,48 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nils Wistoff +# Noah Huetter + +open_hw_manager + +connect_hw_server -url $::env(HOST):$::env(PORT) +open_hw_target $::env(HOST):$::env(PORT)/$::env(FPGA_PATH) + +set file $::env(FILE) +set offset $::env(OFFSET) +set mcs_file image.mcs + +if {$::env(BOARD) eq "vcu128"} { + set hw_device [get_hw_devices xcvu37p_0] + set hw_mem_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] +} + +# Create flash configuration file +write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offset $file" \ + -checksum \ + -file $mcs_file + +set_property PARAM.FREQUENCY 15000000 [get_hw_targets *] + +create_hw_cfgmem -hw_device $hw_device $hw_mem_device +set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] +set_property PROGRAM.ADDRESS_RANGE {use_file} $hw_cfgmem +set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +set_property PROGRAM.PRM_FILE {} $hw_cfgmem +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem +set_property PROGRAM.BLANK_CHECK 0 $hw_cfgmem +set_property PROGRAM.ERASE 1 $hw_cfgmem +set_property PROGRAM.CFG_PROGRAM 1 $hw_cfgmem +set_property PROGRAM.VERIFY 1 $hw_cfgmem +set_property PROGRAM.CHECKSUM 0 $hw_cfgmem + +# Create bitstream to access SPI flash +create_hw_bitstream -hw_device $hw_device [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_device]; +program_hw_devices $hw_device; +refresh_hw_device $hw_device; + +# Program SPI flash +program_hw_cfgmem -hw_cfgmem $hw_cfgmem diff --git a/target/xilinx/scripts/program.tcl b/target/xilinx/scripts/program.tcl index 846519a67..02dac55ac 100644 --- a/target/xilinx/scripts/program.tcl +++ b/target/xilinx/scripts/program.tcl @@ -8,21 +8,16 @@ open_hw_manager connect_hw_server -url $::env(HOST):$::env(PORT) +open_hw_target $::env(HOST):$::env(PORT)/$::env(FPGA_PATH) if {$::env(BOARD) eq "genesys2"} { - open_hw_target $::env(HOST):$::env(PORT)/$::env(FPGA_PATH) - - current_hw_device [get_hw_devices xc7k325t_0] - set_property PROGRAM.FILE $::env(BIT) [get_hw_devices xc7k325t_0] - program_hw_devices [get_hw_devices xc7k325t_0] - refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0] -} elseif {$::env(BOARD) eq "vc707"} { - open_hw_target {$::env(HOST):$::env(PORT)/$::env(FPGA_PATH)} - - current_hw_device [get_hw_devices xc7vx485t_0] - set_property PROGRAM.FILE $::env(BIT) [get_hw_devices xc7vx485t_0] - program_hw_devices [get_hw_devices xc7vx485t_0] - refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0] -} else { - exit 1 + set hw_device [get_hw_devices xc7k325t_0] } +if {$::env(BOARD) eq "vcu128"} { + set hw_device [get_hw_devices xcvu37p_0] +} + +current_hw_device $hw_device +set_property PROGRAM.FILE $::env(BIT) $hw_device +program_hw_devices $hw_device +refresh_hw_device [lindex $hw_device 0] diff --git a/target/xilinx/scripts/prologue.tcl b/target/xilinx/scripts/prologue.tcl index 4985d3d18..4cb96c53c 100644 --- a/target/xilinx/scripts/prologue.tcl +++ b/target/xilinx/scripts/prologue.tcl @@ -14,4 +14,4 @@ set_param general.maxThreads 8 #set_msg_config -id {[Synth 8-5858]} -new_severity "info" -#set_msg_config -id {[Synth 8-4480]} -limit 1000 \ No newline at end of file +#set_msg_config -id {[Synth 8-4480]} -limit 1000 diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl index c99247e94..29b281625 100644 --- a/target/xilinx/scripts/run.tcl +++ b/target/xilinx/scripts/run.tcl @@ -4,21 +4,20 @@ # # Author: Florian Zaruba -# hard-coded to Genesys 2 for the moment - -if {$::env(BOARD) eq "genesys2"} { - add_files -fileset constrs_1 -norecurse constraints/genesys2.xdc -} elseif {$::env(BOARD) eq "kc705"} { - add_files -fileset constrs_1 -norecurse constraints/kc705.xdc -} elseif {$::env(BOARD) eq "vc707"} { - add_files -fileset constrs_1 -norecurse constraints/vc707.xdc -} else { +# Contraints files selection +switch $::env(BOARD) { + "genesys2" - "kc705" - "vc707" - "vcu128" - "zcu102" { + import_files -fileset constrs_1 -norecurse constraints/cheshire.xdc + import_files -fileset constrs_1 -norecurse constraints/$::env(BOARD).xdc + } + default { exit 1 + } } -read_ip { \ - "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ -} +# Ips selection +set ips $::env(IP_PATHS) +read_ip $ips source scripts/add_sources.tcl @@ -26,8 +25,6 @@ set_property top ${project}_top_xilinx [current_fileset] update_compile_order -fileset sources_1 -add_files -fileset constrs_1 -norecurse constraints/$project.xdc - set_property strategy Flow_PerfOptimized_high [get_runs synth_1] set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] @@ -37,9 +34,10 @@ synth_design -rtl -name rtl_1 set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] +# Synthesis launch_runs synth_1 wait_on_run synth_1 -open_run synth_1 +open_run synth_1 -name synth_1 exec mkdir -p reports/ exec rm -rf reports/* @@ -51,13 +49,63 @@ report_utilization -hierarchical -file re report_cdc -file reports/$project.cdc.rpt report_clock_interaction -file reports/$project.clock_interaction.rpt +# Instantiate ILA +set DEBUG [llength [get_nets -hier -filter {MARK_DEBUG == 1}]] +if ($DEBUG) { + remove_cell [get_cells -hier -filter {ORIG_REF_NAME == "unread" || REF_NAME == "unread"}] + # Create core + puts "Creating debug core..." + create_debug_core u_ila_0 ila + set_property -dict "ALL_PROBE_SAME_MU true ALL_PROBE_SAME_MU_CNT 4 C_ADV_TRIGGER true C_DATA_DEPTH 16384 \ + C_EN_STRG_QUAL true C_INPUT_PIPE_STAGES 0 C_TRIGIN_EN false C_TRIGOUT_EN false" [get_debug_cores u_ila_0] + ## Clock + set_property port_width 1 [get_debug_ports u_ila_0/clk] + connect_debug_port u_ila_0/clk [get_nets soc_clk] + # Get nets to debug + set debugNets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]] + set netNameLast "" + set probe_i 0 + # Loop through all nets (add extra list element to ensure last net is processed) + foreach net [concat $debugNets {""}] { + # Remove trailing array index + regsub {\[[0-9]*\]$} $net {} netName + # Create probe after all signals with the same name have been collected + if {$netNameLast != $netName} { + if {$netNameLast != ""} { + puts "Creating probe $probe_i with width [llength $sigList] for signal '$netNameLast'" + # probe0 already exists, and does not need to be created + if {$probe_i != 0} { + create_debug_port u_ila_0 probe + } + set_property port_width [llength $sigList] [get_debug_ports u_ila_0/probe$probe_i] + set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe$probe_i] + connect_debug_port u_ila_0/probe$probe_i [get_nets $sigList] + incr probe_i + } + set sigList "" + } + lappend sigList $net + set netNameLast $netName + } + # Need to save save constraints before implementing the core + # set_property target_constrs_file cheshire.srcs/constrs_1/imports/constraints/$::env(BOARD).xdc [current_fileset -constrset] + save_constraints -force + implement_debug_core + write_debug_probes -force probes.ltx +} + +# Incremental implementation +if {[info exists $::env(ROUTED_DCP)] && [file exists $::env(ROUTED_DCP)]} { + set_property incremental_checkpoint $ $::env(ROUTED_DCP) [get_runs impl_1] +} + +# Implementation launch_runs impl_1 wait_on_run impl_1 launch_runs impl_1 -to_step write_bitstream wait_on_run impl_1 -#Check timing constraints -open_run impl_1 +# Check timing constraints set timingrep [report_timing_summary -no_header -no_detailed_paths -return_string] if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} { if {! [string match -nocase {*timing constraints are met*} $timingrep]} { @@ -66,12 +114,12 @@ if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} { } } -# output Verilog netlist + SDC for timing simulation +# Output Verilog netlist + SDC for timing simulation write_verilog -force -mode funcsim out/${project}_funcsim.v write_verilog -force -mode timesim out/${project}_timesim.v -write_sdf -force out/${project}_timesim.sdf +# write_sdf -force out/${project}_timesim.sdf -# reports +# Reports exec mkdir -p reports/ exec rm -rf reports/* check_timing -file reports/${project}.check_timing.rpt diff --git a/target/xilinx/sim/run_simulation.tcl b/target/xilinx/sim/run_simulation.tcl new file mode 100644 index 000000000..b02604606 --- /dev/null +++ b/target/xilinx/sim/run_simulation.tcl @@ -0,0 +1,48 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +source ../scripts/add_sources_vsim.tcl + +if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} { + source ips/xlnx_clk_wiz/questa/compile.do + +if {[string first "xlnx_vio" $::env(IPS)] != -1} { + source ips/xlnx_vio/questa/compile.do +}} + +if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} { + source ips/xlnx_mig_7_ddr3_ex/questa/compile.do + source ips/xlnx_mig_7_ddr3/questa/compile.do + vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v" +} + +if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} { + source ips/xlnx_mig_ddr4_ex/questa/compile.do + source ips/xlnx_mig_ddr4/questa/compile.do + vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv" +} + +# Note : this testbench does not implenent the ddr4 memory model +set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl" + +set XLIB_ARGS "-L secureip -L xpm -L unisims_ver -L unimacro_ver -L work -L xil_defaultlib" + +if {![info exists VOPTARGS]} { + set VOPTARGS "+acc" +} + +set flags "-permissive -suppress 3009 -suppress 8386 -error 7" + +set pargs "" +if {[info exists BOOTMODE]} { append pargs "+BOOTMODE=${BOOTMODE} " } +if {[info exists PRELMODE]} { append pargs "+PRELMODE=${PRELMODE} " } +if {[info exists BINARY]} { append pargs "+BINARY=${BINARY} " } +if {[info exists IMAGE]} { append pargs "+IMAGE=${IMAGE} " } + +eval "vsim ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${XLIB_ARGS} ${pargs} ${flags} + +set StdArithNoWarnings 1 +set NumericStdNoWarnings 1 diff --git a/target/xilinx/sim/setup_simulation.tcl b/target/xilinx/sim/setup_simulation.tcl new file mode 100644 index 000000000..d12549aea --- /dev/null +++ b/target/xilinx/sim/setup_simulation.tcl @@ -0,0 +1,35 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set command "" +set script_path [ file dirname [ file normalize [ info script ] ] ] + +if { $argc == 1 } { + set command [lindex $argv 0] +} + +puts "Running with SIMULATOR_PATH=$::env(SIMULATOR_PATH) ; GCC_PATH=$::env(GCC_PATH) ; XILINX_SIMLIB_PATH=$::env(XILINX_SIMLIB_PATH)" + +# If you do this part from GUI : +# -simulator questa +# -simulator_exec_path {/usr/pack/questa-2022.3-bt/questasim/bin} +# -gcc_exec_path {/usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin} +# -family ... +# -library unisim +# -dir {~/xlib_questa-2022.3} +if { $command == "compile_simlib" } { + compile_simlib -simulator questa -simulator_exec_path {$::env(SIMULATOR_PATH)} \ + -gcc_exec_path {$::env(GCC_PATH)} -family all \ + -language verilog -dir {$::env(XILINX_SIMLIB_PATH)} -verbose + +} elseif { $command == "export_simulation" } { + open_project $::env(VIVADO_PROJECT) + export_simulation -simulator questa -directory "./ips" -lib_map_path "$::env(XILINX_SIMLIB_PATH)" \ + -absolute_path -force -of_objects [get_ips *] + +} else { + puts "[$argv0] Unknown command: $command" +} diff --git a/target/xilinx/sim/simulate.mk b/target/xilinx/sim/simulate.mk new file mode 100644 index 000000000..1005fe307 --- /dev/null +++ b/target/xilinx/sim/simulate.mk @@ -0,0 +1,58 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +CHS_XIL_SIM_DIR ?= $(CHS_XIL_DIR)/sim + +XILINX_SIMLIB_PATH ?= ~/xlib_questa-2022.3_vivado-2022.1 +SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin +GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin + +ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) + +# Pre-generated/modified example projects (contain the simulation top level) +ifneq ($(filter xlnx_mig_ddr4,$(ips-names)),) + ip-example-projects := xlnx_mig_ddr4_ex +endif +ifneq ($(filter xlnx_mig_7_ddr3,$(ips-names)),) + ip-example-projects := xlnx_mig_7_ddr3_ex +endif + +ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects))) + +VIVADOENV_SIM := $(VIVADOENV) \ + XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ + SIMULATOR_PATH=$(SIMULATOR_PATH) \ + GCC_PATH=$(GCC_PATH) \ + VIVADO_PROJECT=../${PROJECT}.xpr +VLOG_ARGS := -suppress 2583 -suppress 13314 + +# Fetch example projects at IIS (containing SRAM behavioral models) +$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips + +# Generate simulation libraries +$(XILINX_SIMLIB_PATH)/modelsim.ini: + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" + +# +$(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" + +$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl: + $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@ + +chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl + mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib + cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR) + chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini + cd $(CHS_XIL_SIM_DIR) && IPS="$(ips-names)" questa-2022.3 vsim -work work -do "run_simulation.tcl" + +chs-xil-clean-sim: + cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini + +.PHONY: clean-sim sim diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index f9763f547..3f704e289 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -1,69 +1,98 @@ -// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright 2023 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // // Nicole Narr // Christopher Reinwardt +// Cyril Koenig `include "cheshire/typedef.svh" +`include "phy_definitions.svh" module cheshire_top_xilinx import cheshire_pkg::*; ( - input logic sysclk_p, - input logic sysclk_n, +`ifdef USE_RESET + input logic cpu_reset, +`endif +`ifdef USE_RESETN input logic cpu_resetn, +`endif - input logic test_mode_i, + // System clock for clk_wiz + input logic sys_clk_p, + input logic sys_clk_n, +`ifdef USE_SWITCHES + input logic testmode_i, input logic [1:0] boot_mode_i, +`endif - output logic uart_tx_o, - input logic uart_rx_i, - +`ifdef USE_JTAG input logic jtag_tck_i, - input logic jtag_trst_ni, input logic jtag_tms_i, input logic jtag_tdi_i, output logic jtag_tdo_o, - +`ifdef USE_JTAG_TRSTN + input logic jtag_trst_ni, +`endif +`ifdef USE_JTAG_VDDGND + output logic jtag_vdd_o, + output logic jtag_gnd_o, +`endif +`endif + +`ifdef USE_I2C inout wire i2c_scl_io, inout wire i2c_sda_io, +`endif +`ifdef USE_SD input logic sd_cd_i, output logic sd_cmd_o, inout wire [3:0] sd_d_io, output logic sd_reset_o, output logic sd_sclk_o, +`endif +`ifdef USE_FAN input logic [3:0] fan_sw, output logic fan_pwm, +`endif - // DDR3 DRAM interface - output wire [14:0] ddr3_addr, - output wire [2:0] ddr3_ba, - output wire ddr3_cas_n, - output wire [0:0] ddr3_ck_n, - output wire [0:0] ddr3_ck_p, - output wire [0:0] ddr3_cke, - output wire [0:0] ddr3_cs_n, - output wire [3:0] ddr3_dm, - inout wire [31:0] ddr3_dq, - inout wire [3:0] ddr3_dqs_n, - inout wire [3:0] ddr3_dqs_p, - output wire [0:0] ddr3_odt, - output wire ddr3_ras_n, - output wire ddr3_reset_n, - output wire ddr3_we_n, +`ifdef USE_QSPI +`ifndef USE_STARTUPE3 + // TODO: off-chip qspi interface +`endif // USE_STARTUPE3 +`endif // USE_QSPI +`ifdef USE_VGA // VGA Colour signals output logic [4:0] vga_b, output logic [5:0] vga_g, output logic [4:0] vga_r, - // VGA Sync signals output logic vga_hs, - output logic vga_vs + output logic vga_vs, +`endif + +`ifdef USE_SERIAL + // DDR Link + output logic [4:0] ddr_link_o, + output logic ddr_link_clk_o, +`endif + + // Phy interface for DRAMs +`ifdef USE_DDR4 + `DDR4_INTF +`endif +`ifdef USE_DDR3 + `DDR3_INTF +`endif + + output logic uart_tx_o, + input logic uart_rx_i + ); // Configure cheshire for FPGA mapping @@ -152,40 +181,74 @@ module cheshire_top_xilinx localparam cheshire_cfg_t CheshireFPGACfg = FPGACfg; `CHESHIRE_TYPEDEF_ALL(, CheshireFPGACfg) - axi_llc_req_t axi_llc_mst_req, dram_req, dram_req_cdc; - axi_llc_rsp_t axi_llc_mst_rsp, dram_resp, dram_resp_cdc; + axi_llc_req_t axi_llc_mst_req; + axi_llc_rsp_t axi_llc_mst_rsp; - wire dram_clock_out; - wire dram_sync_reset; - wire soc_clk; + /////////////////////////// + // Clk reset definitions // + /////////////////////////// - logic rst_n; + `ifdef USE_RESET + logic cpu_resetn; + assign cpu_resetn = ~cpu_reset; + `elsif USE_RESETN + logic cpu_reset; + assign cpu_reset = ~cpu_resetn; + `endif + logic sys_rst; - // Statically assign the response user signals - // B Channel user - assign dram_resp.b.user = '0; - - // R Channel user - assign dram_resp.r.user = '0; + (* dont_touch = "yes" *) wire soc_clk; + (* dont_touch = "yes" *) wire rst_n; /////////////////// - // Clock Divider // + // GPIOs // /////////////////// - clk_int_div #( - .DIV_VALUE_WIDTH ( 4 ), - .DEFAULT_DIV_VALUE ( 4'h4 ), - .ENABLE_CLOCK_IN_RESET ( 1'b0 ) - ) i_sys_clk_div ( - .clk_i ( dram_clock_out ), - .rst_ni ( ~dram_sync_reset ), - .en_i ( 1'b1 ), - .test_mode_en_i ( testmode_i ), - .div_i ( 4'h4 ), - .div_valid_i ( 1'b0 ), - .div_ready_o ( ), - .clk_o ( soc_clk ), - .cycl_count_o ( ) + // Tie off signals if no switches on the board +`ifndef USE_SWITCHES + logic testmode_i; + logic [1:0] boot_mode_i; + assign testmode_i = '0; + assign boot_mode_i = 2'b00; +`endif + + // Give VDD and GND to JTAG dongle +`ifdef USE_JTAG_VDDGND + assign jtag_vdd_o = '1; + assign jtag_gnd_o = '0; +`endif +`ifndef USE_JTAG_TRSTN + logic jtag_trst_ni; + assign jtag_trst_ni = '1; +`endif + + ////////////////// + // Clock Wizard // + ////////////////// + + wire sys_clk; + + // Get from the diff board pins a single ended buffered clock that + // can be sent to clk_wiz and DDR separately (without cascading MMCMs) + // As sys_clk frequency depends on the boards /!\ in IPs configurations + IBUFDS # + ( + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_sys_clk + ( + .I (sys_clk_p), + .IB (sys_clk_n), + .O (sys_clk) + ); + + xlnx_clk_wiz i_xlnx_clk_wiz ( + .clk_in1 ( sys_clk ), + .reset ( '0 ), + .clk_100 ( ), + .clk_50 ( soc_clk ), + .clk_20 ( ), + .clk_10 ( ) ); ///////////////////// @@ -194,133 +257,62 @@ module cheshire_top_xilinx rstgen i_rstgen_main ( .clk_i ( soc_clk ), - .rst_ni ( ~dram_sync_reset ), - .test_mode_i ( test_en ), + .rst_ni ( ~sys_rst ), + .test_mode_i ( testmode_i ), .rst_no ( rst_n ), .init_no ( ) // keep open ); + /////////////////// + // VIOs // + /////////////////// - /////////////////////////////////////////// - // AXI Clock Domain Crossing SoC -> DRAM // - /////////////////////////////////////////// - - axi_cdc #( - .aw_chan_t ( axi_llc_aw_chan_t ), - .w_chan_t ( axi_llc_w_chan_t ), - .b_chan_t ( axi_llc_b_chan_t ), - .ar_chan_t ( axi_llc_ar_chan_t ), - .r_chan_t ( axi_llc_r_chan_t ), - .axi_req_t ( axi_llc_req_t ), - .axi_resp_t ( axi_llc_rsp_t ), - .LogDepth ( 1 ) - ) i_axi_cdc_mig ( - .src_clk_i ( soc_clk ), - .src_rst_ni ( rst_n ), - .src_req_i ( axi_llc_mst_req ), - .src_resp_o ( axi_llc_mst_rsp ), - .dst_clk_i ( dram_clock_out ), - .dst_rst_ni ( rst_n ), - .dst_req_o ( dram_req_cdc ), - .dst_resp_i ( dram_resp_cdc ) - ); + logic vio_reset, vio_boot_mode_sel; + logic [1:0] boot_mode, vio_boot_mode; - // AXI CUT (spill register) between the AXI CDC and the MIG to - // reduce timing pressure - axi_cut #( - .Bypass ( 1'b0 ), - .aw_chan_t ( axi_llc_aw_chan_t ), - .w_chan_t ( axi_llc_w_chan_t ), - .b_chan_t ( axi_llc_b_chan_t ), - .ar_chan_t ( axi_llc_ar_chan_t ), - .r_chan_t ( axi_llc_r_chan_t ), - .axi_req_t ( axi_llc_req_t ), - .axi_resp_t ( axi_llc_rsp_t ) - ) i_axi_cut_soc_dram ( - .clk_i ( dram_clock_out ), - .rst_ni ( rst_n ), - - .slv_req_i ( dram_req_cdc ), - .slv_resp_o ( dram_resp_cdc ), - - .mst_req_o ( dram_req ), - .mst_resp_i ( dram_resp ) +`ifdef USE_VIO + xlnx_vio i_xlnx_vio ( + .clk(soc_clk), + .probe_out0(vio_reset), + .probe_out1(vio_boot_mode), + .probe_out2(vio_boot_mode_sel) ); +`else + assign vio_reset = '0; + assign vio_boot_mode = '0; + assign vio_boot_mode_sel = '0; +`endif + + assign sys_rst = ~cpu_resetn | vio_reset; + assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; ////////////// // DRAM MIG // ////////////// - xlnx_mig_7_ddr3 i_dram ( - .sys_clk_p ( sysclk_p ), - .sys_clk_n ( sysclk_n ), - .ddr3_dq, - .ddr3_dqs_n, - .ddr3_dqs_p, - .ddr3_addr, - .ddr3_ba, - .ddr3_ras_n, - .ddr3_cas_n, - .ddr3_we_n, - .ddr3_reset_n, - .ddr3_ck_p, - .ddr3_ck_n, - .ddr3_cke, - .ddr3_cs_n, - .ddr3_dm, - .ddr3_odt, - .mmcm_locked ( ), // keep open - .app_sr_req ( '0 ), - .app_ref_req ( '0 ), - .app_zq_req ( '0 ), - .app_sr_active ( ), // keep open - .app_ref_ack ( ), // keep open - .app_zq_ack ( ), // keep open - .ui_clk ( dram_clock_out ), - .ui_clk_sync_rst ( dram_sync_reset ), - .aresetn ( rst_n ), - .s_axi_awid ( dram_req.aw.id ), - .s_axi_awaddr ( dram_req.aw.addr[29:0] ), - .s_axi_awlen ( dram_req.aw.len ), - .s_axi_awsize ( dram_req.aw.size ), - .s_axi_awburst ( dram_req.aw.burst ), - .s_axi_awlock ( dram_req.aw.lock ), - .s_axi_awcache ( dram_req.aw.cache ), - .s_axi_awprot ( dram_req.aw.prot ), - .s_axi_awqos ( dram_req.aw.qos ), - .s_axi_awvalid ( dram_req.aw_valid ), - .s_axi_awready ( dram_resp.aw_ready ), - .s_axi_wdata ( dram_req.w.data ), - .s_axi_wstrb ( dram_req.w.strb ), - .s_axi_wlast ( dram_req.w.last ), - .s_axi_wvalid ( dram_req.w_valid ), - .s_axi_wready ( dram_resp.w_ready ), - .s_axi_bready ( dram_req.b_ready ), - .s_axi_bid ( dram_resp.b.id ), - .s_axi_bresp ( dram_resp.b.resp ), - .s_axi_bvalid ( dram_resp.b_valid ), - .s_axi_arid ( dram_req.ar.id ), - .s_axi_araddr ( dram_req.ar.addr[29:0] ), - .s_axi_arlen ( dram_req.ar.len ), - .s_axi_arsize ( dram_req.ar.size ), - .s_axi_arburst ( dram_req.ar.burst ), - .s_axi_arlock ( dram_req.ar.lock ), - .s_axi_arcache ( dram_req.ar.cache ), - .s_axi_arprot ( dram_req.ar.prot ), - .s_axi_arqos ( dram_req.ar.qos ), - .s_axi_arvalid ( dram_req.ar_valid ), - .s_axi_arready ( dram_resp.ar_ready ), - .s_axi_rready ( dram_req.r_ready ), - .s_axi_rid ( dram_resp.r.id ), - .s_axi_rdata ( dram_resp.r.data ), - .s_axi_rresp ( dram_resp.r.resp ), - .s_axi_rlast ( dram_resp.r.last ), - .s_axi_rvalid ( dram_resp.r_valid ), - .init_calib_complete ( ), // keep open - .device_temp ( ), // keep open - .sys_rst ( cpu_resetn ) +`ifdef USE_DDR + dram_wrapper #( + .axi_soc_aw_chan_t ( axi_llc_aw_chan_t ), + .axi_soc_w_chan_t ( axi_llc_w_chan_t ), + .axi_soc_b_chan_t ( axi_llc_b_chan_t ), + .axi_soc_ar_chan_t ( axi_llc_ar_chan_t ), + .axi_soc_r_chan_t ( axi_llc_r_chan_t ), + .axi_soc_req_t ( axi_llc_req_t ), + .axi_soc_resp_t ( axi_llc_rsp_t ) + ) i_dram_wrapper ( + // Rst + .sys_rst_i ( sys_rst ), + .soc_resetn_i ( rst_n ), + .soc_clk_i ( soc_clk ), + // Sys clk + .dram_clk_i ( sys_clk ), + // Axi + .soc_req_i ( axi_llc_mst_req ), + .soc_rsp_o ( axi_llc_mst_rsp ), + // Phy + .* ); - +`endif ////////////////// // I2C Adaption // @@ -333,6 +325,7 @@ module cheshire_top_xilinx logic i2c_sda_en; logic i2c_scl_en; +`ifdef USE_I2C // Three state buffer for SCL IOBUF #( .DRIVE ( 12 ), @@ -358,51 +351,100 @@ module cheshire_top_xilinx .I ( i2c_sda_soc_out ), .T ( ~i2c_sda_en ) ); +`endif ////////////////// // SPI Adaption // ////////////////// - logic spi_sck_soc; - logic [1:0] spi_cs_soc; - logic [3:0] spi_sd_soc_out; - logic [3:0] spi_sd_soc_in; + (* mark_debug = "true" *) logic spi_sck_soc; + (* mark_debug = "true" *) logic [1:0] spi_cs_soc; + (* mark_debug = "true" *) logic [3:0] spi_sd_soc_out; + (* mark_debug = "true" *) logic [3:0] spi_sd_soc_in; - logic spi_sck_en; - logic [1:0] spi_cs_en; - logic [3:0] spi_sd_en; + (* mark_debug = "true" *) logic spi_sck_en; + (* mark_debug = "true" *) logic [1:0] spi_cs_en; + (* mark_debug = "true" *) logic [3:0] spi_sd_en; +`ifdef USE_SD // Assert reset low => Apply power to the SD Card assign sd_reset_o = 1'b0; - // SCK - SD CLK signal assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1; - // CS - SD DAT3 signal assign sd_d_io[3] = spi_cs_en[0] ? spi_cs_soc[0] : 1'b1; - // MOSI - SD CMD signal assign sd_cmd_o = spi_sd_en[0] ? spi_sd_soc_out[0] : 1'b1; - // MISO - SD DAT0 signal assign spi_sd_soc_in[1] = sd_d_io[0]; - // SD DAT1 and DAT2 signal tie-off - Not used for SPI mode assign sd_d_io[2:1] = 2'b11; - // Bind input side of SoC low for output signals assign spi_sd_soc_in[0] = 1'b0; assign spi_sd_soc_in[2] = 1'b0; assign spi_sd_soc_in[3] = 1'b0; +`endif + ////////////////// + // QSPI // + ////////////////// + +`ifdef USE_QSPI + logic qspi_clk; + logic qspi_clk_ts; + logic [3:0] qspi_dqi; + logic [3:0] qspi_dqo_ts; + logic [3:0] qspi_dqo; + logic [SpihNumCs-1:0] qspi_cs_b; + logic [SpihNumCs-1:0] qspi_cs_b_ts; + + assign qspi_clk = spi_sck_soc; + assign qspi_cs_b = spi_cs_soc; + assign qspi_dqo = spi_sd_soc_out; + assign spi_sd_soc_in = qspi_dqi; + // Tristate - Enable + assign qspi_clk_ts = ~spi_sck_en; + assign qspi_cs_b_ts = ~spi_cs_en; + assign qspi_dqo_ts = ~spi_sd_en; + + // On VCU128/ZCU102, SPI ports are not directly available +`ifdef USE_STARTUPE3 + STARTUPE3 #( + .PROG_USR("FALSE"), + .SIM_CCLK_FREQ(0.0) + ) + STARTUPE3_inst ( + .CFGCLK (), + .CFGMCLK (), + .DI (qspi_dqi), + .EOS (), + .PREQ (), + .DO (qspi_dqo), + .DTS (qspi_dqo_ts), + .FCSBO (qspi_cs_b[1]), + .FCSBTS (qspi_cs_b_ts[1]), + .GSR (1'b0), + .GTS (1'b0), + .KEYCLEARB (1'b1), + .PACK (1'b0), + .USRCCLKO (qspi_clk), + .USRCCLKTS (qspi_clk_ts), + .USRDONEO (1'b1), + .USRDONETS (1'b1) + ); +`else + // TODO: off-chip qspi interface +`endif // USE_STARTUPE3 + +`endif // USE_QSPI ///////////////////////// // "RTC" Clock Divider // ///////////////////////// logic rtc_clk_d, rtc_clk_q; - logic [4:0] counter_d, counter_q; + logic [15:0] counter_d, counter_q; // Divide soc_clk (50 MHz) by 50 => 1 MHz RTC Clock always_comb begin @@ -410,14 +452,14 @@ module cheshire_top_xilinx rtc_clk_d = rtc_clk_q; if(counter_q == 24) begin - counter_d = 5'b0; + counter_d = '0; rtc_clk_d = ~rtc_clk_q; end end always_ff @(posedge soc_clk, negedge rst_n) begin if(~rst_n) begin - counter_q <= 5'b0; + counter_q <= '0; rtc_clk_q <= 0; end else begin counter_q <= counter_d; @@ -425,18 +467,18 @@ module cheshire_top_xilinx end end - ///////////////// // Fan Control // ///////////////// +`ifdef USE_FAN fan_ctrl i_fan_ctrl ( .clk_i ( soc_clk ), .rst_ni ( rst_n ), .pwm_setting_i ( fan_sw ), .fan_pwm_o ( fan_pwm ) ); - +`endif //////////////////////// // Regbus Error Slave // @@ -455,7 +497,6 @@ module cheshire_top_xilinx .rsp_o ( ext_rsp ) ); - ////////////////// // Cheshire SoC // ////////////////// @@ -474,9 +515,9 @@ module cheshire_top_xilinx ) i_cheshire_soc ( .clk_i ( soc_clk ), .rst_ni ( rst_n ), - .test_mode_i, - .boot_mode_i, - .rtc_i ( rtc_clk_q ), + .test_mode_i ( testmode_i ), + .boot_mode_i ( boot_mode ), + .rtc_i ( rtc_clk_q ), .axi_llc_mst_req_o ( axi_llc_mst_req ), .axi_llc_mst_rsp_i ( axi_llc_mst_rsp ), .axi_ext_mst_req_i ( '0 ), @@ -493,45 +534,45 @@ module cheshire_top_xilinx .dbg_active_o ( ), .dbg_ext_req_o ( ), .dbg_ext_unavail_i ( '0 ), +// Serial Link may be disabled +`ifdef USE_SERIAL + .ddr_link_i ( '0 ), + .ddr_link_o, + .ddr_link_clk_i ( 1'b1 ), + .ddr_link_clk_o, +`endif +// External JTAG may be disabled +`ifdef USE_JTAG .jtag_tck_i, .jtag_trst_ni, .jtag_tms_i, .jtag_tdi_i, .jtag_tdo_o, - .jtag_tdo_oe_o ( ), +`endif +// I2C Uses internal signals that are always defined + .i2c_sda_o ( i2c_sda_soc_out ), + .i2c_sda_i ( i2c_sda_soc_in ), + .i2c_sda_en_o ( i2c_sda_en ), + .i2c_scl_o ( i2c_scl_soc_out ), + .i2c_scl_i ( i2c_scl_soc_in ), + .i2c_scl_en_o ( i2c_scl_en ), +// SPI Uses internal signals that are always defined + .spih_sck_o ( spi_sck_soc ), + .spih_sck_en_o ( spi_sck_en ), + .spih_csb_o ( spi_cs_soc ), + .spih_csb_en_o ( spi_cs_en ), + .spih_sd_o ( spi_sd_soc_out ), + .spih_sd_en_o ( spi_sd_en ), + .spih_sd_i ( spi_sd_soc_in ), +`ifdef USE_VGA + .vga_hsync_o ( vga_hs ), + .vga_vsync_o ( vga_vs ), + .vga_red_o ( vga_r ), + .vga_green_o ( vga_g ), + .vga_blue_o ( vga_b ), +`endif .uart_tx_o, - .uart_rx_i, - .uart_rts_no ( ), - .uart_dtr_no ( ), - .uart_cts_ni ( 1'b0 ), - .uart_dsr_ni ( 1'b0 ), - .uart_dcd_ni ( 1'b0 ), - .uart_rin_ni ( 1'b0 ), - .i2c_sda_o ( i2c_sda_soc_out ), - .i2c_sda_i ( i2c_sda_soc_in ), - .i2c_sda_en_o ( i2c_sda_en ), - .i2c_scl_o ( i2c_scl_soc_out ), - .i2c_scl_i ( i2c_scl_soc_in ), - .i2c_scl_en_o ( i2c_scl_en ), - .spih_sck_o ( spi_sck_soc ), - .spih_sck_en_o ( spi_sck_en ), - .spih_csb_o ( spi_cs_soc ), - .spih_csb_en_o ( spi_cs_en ), - .spih_sd_o ( spi_sd_soc_out ), - .spih_sd_en_o ( spi_sd_en ), - .spih_sd_i ( spi_sd_soc_in ), - .gpio_i ( '0 ), - .gpio_o ( ), - .gpio_en_o ( ), - .slink_rcv_clk_i ( '1 ), - .slink_rcv_clk_o ( ), - .slink_i ( '0 ), - .slink_o ( ), - .vga_hsync_o ( vga_hs ), - .vga_vsync_o ( vga_vs ), - .vga_red_o ( vga_r ), - .vga_green_o ( vga_g ), - .vga_blue_o ( vga_b ) + .uart_rx_i ); endmodule diff --git a/target/xilinx/src/dram_wrapper.sv b/target/xilinx/src/dram_wrapper.sv new file mode 100644 index 000000000..56c0f4e2a --- /dev/null +++ b/target/xilinx/src/dram_wrapper.sv @@ -0,0 +1,441 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + + +`include "cheshire/typedef.svh" +`include "phy_definitions.svh" +`include "common_cells/registers.svh" + +module dram_wrapper #( + parameter type axi_soc_aw_chan_t = logic, + parameter type axi_soc_w_chan_t = logic, + parameter type axi_soc_b_chan_t = logic, + parameter type axi_soc_ar_chan_t = logic, + parameter type axi_soc_r_chan_t = logic, + parameter type axi_soc_req_t = logic, + parameter type axi_soc_resp_t = logic +) ( + // System reset + input sys_rst_i, + input dram_clk_i, + // Controller reset + input soc_resetn_i, + input soc_clk_i, + // Phy interfaces +`ifdef USE_DDR4 + `DDR4_INTF +`endif +`ifdef USE_DDR3 + `DDR3_INTF +`endif + // Dram axi interface + input axi_soc_req_t soc_req_i, + output axi_soc_resp_t soc_rsp_o +); + + //////////////////////////////////// + // Configurations and definitions // + //////////////////////////////////// + + typedef struct packed { + bit EnSpill0; + bit EnResizer; + bit EnCDC; + bit EnSpill1; + integer IdWidth; + integer AddrWidth; + integer DataWidth; + integer StrobeWidth; + } dram_cfg_t; + +`ifdef TARGET_VCU128 + localparam dram_cfg_t cfg = '{ + EnSpill0 : 1, + EnResizer : 1, + EnCDC : 1, // 333 MHz axi + EnSpill1 : 1, + IdWidth : 6, + AddrWidth : 32, + DataWidth : 512, + StrobeWidth : 64 + }; +`endif + +`ifdef TARGET_ZCU102 + localparam dram_cfg_t cfg = '{ + EnSpill0 : 1, + EnResizer : 1, + EnCDC : 1, // ??? MHz axi + EnSpill1 : 1, + IdWidth : 6, + AddrWidth : 29, + DataWidth : 128, + StrobeWidth : 16 + }; +`endif + +`ifdef TARGET_GENESYS2 + localparam dram_cfg_t cfg = '{ + EnSpill0 : 1, + EnResizer : 0, + EnCDC : 1, // 200 MHz axi + EnSpill1 : 1, + IdWidth : 6, + AddrWidth : 30, + DataWidth : 64, + StrobeWidth : 8 + }; +`endif + + // Define type after resizer (DRAM AXI) + `AXI_TYPEDEF_ALL(axi_ddr, logic[$bits(soc_req_i.ar.addr)-1:0], logic[$bits(soc_req_i.ar.id)-1:0], + logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0], + logic[$bits(soc_req_i.ar.user)-1:0]) + + // Clock on which is clocked the DRAM AXI + logic dram_axi_clk, dram_rst_o; + + // Signals before resizing + axi_soc_req_t soc_spill_req, spill_resizer_req; + axi_soc_resp_t soc_spill_rsp, spill_resizer_rsp; + + // Signals after resizing + axi_ddr_req_t resizer_cdc_req, cdc_spill_req; + axi_ddr_req_t spill_dram_req; + axi_ddr_resp_t resizer_cdc_rsp, cdc_spill_rsp; + axi_ddr_resp_t spill_dram_rsp; + + // Entry signals + assign soc_spill_req = soc_req_i; + assign soc_rsp_o = soc_spill_rsp; + + ////////////////////////// + // Instianciate Spill 0 // + ////////////////////////// + + if (cfg.EnSpill0) begin : gen_spill_0 + // AXI CUT (spill register) between the AXI CDC and the MIG to + // reduce timing pressure + axi_cut #( + .Bypass (1'b0), + .aw_chan_t (axi_soc_aw_chan_t), + .w_chan_t (axi_soc_w_chan_t), + .b_chan_t (axi_soc_b_chan_t), + .ar_chan_t (axi_soc_ar_chan_t), + .r_chan_t (axi_soc_r_chan_t), + .axi_req_t (axi_soc_req_t), + .axi_resp_t(axi_soc_resp_t) + ) i_axi_cut_soc_dram ( + .clk_i (soc_clk_i), + .rst_ni(soc_resetn_i), + .slv_req_i (soc_spill_req), + .slv_resp_o(soc_spill_rsp), + .mst_req_o (spill_resizer_req), + .mst_resp_i(spill_resizer_rsp) + ); + end else begin : gen_no_spill_0 + assign spill_resizer_req = soc_spill_req; + assign soc_spill_rsp = spill_resizer_rsp; + end + + ///////////////////////////////////// + // Instianciate data width resizer // + ///////////////////////////////////// + + if (cfg.EnResizer) begin : gen_dw_converter + axi_dw_converter #( + .AxiMaxReads (8), + .AxiSlvPortDataWidth($bits(spill_resizer_req.w.data)), + .AxiMstPortDataWidth($bits(resizer_cdc_req.w.data)), + .AxiAddrWidth ($bits(spill_resizer_req.ar.addr)), + .AxiIdWidth ($bits(spill_resizer_req.ar.id)), + // Common aw, ar, b + .aw_chan_t (axi_soc_aw_chan_t), + .b_chan_t (axi_soc_b_chan_t), + .ar_chan_t (axi_soc_ar_chan_t), + // Master w, r + .mst_w_chan_t (axi_ddr_w_chan_t), + .mst_r_chan_t (axi_ddr_r_chan_t), + .axi_mst_req_t (axi_ddr_req_t), + .axi_mst_resp_t (axi_ddr_resp_t), + // Slave w, r + .slv_w_chan_t (axi_soc_w_chan_t), + .slv_r_chan_t (axi_soc_r_chan_t), + .axi_slv_req_t (axi_soc_req_t), + .axi_slv_resp_t (axi_soc_resp_t) + ) axi_dw_converter_ddr4 ( + .clk_i(soc_clk_i), + .rst_ni(soc_resetn_i), + .slv_req_i(spill_resizer_req), + .slv_resp_o(spill_resizer_rsp), + .mst_req_o(resizer_cdc_req), + .mst_resp_i(resizer_cdc_rsp) + ); + end else begin : gen_no_dw_converter + assign resizer_cdc_req = spill_resizer_req; + assign spill_resizer_rsp = resizer_cdc_rsp; + end + + + ////////////////////// + // Instianciate CDC // + ////////////////////// + + if (cfg.EnCDC) begin : gen_cdc + axi_cdc #( + .aw_chan_t (axi_ddr_aw_chan_t), + .w_chan_t (axi_ddr_w_chan_t), + .b_chan_t (axi_ddr_b_chan_t), + .ar_chan_t (axi_ddr_ar_chan_t), + .r_chan_t (axi_ddr_r_chan_t), + .axi_req_t (axi_ddr_req_t), + .axi_resp_t(axi_ddr_resp_t), + .LogDepth (3) + ) i_axi_cdc_mig ( + .src_clk_i (soc_clk_i), + .src_rst_ni(soc_resetn_i), + .src_req_i (resizer_cdc_req), + .src_resp_o(resizer_cdc_rsp), + .dst_clk_i (dram_axi_clk), + .dst_rst_ni(~dram_rst_o), + .dst_req_o (cdc_spill_req), + .dst_resp_i(cdc_spill_rsp) + ); + end else begin : gen_no_cdc + assign cdc_spill_req = resizer_cdc_req; + assign resizer_cdc_rsp = cdc_spill_rsp; + end + + ////////////////////////// + // Instianciate Spill 1 // + ////////////////////////// + + if (cfg.EnSpill1) begin : gen_spill_1 + axi_cut #( + .Bypass (1'b0), + .aw_chan_t (axi_ddr_aw_chan_t), + .w_chan_t (axi_ddr_w_chan_t), + .b_chan_t (axi_ddr_b_chan_t), + .ar_chan_t (axi_ddr_ar_chan_t), + .r_chan_t (axi_ddr_r_chan_t), + .axi_req_t (axi_ddr_req_t), + .axi_resp_t(axi_ddr_resp_t) + ) i_axi_cut_dw_dram ( + .clk_i (dram_axi_clk), + .rst_ni(~dram_rst_o), + .slv_req_i (cdc_spill_req), + .slv_resp_o(cdc_spill_rsp), + .mst_req_o (spill_dram_req), + .mst_resp_i(spill_dram_rsp) + ); + end else begin : gen_no_spill_1 + assign spill_dram_req = cdc_spill_req; + assign cdc_spill_rsp = spill_dram_rsp; + end + + ///////////////// + // ID resizer // + ///////////////// + + // Padding when SoC id > DDR id + localparam IdPadding = $bits(spill_dram_req.aw.id) - cfg.IdWidth; + + // Resize awid and arid before sending to the DDR + logic [cfg.IdWidth-1:0] spill_dram_req_awid, spill_dram_rsp_bid; + logic [cfg.IdWidth-1:0] spill_dram_req_arid, spill_dram_rsp_rid; + // Registers to prepare bid and rid + logic [$bits(spill_dram_req.aw.id)-1:0] spill_dram_rsp_bid_d, spill_dram_rsp_bid_q; + logic [$bits(spill_dram_req.ar.id)-1:0] spill_dram_rsp_rid_d, spill_dram_rsp_rid_q; + `FFAR(spill_dram_rsp_bid_q, spill_dram_rsp_bid_d, '0, dram_axi_clk, dram_rst_o); + `FFAR(spill_dram_rsp_rid_q, spill_dram_rsp_rid_d, '0, dram_axi_clk, dram_rst_o); + + // Process ids + if (IdPadding > 0) begin : gen_downsize_ids + // Sample full rid and bid from arid and awid on request + assign spill_dram_rsp_rid_d = spill_dram_req.ar_valid ? spill_dram_req.ar.id : spill_dram_rsp_rid_q; + assign spill_dram_rsp_bid_d = spill_dram_req.aw_valid ? spill_dram_req.aw.id : spill_dram_rsp_bid_q; + // Send reduced ids to DRAM + assign spill_dram_req_arid = spill_dram_req.ar.id[cfg.IdWidth-1:0]; + assign spill_dram_req_awid = spill_dram_req.aw.id[cfg.IdWidth-1:0]; + // Send full sampled rid and bid to SoC on response + assign spill_dram_rsp.r.id = spill_dram_rsp.r_valid ? { + {IdPadding{1'b0}}, spill_dram_rsp_rid_q + } : '0; + assign spill_dram_rsp.b.id = spill_dram_rsp.b_valid ? { + {IdPadding{1'b0}}, spill_dram_rsp_bid_q + } : '0; + + end else begin : gen_upsize_ids + // Forward arid awid rid bid to and from DDR + assign spill_dram_req_arid = {{-IdPadding{1'b0}}, spill_dram_req.ar.id}; + assign spill_dram_req_awid = {{-IdPadding{1'b0}}, spill_dram_req.aw.id}; + assign spill_dram_rsp.r.id = spill_dram_rsp_rid; + assign spill_dram_rsp.b.id = spill_dram_rsp_bid; + end + + /////////////////////// + // User and address // + /////////////////////// + + assign spill_dram_rsp.b.user = '0; + assign spill_dram_rsp.r.user = '0; + + logic [cfg.AddrWidth-1:0] spill_dram_req_awaddr; + logic [cfg.AddrWidth-1:0] spill_dram_req_araddr; + + assign spill_dram_req_awaddr = spill_dram_req.aw.addr[cfg.AddrWidth-1:0]; + assign spill_dram_req_araddr = spill_dram_req.ar.addr[cfg.AddrWidth-1:0]; + + + /////////////////////// + // Instianciate DDR4 // + /////////////////////// + +`ifdef USE_DDR4 + + xlnx_mig_ddr4 i_dram ( + // Rst + .sys_rst (sys_rst_i), // Active high + .c0_sys_clk_i (dram_clk_i), + .c0_ddr4_aresetn (soc_resetn_i), + // Clk rst out + .c0_ddr4_ui_clk (dram_axi_clk), + .c0_ddr4_ui_clk_sync_rst (dram_rst_o), + // Axi + .c0_ddr4_s_axi_awid (spill_dram_req_awid), + .c0_ddr4_s_axi_awaddr (spill_dram_req_awaddr), + .c0_ddr4_s_axi_awlen (spill_dram_req.aw.len), + .c0_ddr4_s_axi_awsize (spill_dram_req.aw.size), + .c0_ddr4_s_axi_awburst (spill_dram_req.aw.burst), + .c0_ddr4_s_axi_awlock (spill_dram_req.aw.lock), + .c0_ddr4_s_axi_awcache (spill_dram_req.aw.cache), + .c0_ddr4_s_axi_awprot (spill_dram_req.aw.prot), + .c0_ddr4_s_axi_awqos (spill_dram_req.aw.qos), + .c0_ddr4_s_axi_awvalid (spill_dram_req.aw_valid), + .c0_ddr4_s_axi_awready (spill_dram_rsp.aw_ready), + .c0_ddr4_s_axi_wdata (spill_dram_req.w.data), + .c0_ddr4_s_axi_wstrb (spill_dram_req.w.strb), + .c0_ddr4_s_axi_wlast (spill_dram_req.w.last), + .c0_ddr4_s_axi_wvalid (spill_dram_req.w_valid), + .c0_ddr4_s_axi_wready (spill_dram_rsp.w_ready), + .c0_ddr4_s_axi_bready (spill_dram_req.b_ready), + .c0_ddr4_s_axi_bid (spill_dram_rsp_bid), + .c0_ddr4_s_axi_bresp (spill_dram_rsp.b.resp), + .c0_ddr4_s_axi_bvalid (spill_dram_rsp.b_valid), + .c0_ddr4_s_axi_arid (spill_dram_req_arid), + .c0_ddr4_s_axi_araddr (spill_dram_req_araddr), + .c0_ddr4_s_axi_arlen (spill_dram_req.ar.len), + .c0_ddr4_s_axi_arsize (spill_dram_req.ar.size), + .c0_ddr4_s_axi_arburst (spill_dram_req.ar.burst), + .c0_ddr4_s_axi_arlock (spill_dram_req.ar.lock), + .c0_ddr4_s_axi_arcache (spill_dram_req.ar.cache), + .c0_ddr4_s_axi_arprot (spill_dram_req.ar.prot), + .c0_ddr4_s_axi_arqos (spill_dram_req.ar.qos), + .c0_ddr4_s_axi_arvalid (spill_dram_req.ar_valid), + .c0_ddr4_s_axi_arready (spill_dram_rsp.ar_ready), + .c0_ddr4_s_axi_rready (spill_dram_req.r_ready), + .c0_ddr4_s_axi_rid (spill_dram_rsp_rid), + .c0_ddr4_s_axi_rdata (spill_dram_rsp.r.data), + .c0_ddr4_s_axi_rresp (spill_dram_rsp.r.resp), + .c0_ddr4_s_axi_rlast (spill_dram_rsp.r.last), + .c0_ddr4_s_axi_rvalid (spill_dram_rsp.r_valid), +`ifdef TARGET_VCU128 + // Axi ctrl + .c0_ddr4_s_axi_ctrl_awvalid('0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr ('0), + .c0_ddr4_s_axi_ctrl_wvalid ('0), + .c0_ddr4_s_axi_ctrl_wready (), + .c0_ddr4_s_axi_ctrl_wdata ('0), + .c0_ddr4_s_axi_ctrl_bvalid (), + .c0_ddr4_s_axi_ctrl_bready ('0), + .c0_ddr4_s_axi_ctrl_bresp (), + .c0_ddr4_s_axi_ctrl_arvalid('0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr ('0), + .c0_ddr4_s_axi_ctrl_rvalid (), + .c0_ddr4_s_axi_ctrl_rready ('0), + .c0_ddr4_s_axi_ctrl_rdata (), + .c0_ddr4_s_axi_ctrl_rresp (), + .c0_ddr4_interrupt (), +`endif + // Others + .c0_init_calib_complete (), // keep open + .addn_ui_clkout1 (dram_clk_o), + .dbg_clk (), + .dbg_bus (), + // Phy + .* + ); + +`endif // USE_DDR4 + + + /////////////////////// + // Instianciate DDR3 // + /////////////////////// + + +`ifdef USE_DDR3 + + xlnx_mig_7_ddr3 i_dram ( + .sys_rst (sys_rst_i), // Active high + .sys_clk_i (dram_clk_i), + .ui_clk (dram_axi_clk), + .ui_clk_sync_rst (dram_rst_o), + .mmcm_locked (), // keep open + .app_sr_req ('0), + .app_ref_req ('0), + .app_zq_req ('0), + .app_sr_active (), // keep open + .app_ref_ack (), // keep open + .app_zq_ack (), // keep open + .aresetn (soc_resetn_i), + .s_axi_awid (spill_dram_req_awid), + .s_axi_awaddr (spill_dram_req.aw.addr[29:0]), + .s_axi_awlen (spill_dram_req.aw.len), + .s_axi_awsize (spill_dram_req.aw.size), + .s_axi_awburst (spill_dram_req.aw.burst), + .s_axi_awlock (spill_dram_req.aw.lock), + .s_axi_awcache (spill_dram_req.aw.cache), + .s_axi_awprot (spill_dram_req.aw.prot), + .s_axi_awqos (spill_dram_req.aw.qos), + .s_axi_awvalid (spill_dram_req.aw_valid), + .s_axi_awready (spill_dram_rsp.aw_ready), + .s_axi_wdata (spill_dram_req.w.data), + .s_axi_wstrb (spill_dram_req.w.strb), + .s_axi_wlast (spill_dram_req.w.last), + .s_axi_wvalid (spill_dram_req.w_valid), + .s_axi_wready (spill_dram_rsp.w_ready), + .s_axi_bready (spill_dram_req.b_ready), + .s_axi_bid (spill_dram_rsp_bid), + .s_axi_bresp (spill_dram_rsp.b.resp), + .s_axi_bvalid (spill_dram_rsp.b_valid), + .s_axi_arid (spill_dram_req_arid), + .s_axi_araddr (spill_dram_req.ar.addr[29:0]), + .s_axi_arlen (spill_dram_req.ar.len), + .s_axi_arsize (spill_dram_req.ar.size), + .s_axi_arburst (spill_dram_req.ar.burst), + .s_axi_arlock (spill_dram_req.ar.lock), + .s_axi_arcache (spill_dram_req.ar.cache), + .s_axi_arprot (spill_dram_req.ar.prot), + .s_axi_arqos (spill_dram_req.ar.qos), + .s_axi_arvalid (spill_dram_req.ar_valid), + .s_axi_arready (spill_dram_rsp.ar_ready), + .s_axi_rready (spill_dram_req.r_ready), + .s_axi_rid (spill_dram_rsp_rid), + .s_axi_rdata (spill_dram_rsp.r.data), + .s_axi_rresp (spill_dram_rsp.r.resp), + .s_axi_rlast (spill_dram_rsp.r.last), + .s_axi_rvalid (spill_dram_rsp.r_valid), + .init_calib_complete(), // keep open + .device_temp (), // keep open + // Phy + .* + ); +`endif // USE_DDR3 + +endmodule diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh new file mode 100644 index 000000000..adb3988cb --- /dev/null +++ b/target/xilinx/src/phy_definitions.svh @@ -0,0 +1,93 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +`ifdef TARGET_VCU128 + `define USE_RESET + `define USE_JTAG + `define USE_JTAG_VDDGND + `define USE_DDR4 + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO +`endif + +`ifdef TARGET_GENESYS2 + `define USE_RESETN + `define USE_JTAG + `define USE_JTAG_TRSTN + `define USE_SD + `define USE_SWITCHES + `define USE_DDR3 + `define USE_FAN + `define USE_VIO +`endif + +`ifdef TARGET_ZCU102 + `define USE_RESET + `define USE_JTAG + `define USE_DDR4 + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO +`endif + +///////////////////// +// DRAM INTERFACES // +///////////////////// + +`ifdef USE_DDR4 +`define USE_DDR +`endif +`ifdef USE_DDR3 +`define USE_DDR +`endif + +`define DDR4_INTF \ + /* DDR4 intf */ \ + output c0_ddr4_reset_n, \ + output [0:0] c0_ddr4_ck_t, \ + output [0:0] c0_ddr4_ck_c, \ + output c0_ddr4_act_n, \ + output [16:0] c0_ddr4_adr, \ + output [1:0] c0_ddr4_ba, \ + output [0:0] c0_ddr4_bg, \ + output [0:0] c0_ddr4_cke, \ + output [0:0] c0_ddr4_odt, \ +`ifdef TARGET_VCU128 \ + output [1:0] c0_ddr4_cs_n, \ + inout [8:0] c0_ddr4_dm_dbi_n, \ + inout [71:0] c0_ddr4_dq, \ + inout [8:0] c0_ddr4_dqs_c, \ + inout [8:0] c0_ddr4_dqs_t, \ +`endif \ +`ifdef TARGET_ZCU102 \ + output [0:0] c0_ddr4_cs_n, \ + inout [1:0] c0_ddr4_dm_dbi_n, \ + inout [15:0] c0_ddr4_dq, \ + inout [1:0] c0_ddr4_dqs_c, \ + inout [1:0] c0_ddr4_dqs_t, \ +`endif + +`define DDR3_INTF \ + output ddr3_ck_p, \ + output ddr3_ck_n, \ + inout [31:0] ddr3_dq, \ + inout [3:0] ddr3_dqs_n, \ + inout [3:0] ddr3_dqs_p, \ + output [14:0] ddr3_addr, \ + output [2:0] ddr3_ba, \ + output ddr3_ras_n, \ + output ddr3_cas_n, \ + output ddr3_we_n, \ + output ddr3_reset_n, \ + output [0:0] ddr3_cke, \ + output [0:0] ddr3_cs_n, \ + output [3:0] ddr3_dm, \ + output [0:0] ddr3_odt, + +`define ila(__name, __signal) \ + (* dont_touch = "yes" *) (* mark_debug = "true" *) logic [$bits(__signal)-1:0] __name; \ + assign __name = __signal; diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk new file mode 100644 index 000000000..291d4a0d4 --- /dev/null +++ b/target/xilinx/xilinx.mk @@ -0,0 +1,115 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig + +CHS_XIL_DIR ?= $(CHS_ROOT)/target/xilinx +VIVADO ?= vitis-2020.2 vivado + +PROJECT ?= cheshire +ip-dir := $(CHS_XIL_DIR)/xilinx + +# Select board specific variables +ifeq ($(BOARD),vcu128) + XILINX_PART ?= xcvu37p-fsvh2892-2L-e + XILINX_BOARD ?= xilinx.com:vcu128:part0:1.0 + XILINX_PORT ?= 3232 + FPGA_PATH ?= xilinx_tcf/Xilinx/091847100638A + XILINX_HOST ?= bordcomputer + ips-names := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio + ifeq ($(INT_JTAG),1) + xilinx_targs += -t bscane + endif +endif +ifeq ($(BOARD),genesys2) + XILINX_PART ?= xc7k325tffg900-2 + XILINX_BOARD ?= digilentinc.com:genesys2:part0:1.1 + XILINX_PORT ?= 3332 + XILINX_HOST ?= bordcomputer + FPGA_PATH ?= xilinx_tcf/Digilent/200300A8C60DB + ips-names := xlnx_mig_7_ddr3 xlnx_clk_wiz xlnx_vio +endif +ifeq ($(BOARD),zcu102) + XILINX_PART ?= xczu9eg-ffvb1156-2-e + XILINX_BOARD ?= xilinx.com:zcu102:part0:3.4 + ips-names := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio +endif + +# Location of ip outputs +ips := $(addprefix $(CHS_XIL_DIR)/,$(addsuffix .xci ,$(basename $(ips-names)))) +# Derive bender args from enabled ips +xilinx_targs += -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 +xilinx_targs += $(foreach ip-name,$(ips-names),$(addprefix -t ,$(ip-name))) +xilinx_targs += $(addprefix -t ,$(BOARD)) + +# Outputs +out := $(CHS_XIL_DIR)/out +bit := $(out)/$(PROJECT)_top_xilinx.bit +mcs := $(out)/$(PROJECT)_top_xilinx.mcs + +# Vivado variables +VIVADOENV ?= PROJECT=$(PROJECT) \ + BOARD=$(BOARD) \ + XILINX_PART=$(XILINX_PART) \ + XILINX_BOARD=$(XILINX_BOARD) \ + PORT=$(XILINX_PORT) \ + HOST=$(XILINX_HOST) \ + FPGA_PATH=$(FPGA_PATH) \ + BIT=$(bit) \ + IP_PATHS="$(foreach ip-name,$(ips-names),xilinx/$(ip-name)/$(ip-name).srcs/sources_1/ip/$(ip-name)/$(ip-name).xci)" \ + ROUTED_DCP=$(ROUTED_DCP) \ + CHECK_TIMING=$(CHECK_TIMING) + +MODE ?= batch +VIVADOFLAGS ?= -nojournal -mode $(MODE) + +chs-xil-all: $(bit) + +# Generate mcs from bitstream +$(mcs): $(bit) + cd $(CHS_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ + +# Compile bitstream +$(bit): $(ips) $(CHS_XIL_DIR)/scripts/add_sources.tcl + @mkdir -p $(out) + cd $(CHS_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/prologue.tcl -source scripts/run.tcl + cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.bit $(out) + cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.ltx $(out) + cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.dcp $(out) + +# Generate ips +%.xci: + @echo $@ + @echo $(CHS_XIL_DIR) + @echo "Generating IP $(basename $@)" + IP_NAME=$(basename $(notdir $@)) ; cd $(ip-dir)/$$IP_NAME && $(MAKE) clean && $(VIVADOENV) VIVADO="$(VIVADO)" $(MAKE) + IP_NAME=$(basename $(notdir $@)) ; cp $(ip-dir)/$$IP_NAME/$$IP_NAME.srcs/sources_1/ip/$$IP_NAME/$$IP_NAME.xci $@ + +chs-xil-gui: + @echo "Starting $(vivado) GUI" + cd $(CHS_XIL_DIR) && $(VIVADOENV) $(VIVADO) -nojournal -mode gui $(PROJECT).xpr & + +chs-xil-program: #$(bit) + @echo "Programming board $(BOARD) ($(XILINX_PART))" + $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source $(CHS_XIL_DIR)/scripts/program.tcl + +chs-xil-flash: $(CHS_SW_DIR)/boot/linux-${BOARD}.gpt.bin + $(VIVADOENV) FILE=$< OFFSET=0 $(VIVADO) $(VIVADOFLAGS) -source $(CHS_XIL_DIR)/scripts/flash_spi.tcl + +chs-xil-clean: + cd $(CHS_XIL_DIR) && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).srcs $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim + +# Re-compile only top and not ips +chs-xil-rebuild-top: + ${MAKE} chs-xil-clean + find $(CHS_XIL_DIR)/xilinx -wholename "**/*.srcs/**/*.xci" | xargs -n 1 -I {} cp {} $(CHS_XIL_DIR) + ${MAKE} $(bit) + +# Bender script +$(CHS_XIL_DIR)/scripts/add_sources.tcl: Bender.yml + $(BENDER) script vivado $(xilinx_targs) > $@ + +.PHONY: chs-xil-gui chs-xil-program chs-xil-flash chs-xil-clean chs-xil-rebuild-top chs-xil-all diff --git a/target/xilinx/xilinx/common.mk b/target/xilinx/xilinx/common.mk index b75c9bfa7..457496ed9 100644 --- a/target/xilinx/xilinx/common.mk +++ b/target/xilinx/xilinx/common.mk @@ -25,3 +25,4 @@ clean: rm -rf vivado*.str rm -rf xgui rm -rf .Xil + rm -rf tmp diff --git a/target/xilinx/xilinx/xlnx_protocol_checker/Makefile b/target/xilinx/xilinx/xlnx_clk_wiz/Makefile similarity index 85% rename from target/xilinx/xilinx/xlnx_protocol_checker/Makefile rename to target/xilinx/xilinx/xlnx_clk_wiz/Makefile index f67c6a7b6..8fa393238 100644 --- a/target/xilinx/xilinx/xlnx_protocol_checker/Makefile +++ b/target/xilinx/xilinx/xlnx_clk_wiz/Makefile @@ -2,5 +2,5 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -PROJECT:=xlnx_protocol_checker +PROJECT:=xlnx_clk_wiz include ../common.mk \ No newline at end of file diff --git a/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl b/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl new file mode 100644 index 000000000..7b734a1c0 --- /dev/null +++ b/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl @@ -0,0 +1,113 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_clk_wiz + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $ipName + +if {$::env(BOARD) eq "vcu128"} { + set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.USE_RESET {true} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT2_JITTER {132.683} \ + CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT3_JITTER {162.167} \ + CONFIG.CLKOUT3_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT4_JITTER {188.586} \ + CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ + ] [get_ips $ipName] +} + +if {$::env(BOARD) eq "zcu102"} { + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {300.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {101.475} \ + CONFIG.CLKOUT1_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT2_JITTER {116.415} \ + CONFIG.CLKOUT2_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT3_JITTER {140.023} \ + CONFIG.CLKOUT3_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT4_JITTER {160.570} \ + CONFIG.CLKOUT4_PHASE_ERROR {77.836} \ + ] [get_ips $ipName] +} + +if {$::env(BOARD) eq "genesys2"} { + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {200.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {20} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {50} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {100} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {112.316} \ + CONFIG.CLKOUT1_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT2_JITTER {129.198} \ + CONFIG.CLKOUT2_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT3_JITTER {155.330} \ + CONFIG.CLKOUT3_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT4_JITTER {178.053} \ + CONFIG.CLKOUT4_PHASE_ERROR {89.971} \ + ] [get_ips $ipName] +} + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj index eca037822..3dbebfc34 100755 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj +++ b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj @@ -10,9 +10,9 @@ Enabled xc7k325t-ffg900/-2 4.1 - Differential + No Buffer Use System Clock - ACTIVE LOW + ACTIVE HIGH FALSE 0 50 Ohms @@ -116,9 +116,6 @@ - - - diff --git a/target/xilinx/xilinx/xlnx_mig_ddr4/Makefile b/target/xilinx/xilinx/xlnx_mig_ddr4/Makefile new file mode 100644 index 000000000..5624b3bf4 --- /dev/null +++ b/target/xilinx/xilinx/xlnx_mig_ddr4/Makefile @@ -0,0 +1,6 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +PROJECT:=xlnx_mig_ddr4 +include ../common.mk diff --git a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl new file mode 100644 index 000000000..aef051e47 --- /dev/null +++ b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl @@ -0,0 +1,62 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_mig_ddr4 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name $ipName + + +if {$::env(BOARD) eq "vcu128"} { + set_property -dict [list CONFIG.C0.DDR4_Clamshell {true} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.DDR4_InputClockPeriod {10000} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiIDWidth {6} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + ] [get_ips $ipName] + +} elseif {$::env(BOARD) eq "zcu102"} { + set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \ + CONFIG.C0.DDR4_DataWidth {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_AxiDataWidth {128} \ + CONFIG.C0.DDR4_AxiAddressWidth {29} \ + CONFIG.C0.DDR4_AxiIDWidth {6} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + ] [get_ips $ipName] +} + + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl b/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl deleted file mode 100644 index 2e6ebfcf1..000000000 --- a/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -set ipName xlnx_protocol_checker - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_protocol_checker -vendor xilinx.com -library ip -version 2.0 -module_name $ipName - -set_property -dict [list CONFIG.ADDR_WIDTH {48} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.AWUSER_WIDTH {1} \ - CONFIG.ARUSER_WIDTH {1} \ - CONFIG.RUSER_WIDTH {1} \ - CONFIG.WUSER_WIDTH {1} \ - CONFIG.BUSER_WIDTH {1} \ - CONFIG.MAX_AW_WAITS {1024} \ - CONFIG.MAX_AR_WAITS {1024} \ - CONFIG.MAX_W_WAITS {1024} \ - CONFIG.MAX_R_WAITS {1024} \ - CONFIG.MAX_B_WAITS {1024} \ - CONFIG.MAX_CONTINUOUS_WTRANSFERS_WAITS {1024} \ - CONFIG.MAX_WLAST_TO_AWVALID_WAITS {1024} \ - CONFIG.MAX_WRITE_TO_BVALID_WAITS {1024} \ - CONFIG.MAX_CONTINUOUS_RTRANSFERS_WAITS {1024} \ - ] [get_ips $ipName] - - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/target/xilinx/xilinx/xlnx_vio/Makefile b/target/xilinx/xilinx/xlnx_vio/Makefile new file mode 100644 index 000000000..70dcc3263 --- /dev/null +++ b/target/xilinx/xilinx/xlnx_vio/Makefile @@ -0,0 +1,6 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +PROJECT:=xlnx_vio +include ../common.mk diff --git a/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl b/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl new file mode 100644 index 000000000..4d5632369 --- /dev/null +++ b/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl @@ -0,0 +1,41 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_vio + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $ipName + +if {$::env(BOARD) eq "vcu128"} { +set_property -dict [list CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $ipName] +} elseif {$::env(BOARD) eq "genesys2"} { +set_property -dict [list CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $ipName] +} + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1