diff --git a/Bender.yml b/Bender.yml
index f9157cfd..724596e5 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -29,7 +29,7 @@ dependencies:
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             rev: d1d3135    }  # TODO: master commit; use next release once out
-  unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.1  }
+  unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.5  }
 
 export_include_dirs:
   - hw/include
diff --git a/docs/um/arch.md b/docs/um/arch.md
index f8f6ae19..01df2ff7 100644
--- a/docs/um/arch.md
+++ b/docs/um/arch.md
@@ -147,6 +147,7 @@ The internal interconnect exposes the following parameters:
 | `AxiMax(Mst|Slv)Trans`      | `shrt_bt`    | AXI4 maximum inflight transactions at crossbar    |
 | `AxiUserDefault`            | `doub_bt`    | AXI4 default user value amended by user features  |
 | `AxiUserAmo(Msb|Lsb)`       | `dw_bt`      | AXI4 user channel bit-range used by RISC-V AMOs   |
+| `AxiUserErr(Bits|Lsb)`      | `dw_bt`      | AXI4 user channel bit-range for custom errors     |
 | `RegMax(Read|Write)Txns`    | `dw_bt`      | Max. inflight transactions at Regbus AMO filter   |
 | `RegAmoNumCuts`             | `aw_bt`      | Number of timing cuts inside Regbus AMO filter    |
 | `RegAmoPostCut`             | `bit`        | Whether to insert a cut after Regbus AMO filter   |
@@ -157,7 +158,7 @@ The internal interconnect exposes the following parameters:
 
 Both the AXI4 and Regbus interconnects support exposing a limited number of external manager and subordinate ports; this is the intended mechanism through which Cheshire can be integrated with wrapping SoCs' memory systems.
 
-The parameters `AxiUserDefault` and `AxiUserAmo(Msb|Lsb)` define the AXI4 default user channel assignment and ID slice for atomics, respectively.
+The parameter `AxiUserDefault` defines the default AXI4 user signal assignment. `AxiUserAmo(Msb|Lsb)` and `AxiUserErr(Bits|Lsb)` define which bits of the user signals identify RISC-V atomics managers and communicate custom errors, respectively.
 
 The AXI4 interconnect has two optional features. `AxiRt` adds traffic regulation units to each AXI4 manager to provide bandwidth and traffic control for real-time applications. `BusErr` adds the UNBENT bus error reporter to all managers spawning requests and imprecisely reports AXI4 error responses through a Regbus-mapped interface.
 
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
index 18c53ccb..014f4ab3 100644
--- a/hw/cheshire_pkg.sv
+++ b/hw/cheshire_pkg.sv
@@ -97,6 +97,8 @@ package cheshire_pkg;
     // A '0 user signal indicates no atomics.
     dw_bt   AxiUserAmoMsb;
     dw_bt   AxiUserAmoLsb;
+    dw_bt   AxiUserErrBits;
+    dw_bt   AxiUserErrLsb;
     doub_bt AxiUserDefault; // Default user assignment, adjusted by user features (AMO)
     // Reg parameters
     dw_bt   RegMaxReadTxns;
@@ -525,6 +527,8 @@ package cheshire_pkg;
     AxiMaxSlvTrans    : 24,
     AxiUserAmoMsb     : 1, // Convention: lower AMO bits for cores, MSB for serial link
     AxiUserAmoLsb     : 0, // Convention: lower AMO bits for cores, MSB for serial link
+    AxiUserErrBits    : 0,
+    AxiUserErrLsb     : 0,
     AxiUserDefault    : 0,
     RegMaxReadTxns    : 8,
     RegMaxWriteTxns   : 8,
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index 03566135..ba1516a5 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -634,8 +634,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       axi_err_unit_wrap #(
         .AddrWidth          ( Cfg.AddrWidth ),
         .IdWidth            ( Cva6IdWidth   ),
-        .UserErrBits        ( 0 ),
-        .UserErrBitsOffset  ( 0 ),
+        .UserErrBits        ( Cfg.AxiUserErrBits ),
+        .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
         .NumOutstanding     ( Cfg.CoreMaxTxns ),
         .NumStoredErrors    ( 4 ),
         .DropOldest         ( 1'b0 ),
@@ -1447,8 +1447,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       axi_err_unit_wrap #(
         .AddrWidth          ( Cfg.AddrWidth     ),
         .IdWidth            ( Cfg.AxiMstIdWidth ),
-        .UserErrBits        ( 0 ),
-        .UserErrBitsOffset  ( 0 ),
+        .UserErrBits        ( Cfg.AxiUserErrBits ),
+        .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
         .NumOutstanding     ( Cfg.CoreMaxTxns ),
         .NumStoredErrors    ( 4 ),
         .DropOldest         ( 1'b0 ),
@@ -1619,8 +1619,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       axi_err_unit_wrap #(
         .AddrWidth          ( Cfg.AddrWidth     ),
         .IdWidth            ( Cfg.AxiMstIdWidth ),
-        .UserErrBits        ( 0 ),
-        .UserErrBitsOffset  ( 0 ),
+        .UserErrBits        ( Cfg.AxiUserErrBits ),
+        .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
         .NumOutstanding     ( Cfg.CoreMaxTxns ),
         .NumStoredErrors    ( 4 ),
         .DropOldest         ( 1'b0 ),