From 586fbd9f4c1867f8b679f2f8f1cf794e8f53f506 Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Wed, 19 Jul 2023 16:22:18 +0200 Subject: [PATCH] vip: Simplify external port connection --- target/sim/src/fixture_cheshire_soc.sv | 26 +++----- target/sim/src/vip_cheshire_soc.sv | 85 +++++++++++++++++--------- 2 files changed, 63 insertions(+), 48 deletions(-) diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index a0adc5093..71329bf0f 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -148,27 +148,17 @@ module fixture_cheshire_soc; // VIP // /////////// - AXI_BUS #( - .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), - .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), - .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ), - .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) - ) axi_unused_ext_mst (); - - assign axi_unused_ext_mst.aw_valid = '0; - assign axi_unused_ext_mst.w_valid = '0; - assign axi_unused_ext_mst.b_ready = '1; - assign axi_unused_ext_mst.ar_valid = '0; - assign axi_unused_ext_mst.r_ready = '1; + axi_mst_req_t axi_slink_mst_req; + axi_mst_rsp_t axi_slink_mst_rsp; + + assign axi_slink_ext_mst_req = '0; vip_cheshire_soc #( .DutCfg ( DutCfg ), .axi_ext_llc_req_t ( axi_llc_req_t ), - .axi_ext_llc_rsp_t ( axi_llc_rsp_t ) - ) vip ( - // The external axi driver is unconnected in cheshire - .axi_ext_mst (axi_unused_ext_mst), - .* - ); + .axi_ext_llc_rsp_t ( axi_llc_rsp_t ), + .axi_ext_mst_req_t ( axi_mst_req_t ), + .axi_ext_mst_rsp_t ( axi_mst_rsp_t ) + ) vip (.*); endmodule diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index f6098583c..1d6ec1374 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -14,6 +14,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( parameter cheshire_cfg_t DutCfg = '0, parameter type axi_ext_llc_req_t = logic, parameter type axi_ext_llc_rsp_t = logic, + parameter type axi_ext_mst_req_t = logic, + parameter type axi_ext_mst_rsp_t = logic, // Timing parameter time ClkPeriodSys = 5ns, parameter time ClkPeriodJtag = 20ns, @@ -31,6 +33,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( parameter int unsigned SlinkMaxWaitR = 5, parameter int unsigned SlinkMaxWaitResp = 20, parameter int unsigned SlinkBurstBytes = 1024, + parameter int unsigned SlinkMaxTxns = 32, + parameter int unsigned SlinkMaxTxnsPerId = 16, parameter bit SlinkAxiDebug = 0, // Derived Parameters; *do not override* parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth/8, @@ -44,8 +48,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // External AXI LLC (DRAM) port input axi_ext_llc_req_t axi_llc_mst_req, output axi_ext_llc_rsp_t axi_llc_mst_rsp, - // External virtual AXI ports - AXI_BUS.Slave axi_ext_mst, + // External serial link AXI port + input axi_ext_mst_req_t axi_slink_mst_req, + output axi_ext_mst_rsp_t axi_slink_mst_rsp, // JTAG interface output logic jtag_tck, output logic jtag_trst_n, @@ -549,31 +554,28 @@ module vip_cheshire_soc import cheshire_pkg::*; #( axi_mst_req_t slink_axi_mst_req, slink_axi_slv_req; axi_mst_rsp_t slink_axi_mst_rsp, slink_axi_slv_rsp; - // AXI driver port AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), - .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), - .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ), - .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) - ) axi_drv_mst_dv ( + .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), + .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), + .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ), + .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) + ) slink_mst_vip_dv ( .clk_i ( clk ) ); - AXI_BUS #( - .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), - .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), - .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ), - .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) - ) axi_drv_mst (); - - `AXI_ASSIGN (axi_drv_mst, axi_drv_mst_dv) - AXI_BUS #( .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ), .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) - ) slink_mst(); + ) slink_mst_ext(), slink_mst_vip(), slink_mst(); + + AXI_BUS #( + .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), + .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), + .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ), + .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) + ) slink_mst_mux(); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), @@ -584,16 +586,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .clk_i ( clk ) ); - `AXI_ASSIGN_TO_REQ(slink_axi_mst_req, slink_mst) - `AXI_ASSIGN_FROM_RESP(slink_mst, slink_axi_mst_rsp) - - `AXI_ASSIGN_FROM_REQ(slink_slv, slink_axi_slv_req) - `AXI_ASSIGN_TO_RESP(slink_axi_slv_rsp, slink_slv) - // Multiplex internal and external AXI requests axi_mux_intf #( - .SLV_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth-1 ), - .MST_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ), + .SLV_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ), + .MST_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ), .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ), @@ -602,10 +598,39 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .clk_i ( clk ), .rst_ni ( rst_n ), .test_i ( '0 ), - .slv ( {axi_drv_mst, axi_ext_mst} ), - .mst ( slink_mst ) + .slv ( '{slink_mst_vip, slink_mst_ext} ), + .mst ( slink_mst_mux ) + ); + + // Serialize away added AXI index bits + axi_id_serialize_intf #( + .AXI_SLV_PORT_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ), + .AXI_SLV_PORT_MAX_TXNS ( SlinkMaxTxns ), + .AXI_MST_PORT_ID_WIDTH ( DutCfg.AxiMstIdWidth ), + .AXI_MST_PORT_MAX_UNIQ_IDS ( 2**DutCfg.AxiMstIdWidth ), + .AXI_MST_PORT_MAX_TXNS_PER_ID ( SlinkMaxTxnsPerId ), + .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), + .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), + .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) + ) i_axi_id_serialize_slink ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .slv ( slink_mst_mux ), + .mst ( slink_mst ) ); + `AXI_ASSIGN (slink_mst_vip, slink_mst_vip_dv) + + `AXI_ASSIGN_FROM_REQ(slink_mst_ext, axi_slink_mst_req) + `AXI_ASSIGN_TO_RESP(axi_slink_mst_rsp, slink_mst_ext) + + `AXI_ASSIGN_TO_REQ(slink_axi_mst_req, slink_mst) + `AXI_ASSIGN_FROM_RESP(slink_mst, slink_axi_mst_rsp) + + `AXI_ASSIGN_FROM_REQ(slink_slv, slink_axi_slv_req) + `AXI_ASSIGN_TO_RESP(slink_axi_slv_rsp, slink_slv) + + // Mirror instance of serial link, reflecting another chip serial_link #( .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), @@ -671,13 +696,13 @@ module vip_cheshire_soc import cheshire_pkg::*; #( typedef axi_test::axi_driver #( .AW ( DutCfg.AddrWidth ), .DW ( DutCfg.AxiDataWidth ), - .IW ( DutCfg.AxiMstIdWidth-1 ), + .IW ( DutCfg.AxiMstIdWidth ), .UW ( DutCfg.AxiUserWidth ), .TA ( ClkPeriodSys * TAppl ), .TT ( ClkPeriodSys * TTest ) ) slink_axi_driver_t; - slink_axi_driver_t slink_axi_driver = new (axi_drv_mst_dv); + slink_axi_driver_t slink_axi_driver = new (slink_mst_vip_dv); initial begin @(negedge rst_n);