diff --git a/Bender.lock b/Bender.lock
index 3da77531..ef8a4a6d 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -162,7 +162,7 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp-ethernet:
-    revision: bf5fc0055a4d3258361e38ee977566fa312570f0
+    revision: 28fd13f7887c9bf0e9548b56a8706378c9cc01cd
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp-ethernet.git
diff --git a/Bender.yml b/Bender.yml
index 32c29e56..71f1f2af 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -23,14 +23,14 @@ dependencies:
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
   cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1.0.0 }
-  iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.2  }
+  iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.0  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
   register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.3  }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
-  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "bf5fc00"  } # branch: cl/eth_idma
+  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "28fd13f"  } # branch: cl/eth_idma
 
 export_include_dirs:
   - hw/include
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index 973d4366..cfccb3b4 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -29,6 +29,7 @@ module cheshire_soc import cheshire_pkg::*; #(
   input  logic [1:0]  boot_mode_i,
   input  logic        rtc_i,
   input  logic        eth_clk125_i,
+  input  logic        eth_clk125q_i,
   input  logic        eth_clk200_i,
   // External AXI LLC (DRAM) port
   output axi_ext_llc_req_t axi_llc_mst_req_o,
@@ -1312,7 +1313,8 @@ module cheshire_soc import cheshire_pkg::*; #(
     ) i_tx_eth_idma_wrap (
       .clk_i,
       .rst_ni, 
-      .eth_clk_i           ( eth_clk125_i ),
+      .eth_clk125_i        ( eth_clk125_i ),
+      .eth_clk125q_i       ( eth_clk125q_i),
       .eth_clk200_i        ( eth_clk200_i ),
       .phy_rx_clk_i        ( eth_rxck_i   ),
       .phy_rxd_i           ( eth_rxd_i    ),
diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv
index 27a5ef11..8124f494 100644
--- a/target/sim/src/fixture_cheshire_soc.sv
+++ b/target/sim/src/fixture_cheshire_soc.sv
@@ -49,7 +49,8 @@ module fixture_cheshire_soc #(
   logic i2c_scl_i;
   logic i2c_scl_en;
 
-  logic       eth_clk_125;
+  logic       eth_clk125;
+  logic       eth_clk125q;
   logic       eth_rxck;
   logic [3:0] eth_rxd;
   logic       eth_rxctl;
@@ -128,7 +129,8 @@ module fixture_cheshire_soc #(
     .i2c_scl_o          ( i2c_scl_o  ),
     .i2c_scl_i          ( i2c_scl_i  ),
     .i2c_scl_en_o       ( i2c_scl_en ),
-    .eth_clk125_i       ( eth_clk_125 ),
+    .eth_clk125_i       ( eth_clk125  ),
+    .eth_clk125q_i      ( eth_clk125q ),
     .eth_rxck_i         ( eth_rxck    ),
     .eth_rxd_i          ( eth_rxd     ),
     .eth_rxctl_i        ( eth_rxctl   ),
diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
index 823e5bee..76685f5f 100644
--- a/target/sim/src/vip_cheshire_soc.sv
+++ b/target/sim/src/vip_cheshire_soc.sv
@@ -21,7 +21,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   parameter time          ClkPeriodSys      = 5ns,
   parameter time          ClkPeriodJtag     = 20ns,
   parameter time          ClkPeriodRtc      = 30518ns,
-  parameter time          ClkPeriodEth125   = 8ns,
+  parameter time          ClkPeriodEth      = 8ns,
   parameter int unsigned  RstCycles         = 5,
   parameter real          TAppl             = 0.1,
   parameter real          TTest             = 0.9,
@@ -70,7 +70,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   inout  wire [SpihNumCs-1:0] spih_csb,
   inout  wire [ 3:0]          spih_sd,
   // Ethernet interface
-  output logic                eth_clk_125,
+  output logic                eth_clk125,
+  output logic                eth_clk125q,
   input  logic [ 3:0]         eth_txd,
   output logic [ 3:0]         eth_rxd,
   input  logic                eth_txck,
@@ -653,7 +654,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   ) i_rx_eth_idma_wrap (
     .clk_i               ( clk             ),
     .rst_ni              ( rst_n           ),  
-    .eth_clk_i           ( eth_clk_125     ),
+    .eth_clk125_i        ( eth_clk125      ),
+    .eth_clk125q_i       ( eth_clk125q     ),
     .phy_rx_clk_i        ( eth_txck        ),
     .phy_rxd_i           ( eth_txd         ),
     .phy_rx_ctl_i        ( eth_txctl       ),
@@ -709,10 +711,21 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   
   initial begin
     forever begin
-    eth_clk_125 <= 0;
-    #(ClkPeriodEth125/2);
-    eth_clk_125 <= 1;
-    #(ClkPeriodEth125/2);
+    eth_clk125 <= 1;
+    #(ClkPeriodEth/2);
+    eth_clk125 <= 0;
+    #(ClkPeriodEth/2);
+    end
+  end
+
+  initial begin
+    forever begin
+    eth_clk125q <= 0;
+    #(ClkPeriodEth/4);
+    eth_clk125q <= 1;
+    #(ClkPeriodEth/2);
+    eth_clk125q <= 0;
+    #(ClkPeriodEth/4);
     end
   end