diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc
index 0e9295d97..ae0350653 100644
--- a/target/xilinx/constraints/cheshire.xdc
+++ b/target/xilinx/constraints/cheshire.xdc
@@ -20,11 +20,8 @@ set UART_IO_SPEED 200.0
# Clocks #
##########
-# Clk_wiz clocks
-create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10]
-create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20]
-create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50]
-create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100]
+# Clk_wiz clocks are named clk_(100,50,20,10)_xlnx_clk_wiz
+# They are on pins : i_xlnx_clk_wiz/inst/mmcme4_adv_inst/CLKOUT(0,1,2,3)
# System Clock
# [see in board.xdc]
@@ -85,6 +82,8 @@ set_false_path -hold -to [get_ports uart_tx_o]
# Disable hold checks
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}]
+
# src false path
set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}]
# dst false path
diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc
index f90529734..a55db78d3 100644
--- a/target/xilinx/constraints/vcu128.xdc
+++ b/target/xilinx/constraints/vcu128.xdc
@@ -10,19 +10,22 @@
set SYS_TCK 10
create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
-set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
#############
# Mig clock #
#############
-# Dram axi clock : 833ps * 4
-set MIG_TCK 3.332
-set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
-create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
-set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk}
-set_false_path -hold -through $MIG_RST
-set_max_delay -through $MIG_RST $MIG_TCK
+# Dram axi clock : 750ps * 4
+set MIG_TCK 3
+create_generated_clock -source [get_pins i_dram_wrapper/i_dram/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0] \
+ -divide_by 1 -add -master_clock mmcm_clkout0 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+# Aynch reset in
+set MIG_RST_I [get_pin i_dram_wrapper/i_dram/inst/c0_ddr4_aresetn]
+set_false_path -hold -setup -through $MIG_RST_I
+# Synch reset out
+set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+set_false_path -hold -through $MIG_RST_O
+set_max_delay -through $MIG_RST_O $MIG_TCK
########
# CDCs #
diff --git a/target/xilinx/src/dram_wrapper.sv b/target/xilinx/src/dram_wrapper.sv
index 5af529a23..4c7de91e9 100644
--- a/target/xilinx/src/dram_wrapper.sv
+++ b/target/xilinx/src/dram_wrapper.sv
@@ -41,10 +41,7 @@ module dram_wrapper #(
////////////////////////////////////
typedef struct packed {
- bit EnSpill0;
- bit EnResizer;
bit EnCDC;
- bit EnSpill1;
integer IdWidth;
integer AddrWidth;
integer DataWidth;
@@ -53,11 +50,8 @@ module dram_wrapper #(
`ifdef TARGET_VCU128
localparam dram_cfg_t cfg = '{
- EnSpill0 : 1,
- EnResizer : 1,
- EnCDC : 1, // 333 MHz axi
- EnSpill1 : 1,
- IdWidth : 6,
+ EnCDC : 1, // 333 MHz axi (attention CDC logdepth)
+ IdWidth : 4,
AddrWidth : 32,
DataWidth : 512,
StrobeWidth : 64
@@ -66,11 +60,8 @@ module dram_wrapper #(
`ifdef TARGET_ZCU102
localparam dram_cfg_t cfg = '{
- EnSpill0 : 1,
- EnResizer : 1,
- EnCDC : 1, // ??? MHz axi
- EnSpill1 : 1,
- IdWidth : 6,
+ EnCDC : 1, // ??? MHz axi (attention CDC logdepth)
+ IdWidth : 4,
AddrWidth : 29,
DataWidth : 128,
StrobeWidth : 16
@@ -79,106 +70,118 @@ module dram_wrapper #(
`ifdef TARGET_GENESYS2
localparam dram_cfg_t cfg = '{
- EnSpill0 : 1,
- EnResizer : 0,
- EnCDC : 1, // 200 MHz axi
- EnSpill1 : 1,
- IdWidth : 6,
+ EnCDC : 1, // 200 MHz axi (attention CDC logdepth)
+ IdWidth : 4,
AddrWidth : 30,
DataWidth : 64,
StrobeWidth : 8
};
`endif
- // Define type after resizer (DRAM AXI)
- `AXI_TYPEDEF_ALL(axi_ddr, logic[$bits(soc_req_i.ar.addr)-1:0], logic[$bits(soc_req_i.ar.id)-1:0],
+ localparam SoC_DataWidth = $bits(soc_req_i.w.data);
+ localparam SoC_IdWidth = $bits(soc_req_i.ar.id);
+ localparam SoC_UserWidth = $bits(soc_req_i.ar.user);
+ localparam SoC_AddrWidth = $bits(soc_req_i.ar.addr);
+
+ // Define type after data width and address resizer
+ `AXI_TYPEDEF_ALL(axi_dw, logic[SoC_AddrWidth-1:0], logic[SoC_IdWidth-1:0],
+ logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0],
+ logic[SoC_UserWidth-1:0])
+
+ // Define type after data & id width resizers
+ `AXI_TYPEDEF_ALL(axi_dw_iw, logic[SoC_AddrWidth-1:0], logic[cfg.IdWidth-1:0],
logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0],
- logic[$bits(soc_req_i.ar.user)-1:0])
+ logic[SoC_UserWidth-1:0])
// Clock on which is clocked the DRAM AXI
logic dram_axi_clk, dram_rst_o;
// Signals before resizing
- axi_soc_req_t soc_spill_req, spill_resizer_req;
- axi_soc_resp_t soc_spill_rsp, spill_resizer_rsp;
+ axi_soc_req_t soc_dresizer_req;
+ axi_soc_resp_t soc_dresizer_rsp;
- // Signals after resizing
- axi_ddr_req_t resizer_cdc_req, cdc_spill_req;
- axi_ddr_req_t spill_dram_req;
- axi_ddr_resp_t resizer_cdc_rsp, cdc_spill_rsp;
- axi_ddr_resp_t spill_dram_rsp;
+ // Signals after data width resizing
+ axi_dw_req_t dresizer_iresizer_req;
+ axi_dw_resp_t dresizer_iresizer_rsp;
+
+ // Signals after id width resizing
+ axi_dw_iw_req_t iresizer_cdc_req, cdc_dram_req;
+ axi_dw_iw_resp_t iresizer_cdc_rsp, cdc_dram_rsp;
// Entry signals
- assign soc_spill_req = soc_req_i;
- assign soc_rsp_o = soc_spill_rsp;
-
- //////////////////////////
- // Instianciate Spill 0 //
- //////////////////////////
-
- if (cfg.EnSpill0) begin : gen_spill_0
- // AXI CUT (spill register) between the AXI CDC and the MIG to
- // reduce timing pressure
- axi_cut #(
- .Bypass (1'b0),
- .aw_chan_t (axi_soc_aw_chan_t),
- .w_chan_t (axi_soc_w_chan_t),
- .b_chan_t (axi_soc_b_chan_t),
- .ar_chan_t (axi_soc_ar_chan_t),
- .r_chan_t (axi_soc_r_chan_t),
- .axi_req_t (axi_soc_req_t),
- .axi_resp_t(axi_soc_resp_t)
- ) i_axi_cut_soc_dram (
- .clk_i (soc_clk_i),
- .rst_ni(soc_resetn_i),
- .slv_req_i (soc_spill_req),
- .slv_resp_o(soc_spill_rsp),
- .mst_req_o (spill_resizer_req),
- .mst_resp_i(spill_resizer_rsp)
- );
- end else begin : gen_no_spill_0
- assign spill_resizer_req = soc_spill_req;
- assign soc_spill_rsp = spill_resizer_rsp;
- end
+ assign soc_dresizer_req = soc_req_i;
+ assign soc_rsp_o = soc_dresizer_rsp;
/////////////////////////////////////
// Instianciate data width resizer //
/////////////////////////////////////
- if (cfg.EnResizer) begin : gen_dw_converter
+ if (cfg.DataWidth != SoC_DataWidth) begin : gen_dw_converter
axi_dw_converter #(
.AxiMaxReads (8),
- .AxiSlvPortDataWidth($bits(spill_resizer_req.w.data)),
- .AxiMstPortDataWidth($bits(resizer_cdc_req.w.data)),
- .AxiAddrWidth ($bits(spill_resizer_req.ar.addr)),
- .AxiIdWidth ($bits(spill_resizer_req.ar.id)),
+ .AxiSlvPortDataWidth(SoC_DataWidth),
+ .AxiMstPortDataWidth(cfg.DataWidth),
+ .AxiAddrWidth (SoC_AddrWidth),
+ .AxiIdWidth (SoC_IdWidth ),
// Common aw, ar, b
.aw_chan_t (axi_soc_aw_chan_t),
.b_chan_t (axi_soc_b_chan_t),
.ar_chan_t (axi_soc_ar_chan_t),
// Master w, r
- .mst_w_chan_t (axi_ddr_w_chan_t),
- .mst_r_chan_t (axi_ddr_r_chan_t),
- .axi_mst_req_t (axi_ddr_req_t),
- .axi_mst_resp_t (axi_ddr_resp_t),
+ .mst_w_chan_t (axi_dw_w_chan_t),
+ .mst_r_chan_t (axi_dw_r_chan_t),
+ .axi_mst_req_t (axi_dw_req_t),
+ .axi_mst_resp_t (axi_dw_resp_t),
// Slave w, r
.slv_w_chan_t (axi_soc_w_chan_t),
.slv_r_chan_t (axi_soc_r_chan_t),
.axi_slv_req_t (axi_soc_req_t),
.axi_slv_resp_t (axi_soc_resp_t)
) axi_dw_converter_ddr4 (
- .clk_i(soc_clk_i),
- .rst_ni(soc_resetn_i),
- .slv_req_i(spill_resizer_req),
- .slv_resp_o(spill_resizer_rsp),
- .mst_req_o(resizer_cdc_req),
- .mst_resp_i(resizer_cdc_rsp)
+ .clk_i (soc_clk_i),
+ .rst_ni (soc_resetn_i),
+ .slv_req_i (soc_dresizer_req),
+ .slv_resp_o(soc_dresizer_rsp),
+ .mst_req_o (dresizer_iresizer_req),
+ .mst_resp_i(dresizer_iresizer_rsp)
);
end else begin : gen_no_dw_converter
- assign resizer_cdc_req = spill_resizer_req;
- assign spill_resizer_rsp = resizer_cdc_rsp;
+ assign dresizer_iresizer_req = soc_dresizer_req;
+ assign soc_dresizer_rsp = dresizer_iresizer_rsp;
end
+ /////////////////
+ // ID resizer //
+ /////////////////
+
+if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter
+ axi_iw_converter #(
+ .AxiAddrWidth ( SoC_AddrWidth ),
+ .AxiDataWidth ( cfg.DataWidth ),
+ .AxiUserWidth ( SoC_UserWidth ),
+ .AxiSlvPortIdWidth ( SoC_IdWidth ),
+ .AxiSlvPortMaxUniqIds ( 1 ),
+ .AxiSlvPortMaxTxnsPerId( 1 ),
+ .AxiSlvPortMaxTxns ( 1 ),
+ .AxiMstPortIdWidth ( cfg.IdWidth ),
+ .AxiMstPortMaxUniqIds ( 1 ),
+ .AxiMstPortMaxTxnsPerId( 1 ),
+ .slv_req_t ( axi_dw_req_t ),
+ .slv_resp_t ( axi_dw_resp_t ),
+ .mst_req_t ( axi_dw_iw_req_t ),
+ .mst_resp_t ( axi_dw_iw_resp_t )
+ ) i_axi_iw_convert (
+ .clk_i ( soc_clk_i ),
+ .rst_ni ( soc_resetn_i ),
+ .slv_req_i ( dresizer_iresizer_req ),
+ .slv_resp_o ( dresizer_iresizer_rsp ),
+ .mst_req_o ( iresizer_cdc_req ),
+ .mst_resp_i ( iresizer_cdc_rsp )
+ );
+ end else begin : gen_no_iw_converter
+ assign iresizer_cdc_req = dresizer_iresizer_req;
+ assign dresizer_iresizer_rsp = iresizer_cdc_rsp;
+ end
//////////////////////
// Instianciate CDC //
@@ -186,97 +189,41 @@ module dram_wrapper #(
if (cfg.EnCDC) begin : gen_cdc
axi_cdc #(
- .aw_chan_t (axi_ddr_aw_chan_t),
- .w_chan_t (axi_ddr_w_chan_t),
- .b_chan_t (axi_ddr_b_chan_t),
- .ar_chan_t (axi_ddr_ar_chan_t),
- .r_chan_t (axi_ddr_r_chan_t),
- .axi_req_t (axi_ddr_req_t),
- .axi_resp_t(axi_ddr_resp_t),
- .LogDepth (3)
+ .aw_chan_t (axi_dw_iw_aw_chan_t),
+ .w_chan_t (axi_dw_iw_w_chan_t),
+ .b_chan_t (axi_dw_iw_b_chan_t),
+ .ar_chan_t (axi_dw_iw_ar_chan_t),
+ .r_chan_t (axi_dw_iw_r_chan_t),
+ .axi_req_t (axi_dw_iw_req_t),
+ .axi_resp_t(axi_dw_iw_resp_t),
+ .LogDepth (4)
) i_axi_cdc_mig (
.src_clk_i (soc_clk_i),
.src_rst_ni(soc_resetn_i),
- .src_req_i (resizer_cdc_req),
- .src_resp_o(resizer_cdc_rsp),
+ .src_req_i (iresizer_cdc_req),
+ .src_resp_o(iresizer_cdc_rsp),
.dst_clk_i (dram_axi_clk),
.dst_rst_ni(~dram_rst_o),
- .dst_req_o (cdc_spill_req),
- .dst_resp_i(cdc_spill_rsp)
+ .dst_req_o (cdc_dram_req),
+ .dst_resp_i(cdc_dram_rsp)
);
end else begin : gen_no_cdc
- assign cdc_spill_req = resizer_cdc_req;
- assign resizer_cdc_rsp = cdc_spill_rsp;
- end
-
- //////////////////////////
- // Instianciate Spill 1 //
- //////////////////////////
-
- if (cfg.EnSpill1) begin : gen_spill_1
- axi_cut #(
- .Bypass (1'b0),
- .aw_chan_t (axi_ddr_aw_chan_t),
- .w_chan_t (axi_ddr_w_chan_t),
- .b_chan_t (axi_ddr_b_chan_t),
- .ar_chan_t (axi_ddr_ar_chan_t),
- .r_chan_t (axi_ddr_r_chan_t),
- .axi_req_t (axi_ddr_req_t),
- .axi_resp_t(axi_ddr_resp_t)
- ) i_axi_cut_dw_dram (
- .clk_i (dram_axi_clk),
- .rst_ni(~dram_rst_o),
- .slv_req_i (cdc_spill_req),
- .slv_resp_o(cdc_spill_rsp),
- .mst_req_o (spill_dram_req),
- .mst_resp_i(spill_dram_rsp)
- );
- end else begin : gen_no_spill_1
- assign spill_dram_req = cdc_spill_req;
- assign cdc_spill_rsp = spill_dram_rsp;
- end
-
- /////////////////
- // ID resizer //
- /////////////////
-
- // Padding when SoC id > DDR id
- localparam IdPadding = $bits(spill_dram_req.aw.id) - cfg.IdWidth;
-
- // Resize awid and arid before sending to the DDR
- logic [cfg.IdWidth-1:0] spill_dram_req_awid, spill_dram_rsp_bid;
- logic [cfg.IdWidth-1:0] spill_dram_req_arid, spill_dram_rsp_rid;
- // Registers to prepare bid and rid
- logic [$bits(spill_dram_req.aw.id)-1:0] spill_dram_rsp_bid_d, spill_dram_rsp_bid_q;
- logic [$bits(spill_dram_req.ar.id)-1:0] spill_dram_rsp_rid_d, spill_dram_rsp_rid_q;
- `FFAR(spill_dram_rsp_bid_q, spill_dram_rsp_bid_d, '0, dram_axi_clk, dram_rst_o);
- `FFAR(spill_dram_rsp_rid_q, spill_dram_rsp_rid_d, '0, dram_axi_clk, dram_rst_o);
-
- // Process ids
- if (IdPadding > 0) begin : gen_downsize_ids
- // NOT SUPPORTED
- do_not_enter_here i_error();
-
- end else begin : gen_upsize_ids
- // Forward arid awid rid bid to and from DDR
- assign spill_dram_req_arid = {{-IdPadding{1'b0}}, spill_dram_req.ar.id};
- assign spill_dram_req_awid = {{-IdPadding{1'b0}}, spill_dram_req.aw.id};
- assign spill_dram_rsp.r.id = spill_dram_rsp_rid;
- assign spill_dram_rsp.b.id = spill_dram_rsp_bid;
+ assign cdc_dram_req = iresizer_cdc_req;
+ assign iresizer_cdc_rsp = cdc_dram_rsp;
end
///////////////////////
// User and address //
///////////////////////
- assign spill_dram_rsp.b.user = '0;
- assign spill_dram_rsp.r.user = '0;
+ assign cdc_dram_rsp.b.user = '0;
+ assign cdc_dram_rsp.r.user = '0;
- logic [cfg.AddrWidth-1:0] spill_dram_req_awaddr;
- logic [cfg.AddrWidth-1:0] spill_dram_req_araddr;
+ logic [cfg.AddrWidth-1:0] cdc_dram_req_aw_addr;
+ logic [cfg.AddrWidth-1:0] cdc_dram_req_ar_addr;
- assign spill_dram_req_awaddr = spill_dram_req.aw.addr[cfg.AddrWidth-1:0];
- assign spill_dram_req_araddr = spill_dram_req.ar.addr[cfg.AddrWidth-1:0];
+ assign cdc_dram_req_aw_addr = cdc_dram_req.aw.addr[cfg.AddrWidth-1:0];
+ assign cdc_dram_req_ar_addr = cdc_dram_req.ar.addr[cfg.AddrWidth-1:0];
///////////////////////
@@ -294,43 +241,43 @@ module dram_wrapper #(
.c0_ddr4_ui_clk (dram_axi_clk),
.c0_ddr4_ui_clk_sync_rst (dram_rst_o),
// Axi
- .c0_ddr4_s_axi_awid (spill_dram_req_awid),
- .c0_ddr4_s_axi_awaddr (spill_dram_req_awaddr),
- .c0_ddr4_s_axi_awlen (spill_dram_req.aw.len),
- .c0_ddr4_s_axi_awsize (spill_dram_req.aw.size),
- .c0_ddr4_s_axi_awburst (spill_dram_req.aw.burst),
- .c0_ddr4_s_axi_awlock (spill_dram_req.aw.lock),
- .c0_ddr4_s_axi_awcache (spill_dram_req.aw.cache),
- .c0_ddr4_s_axi_awprot (spill_dram_req.aw.prot),
- .c0_ddr4_s_axi_awqos (spill_dram_req.aw.qos),
- .c0_ddr4_s_axi_awvalid (spill_dram_req.aw_valid),
- .c0_ddr4_s_axi_awready (spill_dram_rsp.aw_ready),
- .c0_ddr4_s_axi_wdata (spill_dram_req.w.data),
- .c0_ddr4_s_axi_wstrb (spill_dram_req.w.strb),
- .c0_ddr4_s_axi_wlast (spill_dram_req.w.last),
- .c0_ddr4_s_axi_wvalid (spill_dram_req.w_valid),
- .c0_ddr4_s_axi_wready (spill_dram_rsp.w_ready),
- .c0_ddr4_s_axi_bready (spill_dram_req.b_ready),
- .c0_ddr4_s_axi_bid (spill_dram_rsp_bid),
- .c0_ddr4_s_axi_bresp (spill_dram_rsp.b.resp),
- .c0_ddr4_s_axi_bvalid (spill_dram_rsp.b_valid),
- .c0_ddr4_s_axi_arid (spill_dram_req_arid),
- .c0_ddr4_s_axi_araddr (spill_dram_req_araddr),
- .c0_ddr4_s_axi_arlen (spill_dram_req.ar.len),
- .c0_ddr4_s_axi_arsize (spill_dram_req.ar.size),
- .c0_ddr4_s_axi_arburst (spill_dram_req.ar.burst),
- .c0_ddr4_s_axi_arlock (spill_dram_req.ar.lock),
- .c0_ddr4_s_axi_arcache (spill_dram_req.ar.cache),
- .c0_ddr4_s_axi_arprot (spill_dram_req.ar.prot),
- .c0_ddr4_s_axi_arqos (spill_dram_req.ar.qos),
- .c0_ddr4_s_axi_arvalid (spill_dram_req.ar_valid),
- .c0_ddr4_s_axi_arready (spill_dram_rsp.ar_ready),
- .c0_ddr4_s_axi_rready (spill_dram_req.r_ready),
- .c0_ddr4_s_axi_rid (spill_dram_rsp_rid),
- .c0_ddr4_s_axi_rdata (spill_dram_rsp.r.data),
- .c0_ddr4_s_axi_rresp (spill_dram_rsp.r.resp),
- .c0_ddr4_s_axi_rlast (spill_dram_rsp.r.last),
- .c0_ddr4_s_axi_rvalid (spill_dram_rsp.r_valid),
+ .c0_ddr4_s_axi_awid (cdc_dram_req.aw.id),
+ .c0_ddr4_s_axi_awaddr (cdc_dram_req_aw_addr),
+ .c0_ddr4_s_axi_awlen (cdc_dram_req.aw.len),
+ .c0_ddr4_s_axi_awsize (cdc_dram_req.aw.size),
+ .c0_ddr4_s_axi_awburst (cdc_dram_req.aw.burst),
+ .c0_ddr4_s_axi_awlock (cdc_dram_req.aw.lock),
+ .c0_ddr4_s_axi_awcache (cdc_dram_req.aw.cache),
+ .c0_ddr4_s_axi_awprot (cdc_dram_req.aw.prot),
+ .c0_ddr4_s_axi_awqos (cdc_dram_req.aw.qos),
+ .c0_ddr4_s_axi_awvalid (cdc_dram_req.aw_valid),
+ .c0_ddr4_s_axi_awready (cdc_dram_rsp.aw_ready),
+ .c0_ddr4_s_axi_wdata (cdc_dram_req.w.data),
+ .c0_ddr4_s_axi_wstrb (cdc_dram_req.w.strb),
+ .c0_ddr4_s_axi_wlast (cdc_dram_req.w.last),
+ .c0_ddr4_s_axi_wvalid (cdc_dram_req.w_valid),
+ .c0_ddr4_s_axi_wready (cdc_dram_rsp.w_ready),
+ .c0_ddr4_s_axi_bready (cdc_dram_req.b_ready),
+ .c0_ddr4_s_axi_bid (cdc_dram_rsp.b.id),
+ .c0_ddr4_s_axi_bresp (cdc_dram_rsp.b.resp),
+ .c0_ddr4_s_axi_bvalid (cdc_dram_rsp.b_valid),
+ .c0_ddr4_s_axi_arid (cdc_dram_req.ar.id),
+ .c0_ddr4_s_axi_araddr (cdc_dram_req_ar_addr),
+ .c0_ddr4_s_axi_arlen (cdc_dram_req.ar.len),
+ .c0_ddr4_s_axi_arsize (cdc_dram_req.ar.size),
+ .c0_ddr4_s_axi_arburst (cdc_dram_req.ar.burst),
+ .c0_ddr4_s_axi_arlock (cdc_dram_req.ar.lock),
+ .c0_ddr4_s_axi_arcache (cdc_dram_req.ar.cache),
+ .c0_ddr4_s_axi_arprot (cdc_dram_req.ar.prot),
+ .c0_ddr4_s_axi_arqos (cdc_dram_req.ar.qos),
+ .c0_ddr4_s_axi_arvalid (cdc_dram_req.ar_valid),
+ .c0_ddr4_s_axi_arready (cdc_dram_rsp.ar_ready),
+ .c0_ddr4_s_axi_rready (cdc_dram_req.r_ready),
+ .c0_ddr4_s_axi_rid (cdc_dram_rsp.r.id),
+ .c0_ddr4_s_axi_rdata (cdc_dram_rsp.r.data),
+ .c0_ddr4_s_axi_rresp (cdc_dram_rsp.r.resp),
+ .c0_ddr4_s_axi_rlast (cdc_dram_rsp.r.last),
+ .c0_ddr4_s_axi_rvalid (cdc_dram_rsp.r_valid),
`ifdef TARGET_VCU128
// Axi ctrl
.c0_ddr4_s_axi_ctrl_awvalid('0),
@@ -383,43 +330,43 @@ module dram_wrapper #(
.app_ref_ack (), // keep open
.app_zq_ack (), // keep open
.aresetn (soc_resetn_i),
- .s_axi_awid (spill_dram_req_awid),
- .s_axi_awaddr (spill_dram_req.aw.addr[29:0]),
- .s_axi_awlen (spill_dram_req.aw.len),
- .s_axi_awsize (spill_dram_req.aw.size),
- .s_axi_awburst (spill_dram_req.aw.burst),
- .s_axi_awlock (spill_dram_req.aw.lock),
- .s_axi_awcache (spill_dram_req.aw.cache),
- .s_axi_awprot (spill_dram_req.aw.prot),
- .s_axi_awqos (spill_dram_req.aw.qos),
- .s_axi_awvalid (spill_dram_req.aw_valid),
- .s_axi_awready (spill_dram_rsp.aw_ready),
- .s_axi_wdata (spill_dram_req.w.data),
- .s_axi_wstrb (spill_dram_req.w.strb),
- .s_axi_wlast (spill_dram_req.w.last),
- .s_axi_wvalid (spill_dram_req.w_valid),
- .s_axi_wready (spill_dram_rsp.w_ready),
- .s_axi_bready (spill_dram_req.b_ready),
- .s_axi_bid (spill_dram_rsp_bid),
- .s_axi_bresp (spill_dram_rsp.b.resp),
- .s_axi_bvalid (spill_dram_rsp.b_valid),
- .s_axi_arid (spill_dram_req_arid),
- .s_axi_araddr (spill_dram_req.ar.addr[29:0]),
- .s_axi_arlen (spill_dram_req.ar.len),
- .s_axi_arsize (spill_dram_req.ar.size),
- .s_axi_arburst (spill_dram_req.ar.burst),
- .s_axi_arlock (spill_dram_req.ar.lock),
- .s_axi_arcache (spill_dram_req.ar.cache),
- .s_axi_arprot (spill_dram_req.ar.prot),
- .s_axi_arqos (spill_dram_req.ar.qos),
- .s_axi_arvalid (spill_dram_req.ar_valid),
- .s_axi_arready (spill_dram_rsp.ar_ready),
- .s_axi_rready (spill_dram_req.r_ready),
- .s_axi_rid (spill_dram_rsp_rid),
- .s_axi_rdata (spill_dram_rsp.r.data),
- .s_axi_rresp (spill_dram_rsp.r.resp),
- .s_axi_rlast (spill_dram_rsp.r.last),
- .s_axi_rvalid (spill_dram_rsp.r_valid),
+ .s_axi_awid (cdc_dram_req.aw.id),
+ .s_axi_awaddr (cdc_dram_req_aw_addr),
+ .s_axi_awlen (cdc_dram_req.aw.len),
+ .s_axi_awsize (cdc_dram_req.aw.size),
+ .s_axi_awburst (cdc_dram_req.aw.burst),
+ .s_axi_awlock (cdc_dram_req.aw.lock),
+ .s_axi_awcache (cdc_dram_req.aw.cache),
+ .s_axi_awprot (cdc_dram_req.aw.prot),
+ .s_axi_awqos (cdc_dram_req.aw.qos),
+ .s_axi_awvalid (cdc_dram_req.aw_valid),
+ .s_axi_awready (cdc_dram_rsp.aw_ready),
+ .s_axi_wdata (cdc_dram_req.w.data),
+ .s_axi_wstrb (cdc_dram_req.w.strb),
+ .s_axi_wlast (cdc_dram_req.w.last),
+ .s_axi_wvalid (cdc_dram_req.w_valid),
+ .s_axi_wready (cdc_dram_rsp.w_ready),
+ .s_axi_bready (cdc_dram_req.b_ready),
+ .s_axi_bid (cdc_dram_rsp.b.id),
+ .s_axi_bresp (cdc_dram_rsp.b.resp),
+ .s_axi_bvalid (cdc_dram_rsp.b_valid),
+ .s_axi_arid (cdc_dram_req.ar.id),
+ .s_axi_araddr (cdc_dram_req_ar_addr),
+ .s_axi_arlen (cdc_dram_req.ar.len),
+ .s_axi_arsize (cdc_dram_req.ar.size),
+ .s_axi_arburst (cdc_dram_req.ar.burst),
+ .s_axi_arlock (cdc_dram_req.ar.lock),
+ .s_axi_arcache (cdc_dram_req.ar.cache),
+ .s_axi_arprot (cdc_dram_req.ar.prot),
+ .s_axi_arqos (cdc_dram_req.ar.qos),
+ .s_axi_arvalid (cdc_dram_req.ar_valid),
+ .s_axi_arready (cdc_dram_rsp.ar_ready),
+ .s_axi_rready (cdc_dram_req.r_ready),
+ .s_axi_rid (cdc_dram_rsp.r.id),
+ .s_axi_rdata (cdc_dram_rsp.r.data),
+ .s_axi_rresp (cdc_dram_rsp.r.resp),
+ .s_axi_rlast (cdc_dram_rsp.r.last),
+ .s_axi_rvalid (cdc_dram_rsp.r_valid),
.init_calib_complete(), // keep open
.device_temp (), // keep open
// Phy
diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
index 3dbebfc34..d1551273a 100755
--- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
+++ b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj
@@ -149,7 +149,7 @@
RD_PRI_REG
30
64
- 6
+ 4
0
diff --git a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl
index aef051e47..7417e93cb 100644
--- a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl
+++ b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl
@@ -28,7 +28,7 @@ if {$::env(BOARD) eq "vcu128"} {
CONFIG.C0.DDR4_Ecc {true} \
CONFIG.C0.DDR4_AxiDataWidth {512} \
CONFIG.C0.DDR4_AxiAddressWidth {32} \
- CONFIG.C0.DDR4_AxiIDWidth {6} \
+ CONFIG.C0.DDR4_AxiIDWidth {4} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.BANK_GROUP_WIDTH {1} \
CONFIG.C0.CS_WIDTH {2} \
@@ -45,7 +45,7 @@ if {$::env(BOARD) eq "vcu128"} {
CONFIG.C0.DDR4_CasWriteLatency {12} \
CONFIG.C0.DDR4_AxiDataWidth {128} \
CONFIG.C0.DDR4_AxiAddressWidth {29} \
- CONFIG.C0.DDR4_AxiIDWidth {6} \
+ CONFIG.C0.DDR4_AxiIDWidth {4} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.System_Clock {No_Buffer} \
CONFIG.Reference_Clock {No_Buffer} \