From 903658b972109a996e244bd460a2aed6ed24d02e Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Tue, 21 May 2024 18:56:33 +0200 Subject: [PATCH] fix constraints --- target/xilinx/constraints/genesys2.xdc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 8ee87fb4..e5bf3098 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -14,6 +14,8 @@ # 200 MHz input clock set SYS_TCK 5 create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk] + # SoC clock is generated by clock wizard and its constraints set SOC_TCK 20.0 @@ -54,6 +56,9 @@ set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk_sync_rst] set_false_path -hold -through $MIG_RST_O set_max_delay -through $MIG_RST_O $MIG_TCK +set_false_path -from [get_pins i_vio/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/Probe_out_reg[*]/C] -to [get_pins i_dram_wrapper/i_dram/u_mig7s_mig/u_ddr3_infrastructure/rstdiv0_sync_r*_reg_rep__*/PRE] + + # Limit delay across DRAM CDC (hold already false-pathed) set_max_delay -datapath_only \ -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ @@ -104,14 +109,15 @@ set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_cl set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { sys_resetn }]; #IO_0_14 Sch=cpu_resetn ## Switches -set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] -set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[1] }]; #IO_25_16 Sch=sw[1] -set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[0] }]; #IO_L19P_T3_16 Sch=sw[2] -set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] -set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] -set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] +set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS18 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] +set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS18 } [get_ports { boot_mode_i[1] }]; #IO_25_16 Sch=sw[1] +set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[0] }]; #IO_L19P_T3_16 Sch=sw[2] +set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] +set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] +set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS18 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { test_mode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] + # UART set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L1P_T0_12 Sch=uart_rx_out set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_0_12 Sch=uart_tx_in