From 97662bea1eb190b6b98c1f547d825d9d9aa6449d Mon Sep 17 00:00:00 2001 From: Alessandro Ottaviano Date: Tue, 8 Aug 2023 18:46:53 +0200 Subject: [PATCH] hw: Expose `NumExtIntrSyncs` as design parameter (#64) * hw: Expose `NumExtIntrSyncs` as design parameter * target/xilinx: Update default number of sync stages for intrs --- hw/cheshire_pkg.sv | 3 ++- hw/cheshire_soc.sv | 2 +- target/xilinx/src/cheshire_top_xilinx.sv | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 8315c61b..3715076d 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -79,6 +79,7 @@ package cheshire_pkg; byte_bt NumExtOutIntrTgts; shrt_bt NumExtOutIntrs; shrt_bt ClicIntCtlBits; + shrt_bt NumExtIntrSyncs; // AXI parameters aw_bt AddrWidth; dw_bt AxiDataWidth; @@ -217,7 +218,6 @@ package cheshire_pkg; } cheshire_xeip_t; // Interrupt parameters - localparam int unsigned NumExtIntrSyncs = 2; localparam int unsigned NumIntIntrs = $bits(cheshire_int_intr_t); localparam int unsigned NumIrqCtxts = $bits(cheshire_xeip_t); localparam int unsigned NumCoreIrqs = $bits(cheshire_core_ip_t); @@ -478,6 +478,7 @@ package cheshire_pkg; NumExtOutIntrTgts : 0, NumExtOutIntrs : 0, ClicIntCtlBits : ariane_pkg::ArianeDefaultConfig.CLICIntCtlBits, + NumExtIntrSyncs : 2, // Interconnect AddrWidth : 48, AxiDataWidth : 64, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index a9929b74..9529de0e 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -150,7 +150,7 @@ module cheshire_soc import cheshire_pkg::*; #( // External interrupts must be synchronized to this domain for (genvar i = 0; i <= iomsb(Cfg.NumExtInIntrs); i++) begin : gen_ext_in_intr_syncs sync #( - .STAGES ( NumExtIntrSyncs ), + .STAGES ( Cfg.NumExtIntrSyncs ), .ResetValue ( 1'b0 ) ) i_ext_intr_sync ( .clk_i, diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 99dcd95d..f9763f54 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -78,6 +78,8 @@ module cheshire_top_xilinx NumCores : 1, CoreMaxTxns : 8, CoreMaxTxnsPerId : 4, + // Interrupts + NumExtIntrSyncs : 2, // Interconnect AddrWidth : 48, AxiDataWidth : 64,