diff --git a/Bender.yml b/Bender.yml index 293ece73f..179578587 100644 --- a/Bender.yml +++ b/Bender.yml @@ -47,7 +47,7 @@ sources: - target/sim/src/fixture_cheshire_soc.sv - target/sim/src/tb_cheshire_soc.sv - - target: all(fpga, xilinx) + - target: any(fpga, xilinx) files: - target/xilinx/src/fan_ctrl.sv - target/xilinx/src/dram_wrapper.sv diff --git a/cheshire.mk b/cheshire.mk index acbde4b70..fbb8f78c5 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -55,7 +55,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= e702b4ce754c3b7c9a864a2ce8e2d2fa013056ea +CHS_NONFREE_COMMIT ?= 65f089e9218084e872009cf1c557965914cacf05 chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -158,3 +158,4 @@ chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl ############# include $(CHS_ROOT)/target/xilinx/xilinx.mk +include $(CHS_XIL_DIR)/sim/simulate.mk diff --git a/hw/bootrom/cheshire_bootrom.c b/hw/bootrom/cheshire_bootrom.c index 675cb8617..fe147ebc5 100644 --- a/hw/bootrom/cheshire_bootrom.c +++ b/hw/bootrom/cheshire_bootrom.c @@ -19,6 +19,16 @@ #include "hal/uart_debug.h" #include "gpt.h" +// Todo do this nicer +#define SPI_OFFSET 0x6000000 +#ifndef SPI_OFFSET +#define SPI_OFFSET 0 +#endif +int off_set_spi_sdcard_read_checkcrc(void *priv, void *buf, uint64_t addr, uint64_t len) { + return spi_sdcard_read_checkcrc(priv, buf, addr + SPI_OFFSET, len); +} + + int boot_passive(uint64_t core_freq) { // Initialize UART with debug settings uart_debug_init(&__base_uart, core_freq); @@ -42,7 +52,7 @@ int boot_spi_sdcard(uint64_t core_freq, uint64_t rtc_freq) { CHECK_CALL(spi_sdcard_init(&device, core_freq)) // Wait for device to be initialized (1ms, round up extra tick to be sure) clint_spin_until((1000 * rtc_freq) / (1000 * 1000) + 1); - return gpt_boot_part_else_raw(spi_sdcard_read_checkcrc, &device, &__base_spm, + return gpt_boot_part_else_raw(off_set_spi_sdcard_read_checkcrc, &device, &__base_spm, __BOOT_SPM_MAX_LBAS, __BOOT_ZSL_TYPE_GUID, 0); } diff --git a/hw/bootrom/cheshire_bootrom.sv b/hw/bootrom/cheshire_bootrom.sv index a436e003c..b915b6668 100644 --- a/hw/bootrom/cheshire_bootrom.sv +++ b/hw/bootrom/cheshire_bootrom.sv @@ -74,7 +74,7 @@ module cheshire_bootrom #( 042: data_o = 32'h43014281 /* 0x00a8 */; 043: data_o = 32'h0ff0000f /* 0x00ac */; 044: data_o = 32'h0000100f /* 0x00b0 */; - 045: data_o = 32'h3f4010ef /* 0x00b4 */; + 045: data_o = 32'h3fa010ef /* 0x00b4 */; 046: data_o = 32'h65130506 /* 0x00b8 */; 047: data_o = 32'h02970015 /* 0x00bc */; 048: data_o = 32'h82930100 /* 0x00c0 */; @@ -1040,586 +1040,586 @@ module cheshire_bootrom #( 1008: data_o = 32'h694264e2 /* 0x0fc0 */; 1009: data_o = 32'h0007851b /* 0x0fc4 */; 1010: data_o = 32'h80826145 /* 0x0fc8 */; - 1011: data_o = 32'hd4010113 /* 0x0fcc */; - 1012: data_o = 32'h29613023 /* 0x0fd0 */; - 1013: data_o = 32'h00d60b33 /* 0x0fd4 */; - 1014: data_o = 32'h29513423 /* 0x0fd8 */; - 1015: data_o = 32'h27713c23 /* 0x0fdc */; - 1016: data_o = 32'h27a13023 /* 0x0fe0 */; - 1017: data_o = 32'h2a113c23 /* 0x0fe4 */; - 1018: data_o = 32'h2a813823 /* 0x0fe8 */; - 1019: data_o = 32'h2a913423 /* 0x0fec */; - 1020: data_o = 32'h2b213023 /* 0x0ff0 */; - 1021: data_o = 32'h29313c23 /* 0x0ff4 */; - 1022: data_o = 32'h29413823 /* 0x0ff8 */; - 1023: data_o = 32'h27813823 /* 0x0ffc */; - 1024: data_o = 32'h27913423 /* 0x1000 */; - 1025: data_o = 32'h25b13c23 /* 0x1004 */; - 1026: data_o = 32'h1ffb7b13 /* 0x1008 */; - 1027: data_o = 32'h8aae8d2a /* 0x100c */; - 1028: data_o = 32'h1ff67b93 /* 0x1010 */; - 1029: data_o = 32'h000b1463 /* 0x1014 */; - 1030: data_o = 32'h20000b13 /* 0x1018 */; - 1031: data_o = 32'h1ff68413 /* 0x101c */; - 1032: data_o = 32'h0793945e /* 0x1020 */; - 1033: data_o = 32'h8025faa0 /* 0x1024 */; - 1034: data_o = 32'h02f102a3 /* 0x1028 */; - 1035: data_o = 32'h24040a63 /* 0x102c */; - 1036: data_o = 32'h0b634785 /* 0x1030 */; - 1037: data_o = 32'h059310f4 /* 0x1034 */; - 1038: data_o = 32'h82250520 /* 0x1038 */; - 1039: data_o = 32'h0186579b /* 0x103c */; - 1040: data_o = 32'h0ff67693 /* 0x1040 */; - 1041: data_o = 32'h07a21682 /* 0x1044 */; - 1042: data_o = 32'h06b78fd5 /* 0x1048 */; - 1043: data_o = 32'h571b00ff /* 0x104c */; - 1044: data_o = 32'h8e750086 /* 0x1050 */; - 1045: data_o = 32'h57fd8e5d /* 0x1054 */; - 1046: data_o = 32'h93810762 /* 0x1058 */; - 1047: data_o = 32'h8e5d8ff9 /* 0x105c */; - 1048: data_o = 32'he8b28e4d /* 0x1060 */; - 1049: data_o = 32'h05130894 /* 0x1064 */; - 1050: data_o = 32'h47010551 /* 0x1068 */; - 1051: data_o = 32'h05418593 /* 0x106c */; - 1052: data_o = 32'h0006c783 /* 0x1070 */; - 1053: data_o = 32'h0017171b /* 0x1074 */; - 1054: data_o = 32'h8fb90685 /* 0x1078 */; - 1055: data_o = 32'h0ff7f793 /* 0x107c */; - 1056: data_o = 32'hc70397ae /* 0x1080 */; - 1057: data_o = 32'h15e30007 /* 0x1084 */; - 1058: data_o = 32'h1793fed5 /* 0x1088 */; - 1059: data_o = 32'he7930017 /* 0x108c */; - 1060: data_o = 32'h17a20017 /* 0x1090 */; - 1061: data_o = 32'he8828fd1 /* 0x1094 */; - 1062: data_o = 32'h2583f43e /* 0x1098 */; - 1063: data_o = 32'h478d010d /* 0x109c */; - 1064: data_o = 32'h103cc8be /* 0x10a0 */; - 1065: data_o = 32'h4685f0be /* 0x10a4 */; - 1066: data_o = 32'h08904799 /* 0x10a8 */; - 1067: data_o = 32'hec82856a /* 0x10ac */; - 1068: data_o = 32'hf4bef882 /* 0x10b0 */; - 1069: data_o = 32'hc85ff0ef /* 0x10b4 */; - 1070: data_o = 32'h00050d9b /* 0x10b8 */; - 1071: data_o = 32'h040d9863 /* 0x10bc */; - 1072: data_o = 32'h02814703 /* 0x10c0 */; - 1073: data_o = 32'h04c00793 /* 0x10c4 */; - 1074: data_o = 32'h010d2583 /* 0x10c8 */; - 1075: data_o = 32'h20f70e63 /* 0x10cc */; - 1076: data_o = 32'h4a1144a1 /* 0x10d0 */; - 1077: data_o = 32'h02510993 /* 0x10d4 */; - 1078: data_o = 32'ha0294905 /* 0x10d8 */; - 1079: data_o = 32'h02510783 /* 0x10dc */; - 1080: data_o = 32'h0607d763 /* 0x10e0 */; - 1081: data_o = 32'h010d2583 /* 0x10e4 */; - 1082: data_o = 32'h4685e882 /* 0x10e8 */; - 1083: data_o = 32'h856a0890 /* 0x10ec */; - 1084: data_o = 32'hf882ec82 /* 0x10f0 */; - 1085: data_o = 32'hf0cec8d2 /* 0x10f4 */; - 1086: data_o = 32'hf0eff4ca /* 0x10f8 */; - 1087: data_o = 32'h0d9bc3ff /* 0x10fc */; - 1088: data_o = 32'h34fd0005 /* 0x1100 */; - 1089: data_o = 32'h000d9463 /* 0x1104 */; - 1090: data_o = 32'h4dc9f8f1 /* 0x1108 */; - 1091: data_o = 32'h2b813083 /* 0x110c */; - 1092: data_o = 32'h2b013403 /* 0x1110 */; - 1093: data_o = 32'h2a813483 /* 0x1114 */; - 1094: data_o = 32'h2a013903 /* 0x1118 */; - 1095: data_o = 32'h29813983 /* 0x111c */; - 1096: data_o = 32'h29013a03 /* 0x1120 */; - 1097: data_o = 32'h28813a83 /* 0x1124 */; - 1098: data_o = 32'h28013b03 /* 0x1128 */; - 1099: data_o = 32'h27813b83 /* 0x112c */; - 1100: data_o = 32'h27013c03 /* 0x1130 */; - 1101: data_o = 32'h26813c83 /* 0x1134 */; - 1102: data_o = 32'h26013d03 /* 0x1138 */; - 1103: data_o = 32'h3d83856e /* 0x113c */; - 1104: data_o = 32'h01132581 /* 0x1140 */; - 1105: data_o = 32'h80822c01 /* 0x1144 */; - 1106: data_o = 32'h05100593 /* 0x1148 */; - 1107: data_o = 32'h37b3b5fd /* 0x114c */; - 1108: data_o = 32'h6c850170 /* 0x1150 */; - 1109: data_o = 32'h8793ec3e /* 0x1154 */; - 1110: data_o = 32'he43e800c /* 0x1158 */; - 1111: data_o = 32'h97de089c /* 0x115c */; - 1112: data_o = 32'h417a8ab3 /* 0x1160 */; - 1113: data_o = 32'he83e4c01 /* 0x1164 */; - 1114: data_o = 32'h0c936709 /* 0x1168 */; - 1115: data_o = 32'h49917107 /* 0x116c */; - 1116: data_o = 32'h02510913 /* 0x1170 */; - 1117: data_o = 32'h0a134485 /* 0x1174 */; - 1118: data_o = 32'ha0390ff0 /* 0x1178 */; - 1119: data_o = 32'h160c8463 /* 0x117c */; - 1120: data_o = 32'h02514683 /* 0x1180 */; - 1121: data_o = 32'h03469563 /* 0x1184 */; - 1122: data_o = 32'h010d2583 /* 0x1188 */; - 1123: data_o = 32'h4685f402 /* 0x118c */; - 1124: data_o = 32'h856a1030 /* 0x1190 */; - 1125: data_o = 32'he482f802 /* 0x1194 */; - 1126: data_o = 32'hfc4ad44e /* 0x1198 */; - 1127: data_o = 32'hf0efe0a6 /* 0x119c */; - 1128: data_o = 32'h0d9bb9bf /* 0x11a0 */; - 1129: data_o = 32'h3cfd0005 /* 0x11a4 */; - 1130: data_o = 32'hfc0d8ae3 /* 0x11a8 */; - 1131: data_o = 32'h0713b785 /* 0x11ac */; - 1132: data_o = 32'h91630fe0 /* 0x11b0 */; - 1133: data_o = 32'h0e6318e6 /* 0x11b4 */; - 1134: data_o = 32'h0713100c /* 0x11b8 */; - 1135: data_o = 32'h0163fff4 /* 0x11bc */; - 1136: data_o = 32'h88d610ec /* 0x11c0 */; - 1137: data_o = 32'h8cc6e002 /* 0x11c4 */; - 1138: data_o = 32'h20088a13 /* 0x11c8 */; - 1139: data_o = 32'h491189c6 /* 0x11cc */; - 1140: data_o = 32'h10000493 /* 0x11d0 */; - 1141: data_o = 32'hf802f402 /* 0x11d4 */; - 1142: data_o = 32'h0a098663 /* 0x11d8 */; - 1143: data_o = 32'hd44ae482 /* 0x11dc */; - 1144: data_o = 32'he0a6fc4e /* 0x11e0 */; - 1145: data_o = 32'h010d2583 /* 0x11e4 */; - 1146: data_o = 32'h10304685 /* 0x11e8 */; - 1147: data_o = 32'hf0ef856a /* 0x11ec */; - 1148: data_o = 32'h2501b4bf /* 0x11f0 */; - 1149: data_o = 32'h10098993 /* 0x11f4 */; - 1150: data_o = 32'h1de3e171 /* 0x11f8 */; - 1151: data_o = 32'hf402fd3a /* 0x11fc */; - 1152: data_o = 32'h25834711 /* 0x1200 */; - 1153: data_o = 32'hd43a010d /* 0x1204 */; - 1154: data_o = 32'h02610713 /* 0x1208 */; - 1155: data_o = 32'h4685fc3a /* 0x120c */; - 1156: data_o = 32'h10304709 /* 0x1210 */; - 1157: data_o = 32'hf802856a /* 0x1214 */; - 1158: data_o = 32'he0bae482 /* 0x1218 */; - 1159: data_o = 32'hb1dff0ef /* 0x121c */; - 1160: data_o = 32'hed492501 /* 0x1220 */; - 1161: data_o = 32'h85934681 /* 0x1224 */; - 1162: data_o = 32'hc703e541 /* 0x1228 */; - 1163: data_o = 32'hd61b000c /* 0x122c */; - 1164: data_o = 32'h969b0086 /* 0x1230 */; - 1165: data_o = 32'h8f310086 /* 0x1234 */; - 1166: data_o = 32'h837d1702 /* 0x1238 */; - 1167: data_o = 32'h5703972e /* 0x123c */; - 1168: data_o = 32'h16c20007 /* 0x1240 */; - 1169: data_o = 32'h0c8592c1 /* 0x1244 */; - 1170: data_o = 32'h10e38eb9 /* 0x1248 */; - 1171: data_o = 32'h971bff9a /* 0x124c */; - 1172: data_o = 32'hd69b0086 /* 0x1250 */; - 1173: data_o = 32'h8f550086 /* 0x1254 */; - 1174: data_o = 32'h02615603 /* 0x1258 */; - 1175: data_o = 32'h93411742 /* 0x125c */; - 1176: data_o = 32'h0ce61d63 /* 0x1260 */; - 1177: data_o = 32'hc7956782 /* 0x1264 */; - 1178: data_o = 32'h015b8533 /* 0x1268 */; - 1179: data_o = 32'h0a0d9863 /* 0x126c */; - 1180: data_o = 32'h061365c2 /* 0x1270 */; - 1181: data_o = 32'h06332000 /* 0x1274 */; - 1182: data_o = 32'he0ef4176 /* 0x1278 */; - 1183: data_o = 32'ha821e7ff /* 0x127c */; - 1184: data_o = 32'hb5694d81 /* 0x1280 */; - 1185: data_o = 32'hd43e4789 /* 0x1284 */; - 1186: data_o = 32'he08267a2 /* 0x1288 */; - 1187: data_o = 32'hfc3ee482 /* 0x128c */; - 1188: data_o = 32'h9f63bf91 /* 0x1290 */; - 1189: data_o = 32'h0c05060d /* 0x1294 */; - 1190: data_o = 32'h200a8a93 /* 0x1298 */; - 1191: data_o = 32'hed8416e3 /* 0x129c */; - 1192: data_o = 32'h02634785 /* 0x12a0 */; - 1193: data_o = 32'h05930af4 /* 0x12a4 */; - 1194: data_o = 32'h15a20610 /* 0x12a8 */; - 1195: data_o = 32'h10344701 /* 0x12ac */; - 1196: data_o = 32'h85934605 /* 0x12b0 */; - 1197: data_o = 32'h856a04c5 /* 0x12b4 */; - 1198: data_o = 32'hb55ff0ef /* 0x12b8 */; - 1199: data_o = 32'hb5b98daa /* 0x12bc */; - 1200: data_o = 32'h20000713 /* 0x12c0 */; - 1201: data_o = 32'heeeb0fe3 /* 0x12c4 */; - 1202: data_o = 32'h0893e06e /* 0x12c8 */; - 1203: data_o = 32'h4d850501 /* 0x12cc */; - 1204: data_o = 32'h0b63bddd /* 0x12d0 */; - 1205: data_o = 32'h85630494 /* 0x12d4 */; - 1206: data_o = 32'h4785060b /* 0x12d8 */; - 1207: data_o = 32'h0893e03e /* 0x12dc */; - 1208: data_o = 32'hb5d50501 /* 0x12e0 */; - 1209: data_o = 32'hb51d4de5 /* 0x12e4 */; - 1210: data_o = 32'h4791e882 /* 0x12e8 */; - 1211: data_o = 32'h0793c8be /* 0x12ec */; - 1212: data_o = 32'hf0be0261 /* 0x12f0 */; - 1213: data_o = 32'h47854685 /* 0x12f4 */; - 1214: data_o = 32'h856a0890 /* 0x12f8 */; - 1215: data_o = 32'hf882ec82 /* 0x12fc */; - 1216: data_o = 32'hf0eff4be /* 0x1300 */; - 1217: data_o = 32'h0d9ba37f /* 0x1304 */; - 1218: data_o = 32'h83e30005 /* 0x1308 */; - 1219: data_o = 32'hbbfddc0d /* 0x130c */; - 1220: data_o = 32'h088c865a /* 0x1310 */; - 1221: data_o = 32'he0ef8556 /* 0x1314 */; - 1222: data_o = 32'hbfb5de3f /* 0x1318 */; - 1223: data_o = 32'h063365c2 /* 0x131c */; - 1224: data_o = 32'he0ef417b /* 0x1320 */; - 1225: data_o = 32'hbf85dd7f /* 0x1324 */; - 1226: data_o = 32'h20000713 /* 0x1328 */; - 1227: data_o = 32'hfaeb05e3 /* 0x132c */; - 1228: data_o = 32'hbf596de2 /* 0x1330 */; - 1229: data_o = 32'h02000d93 /* 0x1334 */; - 1230: data_o = 32'h0d93bbd1 /* 0x1338 */; - 1231: data_o = 32'hb3f90210 /* 0x133c */; - 1232: data_o = 32'h88d6e002 /* 0x1340 */; - 1233: data_o = 32'h2783b549 /* 0x1344 */; - 1234: data_o = 32'h3703014d /* 0x1348 */; - 1235: data_o = 32'hd35c000d /* 0x134c */; - 1236: data_o = 32'hd79b4b5c /* 0x1350 */; - 1237: data_o = 32'hdfed01f7 /* 0x1354 */; - 1238: data_o = 32'hd71c479d /* 0x1358 */; - 1239: data_o = 32'hb37d4d81 /* 0x135c */; - 1240: data_o = 32'hb1adc291 /* 0x1360 */; - 1241: data_o = 32'h80824501 /* 0x1364 */; - 1242: data_o = 32'heca67159 /* 0x1368 */; - 1243: data_o = 32'he8ca84ae /* 0x136c */; - 1244: data_o = 32'hf0a2f486 /* 0x1370 */; - 1245: data_o = 32'he0d2e4ce /* 0x1374 */; - 1246: data_o = 32'hf85afc56 /* 0x1378 */; - 1247: data_o = 32'h46a1892a /* 0x137c */; - 1248: data_o = 32'h20000613 /* 0x1380 */; - 1249: data_o = 32'h8526100c /* 0x1384 */; - 1250: data_o = 32'hed519902 /* 0x1388 */; - 1251: data_o = 32'h00001797 /* 0x138c */; - 1252: data_o = 32'hb7837702 /* 0x1390 */; - 1253: data_o = 32'h186387c7 /* 0x1394 */; - 1254: data_o = 32'h46c108f7 /* 0x1398 */; - 1255: data_o = 32'h24800613 /* 0x139c */; - 1256: data_o = 32'h8526858a /* 0x13a0 */; - 1257: data_o = 32'h87aa9902 /* 0x13a4 */; - 1258: data_o = 32'h47a2ed69 /* 0x13a8 */; - 1259: data_o = 32'h05f00993 /* 0x13ac */; - 1260: data_o = 32'hcfad4a01 /* 0x13b0 */; - 1261: data_o = 32'h0a934b01 /* 0x13b4 */; - 1262: data_o = 32'h678305f0 /* 0x13b8 */; - 1263: data_o = 32'h640200c1 /* 0x13bc */; - 1264: data_o = 32'h87b346c1 /* 0x13c0 */; - 1265: data_o = 32'h04260367 /* 0x13c4 */; - 1266: data_o = 32'h8526080c /* 0x13c8 */; - 1267: data_o = 32'h0613943e /* 0x13cc */; - 1268: data_o = 32'h99020204 /* 0x13d0 */; - 1269: data_o = 32'h46c187aa /* 0x13d4 */; - 1270: data_o = 32'h100c8622 /* 0x13d8 */; - 1271: data_o = 32'he3d58526 /* 0x13dc */; - 1272: data_o = 32'h67e26742 /* 0x13e0 */; - 1273: data_o = 32'h000b1863 /* 0x13e4 */; - 1274: data_o = 32'h05f70993 /* 0x13e8 */; - 1275: data_o = 32'h0137f363 /* 0x13ec */; - 1276: data_o = 32'h8a3a89be /* 0x13f0 */; - 1277: data_o = 32'hec638f99 /* 0x13f4 */; - 1278: data_o = 32'h990200fa /* 0x13f8 */; - 1279: data_o = 32'he15187aa /* 0x13fc */; - 1280: data_o = 32'h00001797 /* 0x1400 */; - 1281: data_o = 32'h8107b783 /* 0x1404 */; - 1282: data_o = 32'h07637702 /* 0x1408 */; - 1283: data_o = 32'h678308f7 /* 0x140c */; - 1284: data_o = 32'h0b050081 /* 0x1410 */; - 1285: data_o = 32'hfafb43e3 /* 0x1414 */; - 1286: data_o = 32'h00816783 /* 0x1418 */; - 1287: data_o = 32'h00fb0863 /* 0x141c */; - 1288: data_o = 32'h69e26a42 /* 0x1420 */; - 1289: data_o = 32'h0993a021 /* 0x1424 */; - 1290: data_o = 32'h4a0105f0 /* 0x1428 */; - 1291: data_o = 32'h00198693 /* 0x142c */; - 1292: data_o = 32'h414686b3 /* 0x1430 */; - 1293: data_o = 32'h0dfff597 /* 0x1434 */; - 1294: data_o = 32'h161306a6 /* 0x1438 */; - 1295: data_o = 32'h8593009a /* 0x143c */; - 1296: data_o = 32'h8526bcc5 /* 0x1440 */; - 1297: data_o = 32'h87aa9902 /* 0x1444 */; - 1298: data_o = 32'h6913ed0d /* 0x1448 */; - 1299: data_o = 32'h29010019 /* 0x144c */; - 1300: data_o = 32'h00fff797 /* 0x1450 */; - 1301: data_o = 32'hbb27a823 /* 0x1454 */; - 1302: data_o = 32'h00fff797 /* 0x1458 */; - 1303: data_o = 32'hba878793 /* 0x145c */; - 1304: data_o = 32'hc3c42481 /* 0x1460 */; - 1305: data_o = 32'hf797870e /* 0x1464 */; - 1306: data_o = 32'h270100ff /* 0x1468 */; - 1307: data_o = 32'hb9a78793 /* 0x146c */; - 1308: data_o = 32'h100fc7d8 /* 0x1470 */; - 1309: data_o = 32'hf0970000 /* 0x1474 */; - 1310: data_o = 32'h80e70dff /* 0x1478 */; - 1311: data_o = 32'h079bb8a0 /* 0x147c */; - 1312: data_o = 32'h70a60005 /* 0x1480 */; - 1313: data_o = 32'h64e67406 /* 0x1484 */; - 1314: data_o = 32'h69a66946 /* 0x1488 */; - 1315: data_o = 32'h7ae26a06 /* 0x148c */; - 1316: data_o = 32'h853e7b42 /* 0x1490 */; - 1317: data_o = 32'h80826165 /* 0x1494 */; - 1318: data_o = 32'h00000797 /* 0x1498 */; - 1319: data_o = 32'h7807b783 /* 0x149c */; - 1320: data_o = 32'h16e37722 /* 0x14a0 */; - 1321: data_o = 32'hbf8df6f7 /* 0x14a4 */; - 1322: data_o = 32'h00fff797 /* 0x14a8 */; - 1323: data_o = 32'h87937119 /* 0x14ac */; - 1324: data_o = 32'hf0cab587 /* 0x14b0 */; - 1325: data_o = 32'h0107a903 /* 0x14b4 */; - 1326: data_o = 32'h00fff797 /* 0x14b8 */; - 1327: data_o = 32'hb4878793 /* 0x14bc */; - 1328: data_o = 32'h4bc0f8a2 /* 0x14c0 */; - 1329: data_o = 32'heccef4a6 /* 0x14c4 */; - 1330: data_o = 32'h90011402 /* 0x14c8 */; - 1331: data_o = 32'hfc868522 /* 0x14cc */; - 1332: data_o = 32'he0ef2901 /* 0x14d0 */; - 1333: data_o = 32'h4989fa9f /* 0x14d4 */; - 1334: data_o = 32'h086384aa /* 0x14d8 */; - 1335: data_o = 32'h478d1d39 /* 0x14dc */; - 1336: data_o = 32'h26f90e63 /* 0x14e0 */; - 1337: data_o = 32'h1f634785 /* 0x14e4 */; - 1338: data_o = 32'h37b73cf9 /* 0x14e8 */; - 1339: data_o = 32'h8713016e /* 0x14ec */; - 1340: data_o = 32'hd0026007 /* 0x14f0 */; - 1341: data_o = 32'hd24eec3a /* 0x14f4 */; - 1342: data_o = 32'h5ff78793 /* 0x14f8 */; - 1343: data_o = 32'hff634561 /* 0x14fc */; - 1344: data_o = 32'h35171897 /* 0x1500 */; - 1345: data_o = 32'h05130100 /* 0x1504 */; - 1346: data_o = 32'he82aafe5 /* 0x1508 */; - 1347: data_o = 32'hac6ff0ef /* 0x150c */; - 1348: data_o = 32'h000317b7 /* 0x1510 */; - 1349: data_o = 32'hd4078793 /* 0x1514 */; - 1350: data_o = 32'hc226c03e /* 0x1518 */; - 1351: data_o = 32'h46816582 /* 0x151c */; - 1352: data_o = 32'h08084601 /* 0x1520 */; - 1353: data_o = 32'he0efe402 /* 0x1524 */; - 1354: data_o = 32'h2501ec9f /* 0x1528 */; - 1355: data_o = 32'h16051863 /* 0x152c */; - 1356: data_o = 32'h65825692 /* 0x1530 */; - 1357: data_o = 32'h08086622 /* 0x1534 */; - 1358: data_o = 32'heb7fe0ef /* 0x1538 */; - 1359: data_o = 32'h1f632501 /* 0x153c */; - 1360: data_o = 32'h37971405 /* 0x1540 */; - 1361: data_o = 32'h87930100 /* 0x1544 */; - 1362: data_o = 32'h0737abe7 /* 0x1548 */; - 1363: data_o = 32'hcb988000 /* 0x154c */; - 1364: data_o = 32'h01003797 /* 0x1550 */; - 1365: data_o = 32'hab078793 /* 0x1554 */; - 1366: data_o = 32'h07374b9c /* 0x1558 */; - 1367: data_o = 32'h177de000 /* 0x155c */; - 1368: data_o = 32'h07378ff9 /* 0x1560 */; - 1369: data_o = 32'h8fd92000 /* 0x1564 */; - 1370: data_o = 32'h01003717 /* 0x1568 */; - 1371: data_o = 32'ha9870713 /* 0x156c */; - 1372: data_o = 32'h5582cb1c /* 0x1570 */; - 1373: data_o = 32'h0793f402 /* 0x1574 */; - 1374: data_o = 32'h46850500 /* 0x1578 */; - 1375: data_o = 32'h08081030 /* 0x157c */; - 1376: data_o = 32'he082f802 /* 0x1580 */; - 1377: data_o = 32'hd44ee482 /* 0x1584 */; - 1378: data_o = 32'hf0effc3e /* 0x1588 */; - 1379: data_o = 32'h2501faef /* 0x158c */; - 1380: data_o = 32'h10051663 /* 0x1590 */; - 1381: data_o = 32'h09500593 /* 0x1594 */; - 1382: data_o = 32'h470515a2 /* 0x1598 */; - 1383: data_o = 32'h46014685 /* 0x159c */; - 1384: data_o = 32'h04058593 /* 0x15a0 */; - 1385: data_o = 32'hf0ef0808 /* 0x15a4 */; - 1386: data_o = 32'h19639c7f /* 0x15a8 */; - 1387: data_o = 32'h07970e05 /* 0x15ac */; - 1388: data_o = 32'h17370000 /* 0x15b0 */; - 1389: data_o = 32'hb5830aa0 /* 0x15b4 */; - 1390: data_o = 32'h07326727 /* 0x15b8 */; - 1391: data_o = 32'h46850705 /* 0x15bc */; - 1392: data_o = 32'h08084611 /* 0x15c0 */; - 1393: data_o = 32'h9a9ff0ef /* 0x15c4 */; - 1394: data_o = 32'h0493e971 /* 0x15c8 */; - 1395: data_o = 32'h14a20650 /* 0x15cc */; - 1396: data_o = 32'h03210423 /* 0x15d0 */; - 1397: data_o = 32'h07748493 /* 0x15d4 */; - 1398: data_o = 32'h46814701 /* 0x15d8 */; - 1399: data_o = 32'h85a64601 /* 0x15dc */; - 1400: data_o = 32'hf0ef0808 /* 0x15e0 */; - 1401: data_o = 32'he95d98bf /* 0x15e4 */; - 1402: data_o = 32'h00000797 /* 0x15e8 */; - 1403: data_o = 32'h6407b583 /* 0x15ec */; - 1404: data_o = 32'h10344701 /* 0x15f0 */; - 1405: data_o = 32'h08084601 /* 0x15f4 */; - 1406: data_o = 32'h815ff0ef /* 0x15f8 */; - 1407: data_o = 32'h4783e145 /* 0x15fc */; - 1408: data_o = 32'hfbf90281 /* 0x1600 */; - 1409: data_o = 32'h0fd00593 /* 0x1604 */; - 1410: data_o = 32'h470115a2 /* 0x1608 */; - 1411: data_o = 32'h460d4681 /* 0x160c */; - 1412: data_o = 32'h07a58593 /* 0x1610 */; - 1413: data_o = 32'hf0ef0808 /* 0x1614 */; - 1414: data_o = 32'he149957f /* 0x1618 */; - 1415: data_o = 32'h00000797 /* 0x161c */; - 1416: data_o = 32'h6147b583 /* 0x1620 */; - 1417: data_o = 32'h46854701 /* 0x1624 */; - 1418: data_o = 32'h08084601 /* 0x1628 */; - 1419: data_o = 32'h941ff0ef /* 0x162c */; - 1420: data_o = 32'h64c2e535 /* 0x1630 */; - 1421: data_o = 32'he0000937 /* 0x1634 */; - 1422: data_o = 32'h489c197d /* 0x1638 */; - 1423: data_o = 32'h08086622 /* 0x163c */; - 1424: data_o = 32'h0127f7b3 /* 0x1640 */; - 1425: data_o = 32'h67e2c89c /* 0x1644 */; - 1426: data_o = 32'hc03e5682 /* 0x1648 */; - 1427: data_o = 32'he0ef6582 /* 0x164c */; - 1428: data_o = 32'h2501da1f /* 0x1650 */; - 1429: data_o = 32'h5692e521 /* 0x1654 */; - 1430: data_o = 32'h66226582 /* 0x1658 */; - 1431: data_o = 32'he0ef0808 /* 0x165c */; - 1432: data_o = 32'h2501d91f /* 0x1660 */; - 1433: data_o = 32'h0513ed05 /* 0x1664 */; - 1434: data_o = 32'h05333e80 /* 0x1668 */; - 1435: data_o = 32'h489c02a4 /* 0x166c */; - 1436: data_o = 32'h20000737 /* 0x1670 */; - 1437: data_o = 32'h0127f7b3 /* 0x1674 */; - 1438: data_o = 32'hc89c8fd9 /* 0x1678 */; - 1439: data_o = 32'h000f47b7 /* 0x167c */; - 1440: data_o = 32'h24078793 /* 0x1680 */; - 1441: data_o = 32'h02f55533 /* 0x1684 */; - 1442: data_o = 32'he0ef0505 /* 0x1688 */; - 1443: data_o = 32'h0517a85f /* 0x168c */; - 1444: data_o = 32'h080c0000 /* 0x1690 */; - 1445: data_o = 32'hcd250513 /* 0x1694 */; - 1446: data_o = 32'hcd1ff0ef /* 0x1698 */; - 1447: data_o = 32'h744670e6 /* 0x169c */; - 1448: data_o = 32'h790674a6 /* 0x16a0 */; - 1449: data_o = 32'h610969e6 /* 0x16a4 */; - 1450: data_o = 32'h67b78082 /* 0x16a8 */; - 1451: data_o = 32'hfc020989 /* 0x16ac */; - 1452: data_o = 32'h7ff78793 /* 0x16b0 */; - 1453: data_o = 32'h00255913 /* 0x16b4 */; - 1454: data_o = 32'h00a7f663 /* 0x16b8 */; - 1455: data_o = 32'h02626937 /* 0x16bc */; - 1456: data_o = 32'ha0090913 /* 0x16c0 */; - 1457: data_o = 32'hf84a4785 /* 0x16c4 */; - 1458: data_o = 32'h454ddc3e /* 0x16c8 */; - 1459: data_o = 32'hfc0908e3 /* 0x16cc */; - 1460: data_o = 32'he5e34551 /* 0x16d0 */; - 1461: data_o = 32'h3517fd24 /* 0x16d4 */; - 1462: data_o = 32'h05130100 /* 0x16d8 */; - 1463: data_o = 32'hf42a92a5 /* 0x16dc */; - 1464: data_o = 32'h8f2ff0ef /* 0x16e0 */; - 1465: data_o = 32'h000f17b7 /* 0x16e4 */; - 1466: data_o = 32'hf0f78793 /* 0x16e8 */; - 1467: data_o = 32'hca26c84a /* 0x16ec */; - 1468: data_o = 32'h1e23cc3e /* 0x16f0 */; - 1469: data_o = 32'h65c20001 /* 0x16f4 */; - 1470: data_o = 32'h46856662 /* 0x16f8 */; - 1471: data_o = 32'he0ef1028 /* 0x16fc */; - 1472: data_o = 32'h2501cf1f /* 0x1700 */; - 1473: data_o = 32'h3797fd41 /* 0x1704 */; - 1474: data_o = 32'h87930100 /* 0x1708 */; - 1475: data_o = 32'h07378fa7 /* 0x170c */; - 1476: data_o = 32'hcb988000 /* 0x1710 */; - 1477: data_o = 32'h01003797 /* 0x1714 */; - 1478: data_o = 32'h8ec78793 /* 0x1718 */; - 1479: data_o = 32'h07374b9c /* 0x171c */; - 1480: data_o = 32'h177de000 /* 0x1720 */; - 1481: data_o = 32'h07378ff9 /* 0x1724 */; - 1482: data_o = 32'h8fd92000 /* 0x1728 */; - 1483: data_o = 32'h01003717 /* 0x172c */; - 1484: data_o = 32'h8d470713 /* 0x1730 */; - 1485: data_o = 32'h0793cb1c /* 0x1734 */; - 1486: data_o = 32'h053315e0 /* 0x1738 */; - 1487: data_o = 32'h47b702f4 /* 0x173c */; - 1488: data_o = 32'h8793000f /* 0x1740 */; - 1489: data_o = 32'h55332407 /* 0x1744 */; - 1490: data_o = 32'h050502f5 /* 0x1748 */; - 1491: data_o = 32'h9c3fe0ef /* 0x174c */; - 1492: data_o = 32'hfffff517 /* 0x1750 */; - 1493: data_o = 32'h0513102c /* 0x1754 */; - 1494: data_o = 32'hbf3d3de5 /* 0x1758 */; - 1495: data_o = 32'hdc9d4549 /* 0x175c */; - 1496: data_o = 32'h3b9ad5b7 /* 0x1760 */; - 1497: data_o = 32'ha0058593 /* 0x1764 */; - 1498: data_o = 32'h0295d5b3 /* 0x1768 */; - 1499: data_o = 32'h01002797 /* 0x176c */; - 1500: data_o = 32'h89478793 /* 0x1770 */; - 1501: data_o = 32'h2797f43e /* 0x1774 */; - 1502: data_o = 32'h87930100 /* 0x1778 */; - 1503: data_o = 32'h4b9888a7 /* 0x177c */; - 1504: data_o = 32'h01002797 /* 0x1780 */; - 1505: data_o = 32'h88078793 /* 0x1784 */; - 1506: data_o = 32'hcb989b79 /* 0x1788 */; - 1507: data_o = 32'h01002797 /* 0x178c */; - 1508: data_o = 32'h87478793 /* 0x1790 */; - 1509: data_o = 32'h27975398 /* 0x1794 */; - 1510: data_o = 32'h87930100 /* 0x1798 */; - 1511: data_o = 32'h671386a7 /* 0x179c */; - 1512: data_o = 32'hd3980807 /* 0x17a0 */; - 1513: data_o = 32'h01002797 /* 0x17a4 */; - 1514: data_o = 32'h85c78793 /* 0x17a8 */; - 1515: data_o = 32'h27975398 /* 0x17ac */; - 1516: data_o = 32'h87930100 /* 0x17b0 */; - 1517: data_o = 32'h67138527 /* 0x17b4 */; - 1518: data_o = 32'hd3980027 /* 0x17b8 */; - 1519: data_o = 32'h01002797 /* 0x17bc */; - 1520: data_o = 32'h84478793 /* 0x17c0 */; - 1521: data_o = 32'h27975398 /* 0x17c4 */; - 1522: data_o = 32'h87930100 /* 0x17c8 */; - 1523: data_o = 32'h671383a7 /* 0x17cc */; - 1524: data_o = 32'hd3980017 /* 0x17d0 */; - 1525: data_o = 32'h01002797 /* 0x17d4 */; - 1526: data_o = 32'h82c78793 /* 0x17d8 */; - 1527: data_o = 32'h27975398 /* 0x17dc */; - 1528: data_o = 32'h87930100 /* 0x17e0 */; - 1529: data_o = 32'h67138227 /* 0x17e4 */; - 1530: data_o = 32'h05131007 /* 0x17e8 */; - 1531: data_o = 32'h06135130 /* 0x17ec */; - 1532: data_o = 32'hd3980630 /* 0x17f0 */; - 1533: data_o = 32'h07136685 /* 0x17f4 */; - 1534: data_o = 32'h869b12b0 /* 0x17f8 */; - 1535: data_o = 32'h07939c36 /* 0x17fc */; - 1536: data_o = 32'h553b2570 /* 0x1800 */; - 1537: data_o = 32'h563b02b5 /* 0x1804 */; - 1538: data_o = 32'h154202b6 /* 0x1808 */; - 1539: data_o = 32'h081b9141 /* 0x180c */; - 1540: data_o = 32'h181b0015 /* 0x1810 */; - 1541: data_o = 32'h573b0108 /* 0x1814 */; - 1542: data_o = 32'h260502b7 /* 0x1818 */; - 1543: data_o = 32'h92411642 /* 0x181c */; - 1544: data_o = 32'h02b6d6bb /* 0x1820 */; - 1545: data_o = 32'h17422705 /* 0x1824 */; - 1546: data_o = 32'hd7bb9341 /* 0x1828 */; - 1547: data_o = 32'h9e8902b7 /* 0x182c */; - 1548: data_o = 32'h9e999e91 /* 0x1830 */; - 1549: data_o = 32'h16c285b6 /* 0x1834 */; - 1550: data_o = 32'h278592c1 /* 0x1838 */; - 1551: data_o = 32'h93c117c2 /* 0x183c */; - 1552: data_o = 32'h00f6f363 /* 0x1840 */; - 1553: data_o = 32'h959b85be /* 0x1844 */; - 1554: data_o = 32'hd59b0105 /* 0x1848 */; - 1555: data_o = 32'he5b30105 /* 0x184c */; - 1556: data_o = 32'h16970105 /* 0x1850 */; - 1557: data_o = 32'h25810100 /* 0x1854 */; - 1558: data_o = 32'h7ae68693 /* 0x1858 */; - 1559: data_o = 32'h0107171b /* 0x185c */; - 1560: data_o = 32'h8f51da8c /* 0x1860 */; - 1561: data_o = 32'h01001697 /* 0x1864 */; - 1562: data_o = 32'h86932701 /* 0x1868 */; - 1563: data_o = 32'hdad879c6 /* 0x186c */; - 1564: data_o = 32'h0107971b /* 0x1870 */; - 1565: data_o = 32'h16978f5d /* 0x1874 */; - 1566: data_o = 32'h27010100 /* 0x1878 */; - 1567: data_o = 32'h78a68693 /* 0x187c */; - 1568: data_o = 32'h6741de98 /* 0x1880 */; - 1569: data_o = 32'h17178e59 /* 0x1884 */; - 1570: data_o = 32'h07130100 /* 0x1888 */; - 1571: data_o = 32'hdf5077a7 /* 0x188c */; - 1572: data_o = 32'h0107e7b3 /* 0x1890 */; - 1573: data_o = 32'h01001717 /* 0x1894 */; - 1574: data_o = 32'h07132781 /* 0x1898 */; - 1575: data_o = 32'hc33c76c7 /* 0x189c */; - 1576: data_o = 32'h01001797 /* 0x18a0 */; - 1577: data_o = 32'h76078793 /* 0x18a4 */; - 1578: data_o = 32'h17974b98 /* 0x18a8 */; - 1579: data_o = 32'h87930100 /* 0x18ac */; - 1580: data_o = 32'h67137567 /* 0x18b0 */; - 1581: data_o = 32'hf5170017 /* 0x18b4 */; - 1582: data_o = 32'hcb98ffff /* 0x18b8 */; - 1583: data_o = 32'h0513102c /* 0x18bc */; - 1584: data_o = 32'hbbd9ac05 /* 0x18c0 */; - 1585: data_o = 32'h70e67446 /* 0x18c4 */; - 1586: data_o = 32'h790674a6 /* 0x18c8 */; - 1587: data_o = 32'h610969e6 /* 0x18cc */; - 1588: data_o = 32'he23fe06f /* 0x18d0 */; - 1589: data_o = 32'h00000000 /* 0x18d4 */; - 1590: data_o = 32'h00000000 /* 0x18d8 */; + 1011: data_o = 32'heca67159 /* 0x0fcc */; + 1012: data_o = 32'he8ca84ae /* 0x0fd0 */; + 1013: data_o = 32'hf0a2f486 /* 0x0fd4 */; + 1014: data_o = 32'he0d2e4ce /* 0x0fd8 */; + 1015: data_o = 32'hf85afc56 /* 0x0fdc */; + 1016: data_o = 32'h46a1892a /* 0x0fe0 */; + 1017: data_o = 32'h20000613 /* 0x0fe4 */; + 1018: data_o = 32'h8526100c /* 0x0fe8 */; + 1019: data_o = 32'hed519902 /* 0x0fec */; + 1020: data_o = 32'h00001797 /* 0x0ff0 */; + 1021: data_o = 32'hb7837702 /* 0x0ff4 */; + 1022: data_o = 32'h1863c187 /* 0x0ff8 */; + 1023: data_o = 32'h46c108f7 /* 0x0ffc */; + 1024: data_o = 32'h24800613 /* 0x1000 */; + 1025: data_o = 32'h8526858a /* 0x1004 */; + 1026: data_o = 32'h87aa9902 /* 0x1008 */; + 1027: data_o = 32'h47a2ed69 /* 0x100c */; + 1028: data_o = 32'h05f00993 /* 0x1010 */; + 1029: data_o = 32'hcfad4a01 /* 0x1014 */; + 1030: data_o = 32'h0a934b01 /* 0x1018 */; + 1031: data_o = 32'h678305f0 /* 0x101c */; + 1032: data_o = 32'h640200c1 /* 0x1020 */; + 1033: data_o = 32'h87b346c1 /* 0x1024 */; + 1034: data_o = 32'h04260367 /* 0x1028 */; + 1035: data_o = 32'h8526080c /* 0x102c */; + 1036: data_o = 32'h0613943e /* 0x1030 */; + 1037: data_o = 32'h99020204 /* 0x1034 */; + 1038: data_o = 32'h46c187aa /* 0x1038 */; + 1039: data_o = 32'h100c8622 /* 0x103c */; + 1040: data_o = 32'he3d58526 /* 0x1040 */; + 1041: data_o = 32'h67e26742 /* 0x1044 */; + 1042: data_o = 32'h000b1863 /* 0x1048 */; + 1043: data_o = 32'h05f70993 /* 0x104c */; + 1044: data_o = 32'h0137f363 /* 0x1050 */; + 1045: data_o = 32'h8a3a89be /* 0x1054 */; + 1046: data_o = 32'hec638f99 /* 0x1058 */; + 1047: data_o = 32'h990200fa /* 0x105c */; + 1048: data_o = 32'he15187aa /* 0x1060 */; + 1049: data_o = 32'h00001797 /* 0x1064 */; + 1050: data_o = 32'hbac7b783 /* 0x1068 */; + 1051: data_o = 32'h07637702 /* 0x106c */; + 1052: data_o = 32'h678308f7 /* 0x1070 */; + 1053: data_o = 32'h0b050081 /* 0x1074 */; + 1054: data_o = 32'hfafb43e3 /* 0x1078 */; + 1055: data_o = 32'h00816783 /* 0x107c */; + 1056: data_o = 32'h00fb0863 /* 0x1080 */; + 1057: data_o = 32'h69e26a42 /* 0x1084 */; + 1058: data_o = 32'h0993a021 /* 0x1088 */; + 1059: data_o = 32'h4a0105f0 /* 0x108c */; + 1060: data_o = 32'h00198693 /* 0x1090 */; + 1061: data_o = 32'h414686b3 /* 0x1094 */; + 1062: data_o = 32'h0dfff597 /* 0x1098 */; + 1063: data_o = 32'h161306a6 /* 0x109c */; + 1064: data_o = 32'h8593009a /* 0x10a0 */; + 1065: data_o = 32'h8526f685 /* 0x10a4 */; + 1066: data_o = 32'h87aa9902 /* 0x10a8 */; + 1067: data_o = 32'h6913ed0d /* 0x10ac */; + 1068: data_o = 32'h29010019 /* 0x10b0 */; + 1069: data_o = 32'h00fff797 /* 0x10b4 */; + 1070: data_o = 32'hf527a623 /* 0x10b8 */; + 1071: data_o = 32'h00fff797 /* 0x10bc */; + 1072: data_o = 32'hf4478793 /* 0x10c0 */; + 1073: data_o = 32'hc3c42481 /* 0x10c4 */; + 1074: data_o = 32'hf797870e /* 0x10c8 */; + 1075: data_o = 32'h270100ff /* 0x10cc */; + 1076: data_o = 32'hf3678793 /* 0x10d0 */; + 1077: data_o = 32'h100fc7d8 /* 0x10d4 */; + 1078: data_o = 32'hf0970000 /* 0x10d8 */; + 1079: data_o = 32'h80e70dff /* 0x10dc */; + 1080: data_o = 32'h079bf260 /* 0x10e0 */; + 1081: data_o = 32'h70a60005 /* 0x10e4 */; + 1082: data_o = 32'h64e67406 /* 0x10e8 */; + 1083: data_o = 32'h69a66946 /* 0x10ec */; + 1084: data_o = 32'h7ae26a06 /* 0x10f0 */; + 1085: data_o = 32'h853e7b42 /* 0x10f4 */; + 1086: data_o = 32'h80826165 /* 0x10f8 */; + 1087: data_o = 32'h00001797 /* 0x10fc */; + 1088: data_o = 32'hb1c7b783 /* 0x1100 */; + 1089: data_o = 32'h16e37722 /* 0x1104 */; + 1090: data_o = 32'hbf8df6f7 /* 0x1108 */; + 1091: data_o = 32'hd4010113 /* 0x110c */; + 1092: data_o = 32'h29613023 /* 0x1110 */; + 1093: data_o = 32'h00d60b33 /* 0x1114 */; + 1094: data_o = 32'h29513423 /* 0x1118 */; + 1095: data_o = 32'h27713c23 /* 0x111c */; + 1096: data_o = 32'h27a13023 /* 0x1120 */; + 1097: data_o = 32'h2a113c23 /* 0x1124 */; + 1098: data_o = 32'h2a813823 /* 0x1128 */; + 1099: data_o = 32'h2a913423 /* 0x112c */; + 1100: data_o = 32'h2b213023 /* 0x1130 */; + 1101: data_o = 32'h29313c23 /* 0x1134 */; + 1102: data_o = 32'h29413823 /* 0x1138 */; + 1103: data_o = 32'h27813823 /* 0x113c */; + 1104: data_o = 32'h27913423 /* 0x1140 */; + 1105: data_o = 32'h25b13c23 /* 0x1144 */; + 1106: data_o = 32'h1ffb7b13 /* 0x1148 */; + 1107: data_o = 32'h8aae8d2a /* 0x114c */; + 1108: data_o = 32'h1ff67b93 /* 0x1150 */; + 1109: data_o = 32'h000b1463 /* 0x1154 */; + 1110: data_o = 32'h20000b13 /* 0x1158 */; + 1111: data_o = 32'h1ff68413 /* 0x115c */; + 1112: data_o = 32'h0793945e /* 0x1160 */; + 1113: data_o = 32'h8025faa0 /* 0x1164 */; + 1114: data_o = 32'h02f102a3 /* 0x1168 */; + 1115: data_o = 32'h24040a63 /* 0x116c */; + 1116: data_o = 32'h0b634785 /* 0x1170 */; + 1117: data_o = 32'h059310f4 /* 0x1174 */; + 1118: data_o = 32'h82250520 /* 0x1178 */; + 1119: data_o = 32'h0186579b /* 0x117c */; + 1120: data_o = 32'h0ff67693 /* 0x1180 */; + 1121: data_o = 32'h07a21682 /* 0x1184 */; + 1122: data_o = 32'h06b78fd5 /* 0x1188 */; + 1123: data_o = 32'h571b00ff /* 0x118c */; + 1124: data_o = 32'h8e750086 /* 0x1190 */; + 1125: data_o = 32'h57fd8e5d /* 0x1194 */; + 1126: data_o = 32'h93810762 /* 0x1198 */; + 1127: data_o = 32'h8e5d8ff9 /* 0x119c */; + 1128: data_o = 32'he8b28e4d /* 0x11a0 */; + 1129: data_o = 32'h05130894 /* 0x11a4 */; + 1130: data_o = 32'h47010551 /* 0x11a8 */; + 1131: data_o = 32'h05418593 /* 0x11ac */; + 1132: data_o = 32'h0006c783 /* 0x11b0 */; + 1133: data_o = 32'h0017171b /* 0x11b4 */; + 1134: data_o = 32'h8fb90685 /* 0x11b8 */; + 1135: data_o = 32'h0ff7f793 /* 0x11bc */; + 1136: data_o = 32'hc70397ae /* 0x11c0 */; + 1137: data_o = 32'h15e30007 /* 0x11c4 */; + 1138: data_o = 32'h1793fed5 /* 0x11c8 */; + 1139: data_o = 32'he7930017 /* 0x11cc */; + 1140: data_o = 32'h17a20017 /* 0x11d0 */; + 1141: data_o = 32'he8828fd1 /* 0x11d4 */; + 1142: data_o = 32'h2583f43e /* 0x11d8 */; + 1143: data_o = 32'h478d010d /* 0x11dc */; + 1144: data_o = 32'h103cc8be /* 0x11e0 */; + 1145: data_o = 32'h4685f0be /* 0x11e4 */; + 1146: data_o = 32'h08904799 /* 0x11e8 */; + 1147: data_o = 32'hec82856a /* 0x11ec */; + 1148: data_o = 32'hf4bef882 /* 0x11f0 */; + 1149: data_o = 32'hb45ff0ef /* 0x11f4 */; + 1150: data_o = 32'h00050d9b /* 0x11f8 */; + 1151: data_o = 32'h040d9863 /* 0x11fc */; + 1152: data_o = 32'h02814703 /* 0x1200 */; + 1153: data_o = 32'h04c00793 /* 0x1204 */; + 1154: data_o = 32'h010d2583 /* 0x1208 */; + 1155: data_o = 32'h20f70e63 /* 0x120c */; + 1156: data_o = 32'h4a1144a1 /* 0x1210 */; + 1157: data_o = 32'h02510993 /* 0x1214 */; + 1158: data_o = 32'ha0294905 /* 0x1218 */; + 1159: data_o = 32'h02510783 /* 0x121c */; + 1160: data_o = 32'h0607d763 /* 0x1220 */; + 1161: data_o = 32'h010d2583 /* 0x1224 */; + 1162: data_o = 32'h4685e882 /* 0x1228 */; + 1163: data_o = 32'h856a0890 /* 0x122c */; + 1164: data_o = 32'hf882ec82 /* 0x1230 */; + 1165: data_o = 32'hf0cec8d2 /* 0x1234 */; + 1166: data_o = 32'hf0eff4ca /* 0x1238 */; + 1167: data_o = 32'h0d9bafff /* 0x123c */; + 1168: data_o = 32'h34fd0005 /* 0x1240 */; + 1169: data_o = 32'h000d9463 /* 0x1244 */; + 1170: data_o = 32'h4dc9f8f1 /* 0x1248 */; + 1171: data_o = 32'h2b813083 /* 0x124c */; + 1172: data_o = 32'h2b013403 /* 0x1250 */; + 1173: data_o = 32'h2a813483 /* 0x1254 */; + 1174: data_o = 32'h2a013903 /* 0x1258 */; + 1175: data_o = 32'h29813983 /* 0x125c */; + 1176: data_o = 32'h29013a03 /* 0x1260 */; + 1177: data_o = 32'h28813a83 /* 0x1264 */; + 1178: data_o = 32'h28013b03 /* 0x1268 */; + 1179: data_o = 32'h27813b83 /* 0x126c */; + 1180: data_o = 32'h27013c03 /* 0x1270 */; + 1181: data_o = 32'h26813c83 /* 0x1274 */; + 1182: data_o = 32'h26013d03 /* 0x1278 */; + 1183: data_o = 32'h3d83856e /* 0x127c */; + 1184: data_o = 32'h01132581 /* 0x1280 */; + 1185: data_o = 32'h80822c01 /* 0x1284 */; + 1186: data_o = 32'h05100593 /* 0x1288 */; + 1187: data_o = 32'h37b3b5fd /* 0x128c */; + 1188: data_o = 32'h6c850170 /* 0x1290 */; + 1189: data_o = 32'h8793ec3e /* 0x1294 */; + 1190: data_o = 32'he43e800c /* 0x1298 */; + 1191: data_o = 32'h97de089c /* 0x129c */; + 1192: data_o = 32'h417a8ab3 /* 0x12a0 */; + 1193: data_o = 32'he83e4c01 /* 0x12a4 */; + 1194: data_o = 32'h0c936709 /* 0x12a8 */; + 1195: data_o = 32'h49917107 /* 0x12ac */; + 1196: data_o = 32'h02510913 /* 0x12b0 */; + 1197: data_o = 32'h0a134485 /* 0x12b4 */; + 1198: data_o = 32'ha0390ff0 /* 0x12b8 */; + 1199: data_o = 32'h160c8463 /* 0x12bc */; + 1200: data_o = 32'h02514683 /* 0x12c0 */; + 1201: data_o = 32'h03469563 /* 0x12c4 */; + 1202: data_o = 32'h010d2583 /* 0x12c8 */; + 1203: data_o = 32'h4685f402 /* 0x12cc */; + 1204: data_o = 32'h856a1030 /* 0x12d0 */; + 1205: data_o = 32'he482f802 /* 0x12d4 */; + 1206: data_o = 32'hfc4ad44e /* 0x12d8 */; + 1207: data_o = 32'hf0efe0a6 /* 0x12dc */; + 1208: data_o = 32'h0d9ba5bf /* 0x12e0 */; + 1209: data_o = 32'h3cfd0005 /* 0x12e4 */; + 1210: data_o = 32'hfc0d8ae3 /* 0x12e8 */; + 1211: data_o = 32'h0713b785 /* 0x12ec */; + 1212: data_o = 32'h91630fe0 /* 0x12f0 */; + 1213: data_o = 32'h0e6318e6 /* 0x12f4 */; + 1214: data_o = 32'h0713100c /* 0x12f8 */; + 1215: data_o = 32'h0163fff4 /* 0x12fc */; + 1216: data_o = 32'h88d610ec /* 0x1300 */; + 1217: data_o = 32'h8cc6e002 /* 0x1304 */; + 1218: data_o = 32'h20088a13 /* 0x1308 */; + 1219: data_o = 32'h491189c6 /* 0x130c */; + 1220: data_o = 32'h10000493 /* 0x1310 */; + 1221: data_o = 32'hf802f402 /* 0x1314 */; + 1222: data_o = 32'h0a098663 /* 0x1318 */; + 1223: data_o = 32'hd44ae482 /* 0x131c */; + 1224: data_o = 32'he0a6fc4e /* 0x1320 */; + 1225: data_o = 32'h010d2583 /* 0x1324 */; + 1226: data_o = 32'h10304685 /* 0x1328 */; + 1227: data_o = 32'hf0ef856a /* 0x132c */; + 1228: data_o = 32'h2501a0bf /* 0x1330 */; + 1229: data_o = 32'h10098993 /* 0x1334 */; + 1230: data_o = 32'h1de3e171 /* 0x1338 */; + 1231: data_o = 32'hf402fd3a /* 0x133c */; + 1232: data_o = 32'h25834711 /* 0x1340 */; + 1233: data_o = 32'hd43a010d /* 0x1344 */; + 1234: data_o = 32'h02610713 /* 0x1348 */; + 1235: data_o = 32'h4685fc3a /* 0x134c */; + 1236: data_o = 32'h10304709 /* 0x1350 */; + 1237: data_o = 32'hf802856a /* 0x1354 */; + 1238: data_o = 32'he0bae482 /* 0x1358 */; + 1239: data_o = 32'h9ddff0ef /* 0x135c */; + 1240: data_o = 32'hed492501 /* 0x1360 */; + 1241: data_o = 32'h85934681 /* 0x1364 */; + 1242: data_o = 32'hc703e541 /* 0x1368 */; + 1243: data_o = 32'hd61b000c /* 0x136c */; + 1244: data_o = 32'h969b0086 /* 0x1370 */; + 1245: data_o = 32'h8f310086 /* 0x1374 */; + 1246: data_o = 32'h837d1702 /* 0x1378 */; + 1247: data_o = 32'h5703972e /* 0x137c */; + 1248: data_o = 32'h16c20007 /* 0x1380 */; + 1249: data_o = 32'h0c8592c1 /* 0x1384 */; + 1250: data_o = 32'h10e38eb9 /* 0x1388 */; + 1251: data_o = 32'h971bff9a /* 0x138c */; + 1252: data_o = 32'hd69b0086 /* 0x1390 */; + 1253: data_o = 32'h8f550086 /* 0x1394 */; + 1254: data_o = 32'h02615603 /* 0x1398 */; + 1255: data_o = 32'h93411742 /* 0x139c */; + 1256: data_o = 32'h0ce61d63 /* 0x13a0 */; + 1257: data_o = 32'hc7956782 /* 0x13a4 */; + 1258: data_o = 32'h015b8533 /* 0x13a8 */; + 1259: data_o = 32'h0a0d9863 /* 0x13ac */; + 1260: data_o = 32'h061365c2 /* 0x13b0 */; + 1261: data_o = 32'h06332000 /* 0x13b4 */; + 1262: data_o = 32'he0ef4176 /* 0x13b8 */; + 1263: data_o = 32'ha821d3ff /* 0x13bc */; + 1264: data_o = 32'hb5694d81 /* 0x13c0 */; + 1265: data_o = 32'hd43e4789 /* 0x13c4 */; + 1266: data_o = 32'he08267a2 /* 0x13c8 */; + 1267: data_o = 32'hfc3ee482 /* 0x13cc */; + 1268: data_o = 32'h9f63bf91 /* 0x13d0 */; + 1269: data_o = 32'h0c05060d /* 0x13d4 */; + 1270: data_o = 32'h200a8a93 /* 0x13d8 */; + 1271: data_o = 32'hed8416e3 /* 0x13dc */; + 1272: data_o = 32'h02634785 /* 0x13e0 */; + 1273: data_o = 32'h05930af4 /* 0x13e4 */; + 1274: data_o = 32'h15a20610 /* 0x13e8 */; + 1275: data_o = 32'h10344701 /* 0x13ec */; + 1276: data_o = 32'h85934605 /* 0x13f0 */; + 1277: data_o = 32'h856a04c5 /* 0x13f4 */; + 1278: data_o = 32'ha15ff0ef /* 0x13f8 */; + 1279: data_o = 32'hb5b98daa /* 0x13fc */; + 1280: data_o = 32'h20000713 /* 0x1400 */; + 1281: data_o = 32'heeeb0fe3 /* 0x1404 */; + 1282: data_o = 32'h0893e06e /* 0x1408 */; + 1283: data_o = 32'h4d850501 /* 0x140c */; + 1284: data_o = 32'h0b63bddd /* 0x1410 */; + 1285: data_o = 32'h85630494 /* 0x1414 */; + 1286: data_o = 32'h4785060b /* 0x1418 */; + 1287: data_o = 32'h0893e03e /* 0x141c */; + 1288: data_o = 32'hb5d50501 /* 0x1420 */; + 1289: data_o = 32'hb51d4de5 /* 0x1424 */; + 1290: data_o = 32'h4791e882 /* 0x1428 */; + 1291: data_o = 32'h0793c8be /* 0x142c */; + 1292: data_o = 32'hf0be0261 /* 0x1430 */; + 1293: data_o = 32'h47854685 /* 0x1434 */; + 1294: data_o = 32'h856a0890 /* 0x1438 */; + 1295: data_o = 32'hf882ec82 /* 0x143c */; + 1296: data_o = 32'hf0eff4be /* 0x1440 */; + 1297: data_o = 32'h0d9b8f7f /* 0x1444 */; + 1298: data_o = 32'h83e30005 /* 0x1448 */; + 1299: data_o = 32'hbbfddc0d /* 0x144c */; + 1300: data_o = 32'h088c865a /* 0x1450 */; + 1301: data_o = 32'he0ef8556 /* 0x1454 */; + 1302: data_o = 32'hbfb5ca3f /* 0x1458 */; + 1303: data_o = 32'h063365c2 /* 0x145c */; + 1304: data_o = 32'he0ef417b /* 0x1460 */; + 1305: data_o = 32'hbf85c97f /* 0x1464 */; + 1306: data_o = 32'h20000713 /* 0x1468 */; + 1307: data_o = 32'hfaeb05e3 /* 0x146c */; + 1308: data_o = 32'hbf596de2 /* 0x1470 */; + 1309: data_o = 32'h02000d93 /* 0x1474 */; + 1310: data_o = 32'h0d93bbd1 /* 0x1478 */; + 1311: data_o = 32'hb3f90210 /* 0x147c */; + 1312: data_o = 32'h88d6e002 /* 0x1480 */; + 1313: data_o = 32'h2783b549 /* 0x1484 */; + 1314: data_o = 32'h3703014d /* 0x1488 */; + 1315: data_o = 32'hd35c000d /* 0x148c */; + 1316: data_o = 32'hd79b4b5c /* 0x1490 */; + 1317: data_o = 32'hdfed01f7 /* 0x1494 */; + 1318: data_o = 32'hd71c479d /* 0x1498 */; + 1319: data_o = 32'hb37d4d81 /* 0x149c */; + 1320: data_o = 32'h07b7c689 /* 0x14a0 */; + 1321: data_o = 32'h963e0600 /* 0x14a4 */; + 1322: data_o = 32'h4501b195 /* 0x14a8 */; + 1323: data_o = 32'hf7978082 /* 0x14ac */; + 1324: data_o = 32'h711900ff /* 0x14b0 */; + 1325: data_o = 32'hb5278793 /* 0x14b4 */; + 1326: data_o = 32'ha903f0ca /* 0x14b8 */; + 1327: data_o = 32'hf7970107 /* 0x14bc */; + 1328: data_o = 32'h879300ff /* 0x14c0 */; + 1329: data_o = 32'hf8a2b427 /* 0x14c4 */; + 1330: data_o = 32'hf4a64bc0 /* 0x14c8 */; + 1331: data_o = 32'h1402ecce /* 0x14cc */; + 1332: data_o = 32'h85229001 /* 0x14d0 */; + 1333: data_o = 32'h2901fc86 /* 0x14d4 */; + 1334: data_o = 32'hfa3fe0ef /* 0x14d8 */; + 1335: data_o = 32'h84aa4989 /* 0x14dc */; + 1336: data_o = 32'h1d390863 /* 0x14e0 */; + 1337: data_o = 32'h0e63478d /* 0x14e4 */; + 1338: data_o = 32'h478526f9 /* 0x14e8 */; + 1339: data_o = 32'h3cf91f63 /* 0x14ec */; + 1340: data_o = 32'h016e37b7 /* 0x14f0 */; + 1341: data_o = 32'h60078713 /* 0x14f4 */; + 1342: data_o = 32'hec3ad002 /* 0x14f8 */; + 1343: data_o = 32'h8793d24e /* 0x14fc */; + 1344: data_o = 32'h45615ff7 /* 0x1500 */; + 1345: data_o = 32'h1897ff63 /* 0x1504 */; + 1346: data_o = 32'h01003517 /* 0x1508 */; + 1347: data_o = 32'haf850513 /* 0x150c */; + 1348: data_o = 32'hf0efe82a /* 0x1510 */; + 1349: data_o = 32'h17b7ac0f /* 0x1514 */; + 1350: data_o = 32'h87930003 /* 0x1518 */; + 1351: data_o = 32'hc03ed407 /* 0x151c */; + 1352: data_o = 32'h6582c226 /* 0x1520 */; + 1353: data_o = 32'h46014681 /* 0x1524 */; + 1354: data_o = 32'he4020808 /* 0x1528 */; + 1355: data_o = 32'hec3fe0ef /* 0x152c */; + 1356: data_o = 32'h18632501 /* 0x1530 */; + 1357: data_o = 32'h56921605 /* 0x1534 */; + 1358: data_o = 32'h66226582 /* 0x1538 */; + 1359: data_o = 32'he0ef0808 /* 0x153c */; + 1360: data_o = 32'h2501eb1f /* 0x1540 */; + 1361: data_o = 32'h14051f63 /* 0x1544 */; + 1362: data_o = 32'h01003797 /* 0x1548 */; + 1363: data_o = 32'hab878793 /* 0x154c */; + 1364: data_o = 32'h80000737 /* 0x1550 */; + 1365: data_o = 32'h3797cb98 /* 0x1554 */; + 1366: data_o = 32'h87930100 /* 0x1558 */; + 1367: data_o = 32'h4b9caaa7 /* 0x155c */; + 1368: data_o = 32'he0000737 /* 0x1560 */; + 1369: data_o = 32'h8ff9177d /* 0x1564 */; + 1370: data_o = 32'h20000737 /* 0x1568 */; + 1371: data_o = 32'h37178fd9 /* 0x156c */; + 1372: data_o = 32'h07130100 /* 0x1570 */; + 1373: data_o = 32'hcb1ca927 /* 0x1574 */; + 1374: data_o = 32'hf4025582 /* 0x1578 */; + 1375: data_o = 32'h05000793 /* 0x157c */; + 1376: data_o = 32'h10304685 /* 0x1580 */; + 1377: data_o = 32'hf8020808 /* 0x1584 */; + 1378: data_o = 32'he482e082 /* 0x1588 */; + 1379: data_o = 32'hfc3ed44e /* 0x158c */; + 1380: data_o = 32'hfa8ff0ef /* 0x1590 */; + 1381: data_o = 32'h16632501 /* 0x1594 */; + 1382: data_o = 32'h05931005 /* 0x1598 */; + 1383: data_o = 32'h15a20950 /* 0x159c */; + 1384: data_o = 32'h46854705 /* 0x15a0 */; + 1385: data_o = 32'h85934601 /* 0x15a4 */; + 1386: data_o = 32'h08080405 /* 0x15a8 */; + 1387: data_o = 32'h9c1ff0ef /* 0x15ac */; + 1388: data_o = 32'h0e051963 /* 0x15b0 */; + 1389: data_o = 32'h00000797 /* 0x15b4 */; + 1390: data_o = 32'h0aa01737 /* 0x15b8 */; + 1391: data_o = 32'h66c7b583 /* 0x15bc */; + 1392: data_o = 32'h07050732 /* 0x15c0 */; + 1393: data_o = 32'h46114685 /* 0x15c4 */; + 1394: data_o = 32'hf0ef0808 /* 0x15c8 */; + 1395: data_o = 32'he9719a3f /* 0x15cc */; + 1396: data_o = 32'h06500493 /* 0x15d0 */; + 1397: data_o = 32'h042314a2 /* 0x15d4 */; + 1398: data_o = 32'h84930321 /* 0x15d8 */; + 1399: data_o = 32'h47010774 /* 0x15dc */; + 1400: data_o = 32'h46014681 /* 0x15e0 */; + 1401: data_o = 32'h080885a6 /* 0x15e4 */; + 1402: data_o = 32'h985ff0ef /* 0x15e8 */; + 1403: data_o = 32'h0797e95d /* 0x15ec */; + 1404: data_o = 32'hb5830000 /* 0x15f0 */; + 1405: data_o = 32'h470163a7 /* 0x15f4 */; + 1406: data_o = 32'h46011034 /* 0x15f8 */; + 1407: data_o = 32'hf0ef0808 /* 0x15fc */; + 1408: data_o = 32'he14580ff /* 0x1600 */; + 1409: data_o = 32'h02814783 /* 0x1604 */; + 1410: data_o = 32'h0593fbf9 /* 0x1608 */; + 1411: data_o = 32'h15a20fd0 /* 0x160c */; + 1412: data_o = 32'h46814701 /* 0x1610 */; + 1413: data_o = 32'h8593460d /* 0x1614 */; + 1414: data_o = 32'h080807a5 /* 0x1618 */; + 1415: data_o = 32'h951ff0ef /* 0x161c */; + 1416: data_o = 32'h0797e149 /* 0x1620 */; + 1417: data_o = 32'hb5830000 /* 0x1624 */; + 1418: data_o = 32'h470160e7 /* 0x1628 */; + 1419: data_o = 32'h46014685 /* 0x162c */; + 1420: data_o = 32'hf0ef0808 /* 0x1630 */; + 1421: data_o = 32'he53593bf /* 0x1634 */; + 1422: data_o = 32'h093764c2 /* 0x1638 */; + 1423: data_o = 32'h197de000 /* 0x163c */; + 1424: data_o = 32'h6622489c /* 0x1640 */; + 1425: data_o = 32'hf7b30808 /* 0x1644 */; + 1426: data_o = 32'hc89c0127 /* 0x1648 */; + 1427: data_o = 32'h568267e2 /* 0x164c */; + 1428: data_o = 32'h6582c03e /* 0x1650 */; + 1429: data_o = 32'hd9bfe0ef /* 0x1654 */; + 1430: data_o = 32'he5212501 /* 0x1658 */; + 1431: data_o = 32'h65825692 /* 0x165c */; + 1432: data_o = 32'h08086622 /* 0x1660 */; + 1433: data_o = 32'hd8bfe0ef /* 0x1664 */; + 1434: data_o = 32'hed052501 /* 0x1668 */; + 1435: data_o = 32'h3e800513 /* 0x166c */; + 1436: data_o = 32'h02a40533 /* 0x1670 */; + 1437: data_o = 32'h0737489c /* 0x1674 */; + 1438: data_o = 32'hf7b32000 /* 0x1678 */; + 1439: data_o = 32'h8fd90127 /* 0x167c */; + 1440: data_o = 32'h47b7c89c /* 0x1680 */; + 1441: data_o = 32'h8793000f /* 0x1684 */; + 1442: data_o = 32'h55332407 /* 0x1688 */; + 1443: data_o = 32'h050502f5 /* 0x168c */; + 1444: data_o = 32'ha7ffe0ef /* 0x1690 */; + 1445: data_o = 32'h00000517 /* 0x1694 */; + 1446: data_o = 32'h0513080c /* 0x1698 */; + 1447: data_o = 32'hf0efe0c5 /* 0x169c */; + 1448: data_o = 32'h70e692ff /* 0x16a0 */; + 1449: data_o = 32'h74a67446 /* 0x16a4 */; + 1450: data_o = 32'h69e67906 /* 0x16a8 */; + 1451: data_o = 32'h80826109 /* 0x16ac */; + 1452: data_o = 32'h098967b7 /* 0x16b0 */; + 1453: data_o = 32'h8793fc02 /* 0x16b4 */; + 1454: data_o = 32'h59137ff7 /* 0x16b8 */; + 1455: data_o = 32'hf6630025 /* 0x16bc */; + 1456: data_o = 32'h693700a7 /* 0x16c0 */; + 1457: data_o = 32'h09130262 /* 0x16c4 */; + 1458: data_o = 32'h4785a009 /* 0x16c8 */; + 1459: data_o = 32'hdc3ef84a /* 0x16cc */; + 1460: data_o = 32'h08e3454d /* 0x16d0 */; + 1461: data_o = 32'h4551fc09 /* 0x16d4 */; + 1462: data_o = 32'hfd24e5e3 /* 0x16d8 */; + 1463: data_o = 32'h01003517 /* 0x16dc */; + 1464: data_o = 32'h92450513 /* 0x16e0 */; + 1465: data_o = 32'hf0eff42a /* 0x16e4 */; + 1466: data_o = 32'h17b78ecf /* 0x16e8 */; + 1467: data_o = 32'h8793000f /* 0x16ec */; + 1468: data_o = 32'hc84af0f7 /* 0x16f0 */; + 1469: data_o = 32'hcc3eca26 /* 0x16f4 */; + 1470: data_o = 32'h00011e23 /* 0x16f8 */; + 1471: data_o = 32'h666265c2 /* 0x16fc */; + 1472: data_o = 32'h10284685 /* 0x1700 */; + 1473: data_o = 32'hcebfe0ef /* 0x1704 */; + 1474: data_o = 32'hfd412501 /* 0x1708 */; + 1475: data_o = 32'h01003797 /* 0x170c */; + 1476: data_o = 32'h8f478793 /* 0x1710 */; + 1477: data_o = 32'h80000737 /* 0x1714 */; + 1478: data_o = 32'h3797cb98 /* 0x1718 */; + 1479: data_o = 32'h87930100 /* 0x171c */; + 1480: data_o = 32'h4b9c8e67 /* 0x1720 */; + 1481: data_o = 32'he0000737 /* 0x1724 */; + 1482: data_o = 32'h8ff9177d /* 0x1728 */; + 1483: data_o = 32'h20000737 /* 0x172c */; + 1484: data_o = 32'h37178fd9 /* 0x1730 */; + 1485: data_o = 32'h07130100 /* 0x1734 */; + 1486: data_o = 32'hcb1c8ce7 /* 0x1738 */; + 1487: data_o = 32'h15e00793 /* 0x173c */; + 1488: data_o = 32'h02f40533 /* 0x1740 */; + 1489: data_o = 32'h000f47b7 /* 0x1744 */; + 1490: data_o = 32'h24078793 /* 0x1748 */; + 1491: data_o = 32'h02f55533 /* 0x174c */; + 1492: data_o = 32'he0ef0505 /* 0x1750 */; + 1493: data_o = 32'hf5179bdf /* 0x1754 */; + 1494: data_o = 32'h102cffff /* 0x1758 */; + 1495: data_o = 32'h3d850513 /* 0x175c */; + 1496: data_o = 32'h4549bf3d /* 0x1760 */; + 1497: data_o = 32'hd5b7dc9d /* 0x1764 */; + 1498: data_o = 32'h85933b9a /* 0x1768 */; + 1499: data_o = 32'hd5b3a005 /* 0x176c */; + 1500: data_o = 32'h27970295 /* 0x1770 */; + 1501: data_o = 32'h87930100 /* 0x1774 */; + 1502: data_o = 32'hf43e88e7 /* 0x1778 */; + 1503: data_o = 32'h01002797 /* 0x177c */; + 1504: data_o = 32'h88478793 /* 0x1780 */; + 1505: data_o = 32'h27974b98 /* 0x1784 */; + 1506: data_o = 32'h87930100 /* 0x1788 */; + 1507: data_o = 32'h9b7987a7 /* 0x178c */; + 1508: data_o = 32'h2797cb98 /* 0x1790 */; + 1509: data_o = 32'h87930100 /* 0x1794 */; + 1510: data_o = 32'h539886e7 /* 0x1798 */; + 1511: data_o = 32'h01002797 /* 0x179c */; + 1512: data_o = 32'h86478793 /* 0x17a0 */; + 1513: data_o = 32'h08076713 /* 0x17a4 */; + 1514: data_o = 32'h2797d398 /* 0x17a8 */; + 1515: data_o = 32'h87930100 /* 0x17ac */; + 1516: data_o = 32'h53988567 /* 0x17b0 */; + 1517: data_o = 32'h01002797 /* 0x17b4 */; + 1518: data_o = 32'h84c78793 /* 0x17b8 */; + 1519: data_o = 32'h00276713 /* 0x17bc */; + 1520: data_o = 32'h2797d398 /* 0x17c0 */; + 1521: data_o = 32'h87930100 /* 0x17c4 */; + 1522: data_o = 32'h539883e7 /* 0x17c8 */; + 1523: data_o = 32'h01002797 /* 0x17cc */; + 1524: data_o = 32'h83478793 /* 0x17d0 */; + 1525: data_o = 32'h00176713 /* 0x17d4 */; + 1526: data_o = 32'h2797d398 /* 0x17d8 */; + 1527: data_o = 32'h87930100 /* 0x17dc */; + 1528: data_o = 32'h53988267 /* 0x17e0 */; + 1529: data_o = 32'h01002797 /* 0x17e4 */; + 1530: data_o = 32'h81c78793 /* 0x17e8 */; + 1531: data_o = 32'h10076713 /* 0x17ec */; + 1532: data_o = 32'h51300513 /* 0x17f0 */; + 1533: data_o = 32'h06300613 /* 0x17f4 */; + 1534: data_o = 32'h6685d398 /* 0x17f8 */; + 1535: data_o = 32'h12b00713 /* 0x17fc */; + 1536: data_o = 32'h9c36869b /* 0x1800 */; + 1537: data_o = 32'h25700793 /* 0x1804 */; + 1538: data_o = 32'h02b5553b /* 0x1808 */; + 1539: data_o = 32'h02b6563b /* 0x180c */; + 1540: data_o = 32'h91411542 /* 0x1810 */; + 1541: data_o = 32'h0015081b /* 0x1814 */; + 1542: data_o = 32'h0108181b /* 0x1818 */; + 1543: data_o = 32'h02b7573b /* 0x181c */; + 1544: data_o = 32'h16422605 /* 0x1820 */; + 1545: data_o = 32'hd6bb9241 /* 0x1824 */; + 1546: data_o = 32'h270502b6 /* 0x1828 */; + 1547: data_o = 32'h93411742 /* 0x182c */; + 1548: data_o = 32'h02b7d7bb /* 0x1830 */; + 1549: data_o = 32'h9e919e89 /* 0x1834 */; + 1550: data_o = 32'h85b69e99 /* 0x1838 */; + 1551: data_o = 32'h92c116c2 /* 0x183c */; + 1552: data_o = 32'h17c22785 /* 0x1840 */; + 1553: data_o = 32'hf36393c1 /* 0x1844 */; + 1554: data_o = 32'h85be00f6 /* 0x1848 */; + 1555: data_o = 32'h0105959b /* 0x184c */; + 1556: data_o = 32'h0105d59b /* 0x1850 */; + 1557: data_o = 32'h0105e5b3 /* 0x1854 */; + 1558: data_o = 32'h01001697 /* 0x1858 */; + 1559: data_o = 32'h86932581 /* 0x185c */; + 1560: data_o = 32'h171b7a86 /* 0x1860 */; + 1561: data_o = 32'hda8c0107 /* 0x1864 */; + 1562: data_o = 32'h16978f51 /* 0x1868 */; + 1563: data_o = 32'h27010100 /* 0x186c */; + 1564: data_o = 32'h79668693 /* 0x1870 */; + 1565: data_o = 32'h971bdad8 /* 0x1874 */; + 1566: data_o = 32'h8f5d0107 /* 0x1878 */; + 1567: data_o = 32'h01001697 /* 0x187c */; + 1568: data_o = 32'h86932701 /* 0x1880 */; + 1569: data_o = 32'hde987846 /* 0x1884 */; + 1570: data_o = 32'h8e596741 /* 0x1888 */; + 1571: data_o = 32'h01001717 /* 0x188c */; + 1572: data_o = 32'h77470713 /* 0x1890 */; + 1573: data_o = 32'he7b3df50 /* 0x1894 */; + 1574: data_o = 32'h17170107 /* 0x1898 */; + 1575: data_o = 32'h27810100 /* 0x189c */; + 1576: data_o = 32'h76670713 /* 0x18a0 */; + 1577: data_o = 32'h1797c33c /* 0x18a4 */; + 1578: data_o = 32'h87930100 /* 0x18a8 */; + 1579: data_o = 32'h4b9875a7 /* 0x18ac */; + 1580: data_o = 32'h01001797 /* 0x18b0 */; + 1581: data_o = 32'h75078793 /* 0x18b4 */; + 1582: data_o = 32'h00176713 /* 0x18b8 */; + 1583: data_o = 32'hfffff517 /* 0x18bc */; + 1584: data_o = 32'h102ccb98 /* 0x18c0 */; + 1585: data_o = 32'haba50513 /* 0x18c4 */; + 1586: data_o = 32'h7446bbd9 /* 0x18c8 */; + 1587: data_o = 32'h74a670e6 /* 0x18cc */; + 1588: data_o = 32'h69e67906 /* 0x18d0 */; + 1589: data_o = 32'he06f6109 /* 0x18d4 */; + 1590: data_o = 32'h0000e1df /* 0x18d8 */; 1591: data_o = 32'h00000000 /* 0x18dc */; 1592: data_o = 32'h10210000 /* 0x18e0 */; 1593: data_o = 32'h30632042 /* 0x18e4 */; diff --git a/sw/tests/helloworld.c b/sw/tests/helloworld.c index df250626a..d2e566eeb 100644 --- a/sw/tests/helloworld.c +++ b/sw/tests/helloworld.c @@ -12,6 +12,23 @@ #include "dif/uart.h" #include "params.h" #include "util.h" +#include "printf.h" +#include "hal/spi_s25fs512s.h" + + +#define DUMP_SIZE 64 +void dump_spi(spi_s25fs512s_t *device, uint64_t sector) { + uint8_t read_buf[512]; + + spi_s25fs512s_single_read(device, read_buf, sector*512, 512); + for (int i = 0; i < DUMP_SIZE; i++) { + if (i % 64 == 0) + printf("\r\n%04x : ", sector * 512 + i); + printf("%02x", read_buf[i]); + } + printf("\r\n"); +} + int main(void) { char str[] = "Hello World!\r\n"; @@ -20,5 +37,31 @@ int main(void) { uart_init(&__base_uart, reset_freq, 115200); uart_write_str(&__base_uart, str, sizeof(str)); uart_write_flush(&__base_uart); + + #ifdef TEST_DRAM + for(int i = 0; i < 1024*1024*128; i++) { + *reg32(&__base_dram, 4*i) = i; + } + for(int i = 0; i < 1024*1024*128; i++) { + if (i != *reg32(&__base_dram, 4*i)) { + printf("Error at %x\n", 4*i); + return 1; + } + } + #endif + + #ifdef DUMP_SPI + spi_s25fs512s_t device = { + .spi_freq = MIN(40 * 1000 * 1000, reset_freq / 4), // Up to quarter core freq or 40MHz + .csid = 1}; + + uint32_t init = spi_s25fs512s_init(&device, reset_freq); + printf("Dumping spi : \n\r"); + + for (int i = 0; i < 100; i++) + dump_spi(&device, i); + #endif + + printf("Done\n"); return 0; } diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc index 1eeda34eb..57a8e7fc4 100644 --- a/target/xilinx/constraints/cheshire.xdc +++ b/target/xilinx/constraints/cheshire.xdc @@ -13,21 +13,12 @@ set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux] # The net of which we get the 200 MHz single ended clock from the MIG -set MIG_CLK_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_clock_out]] -set MIG_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_sync_reset]] - set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]] ##################### # Timing Parameters # ##################### -# 333 MHz (max) DRAM Axi clock -set FPGA_TCK 3.0 - -# 200 MHz DRAM Generated clock -set DRAM_TCK 5.0 - # 50 MHz SoC clock set SOC_TCK 20.0 @@ -44,8 +35,15 @@ set UART_IO_SPEED 200.0 # Clocks # ########## +# Clk_wiz clocks +create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10] +create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20] +create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50] +create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100] + # System Clock -create_generated_clock -name clk_soc -source $MIG_CLK_SRC -divide_by 4 [get_nets soc_clk] +# [see in board.xdc] + # JTAG Clock create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] set_input_jitter clk_jtag 1.000 @@ -55,14 +53,7 @@ set_input_jitter clk_jtag 1.000 ################ # JTAG Clock is asynchronous to all other clocks -set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag] - -####################### -# Placement Overrides # -####################### - -# Accept suboptimal BUFG-BUFG cascades -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i] +set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} ######## # JTAG # @@ -77,13 +68,6 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK set_false_path -hold -from [get_ports jtag_trst_ni] -####### -# MIG # -####### - -set_max_delay -from $MIG_RST_SRC $FPGA_TCK -set_false_path -hold -from $MIG_RST_SRC - ######## # UART # ######## @@ -101,15 +85,6 @@ set_false_path -hold -to [get_ports uart_tx_o] # cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew set_property KEEP_HIERARCHY SOFT [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync] set_false_path -hold -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK - -################### -# Reset Generator # -################### - -set_max_delay -from $SOC_RST_SRC $SOC_TCK -set_false_path -hold -from $SOC_RST_SRC -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_xlnx_clk_wiz/inst/clkin1_ibufds/O] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index df3b7b1fb..8387ec19e 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -5,6 +5,29 @@ # Testmode is set to 0 during normal use set_case_analysis 0 [get_ports testmode_i] + +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +############# +# Sys clock # +############# + +create_clock -period 5 -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + + +############# +# Mig clock # +############# + +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period 5 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST 5 + ####### # VGA # ####### @@ -54,8 +77,8 @@ set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] ############### ## Clock Signal -# set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n -# set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p ## Buttons #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc index ce24bce9a..992b14c32 100644 --- a/target/xilinx/constraints/vcu128.xdc +++ b/target/xilinx/constraints/vcu128.xdc @@ -6,6 +6,35 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] + +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +############# +# Sys clock # +############# + +create_clock -period 10 -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +#create_clock -period 10 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST 10 + +set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK +set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK + + + ################################################################################# ############### diff --git a/target/xilinx/constraints/zcu102.xdc b/target/xilinx/constraints/zcu102.xdc index 1a2a1562f..66873965e 100644 --- a/target/xilinx/constraints/zcu102.xdc +++ b/target/xilinx/constraints/zcu102.xdc @@ -1,3 +1,31 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +############# +# Sys clock # +############# + +create_clock -period 8 -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period 8 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST 8 + + +################################################################################# + +############### +# ASSIGN PINS # +############### + ################################################# ### ZCU102 Rev1.0 Master XDC file 09-15-2016 #### ################################################# @@ -183,10 +211,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VC #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 #set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 -#set_property PACKAGE_PIN F21 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property PACKAGE_PIN G21 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 +#set_property PACKAGE_PIN F21 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -> CLK_125_N +#set_property IOSTANDARD LVDS_25 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -> CLK_125_N +#set_property PACKAGE_PIN G21 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -> CLK_125_P +#set_property IOSTANDARD LVDS_25 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -> CLK_125_P #set_property PACKAGE_PIN J20 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 #set_property PACKAGE_PIN J19 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 @@ -618,11 +646,11 @@ set_property IOSTANDARD LVCMOS33 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC #set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 #set_property PACKAGE_PIN AL6 [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 #set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property PACKAGE_PIN AL7 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property PACKAGE_PIN AL8 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 +set_property PACKAGE_PIN AL7 [get_ports "sys_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 => USER_SI570_N +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 => USER_SI570_N +set_property PACKAGE_PIN AL8 [get_ports "sys_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 => USER_SI570_P +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 => USER_SI570_P +#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 #set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 #set_property PACKAGE_PIN AK8 [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 #set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 diff --git a/target/xilinx/scripts/flash.tcl b/target/xilinx/scripts/flash.tcl new file mode 100644 index 000000000..f8c5113fc --- /dev/null +++ b/target/xilinx/scripts/flash.tcl @@ -0,0 +1,50 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nils Wistoff +# Noah Huetter +# + +set mcs_file flash_img.mcs +set file $::env(FILE) +set offset $::env(OFFSET) + +# Create flash configuration file +write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offset $file" \ + -checksum \ + -file $mcs_file + +# Open and connect HW manager +open_hw_manager +connect_hw_server -url $::env(HOST):$::env(PORT) -allow_non_jtag +current_hw_target [get_hw_targets $::env(HOST):$::env(PORT)/$::env(FPGA_PATH)] +set_property PARAM.FREQUENCY 15000000 [get_hw_targets $::env(HOST):$::env(PORT)/$::env(FPGA_PATH)] +open_hw_target +current_hw_device [get_hw_devices xcvu37p_0] + +# Add the SPI flash as configuration memory +set hw_device [get_hw_devices xcvu37p_0] +create_hw_cfgmem -hw_device $hw_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] +set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] +set_property PROGRAM.ADDRESS_RANGE {use_file} $hw_cfgmem +set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +set_property PROGRAM.PRM_FILE {} $hw_cfgmem +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem +set_property PROGRAM.BLANK_CHECK 0 $hw_cfgmem +set_property PROGRAM.ERASE 0 $hw_cfgmem +set_property PROGRAM.CFG_PROGRAM 1 $hw_cfgmem +set_property PROGRAM.VERIFY 0 $hw_cfgmem +set_property PROGRAM.CHECKSUM 0 $hw_cfgmem + +# Create bitstream to access SPI flash +create_hw_bitstream -hw_device $hw_device [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_device]; +program_hw_devices $hw_device; +refresh_hw_device $hw_device; + +# Program SPI flash +program_hw_cfgmem -hw_cfgmem $hw_cfgmem + +# Close connection +close_hw_manager \ No newline at end of file diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl index b274a61f6..bd90b0915 100644 --- a/target/xilinx/scripts/run.tcl +++ b/target/xilinx/scripts/run.tcl @@ -45,8 +45,8 @@ set_property top ${project}_top_xilinx [current_fileset] update_compile_order -fileset sources_1 -set_property strategy Flow_PerfOptimized_high [get_runs synth_1] -set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] +set_property strategy Flow_RuntimeOptimized [get_runs synth_1] +set_property strategy Flow_RuntimeOptimized [get_runs impl_1] set_property XPM_LIBRARIES XPM_MEMORY [current_project] diff --git a/target/xilinx/sim/run_simulation.tcl b/target/xilinx/sim/run_simulation.tcl index d73f41195..35752af10 100644 --- a/target/xilinx/sim/run_simulation.tcl +++ b/target/xilinx/sim/run_simulation.tcl @@ -6,8 +6,11 @@ #source ips/xlnx_mig_7_ddr3_ex/questa/compile.do #source ips/xlnx_mig_7_ddr3/questa/compile.do -source ips/xlnx_mig_ddr4_ex/questa/compile.do -source ips/xlnx_mig_ddr4/questa/compile.do + +#source ips/xlnx_mig_ddr4_ex/questa/compile.do +#source ips/xlnx_mig_ddr4/questa/compile.do +#source ips/xlnx_clk_wiz/questa/compile.do +#source ips/xlnx_vio/questa/compile.do source ../scripts/add_sources_vsim.tcl diff --git a/target/xilinx/sim/simulate.mk b/target/xilinx/sim/simulate.mk index 4230d0583..211131e05 100644 --- a/target/xilinx/sim/simulate.mk +++ b/target/xilinx/sim/simulate.mk @@ -4,11 +4,13 @@ # # Cyril Koenig +CHS_XIL_SIM_DIR ?= $(CHS_XIL_DIR)/sim + XILINX_SIMLIB_PATH ?= ~/xlib_questa-2022.3_vivado-2022.1 SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin -ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ips-names))) +ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) # Pre-generated/modified example projects (contain the simulation top level) ifeq ($(BOARD),vcu128) @@ -18,37 +20,37 @@ ifeq ($(BOARD),genesys2) ip-example-projects := xlnx_mig_7_ddr3_ex endif -ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ip-example-projects))) +ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects))) VIVADOENV_SIM := $(VIVADOENV) \ XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ SIMULATOR_PATH=$(SIMULATOR_PATH) \ GCC_PATH=$(GCC_PATH) \ - VIVADO_PROJECT=../${PROJECT}.xpr + VIVADO_PROJECT=$(CHS_XIL_DIR)/${PROJECT}.xpr VLOG_ARGS := -suppress 2583 -suppress 13314 # Fetch example projects at IIS (containing SRAM behavioral models) -sim/ips/%_ex/questa/compile.do: - tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C sim/ips +$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: + tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips # Generate simulation libraries $(XILINX_SIMLIB_PATH)/modelsim.ini: - cd sim && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" # -sim/ips/%/questa/compile.do: - cd sim && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" +$(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do: + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" -scripts/add_sources_vsim.tcl: - $(BENDER) script vsim -t sim -t test -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 $(bender-targets) --vlog-arg="$(VLOG_ARGS)" > $@ +$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl: + $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@ -sim: ${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) scripts/add_sources_vsim.tcl - mkdir -p sim/questa_lib - cp $(XILINX_SIMLIB_PATH)/modelsim.ini sim - chmod +w sim/modelsim.ini - cd sim && questa-2022.3 vsim -work work -do "run_simulation.tcl" +chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl + mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib + cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR) + chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini + cd $(CHS_XIL_SIM_DIR) && questa-2022.3 vsim -work work -do "run_simulation.tcl" -clean-sim: - rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini +chs-xil-clean-sim: + cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini .PHONY: clean-sim sim diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index c6acf86ec..c8837d5c1 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -126,7 +126,7 @@ module cheshire_top_xilinx RegAmoNumCuts : 1, RegAmoPostCut : 1, // RTC - RtcFreq : 1000000, + RtcFreq : 400000, // Features Bootrom : 1, Uart : 1, @@ -203,6 +203,28 @@ module cheshire_top_xilinx (* dont_touch = "yes" *) wire soc_clk; (* dont_touch = "yes" *) wire rst_n; + /////////////////// + // GPIOs // + /////////////////// + + // Tie off signals if no switches on the board +`ifndef USE_SWITCHES + logic testmode_i; + logic [1:0] boot_mode_i; + assign testmode_i = '0; + assign boot_mode_i = 2'b00; +`endif + + // Give VDD and GND to JTAG dongle +`ifdef USE_JTAG_VDDGND + assign jtag_vdd_o = '1; + assign jtag_gnd_o = '0; +`endif +`ifndef USE_JTAG_TRSTN + logic jtag_trst_ni; + assign jtag_trst_ni = '1; +`endif + ////////////////// // Clock Wizard // ////////////////// @@ -227,8 +249,8 @@ module cheshire_top_xilinx .clk_in1 ( sys_clk ), .reset ( '0 ), .clk_100 ( ), - .clk_50 ( soc_clk ), - .clk_20 ( ), + .clk_50 ( ), + .clk_20 ( soc_clk ), .clk_10 ( ) ); @@ -239,7 +261,7 @@ module cheshire_top_xilinx rstgen i_rstgen_main ( .clk_i ( soc_clk ), .rst_ni ( ~sys_rst ), - .test_mode_i ( test_mode_i ), + .test_mode_i ( testmode_i ), .rst_no ( rst_n ), .init_no ( ) // keep open ); @@ -249,38 +271,23 @@ module cheshire_top_xilinx /////////////////// logic vio_reset, vio_boot_mode_sel; - logic [1:0] vio_boot_mode; + logic [1:0] boot_mode, vio_boot_mode; +`ifdef USE_VIO xlnx_vio i_xlnx_vio ( .clk(soc_clk), .probe_out0(vio_reset), .probe_out1(vio_boot_mode), .probe_out2(vio_boot_mode_sel) ); - assign sys_rst = ~cpu_resetn | vio_reset; - assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; - - /////////////////// - // GPIOs // - /////////////////// - - // Tie off signals if no switches on the board -`ifndef USE_SWITCHES - logic testmode_i; - logic [1:0] boot_mode_i; - assign testmode_i = '0; - assign boot_mode_i = 2'b00; +`else + assign vio_reset = '0; + assign vio_boot_mode = '0; + assign vio_boot_mode_sel = '0; `endif - // Give VDD and GND to JTAG dongle -`ifdef USE_JTAG_VDDGND - assign jtag_vdd_o = '1; - assign jtag_gnd_o = '0; -`endif -`ifndef USE_JTAG_TRSTN - logic jtag_trst_ni; - assign jtag_trst_ni = '1; -`endif + assign sys_rst = ~cpu_resetn | vio_reset; + assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; ////////////// // DRAM MIG // @@ -289,12 +296,12 @@ module cheshire_top_xilinx `ifdef USE_DDR dram_wrapper #( .axi_soc_aw_chan_t ( axi_llc_aw_chan_t ), - .axi_soc_w_chan_t ( axi_llc_w_chan_t ), - .axi_soc_b_chan_t ( axi_llc_b_chan_t ), + .axi_soc_w_chan_t ( axi_llc_w_chan_t ), + .axi_soc_b_chan_t ( axi_llc_b_chan_t ), .axi_soc_ar_chan_t ( axi_llc_ar_chan_t ), - .axi_soc_r_chan_t ( axi_llc_r_chan_t ), - .axi_soc_req_t (axi_llc_req_t), - .axi_soc_resp_t (axi_llc_rsp_t) + .axi_soc_r_chan_t ( axi_llc_r_chan_t ), + .axi_soc_req_t ( axi_llc_req_t ), + .axi_soc_resp_t ( axi_llc_rsp_t ) ) i_dram_wrapper ( // Rst .sys_rst_i ( sys_rst ), @@ -400,7 +407,7 @@ module cheshire_top_xilinx logic [3:0] qspi_dqo_ts; logic [3:0] qspi_dqo; logic [SpihNumCs-1:0] qspi_cs_b; -logic [SpihNumCs-1:0] qspi_cs_b_ts; + logic [SpihNumCs-1:0] qspi_cs_b_ts; assign qspi_clk = spi_sck_soc; assign qspi_cs_b = spi_cs_soc; @@ -451,7 +458,7 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts; logic rtc_clk_d, rtc_clk_q; logic [15:0] counter_d, counter_q; - // Divide soc_clk (50 MHz) by 50 => 1 MHz RTC Clock + // Divide soc_clk (20 MHz) by 50 => 1 MHz RTC Clock always_comb begin counter_d = counter_q + 1; rtc_clk_d = rtc_clk_q; @@ -472,7 +479,6 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts; end end - ///////////////// // Fan Control // ///////////////// @@ -503,7 +509,6 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts; .rsp_o ( ext_rsp ) ); - ////////////////// // Cheshire SoC // ////////////////// diff --git a/target/xilinx/src/dram_wrapper.sv b/target/xilinx/src/dram_wrapper.sv index d5cbc964b..1d554a916 100644 --- a/target/xilinx/src/dram_wrapper.sv +++ b/target/xilinx/src/dram_wrapper.sv @@ -90,8 +90,10 @@ module dram_wrapper #( axi_soc_resp_t soc_spill_rsp, spill_resizer_rsp; // Signals after resizing - axi_ddr_req_t resizer_cdc_req, cdc_spill_req, spill_dram_req; - axi_ddr_resp_t resizer_cdc_rsp, cdc_spill_rsp, spill_dram_rsp; + axi_ddr_req_t resizer_cdc_req, cdc_spill_req; + axi_ddr_req_t spill_dram_req; + axi_ddr_resp_t resizer_cdc_rsp, cdc_spill_rsp; + axi_ddr_resp_t spill_dram_rsp; // Entry signals assign soc_spill_req = soc_req_i; diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh index 9e333bf75..adb3988cb 100644 --- a/target/xilinx/src/phy_definitions.svh +++ b/target/xilinx/src/phy_definitions.svh @@ -8,12 +8,10 @@ `define USE_RESET `define USE_JTAG `define USE_JTAG_VDDGND - `define USE_VIO `define USE_DDR4 `define USE_QSPI `define USE_STARTUPE3 - // DRAM runs at 200MHz - `define DDR_CLK_DIVIDER 4'h4 + `define USE_VIO `endif `ifdef TARGET_GENESYS2 @@ -23,17 +21,17 @@ `define USE_SD `define USE_SWITCHES `define USE_DDR3 - // DRAM runs at 200MHz - `define DDR_CLK_DIVIDER 4'h4 `define USE_FAN + `define USE_VIO `endif `ifdef TARGET_ZCU102 `define USE_RESET `define USE_JTAG `define USE_DDR4 - // DRAM runs at 100MHz - `define DDR_CLK_DIVIDER 4'h2 + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO `endif ///////////////////// @@ -74,8 +72,8 @@ `endif `define DDR3_INTF \ - output ddr3_ck_p, - output ddr3_ck_n, + output ddr3_ck_p, \ + output ddr3_ck_n, \ inout [31:0] ddr3_dq, \ inout [3:0] ddr3_dqs_n, \ inout [3:0] ddr3_dqs_p, \ diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 92ebe550f..cc893b072 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -10,7 +10,7 @@ CHS_XIL_DIR ?= $(CHS_ROOT)/target/xilinx VIVADO ?= vitis-2020.2 vivado PROJECT ?= cheshire -BOARD ?= genesys2 +BOARD ?= vcu128 ip-dir := $(CHS_XIL_DIR)/xilinx # Select board specific variables @@ -96,6 +96,9 @@ chs-xil-rebuild-top: find $(CHS_XIL_DIR)/xilinx -wholename "**/*.srcs/**/*.xci" | xargs -n 1 -I {} cp {} $(CHS_XIL_DIR) ${MAKE} $(bit) +chs-xil-flash: $(CHS_SW_DIR)/boot/linux.gpt.bin + $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) FILE=$(CHS_SW_DIR)/boot/linux.gpt.bin OFFSET=0 -source $(CHS_XIL_DIR)/scripts/program.tcl + # Bender script $(CHS_XIL_DIR)/scripts/add_sources.tcl: Bender.yml $(BENDER) script vivado $(xilinx_targs) > $@ diff --git a/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl b/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl index 135e45539..44b269a16 100644 --- a/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl +++ b/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl @@ -40,8 +40,10 @@ if {$::env(BOARD) eq "vcu128"} { CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ ] [get_ips $ipName] } + if {$::env(BOARD) eq "zcu102"} { - set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {300.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ @@ -52,7 +54,6 @@ if {$::env(BOARD) eq "zcu102"} { CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ - CONFIG.PRIM_SOURCE {No_buffer} \ CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ @@ -71,8 +72,10 @@ if {$::env(BOARD) eq "zcu102"} { CONFIG.CLKOUT4_PHASE_ERROR {77.836} \ ] [get_ips $ipName] } + if {$::env(BOARD) eq "genesys2"} { - set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {200.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ @@ -80,10 +83,9 @@ if {$::env(BOARD) eq "genesys2"} { CONFIG.CLK_OUT2_PORT {clk_50} \ CONFIG.CLK_OUT3_PORT {clk_20} \ CONFIG.CLK_OUT4_PORT {clk_10} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10} \ - CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ CONFIG.CLKIN1_JITTER_PS {50.0} \ CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj index d4b7ff634..8554a2782 100755 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj +++ b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj @@ -12,7 +12,7 @@ 4.1 No Buffer Use System Clock - ACTIVE HIGH + ACTIVE LOW FALSE 0 50 Ohms @@ -22,7 +22,7 @@ 1250 2.0V 4:1 - 100 + 200 0 800 1.000 diff --git a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl index c7393959f..a07e5a4b9 100644 --- a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl +++ b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl @@ -19,6 +19,7 @@ if {$::env(BOARD) eq "vcu128"} { set_property -dict [list CONFIG.C0.DDR4_Clamshell {true} \ CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ CONFIG.C0.DDR4_InputClockPeriod {10000} \ CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ @@ -32,10 +33,9 @@ if {$::env(BOARD) eq "vcu128"} { CONFIG.C0.CS_WIDTH {2} \ CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $ipName] + } elseif {$::env(BOARD) eq "zcu102"} { - set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset} \ - CONFIG.C0_CLOCK_BOARD_INTERFACE {user_si570_sysclk} \ - CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ + set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ CONFIG.C0.DDR4_TimePeriod {833} \ CONFIG.C0.DDR4_InputClockPeriod {3332} \ CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ @@ -45,11 +45,14 @@ if {$::env(BOARD) eq "vcu128"} { CONFIG.C0.DDR4_AxiDataWidth {128} \ CONFIG.C0.DDR4_AxiAddressWidth {29} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ CONFIG.C0.BANK_GROUP_WIDTH {1} \ CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $ipName] } + generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]