diff --git a/cheshire.mk b/cheshire.mk index 7d143de0..e769409d 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -58,7 +58,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= 0e70b230ea113c8d954329be5406b318cd62cc9a +CHS_NONFREE_COMMIT ?= 47fde27eda57f9566872d88baeaac156f3ea181f chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc index 921b3fe7..12bdfbf1 100644 --- a/target/xilinx/constraints/cheshire.xdc +++ b/target/xilinx/constraints/cheshire.xdc @@ -19,15 +19,9 @@ set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets # Timing Parameters # ##################### -# 50 MHz SoC clock -set SOC_TCK 20.0 - # 10 MHz (max) JTAG clock set JTAG_TCK 100.0 -# I2C High-speed mode is 3.2 Mb/s -set I2C_IO_SPEED 312.5 - # UART speed is at most 5 Mb/s set UART_IO_SPEED 200.0 diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 4d48f0b9..0c71ca6f 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -2,10 +2,25 @@ # BOARD SPECIFIC CONSTRAINTS # ############################## +##################### +# Timing Parameters # +##################### + +# 50 MHz SoC clock +set soc_clk clk_50 +set SOC_TCK 20.0 + +# I2C High-speed mode is 3.2 Mb/s +set I2C_IO_SPEED 312.5 + +########## +# Basics # +########## + # Testmode is set to 0 during normal use set_case_analysis 0 [get_ports testmode_i] - +# Remove annoying clk_mux set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux set_property CLOCK_BUFFER_TYPE NONE $all_in_mux @@ -26,7 +41,7 @@ set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} # Dram axi clock : ??? set MIG_TCK 5 -set MIG_RST [get_pins i_dram_wrapper/i_dram/dram_rst_o] +set MIG_RST [get_nets i_dram_wrapper/dram_rst_o] create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk] set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk} set_false_path -hold -through $MIG_RST @@ -37,24 +52,24 @@ set_max_delay -through $MIG_RST $MIG_TCK ######## set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK +set_max_delay -datapath -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $MIG_TCK ####### # VGA # ####### -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*] +# set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports vga*] +# set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*] ############ # Switches # ############ -set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}] -set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}] +set_input_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}] +set_input_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}] -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm] +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports fan_pwm] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports fan_pwm] set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* testmode_i}] set_false_path -hold -from [get_ports {boot_mode* fan_sw* testmode_i}] @@ -66,20 +81,20 @@ set_false_path -hold -to [get_ports fan_pwm] # SPIM # ######## -set_input_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_input_delay -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] -set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] +set_input_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_input_delay -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_output_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] +set_output_delay -max -clock $soc_clk [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] ####### # I2C # ####### -set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] +# set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] +# set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] -set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] +# set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] +# set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] ################################################################################# @@ -130,10 +145,10 @@ set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_r ## SD Card set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd_i }]; #IO_L8N_T1_D12_14 Sch=sd_cd set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd_o }]; #IO_L7N_T1_D10_14 Sch=sd_cmd -set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d_i }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0] -set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io_1 }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1] -set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io_2 }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2] -set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_cs }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3] +set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0] +set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1] +set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2] +set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3] set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk @@ -168,27 +183,27 @@ set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_scl #set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en ## VGA Connector -set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] -set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] -set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] -set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] -set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] - -set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] -set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] -set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] -set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] -set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] - -set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] -set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] -set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] -set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] -set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] - -set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs -set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs +# set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] +# set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] +# set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] +# set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] +# set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] + +# set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] +# set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] +# set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] +# set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] +# set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] +# set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] + +# set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] +# set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] +# set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] +# set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] +# set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] + +# set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs +# set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs ## HDMI in #set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec @@ -486,8 +501,8 @@ set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { jtag_t #set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3] ## IIC Bus -set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl -set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda +# set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl +# set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda ## Display Port IN #set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc index 03e40ff7..d675b720 100644 --- a/target/xilinx/constraints/vcu128.xdc +++ b/target/xilinx/constraints/vcu128.xdc @@ -29,7 +29,7 @@ set_max_delay -through $MIG_RST $MIG_TCK ######## set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK +set_max_delay -datapath -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $MIG_TCK ################################################################################# diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index 07c19188..ae3ea5ac 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -48,14 +48,11 @@ module cheshire_top_xilinx `endif `ifdef USE_SD - input logic sd_cd_i, // Card Detect - output logic sd_cmd_o, - inout logic sd_d_io_1, - inout logic sd_d_io_2, - output logic sd_cs, - input logic sd_d_i, - output logic sd_reset_o, - output logic sd_sclk_o, + input logic sd_cd_i, + output logic sd_cmd_o, + inout wire [3:0] sd_d_io, + output logic sd_reset_o, + output logic sd_sclk_o, `endif `ifdef USE_FAN @@ -368,25 +365,19 @@ module cheshire_top_xilinx (* mark_debug = "true" *) logic [1:0] spi_cs_en; (* mark_debug = "true" *) logic [3:0] spi_sd_en; - - ////////////////// - // SD // - ////////////////// - `ifdef USE_SD // Assert reset low => Apply power to the SD Card assign sd_reset_o = 1'b0; // SCK - SD CLK signal assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1; // CS - SD DAT3 signal - assign sd_cs = spi_cs_en[0] ? spi_cs_soc[0] : 1'b1; + assign sd_d_io[3] = spi_cs_en[0] ? spi_cs_soc[0] : 1'b1; // MOSI - SD CMD signal assign sd_cmd_o = spi_sd_en[0] ? spi_sd_soc_out[0] : 1'b1; // MISO - SD DAT0 signal - assign spi_sd_soc_in[1] = sd_d_i; + assign spi_sd_soc_in[1] = sd_d_io[0]; // SD DAT1 and DAT2 signal tie-off - Not used for SPI mode - assign sd_d_io_1 = 1'b1; - assign sd_d_io_2 = 1'b1; + assign sd_d_io[2:1] = 2'b11; // Bind input side of SoC low for output signals assign spi_sd_soc_in[0] = 1'b0; assign spi_sd_soc_in[2] = 1'b0; @@ -398,13 +389,13 @@ module cheshire_top_xilinx ////////////////// `ifdef USE_QSPI - (* mark_debug = "true" *) logic qspi_clk; - (* mark_debug = "true" *) logic qspi_clk_ts; - (* mark_debug = "true" *) logic [3:0] qspi_dqi; - (* mark_debug = "true" *) logic [3:0] qspi_dqo_ts; - (* mark_debug = "true" *) logic [3:0] qspi_dqo; - (* mark_debug = "true" *) logic [SpihNumCs-1:0] qspi_cs_b; - (* mark_debug = "true" *) logic [SpihNumCs-1:0] qspi_cs_b_ts; + logic qspi_clk; + logic qspi_clk_ts; + logic [3:0] qspi_dqi; + logic [3:0] qspi_dqo_ts; + logic [3:0] qspi_dqo; + logic [SpihNumCs-1:0] qspi_cs_b; + logic [SpihNumCs-1:0] qspi_cs_b_ts; assign qspi_clk = spi_sck_soc; assign qspi_cs_b = spi_cs_soc; @@ -564,13 +555,13 @@ module cheshire_top_xilinx .i2c_scl_i ( i2c_scl_soc_in ), .i2c_scl_en_o ( i2c_scl_en ), // SPI Uses internal signals that are always defined - .spih_sck_o ( spi_sck_soc ), - .spih_sck_en_o ( spi_sck_en ), - .spih_csb_o ( spi_cs_soc ), - .spih_csb_en_o ( spi_cs_en ), - .spih_sd_o ( spi_sd_soc_out ), - .spih_sd_en_o ( spi_sd_en ), - .spih_sd_i ( spi_sd_soc_in ), + .spih_sck_o ( spi_sck_soc ), + .spih_sck_en_o ( spi_sck_en ), + .spih_csb_o ( spi_cs_soc ), + .spih_csb_en_o ( spi_cs_en ), + .spih_sd_o ( spi_sd_soc_out ), + .spih_sd_en_o ( spi_sd_en ), + .spih_sd_i ( spi_sd_soc_in ), `ifdef USE_VGA .vga_hsync_o ( vga_hs ), .vga_vsync_o ( vga_vs ), diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 129c0385..aa27b62c 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -24,8 +24,10 @@ endif ifeq ($(BOARD),genesys2) XILINX_PART ?= xc7k325tffg900-2 XILINX_BOARD ?= digilentinc.com:genesys2:part0:1.1 - ips-names := xlnx_mig_7_ddr3 xlnx_clk_wiz xlnx_vio + XILINX_PORT ?= 3332 + XILINX_HOST ?= bordcomputer FPGA_PATH ?= xilinx_tcf/Digilent/200300A8C60DB + ips-names := xlnx_mig_7_ddr3 xlnx_clk_wiz xlnx_vio endif ifeq ($(BOARD),zcu102) XILINX_PART ?= xczu9eg-ffvb1156-2-e @@ -61,7 +63,7 @@ VIVADOENV ?= PROJECT=$(PROJECT) \ ROUTED_DCP=$(ROUTED_DCP) \ CHECK_TIMING=$(CHECK_TIMING) -MODE ?= gui +MODE ?= batch VIVADOFLAGS ?= -nojournal -mode $(MODE) chs-xil-all: $(bit) @@ -92,7 +94,7 @@ chs-xil-gui: chs-xil-program: #$(bit) @echo "Programming board $(BOARD) ($(XILINX_PART))" - cd $(CHS_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl + $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source $(CHS_XIL_DIR)/scripts/program.tcl chs-xil-clean: cd $(CHS_XIL_DIR) && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).srcs $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim