From f1579801b085bffccb6d349d0c094a5e33cae918 Mon Sep 17 00:00:00 2001
From: Thomas Benz <tbenz@iis.ee.ethz.ch>
Date: Fri, 4 Aug 2023 09:05:17 +0200
Subject: [PATCH] axi_to_reg: Filter zero strobe writes

---
 hw/future/axi_to_reg_v2.sv | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/hw/future/axi_to_reg_v2.sv b/hw/future/axi_to_reg_v2.sv
index 7ab7dbc5..6c760b68 100644
--- a/hw/future/axi_to_reg_v2.sv
+++ b/hw/future/axi_to_reg_v2.sv
@@ -60,8 +60,8 @@ module axi_to_reg_v2 #(
   logic      [NumBanks-1:0] mem_err;
 
   // sub reg buses
-  reg_req_t [NumBanks-1:0] reg_req;
-  reg_rsp_t [NumBanks-1:0] reg_rsp;
+  reg_req_t [NumBanks-1:0] reg_req, valid_req, zero_w_req;
+  reg_rsp_t [NumBanks-1:0] reg_rsp, valid_rsp, zero_w_rsp;
 
   // convert to TCDM first
   axi_to_detailed_mem #(
@@ -129,9 +129,29 @@ module axi_to_reg_v2 #(
       .reg_req_o ( reg_req    [i]      ),
       .reg_rsp_i ( reg_rsp    [i]      )
     );
+
+    // filter zero strobe writes early, directly ack them
+    reg_demux #(
+      .NoPorts ( 32'd2     ),
+      .req_t   ( reg_req_t ),
+      .rsp_t   ( reg_rsp_t )
+    ) i_reg_demux (
+      .clk_i,
+      .rst_ni,
+      .in_select_i ( reg_req[i].write & (reg_req[i].wstrb == '0) ),
+      .in_req_i    ( reg_req[i]                                  ),
+      .in_rsp_o    ( reg_rsp[i]                                  ),
+      .out_req_o   ( {zero_w_req[i], valid_req[i]}               ),
+      .out_rsp_i   ( {zero_w_rsp[i], valid_rsp[i]}               )
+    );
+
+    // ack zero strobe writes here
+    assign zero_w_rsp[i].ready = 1'b1;
+    assign zero_w_rsp[i].error = 1'b0;
+    assign zero_w_rsp[i].rdata = '0;
   end
 
-  // arbitrate over sub buses
+  // arbitrate over valid accesses in sub buses
   reg_mux #(
     .NoPorts( NumBanks     ),
     .AW     ( AxiAddrWidth ),
@@ -141,8 +161,8 @@ module axi_to_reg_v2 #(
   ) i_reg_mux (
     .clk_i,
     .rst_ni,
-    .in_req_i  ( reg_req   ),
-    .in_rsp_o  ( reg_rsp   ),
+    .in_req_i  ( valid_req ),
+    .in_rsp_o  ( valid_rsp ),
     .out_req_o ( reg_req_o ),
     .out_rsp_i ( reg_rsp_i )
   );