diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc
index 281442efb..4d48f0b94 100644
--- a/target/xilinx/constraints/genesys2.xdc
+++ b/target/xilinx/constraints/genesys2.xdc
@@ -130,10 +130,10 @@ set_property -dict { PACKAGE_PIN Y20   IOSTANDARD LVCMOS33 } [get_ports { uart_r
 ## SD Card
 set_property -dict { PACKAGE_PIN P28   IOSTANDARD LVCMOS33 } [get_ports { sd_cd_i }]; #IO_L8N_T1_D12_14 Sch=sd_cd
 set_property -dict { PACKAGE_PIN R29   IOSTANDARD LVCMOS33 } [get_ports { sd_cmd_o }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
-set_property -dict { PACKAGE_PIN R26   IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
-set_property -dict { PACKAGE_PIN R30   IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
-set_property -dict { PACKAGE_PIN P29   IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
-set_property -dict { PACKAGE_PIN T30   IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
+set_property -dict { PACKAGE_PIN R26   IOSTANDARD LVCMOS33 } [get_ports { sd_d_i }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
+set_property -dict { PACKAGE_PIN R30   IOSTANDARD LVCMOS33 } [get_ports { sd_d_io_1 }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
+set_property -dict { PACKAGE_PIN P29   IOSTANDARD LVCMOS33 } [get_ports { sd_d_io_2 }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
+set_property -dict { PACKAGE_PIN T30   IOSTANDARD LVCMOS33 } [get_ports { sd_cs      }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
 set_property -dict { PACKAGE_PIN AE24  IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
 set_property -dict { PACKAGE_PIN R28   IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
 
diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
index 03423da96..07c191888 100644
--- a/target/xilinx/src/cheshire_top_xilinx.sv
+++ b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -50,7 +50,10 @@ module cheshire_top_xilinx
 `ifdef USE_SD
   input  logic          sd_cd_i, // Card Detect
   output logic          sd_cmd_o,
-  inout  wire   [3:0]   sd_d_io,
+  inout  logic          sd_d_io_1,
+  inout  logic          sd_d_io_2,
+  output logic          sd_cs,
+  input  logic          sd_d_i,
   output logic          sd_reset_o,
   output logic          sd_sclk_o,
 `endif
@@ -376,13 +379,14 @@ module cheshire_top_xilinx
   // SCK  - SD CLK signal
   assign sd_sclk_o        = spi_sck_en    ? spi_sck_soc       : 1'b1;
   // CS   - SD DAT3 signal
-  assign sd_d_io[3]       = spi_cs_en[0]  ? spi_cs_soc[0]     : 1'b1;
+  assign sd_cs            = spi_cs_en[0]  ? spi_cs_soc[0]     : 1'b1;
   // MOSI - SD CMD signal
   assign sd_cmd_o         = spi_sd_en[0]  ? spi_sd_soc_out[0] : 1'b1;
   // MISO - SD DAT0 signal
-  assign spi_sd_soc_in[1] = sd_d_io[0];
+  assign spi_sd_soc_in[1] = sd_d_i;
   // SD DAT1 and DAT2 signal tie-off - Not used for SPI mode
-  assign sd_d_io[2:1]     = 2'b11;
+  assign sd_d_io_1        = 1'b1;
+  assign sd_d_io_2        = 1'b1;
   // Bind input side of SoC low for output signals
   assign spi_sd_soc_in[0] = 1'b0;
   assign spi_sd_soc_in[2] = 1'b0;