diff --git a/.gitignore b/.gitignore index db20a918..69693199 100644 --- a/.gitignore +++ b/.gitignore @@ -38,6 +38,17 @@ target/sim/vsim/transcript target/sim/vsim/vsim.wlf target/sim/vsim/work/ +# VCS generated files +target/sim/vcs/compile.*.sh +target/sim/vcs/*.log +target/sim/vcs/AN.DB +target/sim/vcs/simv* +target/sim/vcs/csrc +target/sim/vcs/ucli.key +target/sim/vcs/work* +target/sim/vcs/vc_hdrs.h + + # Xilinx generated files target/xilinx/build target/xilinx/out diff --git a/Bender.lock b/Bender.lock index 1b8a19a1..94673bfb 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,8 +15,8 @@ packages: - apb - register_interface axi: - revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2 - version: 0.39.2 + revision: d864a8ac8237675e946e5aef22e6105eebcac6ed + version: null source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -124,8 +124,8 @@ packages: dependencies: - common_cells idma: - revision: ca1b28816a3706be0bf9ce01378246d5346384f0 - version: 0.5.1 + revision: 1af545111773fd919a20947f86372ee5d608b271 + version: null source: Git: https://github.com/pulp-platform/iDMA.git dependencies: diff --git a/Bender.yml b/Bender.yml index a4ed787b..935a7168 100644 --- a/Bender.yml +++ b/Bender.yml @@ -13,7 +13,7 @@ package: dependencies: apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } + axi: { git: "https://github.com/pulp-platform/axi.git", rev: d864a8ac8237675e946e5aef22e6105eebcac6ed } # branch: ck/vcs axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 } axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 } axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.7 } @@ -23,7 +23,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 } - iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } + iDMA: { git: "https://github.com/pulp-platform/iDMA.git", rev: 1af545111773fd919a20947f86372ee5d608b271 } # branch: ck/flamingo irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } diff --git a/cheshire.mk b/cheshire.mk index 033df453..09e1d549 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -8,10 +8,13 @@ BENDER ?= bender +VLOGAN_BIN ?= vlogan + # Caution: Questasim requires this to point to the *actual* compiler install path CXX_PATH := $(shell which $(CXX)) -VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps +VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps +VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps # Define used paths (prefixed to avoid name conflicts) CHS_ROOT ?= $(shell $(BENDER) path cheshire) @@ -58,7 +61,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= f731b17 +CHS_NONFREE_COMMIT ?= d446ed8 CHS_PHONY += chs-nonfree-init chs-nonfree-init: @@ -142,6 +145,10 @@ $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@ echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@ +$(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml + $(BENDER) script vcs -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN_BIN)" > $@ + chmod +x $@ + .PRECIOUS: $(CHS_ROOT)/target/sim/models $(CHS_ROOT)/target/sim/models: mkdir -p $@ @@ -160,6 +167,7 @@ $(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/t CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl +CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh ########### # DRAMSys # diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 185a06a0..63b4aeb3 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -463,7 +463,7 @@ package cheshire_pkg; // Choose static colocation of IDs based on how heavily used and/or critical they are function automatic cva6_id_map_t gen_cva6_id_map(cheshire_cfg_t cfg); - localparam int unsigned DefaultMapEntry[2] = '{0, 0}; + int unsigned DefaultMapEntry[2] = '{0, 0}; case (cfg.AxiMstIdWidth) // Provide exclusive ID to I-cache to prevent fetch blocking 1: return '{'{Cva6IdBypMmu, 0}, '{Cva6IdBypLoad, 0}, '{Cva6IdBypAccel, 0}, '{Cva6IdBypStore, 0}, diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index cead6f27..35948f7e 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -228,7 +228,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( assign jtag.tdo = jtag_tdo; initial begin - @(negedge rst_n); + wait (!rst_n); jtag_dbg.reset_master(); end @@ -469,6 +469,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( initial begin static byte_bt uart_read_buf [$]; byte_bt bite; + string to_print; wait_for_reset(); forever begin uart_read_byte(bite); @@ -477,7 +478,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( uart_boot_ena = 0; end else if (bite == "\n") begin if (uart_read_buf.size() > 0) begin - $display("[UART] %s", {>>8{uart_read_buf}}); + to_print = {>>8{uart_read_buf}}; + $display("[UART] %s", to_print); uart_read_buf.delete(); end else begin $display("[UART]"); @@ -648,7 +650,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ), .AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ), .AXI_USER_WIDTH ( DutCfg.AxiUserWidth ) - ) slink_mst_ext(), slink_mst_vip(), slink_mst(); + ) slink_mst_ext(), slink_mst_vip(), slink_mst(), slink_slvs_mux[0:1](); AXI_BUS #( .AXI_ADDR_WIDTH ( DutCfg.AddrWidth ), @@ -666,6 +668,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .clk_i ( clk ) ); + `AXI_ASSIGN (slink_slvs_mux[0], slink_mst_ext) + `AXI_ASSIGN (slink_slvs_mux[1], slink_mst_vip) + // Multiplex internal and external AXI requests axi_mux_intf #( .SLV_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ), @@ -678,7 +683,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .clk_i ( clk ), .rst_ni ( rst_n ), .test_i ( test_mode ), - .slv ( '{slink_mst_vip, slink_mst_ext} ), + .slv ( slink_slvs_mux ), .mst ( slink_mst_mux ) ); @@ -785,7 +790,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( slink_axi_driver_t slink_axi_driver = new (slink_mst_vip_dv); initial begin - @(negedge rst_n); + wait (!rst_n); slink_axi_driver.reset_master(); end @@ -951,27 +956,27 @@ endmodule module vip_cheshire_soc_tristate import cheshire_pkg::*; ( // I2C pad IO - output logic i2c_sda_i, - input logic i2c_sda_o, - input logic i2c_sda_en, - output logic i2c_scl_i, - input logic i2c_scl_o, - input logic i2c_scl_en, + output i2c_sda_i, + input i2c_sda_o, + input i2c_sda_en, + output i2c_scl_i, + input i2c_scl_o, + input i2c_scl_en, // SPI host pad IO - input logic spih_sck_o, - input logic spih_sck_en, - input logic [SpihNumCs-1:0] spih_csb_o, - input logic [SpihNumCs-1:0] spih_csb_en, - output logic [ 3:0] spih_sd_i, - input logic [ 3:0] spih_sd_o, - input logic [ 3:0] spih_sd_en, + input spih_sck_o, + input spih_sck_en, + input [SpihNumCs-1:0] spih_csb_o, + input [SpihNumCs-1:0] spih_csb_en, + output [ 3:0] spih_sd_i, + input [ 3:0] spih_sd_o, + input [ 3:0] spih_sd_en, // I2C wires - inout wire i2c_sda, - inout wire i2c_scl, + inout i2c_sda, + inout i2c_scl, // SPI host wires - inout wire spih_sck, - inout wire [SpihNumCs-1:0] spih_csb, - inout wire [ 3:0] spih_sd + inout spih_sck, + inout [SpihNumCs-1:0] spih_csb, + inout [ 3:0] spih_sd ); // I2C diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh new file mode 100755 index 00000000..7e315f9c --- /dev/null +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -0,0 +1,56 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +TESTBENCH=tb_cheshire_soc + +# Set full path to c++ compiler. +if [ -z "${CXX_PATH}" ]; then + if [ -z "${CXX}" ]; then + CXX="g++" + fi + CXX_PATH=`which ${CXX}` +fi + +# Set default VCS binary +[[ -z "${VERDI_VERSION}" ]] && VERDI_VERSION="" +[[ -z "${VCS_VERSION}" ]] && VCS_VERSION="" +[[ -z "${VCS_BIN}" ]] && VCS_BIN="${VCS_VERSION} vcs" + +flags="-full64 -kdb " +# Set default to fast simulation flags. +if [ -z "${VCSARGS}" ]; then + # Use -debug_access+all for waveform debugging + flags+="-O2 -debug_access=r -debug_region=1,${TESTBENCH} " +fi + +flags+="-cpp ${CXX_PATH} " +[[ -n "${SELCFG}" ]] && flags+="-pvalue+SelectedCfg=${SELCFG} " + +pargs="" +[[ -n "${BOOTMODE}" ]] && pargs+="+BOOTMODE=${BOOTMODE} " +[[ -n "${PRELMODE}" ]] && pargs+="+PRELMODE=${PRELMODE} " +[[ -n "${BINARY}" ]] && pargs+="+BINARY=${BINARY} " +[[ -n "${IMAGE}" ]] && pargs+="+IMAGE=${IMAGE} " + +# DRAMSys +if [ -n "${USE_DRAMSYS}" ]; then + flags+="-pvalue UseDramSys=${USE_DRAMSYS} " + if [[ "${USE_DRAMSYS}" == 1 ]]; then + DRAMSYS_ROOT="../dramsys" + DRAMSYS_LIB="${DRAMSYS_ROOT}/build/lib" + pargs+="+DRAMSYS_RES=${DRAMSYS_ROOT}/configs " + pargs+="-sv_lib ${DRAMSYS_LIB}/libDRAMSys_Simulator " + fi +fi + +COLOR_NC='\e[0m' +COLOR_BLUE='\e[0;34m' + +${VCS_BIN} ${flags} ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log + +# Start simulation +printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" +${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs} | tee simulate.log