From 2250bd0a6e8cd1a34c8337fa577a3afb84b436eb Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 18 Jul 2023 10:46:05 +0200 Subject: [PATCH 1/4] Update git links --- Bender.lock | 40 ++++++++++++++++++++-------------------- Bender.yml | 32 ++++++++++++++++---------------- hw/cheshire_soc.sv | 1 + 3 files changed, 37 insertions(+), 36 deletions(-) diff --git a/Bender.lock b/Bender.lock index 7e381585..312f8ee4 100644 --- a/Bender.lock +++ b/Bender.lock @@ -10,15 +10,15 @@ packages: revision: 6c7dde3d749ac8274377745c105da8c8b8cd27c6 version: 0.2.1 source: - Git: https://github.com/pulp-platform/apb_uart + Git: https://github.com/pulp-platform/apb_uart.git dependencies: - apb - register_interface axi: - revision: f24b1faf7bcf651f1aabdef5e8f99ce2fd817c2e - version: 0.39.0-beta.9 + revision: 1c9a10278efe643e40e22c88dbd56243fb3343c8 + version: 0.39.0-beta.10 source: - Git: https://github.com/pulp-platform/axi + Git: https://github.com/pulp-platform/axi.git dependencies: - common_cells - common_verification @@ -27,7 +27,7 @@ packages: revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39 version: 0.2.1 source: - Git: https://github.com/pulp-platform/axi_llc + Git: https://github.com/pulp-platform/axi_llc.git dependencies: - axi - common_cells @@ -38,7 +38,7 @@ packages: revision: 97dcb14ef057cbe5bd70dda2060b5bb9e7e04c6d version: 0.7.0 source: - Git: https://github.com/pulp-platform/axi_riscv_atomics + Git: https://github.com/pulp-platform/axi_riscv_atomics.git dependencies: - axi - common_cells @@ -47,7 +47,7 @@ packages: revision: 07be187d1e954d8090031b32d236ad76dc62ce45 version: 0.1.1 source: - Git: https://github.com/pulp-platform/axi_vga + Git: https://github.com/pulp-platform/axi_vga.git dependencies: - axi - common_cells @@ -56,7 +56,7 @@ packages: revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf version: 2.0.0 source: - Git: https://github.com/pulp-platform/clic + Git: https://github.com/pulp-platform/clic.git dependencies: - common_cells - register_interface @@ -64,7 +64,7 @@ packages: revision: e1357c1d0edddde458aec58363473605f51e539e version: 0.1.0 source: - Git: https://github.com/pulp-platform/clint + Git: https://github.com/pulp-platform/clint.git dependencies: - common_cells - register_interface @@ -72,7 +72,7 @@ packages: revision: 0989ff73d0315922791bf42137c0ce0cbb4a76ca version: 1.30.0 source: - Git: https://github.com/pulp-platform/common_cells + Git: https://github.com/pulp-platform/common_cells.git dependencies: - common_verification - tech_cells_generic @@ -80,13 +80,13 @@ packages: revision: 9c07fa860593b2caabd9b5681740c25fac04b878 version: 0.2.3 source: - Git: https://github.com/pulp-platform/common_verification + Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: revision: bf806ffa1385876ab70b28df488fafe7ea573a7f version: null source: - Git: https://github.com/pulp-platform/cva6 + Git: https://github.com/pulp-platform/cva6.git dependencies: - axi - common_cells @@ -111,7 +111,7 @@ packages: revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 version: null source: - Git: https://github.com/pulp-platform/iDMA + Git: https://github.com/pulp-platform/iDMA.git dependencies: - axi - common_cells @@ -121,7 +121,7 @@ packages: revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3 version: null source: - Git: https://github.com/pulp-platform/irq_router + Git: https://github.com/pulp-platform/irq_router.git dependencies: - axi - common_cells @@ -130,16 +130,16 @@ packages: revision: cd3153de2783abd3d03d0595e6c4b32413c62f14 version: 0.4.0 source: - Git: https://github.com/pulp-platform/opentitan_peripherals + Git: https://github.com/pulp-platform/opentitan_peripherals.git dependencies: - common_cells - register_interface - tech_cells_generic register_interface: - revision: 50270f7f5b0ac512f8c35cfca15b7c70f74b4b0e - version: null + revision: 3b2bf592100b769977c76e51812c55cd742882f6 + version: 0.4.1 source: - Git: https://github.com/pulp-platform/register_interface + Git: https://github.com/pulp-platform/register_interface.git dependencies: - apb - axi @@ -149,7 +149,7 @@ packages: revision: 138d74bcaa90c70180c12215db3776813d2a95f2 version: 0.8.0 source: - Git: https://github.com/pulp-platform/riscv-dbg + Git: https://github.com/pulp-platform/riscv-dbg.git dependencies: - common_cells - tech_cells_generic @@ -157,7 +157,7 @@ packages: revision: 77bec1aebd92b2ebea9962814f2370d5d48390c3 version: 1.1.0 source: - Git: https://github.com/pulp-platform/serial_link + Git: https://github.com/pulp-platform/serial_link.git dependencies: - axi - common_cells diff --git a/Bender.yml b/Bender.yml index 7af6e71a..1ecc1fad 100644 --- a/Bender.yml +++ b/Bender.yml @@ -12,22 +12,22 @@ package: - "Thomas Benz " dependencies: - apb_uart: { git: "https://github.com/pulp-platform/apb_uart", version: 0.2.1 } - axi: { git: "https://github.com/pulp-platform/axi", version: 0.39.0-beta.9 } - axi_llc: { git: "https://github.com/pulp-platform/axi_llc", version: 0.2.1 } - axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics", version: 0.7.0 } - axi_vga: { git: "https://github.com/pulp-platform/axi_vga", version: 0.1.1 } - clint: { git: "https://github.com/pulp-platform/clint", version: 0.1.0 } - common_cells: { git: "https://github.com/pulp-platform/common_cells", version: 1.29.0 } - common_verification: { git: "https://github.com/pulp-platform/common_verification", version: 0.2.0 } - cva6: { git: "https://github.com/pulp-platform/cva6", rev: pulp-v0.3.1 } - iDMA: { git: "https://github.com/pulp-platform/iDMA", rev: 437ffa9 } # TODO: master commit; use next release once out - opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals", version: 0.4.0 } - register_interface: { git: "https://github.com/pulp-platform/register_interface", rev: 50270f7 } # TODO: master commit; use next release once out - riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg", version: 0.8.0 } - serial_link: { git: "https://github.com/pulp-platform/serial_link", version: 1.1.0 } - clic: { git: "https://github.com/pulp-platform/clic", version: 2.0.0 } - irq_router: { git: "https://github.com/pulp-platform/irq_router", rev: d1d3135 } # TODO: master commit; use next release once out + apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.10 } + axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 } + axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.7.0 } + axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 } + clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.1.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } + common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v0.3.1 } + iDMA: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9 } # TODO: master commit; use next release once out + opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } + riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 } + serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 } + clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 } + irq_router: { git: "https://github.com/pulp-platform/irq_router.git", rev: d1d3135 } # TODO: master commit; use next release once out export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index e6383cb3..8fde5b51 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -846,6 +846,7 @@ module cheshire_soc import cheshire_pkg::*; #( ) i_dbg_slv_axi_to_mem ( .clk_i, .rst_ni, + .test_i ( test_mode_i ), .busy_o ( ), .axi_req_i ( dbg_slv_axi_cut_req ), .axi_resp_o ( dbg_slv_axi_cut_rsp ), From d1b4e76b6db7425606beee1b6d339440b72c798d Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 4 Jul 2023 18:41:01 +0200 Subject: [PATCH 2/4] Adapt ATOP configuration --- hw/cheshire_pkg.sv | 9 +++++---- hw/cheshire_soc.sv | 8 +++++--- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 8fee3839..4e845bcb 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -90,7 +90,7 @@ package cheshire_pkg; // A '0 user signal indicates no atomics. dw_bt AxiUserAmoMsb; dw_bt AxiUserAmoLsb; - doub_bt AxiUserAmoDomain; + doub_bt AxiUserDefault; // Default user assignment, adjusted by user features (AMO) // Reg parameters dw_bt RegMaxReadTxns; dw_bt RegMaxWriteTxns; @@ -475,12 +475,13 @@ package cheshire_pkg; // Interconnect AddrWidth : 48, AxiDataWidth : 64, - AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link + AxiUserWidth : 2, // AMO(2) AxiMstIdWidth : 2, AxiMaxMstTrans : 8, AxiMaxSlvTrans : 8, - AxiUserAmoMsb : 1, - AxiUserAmoLsb : 0, + AxiUserAmoMsb : 1, // Convention: bit 0 for core(s), bit 1 for serial link + AxiUserAmoLsb : 0, // Convention: bit 0 for core(s), bit 1 for serial link + AxiUserDefault : 0, RegMaxReadTxns : 8, RegMaxWriteTxns : 8, RegAmoNumCuts : 1, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 8fde5b51..06b4e30a 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -697,9 +697,11 @@ module cheshire_soc import cheshire_pkg::*; #( // As we are core 0, the core 1 and serial link AMO bits should *not* be set. always_comb begin core_ur_req = core_out_req; - core_ur_req.aw.user = Cfg.AxiUserAmoDomain; - core_ur_req.ar.user = Cfg.AxiUserAmoDomain; - core_ur_req.w.user = Cfg.AxiUserAmoDomain; + core_ur_req.aw.user = Cfg.AxiUserDefault; + core_ur_req.ar.user = Cfg.AxiUserDefault; + core_ur_req.w.user = Cfg.AxiUserDefault; + // TODO: for additional cores, assign user bits between LSB and MSB accordingly + // TODO: for any other features, assign user bits accordingly core_out_rsp = core_ur_rsp; end From 9e2fb436b4f29c25948d5fcb0078926aba3aff6e Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 18 Jul 2023 17:36:14 +0200 Subject: [PATCH 3/4] Add user defaults to all AXI masters --- hw/cheshire_soc.sv | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 06b4e30a..79926514 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -905,6 +905,14 @@ module cheshire_soc import cheshire_pkg::*; #( .dmi_resp_o ( dbg_dmi_rsp ) ); + axi_mst_req_t axi_dbg_req; + always_comb begin + axi_in_req[AxiIn.dbg] = axi_dbg_req; + axi_in_req[AxiIn.dbg].aw_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dbg].w_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dbg].ar_user = Cfg.AxiUserDefault; + end + // Debug module system bus access to AXI crossbar axi_from_mem #( .MemAddrWidth ( Cfg.AddrWidth ), @@ -928,7 +936,7 @@ module cheshire_soc import cheshire_pkg::*; #( .mem_rsp_error_o ( dbg_sba_err ), .slv_aw_cache_i ( axi_pkg::CACHE_MODIFIABLE ), .slv_ar_cache_i ( axi_pkg::CACHE_MODIFIABLE ), - .axi_req_o ( axi_in_req[AxiIn.dbg] ), + .axi_req_o ( axi_dbg_req ), .axi_rsp_i ( axi_in_rsp[AxiIn.dbg] ) ); @@ -1424,6 +1432,14 @@ module cheshire_soc import cheshire_pkg::*; #( .mst_resp_i ( dma_cut_rsp ) ); + axi_mst_req_t axi_dma_req; + always_comb begin + axi_in_req[AxiIn.dma] = axi_dma_req; + axi_in_req[AxiIn.dma].aw_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dma].w_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dma].ar_user = Cfg.AxiUserDefault; + end + dma_core_wrap #( .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), @@ -1438,7 +1454,7 @@ module cheshire_soc import cheshire_pkg::*; #( .clk_i, .rst_ni, .testmode_i ( test_mode_i ), - .axi_mst_req_o ( axi_in_req[AxiIn.dma] ), + .axi_mst_req_o ( axi_dma_req ), .axi_mst_rsp_i ( axi_in_rsp[AxiIn.dma] ), .axi_slv_req_i ( dma_cut_req ), .axi_slv_rsp_o ( dma_cut_rsp ) @@ -1550,6 +1566,14 @@ module cheshire_soc import cheshire_pkg::*; #( if (Cfg.Vga) begin : gen_vga + axi_mst_req_t axi_vga_req; + always_comb begin + axi_in_req[AxiIn.vga] = axi_vga_req; + axi_in_req[AxiIn.vga].aw_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.vga].w_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.vga].ar_user = Cfg.AxiUserDefault; + end + axi_vga #( .RedWidth ( Cfg.VgaRedWidth ), .GreenWidth ( Cfg.VgaGreenWidth ), @@ -1569,7 +1593,7 @@ module cheshire_soc import cheshire_pkg::*; #( .test_mode_en_i ( test_mode_i ), .reg_req_i ( reg_out_req[RegOut.vga] ), .reg_rsp_o ( reg_out_rsp[RegOut.vga] ), - .axi_req_o ( axi_in_req[AxiIn.vga] ), + .axi_req_o ( axi_vga_req ), .axi_resp_i ( axi_in_rsp[AxiIn.vga] ), .hsync_o ( vga_hsync_o ), .vsync_o ( vga_vsync_o ), From 535a734e1facab0c23894049d1bb5d13e851207f Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 18 Jul 2023 18:16:23 +0200 Subject: [PATCH 4/4] fixup! Add user defaults to all AXI masters --- hw/cheshire_soc.sv | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 79926514..2bf3302a 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -906,11 +906,12 @@ module cheshire_soc import cheshire_pkg::*; #( ); axi_mst_req_t axi_dbg_req; + always_comb begin axi_in_req[AxiIn.dbg] = axi_dbg_req; - axi_in_req[AxiIn.dbg].aw_user = Cfg.AxiUserDefault; - axi_in_req[AxiIn.dbg].w_user = Cfg.AxiUserDefault; - axi_in_req[AxiIn.dbg].ar_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dbg].aw.user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dbg].w.user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dbg].ar.user = Cfg.AxiUserDefault; end // Debug module system bus access to AXI crossbar @@ -936,7 +937,7 @@ module cheshire_soc import cheshire_pkg::*; #( .mem_rsp_error_o ( dbg_sba_err ), .slv_aw_cache_i ( axi_pkg::CACHE_MODIFIABLE ), .slv_ar_cache_i ( axi_pkg::CACHE_MODIFIABLE ), - .axi_req_o ( axi_dbg_req ), + .axi_req_o ( axi_dbg_req ), .axi_rsp_i ( axi_in_rsp[AxiIn.dbg] ) ); @@ -1433,11 +1434,12 @@ module cheshire_soc import cheshire_pkg::*; #( ); axi_mst_req_t axi_dma_req; + always_comb begin axi_in_req[AxiIn.dma] = axi_dma_req; - axi_in_req[AxiIn.dma].aw_user = Cfg.AxiUserDefault; - axi_in_req[AxiIn.dma].w_user = Cfg.AxiUserDefault; - axi_in_req[AxiIn.dma].ar_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dma].aw.user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dma].w.user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.dma].ar.user = Cfg.AxiUserDefault; end dma_core_wrap #( @@ -1454,7 +1456,7 @@ module cheshire_soc import cheshire_pkg::*; #( .clk_i, .rst_ni, .testmode_i ( test_mode_i ), - .axi_mst_req_o ( axi_dma_req ), + .axi_mst_req_o ( axi_dma_req ), .axi_mst_rsp_i ( axi_in_rsp[AxiIn.dma] ), .axi_slv_req_i ( dma_cut_req ), .axi_slv_rsp_o ( dma_cut_rsp ) @@ -1567,11 +1569,12 @@ module cheshire_soc import cheshire_pkg::*; #( if (Cfg.Vga) begin : gen_vga axi_mst_req_t axi_vga_req; + always_comb begin axi_in_req[AxiIn.vga] = axi_vga_req; - axi_in_req[AxiIn.vga].aw_user = Cfg.AxiUserDefault; - axi_in_req[AxiIn.vga].w_user = Cfg.AxiUserDefault; - axi_in_req[AxiIn.vga].ar_user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.vga].aw.user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.vga].w.user = Cfg.AxiUserDefault; + axi_in_req[AxiIn.vga].ar.user = Cfg.AxiUserDefault; end axi_vga #( @@ -1593,8 +1596,8 @@ module cheshire_soc import cheshire_pkg::*; #( .test_mode_en_i ( test_mode_i ), .reg_req_i ( reg_out_req[RegOut.vga] ), .reg_rsp_o ( reg_out_rsp[RegOut.vga] ), - .axi_req_o ( axi_vga_req ), - .axi_resp_i ( axi_in_rsp[AxiIn.vga] ), + .axi_req_o ( axi_vga_req ), + .axi_resp_i ( axi_in_rsp[AxiIn.vga] ), .hsync_o ( vga_hsync_o ), .vsync_o ( vga_vsync_o ), .red_o ( vga_red_o ),