diff --git a/Bender.yml b/Bender.yml index 8cc0325c11..58b022c985 100644 --- a/Bender.yml +++ b/Bender.yml @@ -299,6 +299,15 @@ sources: - common/local/util/instr_trace_item.svh - common/local/util/ex_trace_item.svh + - target: test + files: + - corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv + - corev_apu/tb/tb_std_cache_subsystem/hdl/amo_intf.sv + - corev_apu/tb/tb_std_cache_subsystem/hdl/dcache_intf.sv + - corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv + - corev_apu/tb/tb_std_cache_subsystem/hdl/sram_intf.sv + - corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv + # TODO target define FPGA target + verification etc # - target: test # files: diff --git a/corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv b/corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv index b812b423f7..5550605ec5 100644 --- a/corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv +++ b/corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv @@ -15,15 +15,39 @@ module cva6 import ariane_pkg::*; #( - parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, - parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth, - parameter int unsigned AxiDataWidth = ariane_axi::DataWidth, - parameter int unsigned AxiIdWidth = ariane_axi::IdWidth, - parameter type axi_ar_chan_t = ariane_axi::ar_chan_t, - parameter type axi_aw_chan_t = ariane_axi::aw_chan_t, - parameter type axi_w_chan_t = ariane_axi::w_chan_t, - parameter type axi_req_t = ariane_axi::req_t, - parameter type axi_rsp_t = ariane_axi::resp_t + parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, + parameter int unsigned AxiAddrWidth = cva6_config_pkg::CVA6ConfigAxiAddrWidth, + parameter int unsigned AxiDataWidth = cva6_config_pkg::CVA6ConfigAxiDataWidth, + parameter int unsigned AxiIdWidth = cva6_config_pkg::CVA6ConfigAxiIdWidth, + parameter type axi_ar_chan_t = ariane_ace::ar_chan_t, + parameter type axi_aw_chan_t = ariane_ace::aw_chan_t, + parameter type axi_w_chan_t = ariane_ace::ariane_axi_w_chan_t, + parameter type axi_req_t = ariane_ace::req_t, + parameter type axi_rsp_t = ariane_ace::resp_t, + // RVFI + parameter type rvfi_probes_t = struct packed { + logic [TRANS_ID_BITS-1:0] issue_pointer; + logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_pointer; + logic flush_unissued_instr; + logic decoded_instr_valid; + logic flush; + logic decoded_instr_ack; + logic issue_instr_ack; + logic fetch_entry_valid; + logic [31:0] instruction; + logic is_compressed; + riscv::xlen_t rs1_forwarding; + riscv::xlen_t rs2_forwarding; + scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr; + exception_t ex_commit; + riscv::priv_lvl_t priv_lvl; + lsu_ctrl_t lsu_ctrl; + logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; + logic [riscv::PLEN-1:0] mem_paddr; + logic debug_mode; + logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + } ) ( input logic clk_i, input logic rst_ni, @@ -39,7 +63,7 @@ module cva6 input logic debug_req_i, // debug request (async) // CLIC interface - unused input logic clic_irq_valid_i, // CLIC interrupt request - input logic [$clog2(ArianeCfg.CLICNumInterruptSrc)-1:0] clic_irq_id_i, // interrupt source ID + input logic [$clog2(CVA6Cfg.CLICNumInterruptSrc)-1:0] clic_irq_id_i, // interrupt source ID input logic [7:0] clic_irq_level_i, // interrupt level is 8-bit from CLIC spec input riscv::priv_lvl_t clic_irq_priv_i, // CLIC interrupt privilege level input logic clic_irq_shv_i, // selective hardware vectoring bit @@ -48,7 +72,7 @@ module cva6 output logic clic_kill_ack_o, // kill acknowledge // RISC-V formal interface port (`rvfi`): // Can be left open when formal tracing is not needed. - output ariane_pkg::rvfi_port_t rvfi_o, + output rvfi_probes_t rvfi_probes_o, output cvxif_pkg::cvxif_req_t cvxif_req_o, input cvxif_pkg::cvxif_resp_t cvxif_resp_i, // L15 (memory side) @@ -64,10 +88,10 @@ module cva6 logic icache_en_csr; logic icache_flush_ctrl_cache; logic icache_miss_cache_perf; - icache_areq_i_t icache_areq_ex_cache; - icache_areq_o_t icache_areq_cache_ex; - icache_dreq_i_t icache_dreq_if_cache; - icache_dreq_o_t icache_dreq_cache_if; + icache_areq_t icache_areq_ex_cache; + icache_arsp_t icache_areq_cache_ex; + icache_dreq_t icache_dreq_if_cache; + icache_drsp_t icache_dreq_cache_if; logic dcache_miss_cache_perf; logic dcache_en_csr_nbdcache; @@ -107,10 +131,10 @@ module cva6 // Cache Subsystem // ------------------- - if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin : WT + if (DCACHE_TYPE == int'(config_pkg::WT)) begin : WT // this is a cache subsystem that is compatible with OpenPiton wt_cache_subsystem #( - .ArianeCfg ( ArianeCfg ) + .CVA6Cfg ( CVA6Cfg ) ) i_cache_subsystem ( // to D$ .clk_i ( clk_i ), @@ -152,7 +176,7 @@ module cva6 // note: this only works with one cacheable region // not as important since this cache subsystem is about to be // deprecated - .ArianeCfg ( ArianeCfg ), + .CVA6Cfg ( CVA6Cfg ), .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiDataWidth ), .AxiIdWidth ( AxiIdWidth ), @@ -202,7 +226,7 @@ module cva6 // ------------------- // pragma translate_off `ifndef VERILATOR - initial ariane_pkg::check_cfg(ArianeCfg); + initial config_pkg::check_cfg(CVA6Cfg); `endif // pragma translate_on diff --git a/corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv b/corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv index ae1c92998d..82cefa14a0 100644 --- a/corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv +++ b/corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv @@ -5,7 +5,7 @@ interface icache_intf ( input logic clk ); // request / response between CPU core and dcache - ariane_pkg::icache_dreq_i_t req; - ariane_pkg::icache_dreq_o_t resp; + ariane_pkg::icache_dreq_t req; + ariane_pkg::icache_drsp_t resp; endinterface diff --git a/corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv b/corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv index e7ef778b54..23e1cf4285 100644 --- a/corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv +++ b/corev_apu/tb/tb_std_cache_subsystem/hdl/tb_std_cache_subsystem_pkg.sv @@ -1,6 +1,7 @@ // Description: test utilities for the standard Ariane cache subsystem. // main package definition package tb_std_cache_subsystem_pkg; + import config_pkg::*; import ariane_pkg::*; import snoop_test::*; import std_cache_pkg::*; @@ -107,7 +108,7 @@ package tb_std_cache_subsystem_pkg; endfunction - function automatic logic [63:0] get_rand_addr_from_cfg(ariane_cfg_t cfg); + function automatic logic [63:0] get_rand_addr_from_cfg(cva6_cfg_t cfg); logic [63:0] start_addr, end_addr, range; logic [31:0] addr_msb, addr_lsb; int region; @@ -179,9 +180,9 @@ package tb_std_cache_subsystem_pkg; virtual amo_intf vif; string name; int verbosity; - ariane_cfg_t cfg; + cva6_cfg_t cfg; - function new (virtual amo_intf vif, ariane_cfg_t cfg, string name="amo_driver"); + function new (virtual amo_intf vif, cva6_cfg_t cfg, string name="amo_driver"); this.vif = vif; vif.req = '0; this.name=name; @@ -459,13 +460,13 @@ package tb_std_cache_subsystem_pkg; class dcache_driver; virtual dcache_intf vif; - ariane_cfg_t cfg; + cva6_cfg_t cfg; string name; int verbosity; logic kill_req; logic kill_armed; - function new (virtual dcache_intf vif, ariane_cfg_t cfg, string name="dcache_driver"); + function new (virtual dcache_intf vif, cva6_cfg_t cfg, string name="dcache_driver"); this.vif = vif; vif.req = '0; vif.req.address_tag = $urandom; @@ -927,13 +928,13 @@ package tb_std_cache_subsystem_pkg; class icache_driver; virtual icache_intf vif; - ariane_cfg_t cfg; + cva6_cfg_t cfg; string name; int verbosity; logic en_random_req; logic random_req_running; - function new (virtual icache_intf vif, ariane_cfg_t cfg, string name="icache_driver"); + function new (virtual icache_intf vif, cva6_cfg_t cfg, string name="icache_driver"); this.vif = vif; this.cfg = cfg; vif.req = '0; @@ -1190,7 +1191,7 @@ package tb_std_cache_subsystem_pkg; virtual dcache_gnt_if gnt_vif; string name; - ariane_cfg_t ArianeCfg; + cva6_cfg_t ArianeCfg; // Cache model cache_line_t [DCACHE_NUM_WORDS-1:0][DCACHE_SET_ASSOC-1:0] cache_status; @@ -1208,7 +1209,7 @@ package tb_std_cache_subsystem_pkg; function new ( virtual dcache_sram_if sram_vif, virtual dcache_gnt_if gnt_vif, - ariane_cfg_t cfg, + cva6_cfg_t cfg, string name="std_cache_scoreboard" ); this.sram_vif = sram_vif; @@ -3040,7 +3041,7 @@ package tb_std_cache_subsystem_pkg; int verbosity; string name; - ariane_cfg_t ArianeCfg; + cva6_cfg_t ArianeCfg; bit enable_mem_check = 1; mailbox #(amo_req) amo_req_mbox [NB_CORES]; @@ -3052,7 +3053,7 @@ package tb_std_cache_subsystem_pkg; function new ( virtual sram_intf #(DCACHE_SET_ASSOC, SRAM_DATA_WIDTH, SRAM_NUM_WORDS) sram_vif [NB_CORES], virtual dcache_sram_if dc_sram_vif [NB_CORES], - ariane_cfg_t cfg, + cva6_cfg_t cfg, string name="std_dcache_checker" ); this.name = name;