From b3c11e6a5a4e98df7bd118134892d76b7b2f3ced Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 5 Mar 2024 18:37:55 +0100 Subject: [PATCH] [WIP] - Cleaning up synchronous clear integration. --- Bender.yml | 2 +- core/cache_subsystem/axi_adapter.sv | 32 ++++------- core/cache_subsystem/cache_ctrl.sv | 15 ++--- .../cva6_hpdcache_if_adapter.sv | 17 +++--- core/cache_subsystem/cva6_icache.sv | 52 +++++++----------- .../cva6_icache_axi_wrapper.sv | 19 ++----- core/cache_subsystem/miss_handler.sv | 43 +++++---------- core/cache_subsystem/tag_cmp.sv | 11 ++-- core/cache_subsystem/wt_axi_adapter.sv | 48 +++++----------- core/cache_subsystem/wt_dcache_ctrl.sv | 34 ++++-------- core/cache_subsystem/wt_dcache_mem.sv | 33 +++++------ core/cache_subsystem/wt_dcache_missunit.sv | 39 ++++--------- core/cache_subsystem/wt_dcache_wbuffer.sv | 40 ++++---------- core/id_stage.sv | 10 +--- core/lsu_bypass.sv | 20 +++---- core/mmu_sv32/cva6_mmu_sv32.sv | 28 +++------- core/mmu_sv32/cva6_ptw_sv32.sv | 37 ++++--------- core/mmu_sv32/cva6_shared_tlb_sv32.sv | 40 +++++--------- core/mmu_sv32/cva6_tlb_sv32.sv | 19 +++---- core/mmu_sv39x4/cva6_mmu_sv39x4.sv | 42 +++++--------- core/mmu_sv39x4/cva6_ptw_sv39x4.sv | 55 ++++++------------- core/mmu_sv39x4/cva6_tlb_sv39x4.sv | 16 ++---- core/serdiv.sv | 42 +++++--------- 23 files changed, 231 insertions(+), 463 deletions(-) diff --git a/Bender.yml b/Bender.yml index 2ff83d4633..acc0a2260d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -9,7 +9,7 @@ package: dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 } common_cells: - { git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 } + { git: "https://github.com/pulp-platform/common_cells", rev: bd4bbe7 } # branch: yt/synch-clear fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv index 85852e9829..4f1f7ada69 100644 --- a/core/cache_subsystem/axi_adapter.sv +++ b/core/cache_subsystem/axi_adapter.sv @@ -16,6 +16,8 @@ */ //import std_cache_pkg::*; +`include "common_cells/registers.svh" + module axi_adapter #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DATA_WIDTH = 256, @@ -461,28 +463,14 @@ module axi_adapter #( // ---------------- // Registers // ---------------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - // start in flushing state and initialize the memory - state_q <= IDLE; - cnt_q <= '0; - cache_line_q <= '0; - addr_offset_q <= '0; - id_q <= '0; - amo_q <= ariane_pkg::AMO_NONE; - size_q <= '0; - outstanding_aw_cnt_q <= '0; - end else begin - state_q <= state_d; - cnt_q <= cnt_d; - cache_line_q <= cache_line_d; - addr_offset_q <= addr_offset_d; - id_q <= id_d; - amo_q <= amo_d; - size_q <= size_d; - outstanding_aw_cnt_q <= outstanding_aw_cnt_d; - end - end + `FFARNC(state_q , state_d , 1'b0, IDLE , clk_i, rst_ni) + `FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(cache_line_q , cache_line_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(addr_offset_q , addr_offset_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(id_q , id_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(amo_q , amo_d , 1'b0, ariane_pkg::AMO_NONE, clk_i, rst_ni) + `FFARNC(size_q , size_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(outstanding_aw_cnt_q , outstanding_aw_cnt_d, 1'b0, '0 , clk_i, rst_ni) function automatic axi_pkg::atop_t atop_from_amo(ariane_pkg::amo_t amo); axi_pkg::atop_t result = 6'b000000; diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv index 3b876c4e52..f07976583c 100644 --- a/core/cache_subsystem/cache_ctrl.sv +++ b/core/cache_subsystem/cache_ctrl.sv @@ -17,6 +17,7 @@ // // Description: Cache controller +`include "common_cells/registers.svh" module cache_ctrl import ariane_pkg::*; @@ -442,17 +443,9 @@ module cache_ctrl // -------------- // Registers // -------------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - state_q <= IDLE; - mem_req_q <= '0; - hit_way_q <= '0; - end else begin - state_q <= state_d; - mem_req_q <= mem_req_d; - hit_way_q <= hit_way_d; - end - end + `FFARNC(state_q , state_d , 1'b0, '0, clk_i, rst_ni) + `FFARNC(mem_req_q , mem_req_d, 1'b0, '0, clk_i, rst_ni) + `FFARNC(hit_way_q , hit_way_d, 1'b0, '0, clk_i, rst_ni) //pragma translate_off `ifndef VERILATOR diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index f3a1d2e040..516af05090 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -9,6 +9,9 @@ // Authors: Cesar Fuguet // Date: February, 2023 // Description: Interface adapter for the CVA6 core + +`include "common_cells/registers.svh" + module cva6_hpdcache_if_adapter import hpdcache_pkg::*; @@ -108,7 +111,7 @@ module cva6_hpdcache_if_adapter logic [ 7:0] amo_data_be; hpdcache_req_op_t amo_op; logic [31:0] amo_resp_word; - logic amo_pending_q; + logic amo_pending_q, amo_pending_n; // AMO logic // {{{ @@ -195,16 +198,12 @@ module cva6_hpdcache_if_adapter : hpdcache_rsp_i.rdata[0]; // }}} - always_ff @(posedge clk_i or negedge rst_ni) begin : amo_pending_ff - if (!rst_ni) begin - amo_pending_q <= 1'b0; - end else begin - amo_pending_q <= + assign amo_pending_n = ( cva6_amo_req_i.req & hpdcache_req_ready_i & ~amo_pending_q) | (~cva6_amo_resp_o.ack & amo_pending_q); - end - end - end + + `FFARNC(amo_pending_q, amo_pending_n, 1'b0, 1'b0, clk_i, rst_ni) + // }}} endgenerate // }}} diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 978c2720bf..63c2f585eb 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -24,6 +24,7 @@ // 3) NC accesses to I/O space are expected to return 32bit from memory. // +`include "common_cells/registers.svh" module cva6_icache import ariane_pkg::*; @@ -494,32 +495,16 @@ module cva6_icache ); end - - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - cl_tag_q <= '0; - flush_cnt_q <= '0; - vaddr_q <= '0; - cmp_en_q <= '0; - cache_en_q <= '0; - flush_q <= '0; - state_q <= FLUSH; - cl_offset_q <= '0; - repl_way_oh_q <= '0; - inv_q <= '0; - end else begin - cl_tag_q <= cl_tag_d; - flush_cnt_q <= flush_cnt_d; - vaddr_q <= vaddr_d; - cmp_en_q <= cmp_en_d; - cache_en_q <= cache_en_d; - flush_q <= flush_d; - state_q <= state_d; - cl_offset_q <= cl_offset_d; - repl_way_oh_q <= repl_way_oh_d; - inv_q <= inv_d; - end - end + `FFARNC(cl_tag_q , cl_tag_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(flush_cnt_q , flush_cnt_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(vaddr_q , vaddr_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(cmp_en_q , cmp_en_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(cache_en_q , cache_en_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(flush_q , flush_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(state_q , state_d , 1'b0, FLUSH, clk_i, rst_ni) + `FFARNC(cl_offset_q , cl_offset_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(repl_way_oh_q , repl_way_oh_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(inv_q , inv_d , 1'b0, '0 , clk_i, rst_ni) /////////////////////////////////////////////////////// // assertions @@ -559,12 +544,17 @@ module cva6_icache vld_mirror <= '{default: '0}; tag_mirror <= '{default: '0}; end else begin - for (int i = 0; i < ICACHE_SET_ASSOC; i++) begin - if (vld_req[i] & vld_we) begin - vld_mirror[vld_addr][i] <= vld_wdata[i]; - tag_mirror[vld_addr][i] <= cl_tag_q; + // if (clear_i) begin + // vld_mirror <= '{default: '0}; + // tag_mirror <= '{default: '0}; + // end else begin + for (int i = 0; i < ICACHE_SET_ASSOC; i++) begin + if (vld_req[i] & vld_we) begin + vld_mirror[vld_addr][i] <= vld_wdata[i]; + tag_mirror[vld_addr][i] <= cl_tag_q; + end end - end + // end end end diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index 4561fc551f..c88c67b243 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -13,6 +13,8 @@ // Description: wrapper module to connect the L1I$ to a 64bit AXI bus. // +`include "common_cells/registers.svh" + module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; @@ -191,18 +193,9 @@ module cva6_icache_axi_wrapper end // Registers - always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf - if (!rst_ni) begin - req_valid_q <= 1'b0; - req_data_q <= '0; - first_q <= 1'b1; - rd_shift_q <= '0; - end else begin - req_valid_q <= req_valid_d; - req_data_q <= req_data_d; - first_q <= first_d; - rd_shift_q <= rd_shift_d; - end - end + `FFARNC(req_valid_q , req_valid_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(req_data_q , req_data_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(first_q , first_d , 1'b0, 1'b0, clk_i, rst_ni) + `FFARNC(rd_shift_q , rd_shift_d , 1'b0, '0 , clk_i, rst_ni) endmodule // cva6_icache_axi_wrapper diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index 0871ba88b6..f8efd70ffe 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -16,6 +16,8 @@ // MISS Handler // -------------- +`include "common_cells/registers.svh" + module miss_handler import ariane_pkg::*; import std_cache_pkg::*; @@ -505,23 +507,12 @@ module miss_handler // -------------------- // Sequential Process // -------------------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - mshr_q <= '0; - state_q <= INIT; - cnt_q <= '0; - evict_way_q <= '0; - evict_cl_q <= '0; - serve_amo_q <= 1'b0; - end else begin - mshr_q <= mshr_d; - state_q <= state_d; - cnt_q <= cnt_d; - evict_way_q <= evict_way_d; - evict_cl_q <= evict_cl_d; - serve_amo_q <= serve_amo_d; - end - end + `FFARNC(mshr_q , mshr_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(state_q , state_d , 1'b0, INIT, clk_i, rst_ni) + `FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(evict_way_q , evict_way_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(evict_cl_q , evict_cl_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(serve_amo_q , serve_amo_d, 1'b0, '0 , clk_i, rst_ni) //pragma translate_off `ifndef VERILATOR @@ -798,19 +789,11 @@ module axi_adapter_arbiter #( endcase end - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - state_q <= IDLE; - sel_q <= '0; - req_q <= '0; - outstanding_cnt_q <= '0; - end else begin - state_q <= state_d; - sel_q <= sel_d; - req_q <= req_d; - outstanding_cnt_q <= outstanding_cnt_d; - end - end + `FFARNC(state_q , state_d , 1'b0, IDLE, clk_i, rst_ni) + `FFARNC(sel_q , sel_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(req_q , req_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(outstanding_cnt_q , outstanding_cnt_d, 1'b0, '0 , clk_i, rst_ni) + // ------------ // Assertions // ------------ diff --git a/core/cache_subsystem/tag_cmp.sv b/core/cache_subsystem/tag_cmp.sv index a378c13b11..06ab736e8c 100644 --- a/core/cache_subsystem/tag_cmp.sv +++ b/core/cache_subsystem/tag_cmp.sv @@ -15,6 +15,9 @@ // Description: Arbitrates access to cache memories, simplified request grant protocol // checks for hit or miss on cache // + +`include "common_cells/registers.svh" + module tag_cmp #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_PORTS = 3, @@ -95,12 +98,6 @@ module tag_cmp #( `endif end - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - id_q <= 0; - end else begin - id_q <= id_d; - end - end + `FFARNC(id_q, id_d, 1'b0, '0, clk_i, rst_ni) endmodule diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 1647f1d072..bfd144ca43 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -13,6 +13,7 @@ // Description: adapter module to connect the L1D$ and L1I$ to a 64bit AXI bus. // +`include "common_cells/registers.svh" module wt_axi_adapter import ariane_pkg::*; @@ -619,39 +620,20 @@ module wt_axi_adapter // assign dcache_rtrn_o.inv.vld = '0; // assign dcache_rtrn_o.inv.all = '0; - always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf - if (!rst_ni) begin - icache_first_q <= 1'b1; - dcache_first_q <= 1'b1; - icache_rd_shift_q <= '0; - icache_rd_shift_user_q <= '0; - dcache_rd_shift_q <= '0; - dcache_rd_shift_user_q <= '0; - icache_rtrn_vld_q <= '0; - dcache_rtrn_vld_q <= '0; - icache_rtrn_tid_q <= '0; - dcache_rtrn_tid_q <= '0; - dcache_rtrn_type_q <= wt_cache_pkg::DCACHE_LOAD_ACK; - dcache_rtrn_inv_q <= '0; - amo_off_q <= '0; - amo_gen_r_q <= 1'b0; - end else begin - icache_first_q <= icache_first_d; - dcache_first_q <= dcache_first_d; - icache_rd_shift_q <= icache_rd_shift_d; - icache_rd_shift_user_q <= icache_rd_shift_user_d; - dcache_rd_shift_q <= dcache_rd_shift_d; - dcache_rd_shift_user_q <= dcache_rd_shift_user_d; - icache_rtrn_vld_q <= icache_rtrn_vld_d; - dcache_rtrn_vld_q <= dcache_rtrn_vld_d; - icache_rtrn_tid_q <= icache_rtrn_tid_d; - dcache_rtrn_tid_q <= dcache_rtrn_tid_d; - dcache_rtrn_type_q <= dcache_rtrn_type_d; - dcache_rtrn_inv_q <= dcache_rtrn_inv_d; - amo_off_q <= amo_off_d; - amo_gen_r_q <= amo_gen_r_d; - end - end + `FFARNC(icache_first_q , icache_first_d , 1'b0, 1'b1 , clk_i, rst_ni) + `FFARNC(dcache_first_q , dcache_first_d , 1'b0, 1'b1 , clk_i, rst_ni) + `FFARNC(icache_rd_shift_q , icache_rd_shift_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(icache_rd_shift_user_q , icache_rd_shift_user_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(dcache_rd_shift_q , dcache_rd_shift_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(dcache_rd_shift_user_q , dcache_rd_shift_user_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(icache_rtrn_vld_q , icache_rtrn_vld_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(dcache_rtrn_vld_q , dcache_rtrn_vld_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(icache_rtrn_tid_q , icache_rtrn_tid_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(dcache_rtrn_tid_q , dcache_rtrn_tid_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(dcache_rtrn_type_q , dcache_rtrn_type_d , 1'b0, wt_cache_pkg::DCACHE_LOAD_ACK, clk_i, rst_ni) + `FFARNC(dcache_rtrn_inv_q , dcache_rtrn_inv_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(amo_off_q , amo_off_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(amo_gen_r_q , amo_gen_r_d , 1'b0, '0 , clk_i, rst_ni) /////////////////////////////////////////////////////// diff --git a/core/cache_subsystem/wt_dcache_ctrl.sv b/core/cache_subsystem/wt_dcache_ctrl.sv index a2e3fe38d1..9bf595efef 100644 --- a/core/cache_subsystem/wt_dcache_ctrl.sv +++ b/core/cache_subsystem/wt_dcache_ctrl.sv @@ -12,6 +12,7 @@ // Date: 13.09.2018 // Description: DCache controller for read port +`include "common_cells/registers.svh" module wt_dcache_ctrl import ariane_pkg::*; @@ -253,30 +254,15 @@ module wt_dcache_ctrl /////////////////////////////////////////////////////// // ff's /////////////////////////////////////////////////////// - - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - state_q <= IDLE; - address_tag_q <= '0; - address_idx_q <= '0; - address_off_q <= '0; - id_q <= '0; - vld_data_q <= '0; - data_size_q <= '0; - rd_req_q <= '0; - rd_ack_q <= '0; - end else begin - state_q <= state_d; - address_tag_q <= address_tag_d; - address_idx_q <= address_idx_d; - address_off_q <= address_off_d; - id_q <= id_d; - vld_data_q <= vld_data_d; - data_size_q <= data_size_d; - rd_req_q <= rd_req_d; - rd_ack_q <= rd_ack_d; - end - end + `FFARNC(state_q , state_d , 1'b0, IDLE, clk_i, rst_ni) + `FFARNC(address_tag_q , address_tag_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(address_idx_q , address_idx_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(address_off_q , address_off_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(id_q , id_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(vld_data_q , vld_data_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(data_size_q , data_size_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(rd_req_q , rd_req_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(rd_ack_q , rd_ack_d , 1'b0, '0 , clk_i, rst_ni) /////////////////////////////////////////////////////// // assertions diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv index b2b41c3c73..6ac11fe78a 100644 --- a/core/cache_subsystem/wt_dcache_mem.sv +++ b/core/cache_subsystem/wt_dcache_mem.sv @@ -25,6 +25,7 @@ // 4) Read ports with same priority are RR arbited. but high prio ports (rd_prio_i[port_nr] = '1b1) will stall // low prio ports (rd_prio_i[port_nr] = '1b0) +`include "common_cells/registers.svh" module wt_dcache_mem import ariane_pkg::*; @@ -340,19 +341,10 @@ module wt_dcache_mem ); end - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - bank_idx_q <= '0; - bank_off_q <= '0; - vld_sel_q <= '0; - cmp_en_q <= '0; - end else begin - bank_idx_q <= bank_idx_d; - bank_off_q <= bank_off_d; - vld_sel_q <= vld_sel_d; - cmp_en_q <= cmp_en_d; - end - end + `FFARNC(bank_idx_q , bank_idx_d, 1'b0, '0, clk_i, rst_ni) + `FFARNC(bank_off_q , bank_off_d, 1'b0, '0, clk_i, rst_ni) + `FFARNC(vld_sel_q , vld_sel_d , 1'b0, '0, clk_i, rst_ni) + `FFARNC(cmp_en_q , cmp_en_d , 1'b0, '0, clk_i, rst_ni) /////////////////////////////////////////////////////// // assertions @@ -404,12 +396,17 @@ module wt_dcache_mem vld_mirror <= '{default: '0}; tag_mirror <= '{default: '0}; end else begin - for (int i = 0; i < DCACHE_SET_ASSOC; i++) begin - if (vld_req[i] & vld_we) begin - vld_mirror[vld_addr][i] <= vld_wdata[i]; - tag_mirror[vld_addr][i] <= wr_cl_tag_i; + // if (clear_i) begin + // vld_mirror <= '{default: '0}; + // tag_mirror <= '{default: '0}; + // end else begin + for (int i = 0; i < DCACHE_SET_ASSOC; i++) begin + if (vld_req[i] & vld_we) begin + vld_mirror[vld_addr][i] <= vld_wdata[i]; + tag_mirror[vld_addr][i] <= wr_cl_tag_i; + end end - end + // end end end diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 8cc3a4f154..66933e26f6 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -13,6 +13,7 @@ // Description: miss controller for WT dcache. Note that the current assumption // is that the port with the highest index issues writes instead of reads. +`include "common_cells/registers.svh" module wt_dcache_missunit import ariane_pkg::*; @@ -592,33 +593,17 @@ module wt_dcache_missunit // ff's /////////////////////////////////////////////////////// - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - state_q <= INIT; - cnt_q <= '0; - enable_q <= '0; - flush_ack_q <= '0; - mshr_vld_q <= '0; - mshr_vld_q1 <= '0; - mshr_q <= '0; - mshr_rdrd_collision_q <= '0; - miss_req_masked_q <= '0; - amo_req_q <= '0; - stores_inflight_q <= '0; - end else begin - state_q <= state_d; - cnt_q <= cnt_d; - enable_q <= enable_d; - flush_ack_q <= flush_ack_d; - mshr_vld_q <= mshr_vld_d; - mshr_vld_q1 <= mshr_vld_q; - mshr_q <= mshr_d; - mshr_rdrd_collision_q <= mshr_rdrd_collision_d; - miss_req_masked_q <= miss_req_masked_d; - amo_req_q <= amo_req_d; - stores_inflight_q <= stores_inflight_d; - end - end + `FFARNC(state_q , state_d , 1'b0, INIT, clk_i, rst_ni) + `FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(enable_q , enable_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(flush_ack_q , flush_ack_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(mshr_vld_q , mshr_vld_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(mshr_vld_q1 , mshr_vld_q , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(mshr_q , mshr_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(mshr_rdrd_collision_q, mshr_rdrd_collision_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(miss_req_masked_q , miss_req_masked_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(amo_req_q , amo_req_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(stores_inflight_q , stores_inflight_d , 1'b0, '0 , clk_i, rst_ni) /////////////////////////////////////////////////////// // assertions diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index 8e9c39d485..bda4adc959 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -48,6 +48,7 @@ // then, only the NC word is written into the write buffer and no further write requests are acknowledged until that // word has been evicted from the write buffer. +`include "common_cells/registers.svh" module wt_dcache_wbuffer import ariane_pkg::*; @@ -544,34 +545,17 @@ module wt_dcache_wbuffer // ff's /////////////////////////////////////////////////////// - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - wbuffer_q <= '{default: '0}; - tx_stat_q <= '{default: '0}; - ni_pending_q <= '0; - check_ptr_q <= '0; - check_ptr_q1 <= '0; - check_en_q <= '0; - check_en_q1 <= '0; - rd_tag_q <= '0; - rd_hit_oh_q <= '0; - wr_cl_vld_q <= '0; - wr_cl_idx_q <= '0; - end else begin - wbuffer_q <= wbuffer_d; - tx_stat_q <= tx_stat_d; - ni_pending_q <= ni_pending_d; - check_ptr_q <= check_ptr_d; - check_ptr_q1 <= check_ptr_q; - check_en_q <= check_en_d; - check_en_q1 <= check_en_q; - rd_tag_q <= rd_tag_d; - rd_hit_oh_q <= rd_hit_oh_d; - wr_cl_vld_q <= wr_cl_vld_d; - wr_cl_idx_q <= wr_cl_idx_d; - end - end - + `FFARNC(wbuffer_q , wbuffer_d , 1'b0, '{default: '0}, clk_i, rst_ni) + `FFARNC(tx_stat_q , tx_stat_d , 1'b0, '{default: '0}, clk_i, rst_ni) + `FFARNC(ni_pending_q , ni_pending_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(check_ptr_q , check_ptr_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(check_ptr_q1 , check_ptr_q , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(check_en_q , check_en_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(check_en_q1 , check_en_q , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(rd_tag_q , rd_tag_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(rd_hit_oh_q , rd_hit_oh_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(wr_cl_vld_q , wr_cl_vld_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(wr_cl_idx_q , wr_cl_idx_d , 1'b0, '0 , clk_i, rst_ni) /////////////////////////////////////////////////////// // assertions diff --git a/core/id_stage.sv b/core/id_stage.sv index dcff46d078..c9ca18400d 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -13,6 +13,8 @@ // Description: Instruction decode, contains the logic for decode, // issue and read operands. +`include "common_cells/registers.svh" + module id_stage #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( @@ -178,11 +180,5 @@ module id_stage #( // ------------------------- // Registers (ID <-> Issue) // ------------------------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - issue_q <= '0; - end else begin - issue_q <= issue_n; - end - end + `FFARNC(issue_q, issue_n, 1'b0, '0, clk_i, rst_ni) endmodule diff --git a/core/lsu_bypass.sv b/core/lsu_bypass.sv index 5790c73a95..dc5fc19604 100644 --- a/core/lsu_bypass.sv +++ b/core/lsu_bypass.sv @@ -23,6 +23,9 @@ // the LSU control should sample it and store it for later application to the units. It does so, by storing it in a // two element FIFO. This is necessary as we only know very late in the cycle whether the load/store will succeed (address check, // TLB hit mainly). So we better unconditionally allow another request to arrive and store this request in case we need to. + +`include "common_cells/registers.svh" + module lsu_bypass import ariane_pkg::*; #( @@ -114,18 +117,9 @@ module lsu_bypass end // registers - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - mem_q <= '0; - status_cnt_q <= '0; - write_pointer_q <= '0; - read_pointer_q <= '0; - end else begin - mem_q <= mem_n; - status_cnt_q <= status_cnt_n; - write_pointer_q <= write_pointer_n; - read_pointer_q <= read_pointer_n; - end - end + `FFARNC(mem_q , mem_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(status_cnt_q , status_cnt_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(write_pointer_q , write_pointer_n, 1'b0, '0, clk_i, rst_ni) + `FFARNC(read_pointer_q , read_pointer_n , 1'b0, '0, clk_i, rst_ni) endmodule diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 9c98793da4..e5252b33d7 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -26,6 +26,8 @@ // 2020-02-17 0.1 S.Jacq MMU Sv32 for CV32A6 // =========================================================================== // +`include "common_cells/registers.svh" + module cva6_mmu_sv32 import ariane_pkg::*; #( @@ -564,23 +566,11 @@ module cva6_mmu_sv32 // ---------- // Registers // ---------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - lsu_vaddr_q <= '0; - lsu_req_q <= '0; - misaligned_ex_q <= '0; - dtlb_pte_q <= '0; - dtlb_hit_q <= '0; - lsu_is_store_q <= '0; - dtlb_is_4M_q <= '0; - end else begin - lsu_vaddr_q <= lsu_vaddr_n; - lsu_req_q <= lsu_req_n; - misaligned_ex_q <= misaligned_ex_n; - dtlb_pte_q <= dtlb_pte_n; - dtlb_hit_q <= dtlb_hit_n; - lsu_is_store_q <= lsu_is_store_n; - dtlb_is_4M_q <= dtlb_is_4M_n; - end - end + `FFARNC(lsu_vaddr_q ,lsu_vaddr_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(lsu_req_q ,lsu_req_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(misaligned_ex_q ,misaligned_ex_n, 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_pte_q ,dtlb_pte_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_hit_q ,dtlb_hit_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(lsu_is_store_q ,lsu_is_store_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_is_4M_q ,dtlb_is_4M_n , 1'b0, '0, clk_i, rst_ni) endmodule diff --git a/core/mmu_sv32/cva6_ptw_sv32.sv b/core/mmu_sv32/cva6_ptw_sv32.sv index 4bd736bd30..e0f936b3fe 100644 --- a/core/mmu_sv32/cva6_ptw_sv32.sv +++ b/core/mmu_sv32/cva6_ptw_sv32.sv @@ -26,6 +26,8 @@ /* verilator lint_off WIDTH */ +`include "common_cells/registers.svh" + module cva6_ptw_sv32 import ariane_pkg::*; #( @@ -370,31 +372,16 @@ module cva6_ptw_sv32 end // sequential process - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - state_q <= IDLE; - is_instr_ptw_q <= 1'b0; - ptw_lvl_q <= LVL1; - tag_valid_q <= 1'b0; - tlb_update_asid_q <= '0; - vaddr_q <= '0; - ptw_pptr_q <= '0; - global_mapping_q <= 1'b0; - data_rdata_q <= '0; - data_rvalid_q <= 1'b0; - end else begin - state_q <= state_d; - ptw_pptr_q <= ptw_pptr_n; - is_instr_ptw_q <= is_instr_ptw_n; - ptw_lvl_q <= ptw_lvl_n; - tag_valid_q <= tag_valid_n; - tlb_update_asid_q <= tlb_update_asid_n; - vaddr_q <= vaddr_n; - global_mapping_q <= global_mapping_n; - data_rdata_q <= req_port_i.data_rdata; - data_rvalid_q <= req_port_i.data_rvalid; - end - end + `FFARNC(state_q , state_d , 1'b0, IDLE, clk_i, rst_ni) + `FFARNC(ptw_pptr_q , ptw_pptr_n , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(is_instr_ptw_q , is_instr_ptw_n , 1'b0, 1'b0, clk_i, rst_ni) + `FFARNC(ptw_lvl_q , ptw_lvl_n , 1'b0, LVL1, clk_i, rst_ni) + `FFARNC(tag_valid_q , tag_valid_n , 1'b0, 1'b0, clk_i, rst_ni) + `FFARNC(tlb_update_asid_q , tlb_update_asid_n , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(vaddr_q , vaddr_n , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(global_mapping_q , global_mapping_n , 1'b0, 1'b0, clk_i, rst_ni) + `FFARNC(data_rdata_q , req_port_i.data_rdata , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(data_rvalid_q , req_port_i.data_rvalid, 1'b0, 1'b0, clk_i, rst_ni) endmodule /* verilator lint_on WIDTH */ diff --git a/core/mmu_sv32/cva6_shared_tlb_sv32.sv b/core/mmu_sv32/cva6_shared_tlb_sv32.sv index 98e2a044a9..18c3e8cff8 100644 --- a/core/mmu_sv32/cva6_shared_tlb_sv32.sv +++ b/core/mmu_sv32/cva6_shared_tlb_sv32.sv @@ -17,6 +17,8 @@ /* verilator lint_off WIDTH */ +`include "common_cells/registers.svh" + module cva6_shared_tlb_sv32 import ariane_pkg::*; #( @@ -229,33 +231,17 @@ module cva6_shared_tlb_sv32 end //tag_comparison // sequential process - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - itlb_vpn_q <= '0; - dtlb_vpn_q <= '0; - tlb_update_asid_q <= '0; - shared_tlb_access_q <= '0; - shared_tlb_vaddr_q <= '0; - shared_tag_valid_q <= '0; - vpn0_q <= '0; - vpn1_q <= '0; - itlb_req_q <= '0; - dtlb_req_q <= '0; - shared_tag_valid <= '0; - end else begin - itlb_vpn_q <= itlb_vaddr_i[riscv::SV-1:12]; - dtlb_vpn_q <= dtlb_vaddr_i[riscv::SV-1:12]; - tlb_update_asid_q <= tlb_update_asid_d; - shared_tlb_access_q <= shared_tlb_access_d; - shared_tlb_vaddr_q <= shared_tlb_vaddr_d; - shared_tag_valid_q <= shared_tag_valid_d; - vpn0_q <= vpn0_d; - vpn1_q <= vpn1_d; - itlb_req_q <= itlb_req_d; - dtlb_req_q <= dtlb_req_d; - shared_tag_valid <= shared_tag_valid_q[tag_rd_addr]; - end - end + `FFARNC(itlb_vpn_q , itlb_vaddr_i[riscv::SV-1:12] , 1'b0, '0, clk_i, rstn_i) + `FFARNC(dtlb_vpn_q , dtlb_vaddr_i[riscv::SV-1:12] , 1'b0, '0, clk_i, rstn_i) + `FFARNC(tlb_update_asid_q , tlb_update_asid_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(shared_tlb_access_q , shared_tlb_access_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(shared_tlb_vaddr_q , shared_tlb_vaddr_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(shared_tag_valid_q , shared_tag_valid_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(vpn0_q , vpn0_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(vpn1_q , vpn1_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(itlb_req_q , itlb_req_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(dtlb_req_q , dtlb_req_d , 1'b0, '0, clk_i, rstn_i) + `FFARNC(shared_tag_valid , shared_tag_valid_q[tag_rd_addr], 1'b0, '0, clk_i, rstn_i) // ------------------ // Update and Flush diff --git a/core/mmu_sv32/cva6_tlb_sv32.sv b/core/mmu_sv32/cva6_tlb_sv32.sv index 79a7c98dc5..3d30a8df4f 100644 --- a/core/mmu_sv32/cva6_tlb_sv32.sv +++ b/core/mmu_sv32/cva6_tlb_sv32.sv @@ -24,6 +24,8 @@ // 2020-02-17 0.1 S.Jacq TLB Sv32 for CV32A6 // =========================================================================== // +`include "common_cells/registers.svh" + module cva6_tlb_sv32 import ariane_pkg::*; #( @@ -224,18 +226,11 @@ module cva6_tlb_sv32 end // sequential process - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - tags_q <= '{default: 0}; - content_q <= '{default: 0}; - plru_tree_q <= '{default: 0}; - end else begin - tags_q <= tags_n; - content_q <= content_n; - plru_tree_q <= plru_tree_n; - end - end - //-------------- + `FFARNC(tags_q ,tags_n , 1'b0, '{defautl: 0}, clk_i, rst_ni) + `FFARNC(content_q ,content_n , 1'b0, '{defautl: 0}, clk_i, rst_ni) + `FFARNC(plru_tree_q ,plru_tree_n, 1'b0, '{defautl: 0}, clk_i, rst_ni) + + //-------------- // Sanity checks //-------------- diff --git a/core/mmu_sv39x4/cva6_mmu_sv39x4.sv b/core/mmu_sv39x4/cva6_mmu_sv39x4.sv index 041bf14fe6..8ffc9c0871 100644 --- a/core/mmu_sv39x4/cva6_mmu_sv39x4.sv +++ b/core/mmu_sv39x4/cva6_mmu_sv39x4.sv @@ -18,6 +18,7 @@ // This module is an adaptation of the MMU Sv39x4 developed // by Florian Zaruba to the Sv39x4 standard. +`include "common_cells/registers.svh" module cva6_mmu_sv39x4 import ariane_pkg::*; @@ -683,33 +684,16 @@ module cva6_mmu_sv39x4 // ---------- // Registers // ---------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - lsu_vaddr_q <= '0; - lsu_gpaddr_q <= '0; - lsu_tinst_q <= '0; - hs_ld_st_inst_q <= '0; - lsu_req_q <= '0; - misaligned_ex_q <= '0; - dtlb_pte_q <= '0; - dtlb_gpte_q <= '0; - dtlb_hit_q <= '0; - lsu_is_store_q <= '0; - dtlb_is_2M_q <= '0; - dtlb_is_1G_q <= '0; - end else begin - lsu_vaddr_q <= lsu_vaddr_n; - lsu_gpaddr_q <= lsu_gpaddr_n; - lsu_tinst_q <= lsu_tinst_n; - hs_ld_st_inst_q <= hs_ld_st_inst_n; - lsu_req_q <= lsu_req_n; - misaligned_ex_q <= misaligned_ex_n; - dtlb_pte_q <= dtlb_pte_n; - dtlb_gpte_q <= dtlb_gpte_n; - dtlb_hit_q <= dtlb_hit_n; - lsu_is_store_q <= lsu_is_store_n; - dtlb_is_2M_q <= dtlb_is_2M_n; - dtlb_is_1G_q <= dtlb_is_1G_n; - end - end + `FFARNC(lsu_vaddr_q ,lsu_vaddr_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(lsu_gpaddr_q ,lsu_gpaddr_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(lsu_tinst_q ,lsu_tinst_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(hs_ld_st_inst_q ,hs_ld_st_inst_n, 1'b0, '0, clk_i, rst_ni) + `FFARNC(lsu_req_q ,lsu_req_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(misaligned_ex_q ,misaligned_ex_n, 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_pte_q ,dtlb_pte_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_gpte_q ,dtlb_gpte_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_hit_q ,dtlb_hit_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(lsu_is_store_q ,lsu_is_store_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_is_2M_q ,dtlb_is_2M_n , 1'b0, '0, clk_i, rst_ni) + `FFARNC(dtlb_is_1G_q ,dtlb_is_1G_n , 1'b0, '0, clk_i, rst_ni) endmodule diff --git a/core/mmu_sv39x4/cva6_ptw_sv39x4.sv b/core/mmu_sv39x4/cva6_ptw_sv39x4.sv index b645c2bc43..9a6ac46cc2 100644 --- a/core/mmu_sv39x4/cva6_ptw_sv39x4.sv +++ b/core/mmu_sv39x4/cva6_ptw_sv39x4.sv @@ -19,6 +19,8 @@ /* verilator lint_off WIDTH */ +`include "common_cells/registers.svh" + module cva6_ptw_sv39x4 import ariane_pkg::*; #( @@ -596,43 +598,22 @@ module cva6_ptw_sv39x4 end // sequential process - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - state_q <= IDLE; - ptw_stage_q <= S_STAGE; - is_instr_ptw_q <= 1'b0; - ptw_lvl_q <= LVL1; - gptw_lvl_q <= LVL1; - tag_valid_q <= 1'b0; - tlb_update_asid_q <= '0; - tlb_update_vmid_q <= '0; - vaddr_q <= '0; - gpaddr_q <= '0; - ptw_pptr_q <= '0; - gptw_pptr_q <= '0; - global_mapping_q <= 1'b0; - data_rdata_q <= '0; - gpte_q <= '0; - data_rvalid_q <= 1'b0; - end else begin - state_q <= state_d; - ptw_stage_q <= ptw_stage_d; - ptw_pptr_q <= ptw_pptr_n; - gptw_pptr_q <= gptw_pptr_n; - is_instr_ptw_q <= is_instr_ptw_n; - ptw_lvl_q <= ptw_lvl_n; - gptw_lvl_q <= gptw_lvl_n; - tag_valid_q <= tag_valid_n; - tlb_update_asid_q <= tlb_update_asid_n; - tlb_update_vmid_q <= tlb_update_vmid_n; - vaddr_q <= vaddr_n; - gpaddr_q <= gpaddr_n; - global_mapping_q <= global_mapping_n; - data_rdata_q <= req_port_i.data_rdata; - gpte_q <= gpte_d; - data_rvalid_q <= req_port_i.data_rvalid; - end - end + `FFARNC(state_q , state_d , 0 , IDLE , clk_i, rst_ni) + `FFARNC(ptw_stage_q , ptw_stage_d , 0 , S_STAGE, clk_i, rst_ni) + `FFARNC(is_instr_ptw_q , is_instr_ptw_n , 1'b0 , 1'b0 , clk_i, rst_ni) + `FFARNC(ptw_lvl_q , ptw_lvl_n , 1'b0 , LVL1 , clk_i, rst_ni) + `FFARNC(gptw_lvl_q , gptw_lvl_n , 1'b0 , LVL1 , clk_i, rst_ni) + `FFARNC(tag_valid_q , tag_valid_n , 1'b0 , 1'b0 , clk_i, rst_ni) + `FFARNC(tlb_update_asid_q , tlb_update_asid_n , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(tlb_update_vmid_q , tlb_update_vmid_n , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(vaddr_q , vaddr_n , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(gpaddr_q , gpaddr_n , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(ptw_pptr_q , ptw_pptr_n , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(gptw_pptr_q , gptw_pptr_n , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(global_mapping_q , global_mapping_n , 1'b0 , 1'b0 , clk_i, rst_ni) + `FFARNC(data_rdata_q , req_port_i.data_rdata , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(gpte_q , gpte_d , 1'b0 , '0 , clk_i, rst_ni) + `FFARNC(data_rvalid_q , req_port_i.data_rvalid, 1'b0 , 1'b0 , clk_i, rst_ni) endmodule /* verilator lint_on WIDTH */ diff --git a/core/mmu_sv39x4/cva6_tlb_sv39x4.sv b/core/mmu_sv39x4/cva6_tlb_sv39x4.sv index f9cf01cb18..fbfa7fceeb 100644 --- a/core/mmu_sv39x4/cva6_tlb_sv39x4.sv +++ b/core/mmu_sv39x4/cva6_tlb_sv39x4.sv @@ -16,6 +16,7 @@ // This module is an adaptation of the Sv39 TLB developed // by Florian Zaruba and David Schaffenrath to the Sv39x4 standard. +`include "common_cells/registers.svh" module cva6_tlb_sv39x4 import ariane_pkg::*; @@ -357,17 +358,10 @@ module cva6_tlb_sv39x4 end // sequential process - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - tags_q <= '{default: 0}; - content_q <= '{default: 0}; - plru_tree_q <= '{default: 0}; - end else begin - tags_q <= tags_n; - content_q <= content_n; - plru_tree_q <= plru_tree_n; - end - end + `FFARNC(tags_q , tags_n , 1'b0, '{default: 0}, clk_i, rst_ni) + `FFARNC(content_q , content_n , 1'b0, '{default: 0}, clk_i, rst_ni) + `FFARNC(plru_tree_q, plru_tree_n, 1'b0, '{default: 0}, clk_i, rst_ni) + //-------------- // Sanity checks //-------------- diff --git a/core/serdiv.sv b/core/serdiv.sv index 328cfc7205..ae08c763e2 100644 --- a/core/serdiv.sv +++ b/core/serdiv.sv @@ -14,6 +14,7 @@ // Date: 18.10.2018 // Description: simple 64bit serial divider +`include "common_cells/registers.svh" module serdiv import ariane_pkg::*; @@ -246,34 +247,17 @@ module serdiv assign op_b_d = (b_reg_en) ? b_mux : op_b_q; assign res_d = (load_en) ? '0 : (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q; - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (~rst_ni) begin - state_q <= IDLE; - op_a_q <= '0; - op_b_q <= '0; - res_q <= '0; - cnt_q <= '0; - id_q <= '0; - rem_sel_q <= 1'b0; - comp_inv_q <= 1'b0; - res_inv_q <= 1'b0; - op_b_zero_q <= 1'b0; - op_b_neg_one_q <= 1'b0; - div_res_zero_q <= 1'b0; - end else begin - state_q <= state_d; - op_a_q <= op_a_d; - op_b_q <= op_b_d; - res_q <= res_d; - cnt_q <= cnt_d; - id_q <= id_d; - rem_sel_q <= rem_sel_d; - comp_inv_q <= comp_inv_d; - res_inv_q <= res_inv_d; - op_b_zero_q <= op_b_zero_d; - op_b_neg_one_q <= op_b_neg_one_d; - div_res_zero_q <= div_res_zero_d; - end - end + `FFARNC(state_q , state_d , 1'b0, IDLE, clk_i, rst_ni) + `FFARNC(op_a_q , op_a_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(op_b_q , op_b_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(res_q , res_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(id_q , id_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(rem_sel_q , rem_sel_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(comp_inv_q , comp_inv_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(res_inv_q , res_inv_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(op_b_zero_q , op_b_zero_d , 1'b0, '0 , clk_i, rst_ni) + `FFARNC(op_b_neg_one_q , op_b_neg_one_d, 1'b0, '0 , clk_i, rst_ni) + `FFARNC(div_res_zero_q , div_res_zero_d, 1'b0, '0 , clk_i, rst_ni) endmodule