From d519ad147f4de57a1ce0a113d2571ac89bf9db50 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Fri, 12 Jul 2024 15:53:37 +0200
Subject: [PATCH] Std cache TB: add bootrom to bender sources

---
 Bender.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Bender.yml b/Bender.yml
index 58b022c985..d37a0efe9e 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -307,6 +307,7 @@ sources:
           - corev_apu/tb/tb_std_cache_subsystem/hdl/icache_intf.sv
           - corev_apu/tb/tb_std_cache_subsystem/hdl/sram_intf.sv
           - corev_apu/tb/tb_std_cache_subsystem/hdl/cva6_cache_dummy.sv
+          - corev_apu/bootrom/bootrom.sv
 
     # TODO target define FPGA target + verification etc
     #   - target: test