From 63379810b4d5c469de3ba1a9aeb90a8387df8543 Mon Sep 17 00:00:00 2001
From: YenHaoChen <howard25336284@gmail.com>
Date: Wed, 26 Jul 2023 08:35:37 +0800
Subject: [PATCH] triggers: fix textra.sbytemask

Ignore corresponding bytes to the scontext and textra.svalue.
Cast 0xff to reg_t for the 34-bit textra64.svalue.
---
 riscv/triggers.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index 39a7330f70..b2b815dad7 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -84,7 +84,7 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept
     assert(CSR_TEXTRA32_SBYTEMASK_LENGTH < CSR_TEXTRA64_SBYTEMASK_LENGTH);
     for (int i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++)
       if (sbytemask & (1 << i))
-        mask &= 0xff << (i * 8);
+        mask &= ~(reg_t(0xff) << (i * 8));
     if ((state->scontext->read() & mask) != (svalue & mask))
       return false;
   } else if (sselect == SSELECT_ASID) {