From d04ee63de08a8dff1261d442f6d1b5b5c31955c7 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Fri, 16 Jun 2023 14:53:29 +0300 Subject: [PATCH 01/25] Use correct flash address for MAX32670 Signed-off-by: Sadik.Ozer --- pyocd/target/builtin/target_MAX32670.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyocd/target/builtin/target_MAX32670.py b/pyocd/target/builtin/target_MAX32670.py index 6dc9f5794..4873dd191 100644 --- a/pyocd/target/builtin/target_MAX32670.py +++ b/pyocd/target/builtin/target_MAX32670.py @@ -145,7 +145,7 @@ class MAX32670(CoreSightTarget): VENDOR = "Maxim" MEMORY_MAP = MemoryMap( - FlashRegion( start=0, length=0x60000, blocksize=0x2000, is_boot_memory=True, algo=FLASH_ALGO), + FlashRegion( start=0x10000000, length=0x60000, blocksize=0x2000, is_boot_memory=True, algo=FLASH_ALGO), RamRegion( start=0x20000000, length=0x28000), ) From 816fe8d5b31030172d084333224bfe57deaaab1f Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Fri, 16 Jun 2023 15:10:26 +0300 Subject: [PATCH 02/25] Add MAX32666FTHR board Signed-off-by: Sadik.Ozer --- pyocd/board/board_ids.py | 1 + pyocd/debug/svd/data/max32665.svd | 23314 ++++++++++++++++++++++ pyocd/target/builtin/__init__.py | 2 + pyocd/target/builtin/target_MAX32666.py | 166 + test/data/binaries/max32666fthr.bin | Bin 0 -> 32776 bytes 5 files changed, 23483 insertions(+) create mode 100644 pyocd/debug/svd/data/max32665.svd create mode 100644 pyocd/target/builtin/target_MAX32666.py create mode 100644 test/data/binaries/max32666fthr.bin diff --git a/pyocd/board/board_ids.py b/pyocd/board/board_ids.py index 1e0f2772b..30ce466ad 100644 --- a/pyocd/board/board_ids.py +++ b/pyocd/board/board_ids.py @@ -107,6 +107,7 @@ class BoardInfo(NamedTuple): "0418": BoardInfo( "MAX32620FTHR", "max32620", "max32620fthr.bin", ), "0420": BoardInfo( "MAX32630HSP3", "max32630", None ), "0421": BoardInfo( "MAX32660EVSYS", "max32660", "max32660evsys.bin", ), + "0422": BoardInfo( "MAX32666FTHR", "max32666", "max32666fthr.bin", ), "0424": BoardInfo( "MAX32670EVKIT", "max32670", "max32670evkit.bin", ), "0451": BoardInfo( "MTB MXChip EMW3166", "stm32f412xg", "mtb_mxchip_emw3166.bin",), "0459": BoardInfo( "MTB Advantech WISE-1530", "stm32f412xg", "mtb_wise-1530.bin", ), diff --git a/pyocd/debug/svd/data/max32665.svd b/pyocd/debug/svd/data/max32665.svd new file mode 100644 index 000000000..9dc82575d --- /dev/null +++ b/pyocd/debug/svd/data/max32665.svd @@ -0,0 +1,23314 @@ + + + Maxim-Integrated + Maxim + max32665 + ARMCM3 + 1.0 + MAX32665 32-bit ARM Cortex-M4 microcontroller, 128KB of system RAM, 4KB of One-Time-Programmable (OTP) memory, 64KB of Boot ROM, 8KB of battery-backed and AES self-encrypted SRAM. + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + 10-bit Analog to Digital Converter + 0x40034000 + 32 + read-write + + 0 + 0x1000 + registers + + + ADC + ADC IRQ + 20 + + + + CTRL + ADC Control + 0x0000 + read-write + + + start + Start ADC Conversion + [0:0] + read-write + + + pwr + ADC Power Up + [1:1] + read-write + + + refbuf_pwr + ADC Reference Buffer Power Up + [3:3] + read-write + + + ref_sel + ADC Reference Select + [4:4] + read-write + + + ref_scale + ADC Reference Scale + [8:8] + read-write + + + scale + ADC Scale + [9:9] + read-write + + + clk_en + ADC Clock Enable + [11:11] + read-write + + + ch_sel + ADC Channel Select + [16:12] + read-write + + + AIN0 + 0 + + + AIN1 + 1 + + + AIN2 + 2 + + + AIN3 + 3 + + + AIN4 + 4 + + + AIN5 + 5 + + + AIN6 + 6 + + + AIN7 + 7 + + + VcoreA + 8 + + + VcoreB + 9 + + + Vrxout + 10 + + + Vtxout + 11 + + + VddA + 12 + + + VddB + VddB/4 + 13 + + + Vddio + Vddio/4 + 14 + + + Vddioh + Vddioh/4 + 15 + + + VregI + VregI/4 + 16 + + + + + adc_divsel + Scales the external inputs, all inputs are scaled the same + [18:17] + read-write + + + DIV1 + 0 + + + DIV2 + 1 + + + DIV3 + 2 + + + DIV4 + 3 + + + + + data_align + ADC Data Alignment Select + [20:20] + read-write + + + + + STATUS + ADC Status + 0x0004 + read-write + + + active + ADC Conversion In Progress + [0:0] + read-only + + + afe_pwr_up_active + AFE Power Up Delay Active + [2:2] + read-only + + + overflow + ADC Overflow + [3:3] + read-only + + + + + DATA + ADC Output Data + 0x0008 + read-write + + + data + ADC Converted Sample Data Output + [15:0] + read-only + + + + + INTR + ADC Interrupt Control Register + 0x000C + read-write + + + done_ie + ADC Done Interrupt Enable + [0:0] + read-write + + + ref_ready_ie + ADC Reference Ready Interrupt Enable + [1:1] + read-write + + + hi_limit_ie + ADC Hi Limit Monitor Interrupt Enable + [2:2] + read-write + + + lo_limit_ie + ADC Lo Limit Monitor Interrupt Enable + [3:3] + read-write + + + overflow_ie + ADC Overflow Interrupt Enable + [4:4] + read-write + + + done_if + ADC Done Interrupt Flag + [16:16] + read-write + oneToClear + + + ref_ready_if + ADC Reference Ready Interrupt Flag + [17:17] + read-write + oneToClear + + + hi_limit_if + ADC Hi Limit Monitor Interrupt Flag + [18:18] + read-write + oneToClear + + + lo_limit_if + ADC Lo Limit Monitor Interrupt Flag + [19:19] + read-write + oneToClear + + + overflow_if + ADC Overflow Interrupt Flag + [20:20] + read-write + oneToClear + + + pending + ADC Interrupt Pending Status + [22:22] + read-only + + + + + 4 + 4 + LIMIT[%s] + ADC Limit + 0x0010 + read-write + + + ch_lo_limit + Low Limit Threshold + [9:0] + read-write + + + ch_hi_limit + High Limit Threshold + [21:12] + read-write + + + ch_sel + ADC Channel Select + [28:24] + read-write + + + ch_lo_limit_en + Low Limit Monitoring Enable + [29:29] + read-write + + + ch_hi_limit_en + High Limit Monitoring Enable + [30:30] + read-write + + + + + + + + AESKEYS + AES Key Registers. + 0x40005000 + + 0x00 + 0x400 + registers + + + + KEY0 + AES Key 0. + 0x000 + 32 + + + KEY1 + AES Key 1. + 0x080 + 32 + + + KEY2 + AES Key 2. + 0x100 + 32 + + + KEY3 + AES Key 3. + 0x180 + 32 + + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0_CH0 + 28 + + + DMA0_CH1 + 29 + + + DMA0_CH2 + 30 + + + DMA0_CH3 + 31 + + + DMA0_CH4 + 68 + + + DMA0_CH5 + 69 + + + DMA0_CH6 + 70 + + + DMA0_CH7 + 71 + + + + CN + DMA Control Register. + 0x000 + + + CH0_IEN + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1_IEN + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2_IEN + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3_IEN + Channel 3 Interrupt Enable. + 3 + 1 + + + CH4_IEN + Channel 4 Interrupt Enable. + 4 + 1 + + + CH5_IEN + Channel 5 Interrupt Enable. + 5 + 1 + + + CH6_IEN + Channel 6 Interrupt Enable. + 6 + 1 + + + CH7_IEN + Channel 7 Interrupt Enable. + 7 + 1 + + + + + INTR + DMA Interrupt Register. + 0x004 + read-only + + + CH0_IPEND + Channel 0 Interrupt Pending. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1_IPEND + Channel 1 Interrupt Pending. + 1 + 1 + + + CH2_IPEND + Channel 2 Interrupt Pending. + 2 + 1 + + + CH3_IPEND + Channel 3 Interrupt Pending. + 3 + 1 + + + CH4_IPEND + Channel 4 Interrupt Pending. + 4 + 1 + + + CH5_IPEND + Channel 5 Interrupt Pending. + 5 + 1 + + + CH6_IPEND + Channel 6 Interrupt Pending. + 6 + 1 + + + CH7_IPEND + Channel 7 Interrupt Pending. + 7 + 1 + + + + + 8 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CFG + DMA Channel Configuration Register. + 0x000 + + + CHEN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQSEL + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI1RX + SPI1 RX + 0x01 + + + SPI2RX + SPI2 RX + 0x02 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + ADC + Analog-to-Digital Converter Channel + 0x09 + + + I2C2RX + I2C2 RX + 0x0A + + + UART2RX + UART2 RX + 0x0E + + + SPI0RX + SPI0 RX + 0x0F + + + USBRXEP1 + USB Endpoint 1 RX + 0x11 + + + USBRXEP2 + USB Endpoint 2 RX + 0x12 + + + USBRXEP3 + USB Endpoint 3 RX + 0x13 + + + USBRXEP4 + USB Endpoint 4 RX + 0x14 + + + USBRXEP5 + USB Endpoint 5 RX + 0x15 + + + USBRXEP6 + USB Endpoint 6 RX + 0x16 + + + USBRXEP7 + USB Endpoint 7 RX + 0x17 + + + USBRXEP8 + USB Endpoint 8 RX + 0x18 + + + USBRXEP9 + USB Endpoint 9 RX + 0x19 + + + USBRXEP10 + USB Endpoint 10 RX + 0x1A + + + USBRXEP11 + USB Endpoint 11 RX + 0x1B + + + SPI1TX + SPI1 TX + 0x21 + + + SPI2TX + SPI2 TX + 0x22 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + I2C2TX + I2C2 TX + 0x2A + + + UART2TX + UART2 TX + 0x2E + + + SPI0TX + SPI0 TX + 0x2F + + + USBTXEP1 + USB Endpoint 1 TX + 0x31 + + + USBTXEP2 + USB Endpoint 2 TX + 0x32 + + + USBTXEP3 + USB Endpoint 3 TX + 0x33 + + + USBTXEP4 + USB Endpoint 4 TX + 0x34 + + + USBTXEP5 + USB Endpoint 5 TX + 0x35 + + + USBTXEP6 + USB Endpoint 6 TX + 0x36 + + + USBTXEP7 + USB Endpoint 7 TX + 0x37 + + + USBTXEP8 + USB Endpoint 8 TX + 0x38 + + + USBTXEP9 + USB Endpoint 9 TX + 0x39 + + + USBTXEP10 + USB Endpoint 10 TX + 0x3A + + + USBTXEP11 + USB Endpoint 11 TX + 0x3B + + + + + REQWAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOSEL + Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + PSSEL + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DISTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BRST + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + CHDIEN + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZIEN + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + ST + DMA Channel Status Register. + 0x004 + + + CH_ST + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_ST + Count-to-Zero (CTZ) Status + 2 + 1 + oneToClear + + ctz_st_enum_rd + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + ctz_st_enum_wr + write + + Clear + Clears the interrupt flag + 1 + + + + + RLD_ST + Reload Status. + 3 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + TO_ST + Time-Out Status. + 6 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRC_RLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + SRC_RLD + Source Address Reload Value. + 0 + 31 + + + + + DST_RLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + DST_RLD + Destination Address Reload Value. + 0 + 31 + + + + + CNT_RLD + DMA Channel Count Reload Register. + 0x01C + + + CNT_RLD + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + RLDEN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + DMA1 + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40035000 + 32 + + 0x00 + 0x1000 + registers + + + DMA1_CH0 + 72 + + + DMA1_CH1 + 73 + + + DMA1_CH2 + 74 + + + DMA1_CH3 + 75 + + + DMA1_CH4 + 76 + + + DMA1_CH5 + 77 + + + DMA1_CH6 + 78 + + + DMA1_CH7 + 79 + + + + + DVS + Dynamic Voltage Scaling + DVS_ + 0x40004800 + + 0x00 + 0x0030 + registers + + + DVS + Dynamic Voltage Scaling Interrupt + 83 + + + + CTL + Control Register + 0x00 + + + MON_ENA + Enable the DVS monitoring circuit + 0 + 1 + + + ADJ_ENA + Enable the power supply adjustment based on measurements + 1 + 1 + + + PS_FB_DIS + Power Supply Feedback Disable + 2 + 1 + + + CTRL_TAP_ENA + Use the TAP Select for automatic adjustment or monitoring + 3 + 1 + + + PROP_DLY + Additional delay to monitor lines + 4 + 2 + + + MON_ONESHOT + Measure delay once + 6 + 1 + + + GO_DIRECT + Operate in automatic mode or move directly + 7 + 1 + + + DIRECT_REG + Step incrementally to target voltage + 8 + 1 + + + PRIME_ENA + Include a delay line priming signal before monitoring + 9 + 1 + + + LIMIT_IE + Enable Limit Error Interrupt + 10 + 1 + + + RANGE_IE + Enable Range Error Interrupt + 11 + 1 + + + ADJ_IE + Enable Adjustment Error Interrupt + 12 + 1 + + + REF_SEL + Select TAP used for voltage adjustment + 13 + 4 + + + INC_VAL + Step size to increment voltage when in automatic mode + 17 + 3 + + + DVS_PS_APB_DIS + Prevent the application code from adjusting Vcore + 20 + 1 + + + DVS_HI_RANGE_ANY + Any high range signal from a delay line will cause a voltage adjustment + 21 + 1 + + + FB_TO_IE + Enable Voltage Adjustment Timeout Interrupt + 22 + 1 + + + FC_LV_IE + Enable Low Voltage Interrupt + 23 + 1 + + + PD_ACK_ENA + Prevent DVS from ack'ing a request to enter a low power mode until in the idle state + 24 + 1 + + + ADJ_ABORT + Causes the DVS to enter the idle state immediately on a request to enter a low power mode + 25 + 1 + + + + + STAT + Status Fields + 0x04 + 0x00000000 + + + DVS_STATE + State machine state + 0 + 4 + + + ADJ_UP_ENA + DVS Raising voltage + 4 + 1 + + + ADJ_DWN_ENA + DVS Lowering voltage + 5 + 1 + + + ADJ_ACTIVE + Adjustment to a Direct Voltage + 6 + 1 + + + CTR_TAP_OK + Tap Enabled and the Tap is withing Hi/Low limits + 7 + 1 + + + CTR_TAP_SEL + Status of selected center tap delay line detect output + 8 + 1 + + + SLOW_TRIP_DET + Provides the current combined status of all selected Low Range delay lines + 9 + 1 + + + FAST_TRIP_DET + Provides the current combined status of all selected High Range delay lines + 10 + 1 + + + PS_IN_RANGE + Indicates if the power supply is in range + 11 + 1 + + + PS_VCNTR + Voltage Count value sent to the power supply + 12 + 7 + + + MON_DLY_OK + Indicates the monitor delay count is at 0 + 19 + 1 + + + ADJ_DLY_OK + Indicates the adjustment delay count is at 0 + 20 + 1 + + + LO_LIMIT_DET + Power supply voltage counter is at low limit + 21 + 1 + + + HI_LIMIT_DET + Power supply voltage counter is at high limit + 22 + 1 + + + VALID_TAP + At least one delay line has been enabled + 23 + 1 + + + LIMIT_ERR + Interrupt flag that indicates a voltage count is at/beyond manufacturer limits + 24 + 1 + + + RANGE_ERR + Interrupt flag that indicates a tap has an invalid value + 25 + 1 + + + ADJ_ERR + Interrupt flag that indicates up and down adjustment requested simultaneously + 26 + 1 + + + REF_SEL_ERR + Indicates the ref select register bit is out of range + 27 + 1 + + + FB_TO_ERR + Interrupt flag that indicates a timeout while adjusting the voltage + 28 + 1 + + + FB_TO_ERR_S + Interrupt flag that mirror FB_TO_ERR and is write one clear + 29 + 1 + + + FC_LV_DET_INT + Interrupt flag that indicates the power supply voltage requested is below the low threshold + 30 + 1 + + + FC_LV_DET_S + Interrupt flag that mirrors FC_LV_DET_INT + 31 + 1 + + + + + DIRECT + Direct control of target voltage + 0x08 + + + VOLTAGE + Sets the target power supply value + 0 + 7 + + + + + MON + Monitor Delay + 0x00C + + + DLY + Number of prescaled clocks between delay line samples + 0 + 24 + + + PRE + Number of clocks before DVS_MON_DLY is decremented + 24 + 8 + + + + + ADJ_UP + Up Delay Register + 0x010 + + + DLY + Number of prescaled clocks between updates of the adjustment delay counter + 0 + 16 + + + PRE + Number of clocks before DVS_ADJ_UP_DLY is decremented + 16 + 8 + + + + + ADJ_DWN + Down Delay Register + 0x014 + + + DLY + Number of prescaled clocks between updates of the adjustment delay counter + 0 + 16 + + + PRE + Number of clocks before DVS_ADJ_DWN_DLY is decremented + 16 + 8 + + + + + THRES_CMP + Up Delay Register + 0x018 + + + VCNTR_THRES_CNT + Value used to determine 'low voltage' range + 0 + 7 + + + VCNTR_THRES_MASK + Mask applied to threshold and vcount to determine if the device is in a low voltage range + 8 + 7 + + + + + 5 + 4 + TAP_SEL[%s] + DVS Tap Select Register + 0x1C + + + LO + Select delay line tap for lower bound of auto adjustment + 0 + 5 + + + LO_TAP_STAT + Returns last delay line tap value + 5 + 1 + + + CTR_TAP_STAT + Returns last delay line tap value + 6 + 1 + + + HI_TAP_STAT + Returns last delay line tap value + 7 + 1 + + + HI + Selects delay line tap for high point of auto adjustment + 8 + 5 + + + CTR + Selects delay line tap for center point of auto adjustment + 16 + 5 + + + COARSE + Selects delay line tap for coarse or fixed delay portion of the line + 24 + 3 + + + DET_DLY + Number of HCLK between delay line launch and sampling + 29 + 2 + + + DELAY_ACT + Set if the delay is active + 31 + 1 + + + + + + + + FCR + Function Control. + 0x40000800 + + 0x00 + 0x400 + registers + + + + FCR + Register 0. + 0x00 + read-write + + + USB_CLK_SEL + USB External Core Clock Select. + 16 + 1 + + + sys + Generated clock from system clock. + 0 + + + dig + Digital clock from a GPIO. + 1 + + + + + QSPI0_FNC_SEL + SPI0 Function Select. + 17 + 1 + + + hirc + High speed 96MHz oscillator. + 0 + + + ext_clk + External clock input. + 1 + + + + + I2C0_SDA_FILTER_EN + I2C0 SDA Pad Deglitcher enable. + 20 + 1 + + + dis + Deglitcher disabled. + 0 + + + en + Deglitcher enabled. + 1 + + + + + I2C0_SCL_FILTER_EN + I2C0 SCL Pad Deglitcher enable. + 21 + 1 + + + dis + Deglitcher disabled. + 0 + + + en + Deglitcher enabled. + 1 + + + + + I2C1_SDA_FILTER_EN + I2C1 SDA Pad Deglitcher enable. + 22 + 1 + + + dis + Deglitcher disabled. + 0 + + + en + Deglitcher enabled. + 1 + + + + + I2C1_SCL_FILTER_EN + I2C1 SCL Pad Deglitcher enable. + 23 + 1 + + + dis + Deglitcher disabled. + 0 + + + en + Deglitcher enabled. + 1 + + + + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CN + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONEIE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AFIE + 9 + 1 + + + + + ECC_DATA + Flash Controller ECC Data Register. + 0x28 + read-only + + + ECC_EVEN + Error Correction Code Even Data. + 0 + 8 + + + ECC_ODD + Error Correction Code Odd Data. + 16 + 8 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTNL + Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACNTL + Access control. + 0 + 32 + + + + + + + + FLC1 + Flash Memory Control. 1 + 0x40029400 + + FLC1 + FLC1 IRQ + 87 + + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SCON + System Control. + 0x00 + 0xFFFFFFFE + + + BSTAPEN + Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. + 0 + 1 + + + dis + Boundary Scan TAP port disabled. + 0 + + + en + Boundary Scan TAP port enabled. + 1 + + + + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + 1 + 2 + + + fix + Fixed Burst abritration. + 0 + + + round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 + 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + + + + CCACHE_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + DCACHE_FLUSH + Data Cache Flush. The system cache(s) will be flushed when this bit is set. + 7 + 1 + + + normal + Normal System Cache Operation + 0 + + + flush + System Cache is flushed + 1 + + + + + SRCC_DIS + SPIXR Cache Controller Disable. Disables the SRCC used for SPIXR code and data cache. Setting this field disables the cache and bypasses the cache line buffer. + 9 + 1 + + + en + Is enabled. + 0 + + + dis + Is Disabled. + 1 + + + + + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CHKRES + ROM Checksum Result. This bit is only valid when CHKRD=1. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + + + + OVR + Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range. + 16 + 2 + + + 0_9V + 0.9V +/- 10% + 0 + + + 1_0V + 1.0V +/- 10% + 1 + + + 1_1V + 1.1V +/- 10% + 2 + + + + + + + RSTR0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + 1 + + reset + read-write + + reset_done + Reset complete. + 0 + + + busy + Starts Reset or indicates reset in progress. + 1 + + + + + WDT0 + Watchdog Timer Reset. + 1 + 1 + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 + 1 + + + TIMER0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + + TIMER1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + + TIMER2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + + TIMER3 + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + 8 + 1 + + + TIMER4 + Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks. + 9 + 1 + + + TIMER5 + Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks. + 10 + 1 + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 13 + 1 + + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. + 14 + 1 + + + I2C0 + I2C0 Reset. + 16 + 1 + + + RTC + Real Time Clock Reset. + 17 + 1 + + + CRYPTO + Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. + 18 + 1 + + + SMPHR + SMPHR Reset. Setting this bit to 1 resets the SMPHR block. + 22 + 1 + + + USB + USB Reset. Setting this bit resets both USB blocks. + 23 + 1 + + + ADC + Analog to Digital Reset. + 26 + 1 + + + DMA1 + DMA 1 Reset. + 27 + 1 + + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 + 1 + + + SRST + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PRST + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYSTEM + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + + + + CLKCN + Clock Control. + 0x08 + 0x00000008 + + + PSC + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + CLKSEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + HIRC + HIRC Clock + 0 + + + XTAL32M + 32MHz Crystal is used for the system clock. + 2 + + + LIRC8 + 8kHz LIRC is used for the system clock. + 3 + + + HIRC96 + The internal 96 MHz oscillator is used for the system clock. + 4 + + + HIRC8 + The internal 8 MHz oscillator is used for the system clock. + 5 + + + XTAL32k + 32kHz is used for the system clock. + 6 + + + + + CKRDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + CCD + Cryptographic clock divider + 15 + 1 + read-only + + + non_div + The cryptographic accelerator clock is running in non-divided mode. + 0 + + + div + The cryptographic accelerator clock is running in divided mode. + 1 + + + + + X32M_EN + 32MHz Crystal Oscillator Enable. + 16 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + X32K_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + HIRC_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + HIRC96M_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 + 1 + + + HIRC8M_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 + 1 + + + HIRC8M_VS + 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M. + 21 + 1 + + + Vcor + VCore Supply + 0 + + + 1V + Dedicated 1v regulated supply. + 1 + + + + + X32M_RDY + 32MHz Crystal Oscillator Ready + 24 + 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + X32K_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + HIRC_RDY + 60MHz HIRC Ready. + 26 + 1 + + + HIRC96M_RDY + 96MHz HIRC Ready. + 27 + 1 + + + HIRC8M_RDY + 8MHz HIRC Ready. + 28 + 1 + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + deepsleep + DeepSleep Mode. + 2 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIOWKEN + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + RTCWKEN + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + USBWKEN + USB Wake Up Enable. This bit enables USB activity as wakeup source. + 6 + 1 + + + WUTWKEN + WUT Wake Up Enable. This bit enables WUT IRQ as wakeup source. + 7 + 1 + + + compwken + COMPARATOR Input Wake Up Enable. This bit enables COMP IRQ activity as wakeup source. + 8 + 1 + + + HIRCPD + HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + HIRC96MPD + 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. + 16 + 1 + + + HIRC8MPD + 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. + 17 + 1 + + + XTALPB + 32MHz Bluetooth Oscillator Bypass. + 20 + 1 + + + + + PCKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 + + + SDHCFRQ + SDHC Clock Frequency. This bits defines the clock frequency of SDHC. + 7 + 1 + + + 48MHz + 0 + + + 24MHz + 1 + + + + + ADCFRQ + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ). + 10 + 4 + + + AONCD + Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider. + 14 + 2 + + + div_4 + PCLK divide by 4. + 0 + + + div_8 + PCLK divide by 8. + 1 + + + div_16 + PCLK divide by 16. + 2 + + + div_32 + PCLK divide by 32. + 3 + + + + + + + PERCKCN0 + Peripheral Clock Disable. + 0x24 + + + GPIO0D + GPIO0 Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + GPIO1D + GPIO1 Disable. + 1 + 1 + + + USBD + USB Disable. + 3 + 1 + + + DMAD + DMA Disable. + 5 + 1 + + + SPI1D + SPI 1 Disable. + 6 + 1 + + + SPI2D + SPI 2 Disable. + 7 + 1 + + + UART0D + UART 0 Disable. + 9 + 1 + + + UART1D + UART 1 Disable. + 10 + 1 + + + I2C0D + I2C 0 Disable. + 13 + 1 + + + CRYPTOD + Crypto Disable. + 14 + 1 + + + TIMER0D + Timer 0 Disable. + 15 + 1 + + + TIMER1D + Timer 1 Disable. + 16 + 1 + + + TIMER2D + Timer 2 Disable. + 17 + 1 + + + TIMER3D + Timer 3 Disable. + 18 + 1 + + + TIMER4D + Timer 4 Disable. + 19 + 1 + + + TIMER5D + Timer 5 Disable. + 20 + 1 + + + ADCD + ADC Disable. + 23 + 1 + + + I2C1D + I2C 1 Disable. + 28 + 1 + + + PTD + PT Clock Disable. + 29 + 1 + + + SPIXIPD + SPI XiP Disable. + 30 + 1 + + + SPIMD + SPI XiP Master Controller Disable. + 31 + 1 + + + + + MEMCKCN + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + SYSRAM0LS + System RAM 0 Light Sleep Mode. + 16 + 1 + + + active + RAM is active. + 0 + + + light_sleep + RAM is in Light Sleep mode. + 1 + + + + + SYSRAM1LS + System RAM 1 Light Sleep Mode. + 17 + 1 + + + SYSRAM2LS + System RAM 2 Light Sleep Mode. + 18 + 1 + + + SYSRAM3LS + System RAM 3 Light Sleep Mode. + 19 + 1 + + + SYSRAM4LS + System RAM 4 Light Sleep Mode. + 20 + 1 + + + SYSRAM5LS + System RAM 5 Light Sleep Mode. + 21 + 1 + + + SYSRAM6LS + System RAM 6 Light Sleep Mode. + 22 + 1 + + + ICACHELS + ICache RAM Light Sleep Mode. + 24 + 1 + + + ICACHEXIPLS + ICACHE-XIP RAM Light Sleep Mode. + 25 + 1 + + + SCACHELS + SysCache RAM Light Sleep Mode. + 26 + 1 + + + CRYPTOLS + CRYPTO RAM Light Sleep Mode. + 27 + 1 + + + USBLS + USB FIFO Light Sleep Mode. + 28 + 1 + + + ROM0LS + ROM Light Sleep Mode. + 29 + 1 + + + ROM1LS + ROM1 Light Sleep Mode. + 30 + 1 + + + ICACHE1LS + ICache RAM Light Sleep Mode. + 31 + 1 + + + + + MEMZCN + Memory Zeroize Control. + 0x2C + + + SRAM0Z + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SRAM1Z + System RAM Block 1. + 1 + 1 + + + SRAM2 + System RAM Block 2. + 2 + 1 + + + SRAM3Z + System RAM Block 3. + 3 + 1 + + + SRAM4Z + System RAM Block 4. + 4 + 1 + + + SRAM5Z + System RAM Block 5. + 5 + 1 + + + SRAM6Z + System RAM Block 6. + 6 + 1 + + + ICACHEZ + Instruction Cache. + 8 + 1 + + + ICACHEXIPZ + Instruction Cache XIP Data and Tag Ram zeroizatoin. + 9 + 1 + + + SCACHEDATAZ + System Cache Data Ram Zeroization. + 10 + 1 + + + SCACHETAGZ + System Cache Tag Zeroization. + 11 + 1 + + + CRYPTOZ + Crypto (MAA) Memory. + 12 + 1 + + + USBFIFOZ + USB FIFO Zeroizatoin. + 13 + 1 + + + ICACHE1Z + Instruction Cache. + 14 + 1 + + + + + SYSST + System Status Register. + 0x40 + + + ICELOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + CODEINTERR + Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. + 1 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 + + + norm + Normal Operating Condition. + 0 + + + memory + Memory Fault. + 1 + + + + + + + RSTR1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + reset_read + read + + reset_done + Reset complete. + 0 + + + busy + Starts reset or indicates reset in progress. + 1 + + + + + PT + PT Reset. + 1 + 1 + + + SPIXIP + SPI XiP Master Reset. + 3 + 1 + + + XSPIM + GSPI XiP Master Controller Reset. + 4 + 1 + + + SDHC + SDHC/SDIO Reset. + 6 + 1 + + + OWIRE + OWIRE Reset. + 7 + 1 + + + WDT1 + WDT1 Reset. + 8 + 1 + + + SPI0 + SPI0 Reset. + 9 + 1 + + + SPIXMEM + SPIXMEM Reset. + 15 + 1 + + + SMPHR + SMPHR Reset. + 16 + 1 + + + WDT2 + WDT2 Reset. + 17 + 1 + + + BTLE + BTLE Reset. + 18 + 1 + + + AUDIO + AUDIO Reset. + 19 + 1 + + + I2C2 + I2C2 Reset. + 20 + 1 + + + RPU + RPU Reset. + 21 + 1 + + + HTMR0 + HTMR0 Reset. + 22 + 1 + + + HTMR1 + HTMR1 Reset. + 23 + 1 + + + DVS + DVS Reset. + 24 + 1 + + + SIMO + SIMO Reset. + 25 + 1 + + + + + PERCKCN1 + Peripheral Clock Disable. + 0x48 + + + BTLED + BTLE Disable. + 0 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + UART2D + UART2 Disable. + 1 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + TRNGD + TRNG Disable. + 2 + 1 + + + SCACHED + System Cache Clock Disable. + 7 + 1 + + + SDMAD + SDMA Clock Disable. + 8 + 1 + + + SMPHRD + Semaphore Clock Disable. + 9 + 1 + + + SDHCD + SDHC/SDIO Clock Disable. + 10 + 1 + + + ICACHEXIPD + ICache XIP Clock Disable. + 12 + 1 + + + OWIRED + One-Wire Clock Disable. + 13 + 1 + + + SPI0D + SPI0 Clock Disable. + 14 + 1 + + + SPIXIPDD + SPI-XIP Data Clock Disable + 20 + 1 + + + DMA1D + DMA1 Clock Disable + 21 + 1 + + + AUDIOD + AUDIO Clock Disable + 23 + 1 + + + I2C2D + I2C 2 Clock Disable + 24 + 1 + + + HTMR0D + HTMR 0 Clock Disable + 25 + 1 + + + HTMR1D + HTMR 1 Clock Disable + 26 + 1 + + + WDT0D + WDT0 Clock Disable + 27 + 1 + + + WDT1D + WDT1 Clock Disable + 28 + 1 + + + WDT2D + WDT2 Clock Disable + 29 + 1 + + + CPU1D + CPU1 Clock Disable + 31 + 1 + + + + + EVENT_EN + Event Enable Register. + 0x4C + + + CPU0DMAEVENT + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + CPU0DMA1EVENT + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + CPU0TXEVENT + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 + + + CPU1DMAEVENT + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 3 + 1 + + + CPU1DMA1EVENT + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 4 + 1 + + + CPU1TXEVENT + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 5 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSSIE + System Status Interrupt Enable Register. + 0x54 + + + ICEULIE + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + CIEIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + SCMFIE + System Cache Memory Fault Interrupt Enable. + 5 + 1 + + + + + ECC_ER + ECC Error Register + 0x64 + + + SYSRAM0ECCERR + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + SYSRAM1ECCERR + ECC System RAM1 Error Flag. Write 1 to clear. + 1 + 1 + + + SYSRAM2ECCERR + ECC System RAM2 Error Flag. Write 1 to clear. + 2 + 1 + + + SYSRAM3ECCERR + ECC System RAM3 Error Flag. Write 1 to clear. + 3 + 1 + + + SYSRAM4ECCERR + ECC System RAM4 Error Flag. Write 1 to clear. + 4 + 1 + + + SYSRAM5ECCERR + ECC System RAM5 Error Flag. Write 1 to clear. + 5 + 1 + + + SYSRAM6ECCERR + ECC System RAM6 Error Flag. Write 1 to clear. + 6 + 1 + + + IC0ECCERR + ECC Icache0 Error Flag. Write 1 to clear. + 8 + 1 + + + IC1ECCERR + ECC Icache1 Error Flag. Write 1 to clear. + 9 + 1 + + + ICXIPECCERR + ECC IcacheXIP Error Flag. Write 1 to clear. + 10 + 1 + + + FL0ECCERR + ECC Flash0 Error Flag. Write 1 to clear. + 11 + 1 + + + FL1ECCERR + ECC Flash1 Error Flag. Write 1 to clear. + 12 + 1 + + + + + ECC_CED + ECC Correctable Error Detected Register + 0x68 + + + SYSRAM0ECCNDED + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + SYSRAM1ECCNDED + ECC System RAM1 Not Double Error Detect. Write 1 to clear. + 1 + 1 + + + SYSRAM2ECCNDED + ECC System RAM2 Not Double Error Detect. Write 1 to clear. + 2 + 1 + + + SYSRAM3ECCNDED + ECC System RAM3 Not Double Error Detect. Write 1 to clear. + 3 + 1 + + + SYSRAM4ECCNDED + ECC System RAM4 Not Double Error Detect. Write 1 to clear. + 4 + 1 + + + SYSRAM5ECCNDED + ECC System RAM5 Not Double Error Detect. Write 1 to clear. + 5 + 1 + + + IC0ECCNDED + ECC Icache0 Not Double Error Detect. Write 1 to clear. + 8 + 1 + + + IC1ECCNDED + ECC Icache1 Not Double Error Detect. Write 1 to clear. + 9 + 1 + + + ICXIPECCNDED + ECC IcacheXIP Not Double Error Detect. Write 1 to clear. + 10 + 1 + + + FL0ECCNDED + ECC Flash0 Not Double Error Detect. Write 1 to clear. + 11 + 1 + + + FL1ECCNDED + ECC Flash1 Not Double Error Detect. Write 1 to clear. + 12 + 1 + + + + + ECC_IRQEN + ECC IRQ Enable Register + 0x6C + + + SYSRAM0ECCEN + System RAM0 ECC Error Interrupt Enable + 0 + 1 + + + SYSRAM1ECCEN + System RAM1 ECC Error Interrupt Enable + 1 + 1 + + + SYSRAM2ECCEN + System RAM2 ECC Error Interrupt Enable + 2 + 1 + + + SYSRAM3ECCEN + System RAM3 ECC Error Interrupt Enable + 3 + 1 + + + SYSRAM4ECCEN + System RAM4 ECC Error Interrupt Enable + 4 + 1 + + + SYSRAM5ECCEN + System RAM5 ECC Error Interrupt Enable + 5 + 1 + + + IC0ECCEN + Icache0 ECC Error Interrupt Enable + 8 + 1 + + + IC1ECCEN + Icache1 ECC Error Interrupt Enable + 9 + 1 + + + ICXIPECCEN + IcacheXIP ECC Error Interrupt Enable + 10 + 1 + + + FL0ECCEN + Flash0 NError ECC Interrupt Enable + 11 + 1 + + + FL1ECCEN + Flash1 ECC Error Interrupt Enable + 12 + 1 + + + + + ECC_ERRAD + ECC Error Address Register + 0x70 + + + DATARAMADDR + ECC Error Address.Data Ram Address. + 0 + 13 + + + DATARAMBANK + ECC Error Address.Data Error Bank. + 14 + 1 + + + DATARAMERR + ECC Error Address.Data Ram Error. + 15 + 1 + + + TAGRAMADDR + ECC Error Address.Tag Ram Address. + 16 + 13 + + + TAGRAMBANK + ECC Error Address.Tag Ram Bank. + 30 + 1 + + + TAGRAMERR + ECC Error Address.Tag Ram Error. + 31 + 1 + + + + + BTLE_LDOCR + BTLE LDO Control Register + 0x74 + + + LDOTXEN + LDOTX Enable + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXOPULLD + LDOTX PULL Disable + 1 + 1 + + + en + enabled. + 0 + + + dis + disabled. + 1 + + + + + LDOTXVSEL + LDOTX Voltage Setting + 2 + 2 + + + 0_7 + 0.7V + 0 + + + 0_85 + 0.85V + 1 + + + 0_9 + 0.9V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDORXEN + LDORX Enable + 4 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXPULLD + LDORX Pulldown + 5 + 1 + + + en + enabled. + 0 + + + dis + disabled. + 1 + + + + + LDORXVSEL + LDORX Output Voltage Setting + 6 + 2 + + + 0_7 + 0.7V + 0 + + + 0_85 + 0.85V + 1 + + + 0_9 + 0.9V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDORXBYP + LDORX Bypass Enable + 8 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXDISCH + LDORX Discharge + 9 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXBYP + LDOTX Bypass Enable + 10 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXDISCH + LDOTX Discharge + 11 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXENDLY + LDOTX Enable Delay + 12 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXENDLY + LDORX Enable Delay + 13 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXBYPENENDLY + LDOTX Bypass Enable Delay + 14 + 1 + + + LDOTXBYPENENDLY + LDORX Bypass Enable Delay + 15 + 1 + + + + + BTLE_LDODCR + BTLE LDO Delay Register + 0x78 + + + BYPDLYCNT + Bypass Delay Count. Count delay base on PCLK. + 0 + 8 + + + LDORXDLYCNT + LDORX Delay Count. Count delay base on PCLK/128. + 8 + 9 + + + LDOTXDLYCNT + LDOTX Delay Count. Count delay base on PCLK/128. + 20 + 9 + + + + + GP0 + General Purpose Register 0 + 0x80 + + + GPR0 + User-defined register RAM. + 0 + 32 + + + + + APB_ASYNC + APB Asynchronous Bridge Select Register + 0x84 + + + APBASYNCI2C0 + Feeds I2C0 with either PCLK or 7.37MHz Clk + 0 + 1 + + + pclk + PCLK Source + 0 + + + 7mclk + 7.37MHz Source + 1 + + + + + APBASYNCI2C1 + Feeds I2C1 with either PCLK or 7.37MHz Clk + 1 + 1 + + + APBASYNCI2C2 + Feeds I2C2 with either PCLK or 7.37MHz Clk + 2 + 1 + + + APBASYNCPT + Feeds PT with either PCLK or 7.37MHz Clk + 3 + 1 + + + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + GPIO_EN + Mask of all of the pins on the port. + 0 + 32 + + + alternate + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + GPIO_OUT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUT_EN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + GPIO_OUT + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + GPIO_OUT_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + GPIO_OUT_CLR + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + GPIO_IN + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_MOD + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + GPIO_INT_MOD + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INT_POL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + GPIO_INT_POL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + IN_EN + GPIO Port Input Enable. + 0x30 + + + GPIO_IN_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Input Disable + 0 + + + en + GPIO Input Enable + 1 + + + + + + + INT_EN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + GPIO_INT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INT_EN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + GPIO_INT_EN_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INT_EN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + GPIO_INT_EN_CLR + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INT_STAT + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + GPIO_INT_STAT + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INT_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + GPIO_WAKE_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WAKE_EN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_DUAL_EDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + GPIO_INT_DUAL_EDGE + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PAD_CFG1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + GPIO_PAD_CFG1 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PAD_CFG2 + GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + GPIO_PAD_CFG2 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + GPIO_EN1 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + GPIO_EN2 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DS0 + GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PS + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + GPIO1 + Individual I/O for each GPIO 1 + 0x40009000 + + GPIO1 + GPIO1 IRQ + 25 + + + + + HTMR + High Speed Timer Module. + 0x4001B000 + + 0x00 + 0xFFF + registers + + + HTimer + HTimer interrupt. + 93 + + + + SEC + HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter. + 0x00 + 0x00000000 + + + RTS + HTimer Long Interval Counter. + 0 + 31 + + + + + SSEC + HTimer Short Interval Counter. This counter ticks ever t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + RTSS + HTimer Short Interval Counter. + 0 + 8 + + + + + RAS + Long Interval Alarm. + 0x08 + 0x00000000 + + + RAS + HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0] + 0 + 20 + + + + + RSSA + HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. + 0x0C + 0x00000000 + + + RSSA + This register contains the reload value for the short interval alarm. + 0 + 32 + + + + + CTRL + HTimer Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + HTEN + HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ADE + Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ASE + Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDYE + HTimer Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ALDF + Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active + 0 + + + pending + Active + 1 + + + + + ALSF + Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + WE + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. + 15 + 1 + + + dis + Not active + 0 + + + en + Active + 1 + + + + + + + + + + HTMR1 + High Speed Timer Module. 1 + 0x4001C000 + + HTMR1 + HTMR1 IRQ + 94 + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL + Control Register. + 0x00 + + + I2C_EN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + MST + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + GEN_CALL_ADDR + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + RX_MODE + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + RX_MODE_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + SW_OUT_EN + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + SCL_CLK_STRETCH_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + SCL_PP_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: drive low for 0, drive high for 1 + 1 + + + + + HS_MODE + Hs-mode Enable. + 15 + 1 + + + dis + Hs-mode disabled. + 0 + + + en + Hs-mode enabled. + 1 + + + + + + + STATUS + Status Register. + 0x04 + + + BUS + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RX_EMPTY + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RX_FULL + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TX_EMPTY + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TX_FULL + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + CLK_MODE + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + + + INT_FL0 + Interrupt Status Register. + 0x08 + + + DONE + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_MODE + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GEN_CALL_ADDR + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_THRESH + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TX_THRESH + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOP + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARB_ER + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TO_ER + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_NACK_ER + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATA_ER + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DO_NOT_RESP_ER + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START_ER + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOP_ER + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_LOCK_OUT + Transmit Lock Out Interrupt. + [15:15] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt. + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt. + [23:23] + + + + + INT_EN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + RX_MODE + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GEN_CALL_ADDR + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RX_THRESH + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_THRESH + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARB_ER + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TO_ER + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADDR_NACK_ER + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATA_ER + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DO_NOT_RESP_ER + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + START_ER + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP_ER + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_LOCK_OUT + TX FIFO Locked Out Interrupt. + [15:15] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when TXLOIE = 1. + 1 + + + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt. + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt. + [23:23] + + + + + INT_FL1 + Interrupt Status Register 1. + 0x10 + + + RX_OVERFLOW + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_UNDERFLOW + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START + START Condition Interrupt. + [2:2] + + + + + INT_EN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RX_OVERFLOW + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TX_UNDERFLOW + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + START + START Condition Interrupt Enable. + [2:2] + + + + + FIFO_LEN + FIFO Configuration Register. + 0x18 + + + RX_LEN + Receive FIFO Length. + [7:0] + read-only + + + TX_LEN + Transmit FIFO Length. + [15:8] + read-only + + + + + RX_CTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + RX_FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + RX_THRESH + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RX_CTRL1 + Receive Control Register 1. + 0x20 + + + RX_CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + RX_FIFO + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TX_CTRL0 + Transmit Control Register 0. + 0x24 + + + TX_PRELOAD + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + TX_AMGC_AFD + TX FIFO General Call Address Match Auto Flush. + [2:2] + + + TX_AMW_AFD + TX FIFO Slave Address Match Write Auto Flush. + [3:3] + + + TX_AMR_AFD + TX FIFO Slave Address Match Read Auto Flush. + [4:4] + + + TX_NACK_AFD + TX FIFO received NACK Auto Flush. + [5:5] + + + TX_FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + TX_THRESH + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TX_CTRL1 + Transmit Control Register 1. + 0x28 + + + TX_READY + Transmit FIFO Preload Ready. + [0:0] + + + TXFIFO + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MASTER_CTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + SL_EX_ADDR + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + MCODE + Master Code. These bits set the Master Code used in Hs-mode operation. + [10:8] + + + SCL_SPEED_UP + Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves. + [11:11] + + + en + Master monitors SCL state. + 0 + + + dis + SCL state monitoring disabled. + 1 + + + + + + + CLK_LO + Clock Low Register. + 0x34 + + + SCL_LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLK_HI + Clock high Register. + 0x38 + + + SCL_HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HS_CLK + HS-Mode Clock Control Register + 0x3C + + + HS_CLK_LO + Slave Address. + [7:0] + + + HS_CLK_HI + Slave Address. + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + TO + Timeout + [15:0] + + + + + DMA + DMA Register. + 0x48 + + + TXEN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RXEN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + SLAVE_ADDR + Slave Address Register. + 0x4C + + + SLAVE_ADDR + Slave Address. + [9:0] + + + EX_ADDR + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + I2C2 + Inter-Integrated Circuit. 2 + 0x4001F000 + + I2C2 + I2C2 IRQ + 62 + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x1000 + registers + + + + CACHE_ID + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + CCHID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + MEMCFG + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCHSZ + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEMSZ + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CACHE_CTRL + Cache Control and Status Register. + 0x0100 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + INVALID + Invalidate. + 0 + 32 + + + + + + + + ICC1 + Instruction Cache Controller Registers 1 + 0x4002AC000 + + + + MCR + Misc Control. + 0x40006C00 + + 0x00 + 0x400 + registers + + + + ECCEN + ECC Enable Register + 0x00 + + + SYSRAM0ECCEN + ECC System RAM Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SYSRAM1ECCEN + ECC System RAM Enable. + 1 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SYSRAM2ECCEN + ECC System RAM Enable. + 2 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SYSRAM3ECCEN + ECC System RAM Enable. + 3 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SYSRAM4ECCEN + ECC System RAM Enable. + 4 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SYSRAM5ECCEN + ECC System RAM Enable. + 5 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + IC0ECCEN + Icache0 ECC Enable. + 8 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + IC1ECCEN + Icache1 ECC Enable. + 9 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + ICXIPFECCEN + IcacheXIP ECC Enable. + 10 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + FL0ECCEN + Flash0 ECC Enable. + 11 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + FL1ECCEN + Flash1 ECC Enable. + 12 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + HIRC96M + 96MHz High Frequency Clock Adjustment Register + 0x04 + + + HIRC96MTR + HIRC96M Trim: Allow user to change 96M Frequency + 0 + 9 + + + default + Default setting. + 0x100 + + + + + + + OUTEN + GPIOOUT_EN Function Enable Register + 0x08 + + + SQWOUT0EN + Allows SQWOUT on GPIO0_19 + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SQWOUT1EN + Allows SQWOUT on GPIO0_27 + 1 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + PDOWNOUT0EN + Allows PDOWN on GPIO0_18 + 2 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + PDOWNOUT1EN + Allows PDOWN on GPIO0_26 + 3 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + AINCOMP + Comparator Power Control Register + 0x0C + + + AINCOMP0PD + Power Down AIN Comp0 + 0 + 1 + + + on + power on + 0 + + + off + power off + 1 + + + + + AINCOMP1PD + Power Down AIN Comp1 + 1 + 1 + + + on + power on + 0 + + + off + power off + 1 + + + + + AINCOMP2PD + Power Down AIN Comp2 + 2 + 1 + + + on + power on + 0 + + + off + power off + 1 + + + + + AINCOMP3PD + Power Down AIN Comp3 + 3 + 1 + + + on + power on + 0 + + + off + power off + 1 + + + + + AINCOMPHYST + Set Hysteresis on Analog Comparators + 4 + 2 + + + + + CTRL + Misc Power State Control Register + 0x10 + + + VDDCSWEN + Allows switching VDDC from VCOREA to VCOREB + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + VDDCSW + Controls switching of VCORE + 1 + 2 + + + USBSWEN_N + USB Switch Control + 3 + 1 + + + off + USB SW off in LP modes + 1 + + + on + USB SW On + 0 + + + + + BUCKCLKSCALEN + Allows Dynamic scaling of SIMO clock, reduces power in LP Modes + 8 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + P1M + Enable the Reset Pad Pull Up Resistors + 9 + 1 + + + 1m + 1MOhm Pullup + 0 + + + 25k + 25kOhm Pullup. + 1 + + + + + RSTN_VOLTAGE_SEL + Error! Description not Found! + 10 + 1 + + + + + + + + OWM + 1-Wire Master Interface. + 0x4003D000 + 32 + read-write + + 0 + 0x1000 + registers + + + OneWire + 67 + + + + CFG + 1-Wire Master Configuration. + 0x0000 + read-write + + + long_line_mode + Long Line Mode. + [0:0] + read-write + + + force_pres_det + Force Line During Presence Detect. + [1:1] + read-write + + + bit_bang_en + Bit Bang Enable. + [2:2] + read-write + + + ext_pullup_mode + Provide an extra output control to control an external pullup. + [3:3] + read-write + + + ext_pullup_enable + Enable External Pullup. + [4:4] + read-write + + + single_bit_mode + Enable Single Bit TX/RX Mode. + [5:5] + read-write + + + overdrive + Enables overdrive speed for 1-Wire operations. + [6:6] + read-write + + + int_pullup_enable + Enable intenral pullup. + [7:7] + read-write + + + + + CLK_DIV_1US + 1-Wire Master Clock Divisor. + 0x0004 + read-write + + + divisor + Clock Divisor for 1Mhz. + [7:0] + read-write + + + + + CTRL_STAT + 1-Wire Master Control/Status. + 0x0008 + read-write + + + start_ow_reset + Start OW Reset. + [0:0] + read-write + + + sra_mode + SRA Mode. + [1:1] + read-write + + + bit_bang_oe + Bit Bang Output Enable. + [2:2] + read-write + + + ow_input + OW Input State. + [3:3] + read-only + + + od_spec_mode + Overdrive Spec Mode. + [4:4] + read-only + + + presence_detect + Presence Pulse Detected. + [5:5] + read-only + + + + + DATA + 1-Wire Master Data Buffer. + 0x000C + read-write + + + tx_rx + TX/RX Buffer. + [7:0] + read-write + + + + + INTFL + 1-Wire Master Interrupt Flags. + 0x0010 + read-write + + + ow_reset_done + OW Reset Sequence Completed. + [0:0] + read-write + + + tx_data_empty + TX Data Empty Interrupt Flag. + [1:1] + read-write + + + rx_data_ready + RX Data Ready Interrupt Flag + [2:2] + read-write + + + line_short + OW Line Short Detected Interrupt Flag. + [3:3] + read-write + + + line_low + OW Line Low Detected Interrupt Flag. + [4:4] + read-write + + + + + INTEN + 1-Wire Master Interrupt Enables. + 0x0014 + read-write + + + ow_reset_done + OW Reset Sequence Completed. + [0:0] + read-write + oneToClear + + + tx_data_empty + Tx Data Empty Interrupt Enable. + [1:1] + read-write + oneToClear + + + rx_data_ready + Rx Data Ready Interrupt Enable. + [2:2] + read-write + oneToClear + + + line_short + OW Line Short Detected Interrupt Enable. + [3:3] + read-write + oneToClear + + + line_low + OW Line Low Detected Interrupt Enable. + [4:4] + read-write + oneToClear + + + + + + + + PT + Pulse Train + Pulse_Train + 0x4003C020 + 32 + read-write + + 0 + 0x0010 + registers + + + + RATE_LENGTH + Pulse Train Configuration + 0x0000 + read-write + + + rate_control + Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. + 0 + 27 + read-write + + + mode + Pulse Train Output Mode/Train Length + 27 + 5 + read-write + + + 32_BIT + Pulse train, 32 bit pattern. + 0 + + + SQUARE_WAVE + Square wave mode. + 1 + + + 2_BIT + Pulse train, 2 bit pattern. + 2 + + + 3_BIT + Pulse train, 3 bit pattern. + 3 + + + 4_BIT + Pulse train, 4 bit pattern. + 4 + + + 5_BIT + Pulse train, 5 bit pattern. + 5 + + + 6_BIT + Pulse train, 6 bit pattern. + 6 + + + 7_BIT + Pulse train, 7 bit pattern. + 7 + + + 8_BIT + Pulse train, 8 bit pattern. + 8 + + + 9_BIT + Pulse train, 9 bit pattern. + 9 + + + 10_BIT + Pulse train, 10 bit pattern. + 10 + + + 11_BIT + Pulse train, 11 bit pattern. + 11 + + + 12_BIT + Pulse train, 12 bit pattern. + 12 + + + 13_BIT + Pulse train, 13 bit pattern. + 13 + + + 14_BIT + Pulse train, 14 bit pattern. + 14 + + + 15_BIT + Pulse train, 15 bit pattern. + 15 + + + 16_BIT + Pulse train, 16 bit pattern. + 16 + + + 17_BIT + Pulse train, 17 bit pattern. + 17 + + + 18_BIT + Pulse train, 18 bit pattern. + 18 + + + 19_BIT + Pulse train, 19 bit pattern. + 19 + + + 20_BIT + Pulse train, 20 bit pattern. + 20 + + + 21_BIT + Pulse train, 21 bit pattern. + 21 + + + 22_BIT + Pulse train, 22 bit pattern. + 22 + + + 23_BIT + Pulse train, 23 bit pattern. + 23 + + + 24_BIT + Pulse train, 24 bit pattern. + 24 + + + 25_BIT + Pulse train, 25 bit pattern. + 25 + + + 26_BIT + Pulse train, 26 bit pattern. + 26 + + + 27_BIT + Pulse train, 27 bit pattern. + 27 + + + 28_BIT + Pulse train, 28 bit pattern. + 28 + + + 29_BIT + Pulse train, 29 bit pattern. + 29 + + + 30_BIT + Pulse train, 30 bit pattern. + 30 + + + 31_BIT + Pulse train, 31 bit pattern. + 31 + + + + + + + TRAIN + Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. + 0x0004 + read-write + + + LOOP + Pulse Train Loop Count + 0x0008 + read-write + + + count + Number of loops for this pulse train to repeat. + 0 + 16 + read-write + + + delay + Delay between loops of the Pulse Train in PT Peripheral Clock cycles + 16 + 12 + read-write + + + + + RESTART + Pulse Train Auto-Restart Configuration. + 0x000C + read-write + + + pt_x_select + Auto-Restart PT X Select + 0 + 5 + read-write + + + on_pt_x_loop_exit + Enable Auto-Restart on PT X Loop Exit + 7 + 1 + read-write + + + pt_y_select + Auto-Restart PT Y Select + 8 + 5 + read-write + + + on_pt_y_loop_exit + Enable Auto-Restart on PT Y Loop Exit + 15 + 1 + read-write + + + + + + + + PT1 + Pulse Train 1 + 0x4003C030 + + + + PT2 + Pulse Train 2 + 0x4003C040 + + + + PT3 + Pulse Train 3 + 0x4003C050 + + + + PT4 + Pulse Train 4 + 0x4003C060 + + + + PT5 + Pulse Train 5 + 0x4003C070 + + + + PT6 + Pulse Train 6 + 0x4003C080 + + + + PT7 + Pulse Train 7 + 0x4003C090 + + + + PT8 + Pulse Train 8 + 0x4003C0A0 + + + + PT9 + Pulse Train 9 + 0x4003C0B0 + + + + PT10 + Pulse Train 10 + 0x4003C0C0 + + + + PT11 + Pulse Train 11 + 0x4003C0D0 + + + + PT12 + Pulse Train 12 + 0x4003C0E0 + + + + PT13 + Pulse Train 13 + 0x4003C0F0 + + + + PT14 + Pulse Train 14 + 0x4003C100 + + + + PT15 + Pulse Train 15 + 0x4003C110 + + + + PTG + Pulse Train Generation + Pulse_Train + 0x4003C000 + 32 + read-write + + 0 + 0x0018 + registers + + + PT + Pulse Train IRQ + 59 + + + + ENABLE + Global Enable/Disable Controls for All Pulse Trains + 0x0000 + read-write + + + pt0 + Enable/Disable control for PT0 + 0 + 1 + read-write + + + pt1 + Enable/Disable control for PT1 + 1 + 1 + read-write + + + pt2 + Enable/Disable control for PT2 + 2 + 1 + read-write + + + pt3 + Enable/Disable control for PT3 + 3 + 1 + read-write + + + pt4 + Enable/Disable control for PT4 + 4 + 1 + read-write + + + pt5 + Enable/Disable control for PT5 + 5 + 1 + read-write + + + pt6 + Enable/Disable control for PT6 + 6 + 1 + read-write + + + pt7 + Enable/Disable control for PT7 + 7 + 1 + read-write + + + pt8 + Enable/Disable control for PT8 + 8 + 1 + read-write + + + pt9 + Enable/Disable control for PT9 + 9 + 1 + read-write + + + pt10 + Enable/Disable control for PT10 + 10 + 1 + read-write + + + pt11 + Enable/Disable control for PT11 + 11 + 1 + read-write + + + pt12 + Enable/Disable control for PT12 + 12 + 1 + read-write + + + pt13 + Enable/Disable control for PT13 + 13 + 1 + read-write + + + pt14 + Enable/Disable control for PT14 + 14 + 1 + read-write + + + pt15 + Enable/Disable control for PT15 + 15 + 1 + read-write + + + + + RESYNC + Global Resync (All Pulse Trains) Control + 0x0004 + read-write + + + pt0 + Resync control for PT0 + 0 + 1 + read-write + + + pt1 + Resync control for PT1 + 1 + 1 + read-write + + + pt2 + Resync control for PT2 + 2 + 1 + read-write + + + pt3 + Resync control for PT3 + 3 + 1 + read-write + + + pt4 + Resync control for PT4 + 4 + 1 + read-write + + + pt5 + Resync control for PT5 + 5 + 1 + read-write + + + pt6 + Resync control for PT6 + 6 + 1 + read-write + + + pt7 + Resync control for PT7 + 7 + 1 + read-write + + + pt8 + Resync control for PT8 + 8 + 1 + read-write + + + pt9 + Resync control for PT9 + 9 + 1 + read-write + + + pt10 + Resync control for PT10 + 10 + 1 + read-write + + + pt11 + Resync control for PT11 + 11 + 1 + read-write + + + pt12 + Resync control for PT12 + 12 + 1 + read-write + + + pt13 + Resync control for PT13 + 13 + 1 + read-write + + + pt14 + Resync control for PT14 + 14 + 1 + read-write + + + pt15 + Resync control for PT15 + 15 + 1 + read-write + + + + + INTFL + Pulse Train Interrupt Flags + 0x0008 + read-write + + + pt0 + Pulse Train 0 Stopped Interrupt Flag + 0 + 1 + read-write + + + pt1 + Pulse Train 1 Stopped Interrupt Flag + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Stopped Interrupt Flag + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Stopped Interrupt Flag + 3 + 1 + read-write + + + pt4 + Pulse Train 4 Stopped Interrupt Flag + 4 + 1 + read-write + + + pt5 + Pulse Train 5 Stopped Interrupt Flag + 5 + 1 + read-write + + + pt6 + Pulse Train 6 Stopped Interrupt Flag + 6 + 1 + read-write + + + pt7 + Pulse Train 7 Stopped Interrupt Flag + 7 + 1 + read-write + + + pt8 + Pulse Train 8 Stopped Interrupt Flag + 8 + 1 + read-write + + + pt9 + Pulse Train 9 Stopped Interrupt Flag + 9 + 1 + read-write + + + pt10 + Pulse Train 10 Stopped Interrupt Flag + 10 + 1 + read-write + + + pt11 + Pulse Train 11 Stopped Interrupt Flag + 11 + 1 + read-write + + + pt12 + Pulse Train 12 Stopped Interrupt Flag + 12 + 1 + read-write + + + pt13 + Pulse Train 13 Stopped Interrupt Flag + 13 + 1 + read-write + + + pt14 + Pulse Train 14 Stopped Interrupt Flag + 14 + 1 + read-write + + + pt15 + Pulse Train 15 Stopped Interrupt Flag + 15 + 1 + read-write + + + + + INTEN + Pulse Train Interrupt Enable/Disable + 0x000C + read-write + + + pt0 + Pulse Train 0 Stopped Interrupt Enable/Disable + 0 + 1 + read-write + + + pt1 + Pulse Train 1 Stopped Interrupt Enable/Disable + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Stopped Interrupt Enable/Disable + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Stopped Interrupt Enable/Disable + 3 + 1 + read-write + + + pt4 + Pulse Train 4 Stopped Interrupt Enable/Disable + 4 + 1 + read-write + + + pt5 + Pulse Train 5 Stopped Interrupt Enable/Disable + 5 + 1 + read-write + + + pt6 + Pulse Train 6 Stopped Interrupt Enable/Disable + 6 + 1 + read-write + + + pt7 + Pulse Train 7 Stopped Interrupt Enable/Disable + 7 + 1 + read-write + + + pt8 + Pulse Train 8 Stopped Interrupt Enable/Disable + 8 + 1 + read-write + + + pt9 + Pulse Train 9 Stopped Interrupt Enable/Disable + 9 + 1 + read-write + + + pt10 + Pulse Train 10 Stopped Interrupt Enable/Disable + 10 + 1 + read-write + + + pt11 + Pulse Train 11 Stopped Interrupt Enable/Disable + 11 + 1 + read-write + + + pt12 + Pulse Train 12 Stopped Interrupt Enable/Disable + 12 + 1 + read-write + + + pt13 + Pulse Train 13 Stopped Interrupt Enable/Disable + 13 + 1 + read-write + + + pt14 + Pulse Train 14 Stopped Interrupt Enable/Disable + 14 + 1 + read-write + + + pt15 + Pulse Train 15 Stopped Interrupt Enable/Disable + 15 + 1 + read-write + + + + + SAFE_EN + Pulse Train Global Safe Enable. + 0x0010 + write-only + + + PT0 + 0 + 1 + write-only + + + PT1 + 1 + 1 + write-only + + + PT2 + 2 + 1 + write-only + + + PT3 + 3 + 1 + write-only + + + PT4 + 4 + 1 + write-only + + + PT5 + 5 + 1 + write-only + + + PT6 + 6 + 1 + write-only + + + PT7 + 7 + 1 + write-only + + + PT8 + 8 + 1 + write-only + + + PT9 + 9 + 1 + write-only + + + PT10 + 10 + 1 + write-only + + + PT11 + 11 + 1 + write-only + + + PT12 + 12 + 1 + write-only + + + PT13 + 13 + 1 + write-only + + + PT14 + 14 + 1 + write-only + + + PT15 + 15 + 1 + write-only + + + + + SAFE_DIS + Pulse Train Global Safe Disable. + 0x0014 + write-only + + + PT0 + 0 + 1 + write-only + + + PT1 + 1 + 1 + write-only + + + PT2 + 2 + 1 + write-only + + + PT3 + 3 + 1 + write-only + + + PT4 + 4 + 1 + write-only + + + PT5 + 5 + 1 + write-only + + + PT6 + 6 + 1 + write-only + + + PT7 + 7 + 1 + write-only + + + PT8 + 8 + 1 + write-only + + + PT9 + 9 + 1 + write-only + + + PT10 + 10 + 1 + write-only + + + PT11 + 11 + 1 + write-only + + + PT12 + 12 + 1 + write-only + + + PT13 + 13 + 1 + write-only + + + PT14 + 14 + 1 + write-only + + + PT15 + 15 + 1 + write-only + + + + + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x400 + registers + + + + LPCN + Low Power Control Register. + 0x00 + + + RAMRET + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 0 + 2 + + + dis + Disable Ram Retention. + 0 + + + en1 + Enable System RAM 0 retention. + 1 + + + en2 + Enable System RAM 0 and 1 retention. + 2 + + + en3 + Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention. + 3 + + + + + BCKGRND + Background Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. + 9 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FWKM + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). + 10 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BGOFF + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode(default). + 1 + + + + + VCOREMD + VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. + 20 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VREGIMD + VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. + 21 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VDDAMD + VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 22 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIOMD + VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 23 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIOHMD + VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 24 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + PORVDDIOMD + VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. + 25 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + PORVDDIOHMD + VDDIOH Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIOH supply in all operating mods. + 26 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + VDDBMD + VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. + 27 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + VRXOUTMD + VRXOUT Bluetooth Receiver Supply Power Monitor Disable . + 28 + 1 + + + VTXOUTMD + VTXOUT Bluetooth Transmitter Supply Power Monitor Disable . + 29 + 1 + + + PDOWNDSLEN + PDOWN DEEPSLEEP Output Enable . + 30 + 1 + + + + + LPWKST0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + + + WAKEST + Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. + 0 + 32 + + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + WAKEEN + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 31 + + + + + LPWKST1 + Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. + 0x0C + + + WAKEST + Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. + 0 + 18 + + + + + LPWKEN1 + Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. + 0x10 + + + WAKEEN + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 31 + + + + + LPPWST + Low Power Peripheral Wakeup Status Register. + 0x30 + + + USBLSWKST + USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. + 0 + 2 + + + USBVBUSWKST + USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. + 2 + 1 + + + SDMAWKST + SDMA Wakeup Status Flag. + 3 + 1 + + + AINCOMP0WKST + Analog Input Comparator 0 Wakeup Status Flag. + 4 + 1 + + + AINCOMP1WKST + Analog Input Comparator 1 Wakeup Status Flag. + 5 + 1 + + + AINCOMP2WKST + Analog Input Comparator 2 Wakeup Status Flag. + 6 + 1 + + + AINCOMP3WKST + Analog Input Comparator 3 Wakeup Status Flag. + 7 + 1 + + + AINCOMP0ST + Analog Input Comparator 0 Output Status Flag. + 8 + 1 + + + AINCOMP1ST + Analog Input Comparator 1 Output Status Flag. + 9 + 1 + + + AINCOMP2ST + Analog Input Comparator 2 Output Status Flag. + 10 + 1 + + + AINCOMP3ST + Analog Input Comparator 3 Output Status Flag. + 11 + 1 + + + BBMODEST + Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. + 16 + 1 + + + RSTWKST + Reset Detect Wakeup Status Flag. + 17 + 1 + + + + + LPPWEN + Low Power Peripheral Wakeup Enable Register. + 0x34 + + + USBLSWKEN + USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set. + 0 + 2 + + + USBVBUSWKEN + USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. + 2 + 1 + + + SDMAWKEN + SDMA Wakeup Enable. + 3 + 1 + + + AINCOMP0WKEN + Analog Input Comparator 0 Wakeup Enable. + 4 + 1 + + + AINCOMP1WKEN + Analog Input Comparator 1 Wakeup Enable. + 5 + 1 + + + AINCOMP2WKEN + Analog Input Comparator 2 Wakeup Enable. + 6 + 1 + + + AINCOMP3WKEN + Analog Input Comparator 3 Wakeup Enable. + 7 + 1 + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + SRAM0SD + System RAM block 0 Shut Down. + 0 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM1SD + System RAM block 1 Shut Down. + 1 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM2SD + System RAM block 2 Shut Down. + 2 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM3SD + System RAM block 3 Shut Down. + 3 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM4SD + System RAM block 4 Shut Down. + 4 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM5SD + System RAM block 5 Shut Down. + 5 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ICACHESD + Instruction Cache RAM Shut Down. + 7 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ICACHEXIPSD + XiP Instruction Cache RAM Shut Down. + 8 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRCCSD + System Cache RAM Shut Down. + 9 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + CRYPTOSD + Crypto MAA RAM Shut Down. + 10 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + USBFIFOSD + USB FIFO Shut Down. + 11 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ROMSD + ROM Shut Down. + 12 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ROM1SD + ROM1 Shut Down. + 13 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + IC1SD + ICache 1 Shut Down. + 14 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + LPVDDPD + Low Power VDD Domain Power Down Control. + 0x44 + + + VREGOBPD + Power down SIMO Vreg B (VCOREB+VDDC) in backup mode. + 0 + 1 + + + up + Enabled in backup mode. + 0 + + + down + Disabled in backup mode. + 1 + + + + + VREGODPD + Power down SIMO Vreg D (BTLE). + 1 + 1 + + + up + Enabled + 0 + + + down + Disabled + 1 + + + + + VDD2PD + Power down VDD2 (CPU0+peripherals). + 8 + 1 + + + up + Enabled + 0 + + + down + Disabled + 1 + + + + + VDD3PD + Power down VDD3 (CPU1+audio). + 9 + 1 + + + up + Enabled + 0 + + + down + Disabled + 1 + + + + + VDD4PD + Power down VDD4 (SDMA+peripherals). + 10 + 1 + + + up + Enabled + 0 + + + down + Disabled + 1 + + + + + VDD5PD + Power down VDD5 (BTLE digital). + 11 + 1 + + + up + Enabled + 0 + + + down + Disabled + 1 + + + + + + + BURETVEC + BACKUP Return Vector Register + 0x48 + + + GPR0 + General Purpose Register 0. + 0 + 32 + + + + + BUAOD + BACKUP AoD Register + 0x4C + + + GPR1 + General Purpose Register 1. + 0 + 32 + + + + + + + + RPU + Resource Protection Unit + 0x40002000 + + 0x00 + 0x1000 + registers + + + + GCR + GCR RPU Register. + 0x0000 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SIR + SIR RPU Register. + 0x0004 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + FCR + FCR RPU Register. + 0x0008 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TPU + TPU RPU Register. + 0x0010 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + RPU + RPU Register. + 0x0020 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + WDT0 + WDT0 RPU Register. + 0x0030 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + WDT1 + WDT1 RPU Register. + 0x0034 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + WDT2 + WDT2 RPU Register. + 0x0038 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SMON + SMON RPU Register. + 0x0040 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SIMO + SIMO RPU Register. + 0x0044 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + DVS + DVS RPU Register. + 0x0048 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + AES + AES RPU Register. + 0x0050 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + RTC + RTC RPU Register. + 0x0060 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + WUT + WUT RPU Register. + 0x0064 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + PWRSEQ + PWRSEQ RPU Register. + 0x0068 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + MCR + MCR RPU Register. + 0x006C + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + GPIO0 + GPIO0 RPU Register. + 0x0080 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + GPIO1 + GPIO1 RPU Register. + 0x0090 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TMR0 + TMR0 RPU Register. + 0x0100 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TMR1 + TMR1 RPU Register. + 0x0110 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TMR2 + TMR2 RPU Register. + 0x0120 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TMR3 + TMR3 RPU Register. + 0x0130 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TMR4 + TMR4 RPU Register. + 0x0140 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TMR5 + TMR5 RPU Register. + 0x0150 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + HTIMER0 + HTIMER0 RPU Register. + 0x01B0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + HTIMER1 + HTIMER1 RPU Register. + 0x01C0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + I2C0_BUS0 + I2C0_BUS0 RPU Register. + 0x01D0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + I2C1_BUS0 + I2C1_BUS0 RPU Register. + 0x01E0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + I2C2_BUS0 + I2C2_BUS0 RPU Register. + 0x01F0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPIXFM + SPIXFM RPU Register. + 0x0260 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPIXFC + SPIXFC RPU Register. + 0x0270 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + DMA0 + DMA0 RPU Register. + 0x0280 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + FLC0 + FLC0 RPU Register. + 0x0290 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + FLC1 + FLC1 RPU Register. + 0x0294 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + ICC0 + ICC0 RPU Register. + 0x02A0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + ICC1 + ICC1 RPU Register. + 0x02A4 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SFCC + SFCC RPU Register. + 0x02F0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SRCC + SRCC RPU Register. + 0x0330 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + ADC + ADC RPU Register. + 0x0340 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + DMA1 + DMA1 RPU Register. + 0x0350 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SDMA + SDMA RPU Register. + 0x0360 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SDHCCTRL + SD Host Controller (APB). + 0x0370 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPIXR + SPIXR RPU Register. + 0x03A0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + PTG_BUS0 + PTG_BUS0 RPU Register. + 0x03C0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + OWM + OWM RPU Register. + 0x03D0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SEMA + SEMA RPU Register. + 0x03E0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + UART0 + UART0 RPU Register. + 0x0420 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + UART1 + UART1 RPU Register. + 0x0430 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + UART2 + UART2 RPU Register. + 0x0440 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPI1 + SPI1 RPU Register. + 0x0460 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPI2 + SPI2 RPU Register. + 0x0470 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + AUDIO + AUDIO RPU Register. + 0x04C0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + TRNG + TRNG RPU Register. + 0x04D0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + BTLE + BTLE RPU Register. + 0x0500 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + I2C0_BUS1 + I2C0_BUS1 RPU Register. + 0x11D0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + I2C1_BUS1 + I2C1_BUS1 RPU Register. + 0x11E0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + I2C2_BUS1 + I2C2_BU1 RPU Register. + 0x11F0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + PTG_BUS1 + PTG_BUS1 RPU Register. + 0x13C0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + USBHS + USBHS RPU Register. + 0x0B10 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SDIO + SDIO/SDHC Target RPU Register. + 0x0B60 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPIXFM_FIFO + SPIXFM_FIFO RPU Register. + 0x0BC0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SPI0 + SPI0 RPU Register. + 0x0BE0 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM0 + SYSRAM0 RPU Register. + 0x0F00 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM1 + SYSRAM1 RPU Register. + 0x0F10 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM2 + SYSRAM2 RPU Register. + 0x0F20 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM3 + SYSRAM3 RPU Register. + 0x0F30 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM4 + SYSRAM4 RPU Register. + 0x0F40 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM5 + SYSRAM5 RPU Register. + 0x0F50 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + SYSRAM6_11 + SYSRAM6-11 RPU Register. + 0x0F60 + + + ACCESS + APB Slave Peripheral Access Disable. + 0 + 32 + + + + + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + RTC Seconds Counter. + 0 + 32 + + + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + SSEC + RTC Sub-second Counter. + 0 + 12 + + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + + + TOD_ALARM + Time-of-day Alarm. + 0 + 20 + + + + + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + SSEC_ALARM + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + RTCE + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ADE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ASE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDYE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ALDF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + ALSF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SQE + Square Wave Output Enable. + 8 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + FT + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + clkDiv8 + RTC Input Clock / 8. + 3 + + + + + ACRE + Asynchronous Counter Read Enable. + 14 + 1 + + + sync + SEC and SSEC registers synchronized and should only be accessed while CTRL.rdy = 1. + 0 + + + async + SEC and SSEC registers are asynchronous and will require software interaction to ensure data accuracy. + 1 + + + + + WE + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VRTC_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FILTER_EN + Enables analog deglitch filter. + 0 + 1 + + + IBIAS_SEL + If IBIAS_EN is 1, selects 4x,2x mode. + 1 + 1 + + + HYST_EN + Enables high current hysteresis buffer. + 2 + 1 + + + IBIAS_EN + Enables higher 4x,2x current modes. + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + 32KOUT + RTC 32kHz Square Wave Output + 5 + 1 + + + + + + + + SDHC + SDHC/SDIO Controller + 0x400B6000 + + 0 + 0x1000 + registers + + + SDHC + 66 + + + + SDMA + SDMA System Address / Argument 2. + 0x00 + 32 + + + ADDR + SDMA System Address / Argument 2 of Auto CMD23. + 0 + 32 + + + + + BLK_SIZE + Block Size. + 0x04 + 16 + + + TRANS + Transfer Block Size. + 0 + 12 + + + HOST_BUFF + Host SDMA Buffer Boundary. + 12 + 3 + + + + + BLK_CNT + Block Count. + 0x06 + 16 + + + COUNT + Blocks Count For Current Transfer. + 0 + 16 + + + + + ARG_1 + Argument 1. + 0x08 + 32 + + + CMD + Command Argument 1. + 0 + 32 + + + + + TRANS + Transfer Mode. + 0x0C + 16 + + + DMA_EN + DMA Enable. + 0 + 1 + + enable + + dma_transfer + 1 + + + non_dma_transfer + 0 + + + + + BLK_CNT_EN + Block Count Enable. + 1 + 1 + + count + + enable + 1 + + + disable + 0 + + + + + AUTO_CMD_EN + Auto CMD Enable. + 2 + 2 + + CMD + + disable + 0 + + + cmd12 + 1 + + + cmd23 + 2 + + + + + READ_WRITE + Data Transfer Direction Select. + 4 + 1 + + read + + read + 1 + + + write + 0 + + + + + MULTI + Multi / Single Block Select. + 5 + 1 + + multi + + enable + 1 + + + disable + 0 + + + + + + + CMD + Command. + 0x0E + 16 + + + RESP_TYPE + Response Type Select. + 0 + 2 + + + CRC_CHK_EN + Command CRC Check Enable. + 3 + 1 + + + IDX_CHK_EN + Command Index Check Enable. + 4 + 1 + + + DATA_PRES_SEL + Data Present Select. + 5 + 1 + + + TYPE + Command Type. + 6 + 2 + + + IDX + Command Index. + 8 + 6 + + + + + 4 + 4 + RESP[%s] + Response 0 Register 0-15. + 0x010 + 32 + + + CMD_RESP + Command Response. + 0 + 32 + + + + + BUFFER + Buffer Data Port. + 0x20 + 32 + + + DATA + Buffer Data. + 0 + 32 + + + + + PRESENT + Present State. + 0x024 + 32 + read-only + + + CMD + Command Inhibit (CMD). + 0 + 1 + read-only + + + DAT + Command Inhibit (DAT). + 1 + 1 + read-only + + + DAT_LINE_ACTIVE + DAT Line Active. + 2 + 1 + read-only + + + RETUNING + Re-Tuning Request. + 3 + 1 + read-only + + + WRITE_TRANSFER + Write Transfer Active. + 8 + 1 + read-only + + + READ_TRANSFER + Read Transfer Active. + 9 + 1 + read-only + + + BUFFER_WRITE + Buffer Write Enable. + 10 + 1 + read-only + + + BUFFER_READ + Buffer Read Enable. + 11 + 1 + read-only + + + CARD_INSERTED + Card Inserted. + 16 + 1 + read-only + + + CARD_STATE + Card State Stable. + 17 + 1 + read-only + + + CARD_DETECT + Card Detect Pin Level. + 18 + 1 + read-only + + + WP + Write Protect Switch Pin Level. + 19 + 1 + read-only + + + DAT_SIGNAL_LEVEL + DAT[3:0] Line Signal Level. + 20 + 4 + + + CMD_SIGNAL_LEVEL + CMD Line Signal Level. + 24 + 1 + + + + + HOST_CN_1 + Host Control 1. + 0x028 + 8 + + + LED_CN + LED Control. + 0 + 1 + + + DATA_TRANSFER_WIDTH + Data Transfer Width. + 1 + 1 + + + HS_EN + High Speed Enable. + 2 + 1 + + + DMA_SELECT + DMA Select. + 3 + 2 + + + EXT_DATA_TRANSFER_WIDTH + Extended Data Transfer Width. + 5 + 1 + + + CARD_DETECT_TEST + Card Detect Test Level. + 6 + 1 + + + CARD_DETECT_SIGNAL + Card Detect Signal Selection. + 7 + 1 + + + + + PWR + Power Control. + 0x029 + 8 + + + BUS_POWER + SD Bus Power. + 0 + 1 + + + BUS_VOLT_SEL + SD Bus Voltage Select. + 1 + 3 + + + + + BLK_GAP + Block Gap Control. + 0x02A + 8 + + + STOP + Stop At Block Gap Request. + 0 + 1 + + + CONT + Continue Request. + 1 + 1 + + + READ_WAIT + Read Wait Control. + 2 + 1 + + + INTR + Interrupt At Block Gap. + 3 + 1 + + + + + WAKEUP + Wakeup Control. + 0x02B + 8 + + + CARD_INT + Wakeup Event Enable On Card Interrupt. + 0 + 1 + + + CARD_INS + Wakeup Event Enable On SD Card Insertion. + 1 + 1 + + + CARD_REM + Wakeup Event Enable On SD Card Removal. + 2 + 1 + + + + + CLK_CN + Clock Control. + 0x02C + 16 + + + INTERNAL_CLK_EN + Internal Clock Enable. + 0 + 1 + + + INTERNAL_CLK_STABLE + Internal Clock Stable. + 1 + 1 + read-only + + + SD_CLK_EN + SD Clock Enable. + 2 + 1 + + + CLK_GEN_SEL + Clock Generator Select. + 5 + 1 + read-only + + + UPPER_SDCLK_FREQ_SEL + Upper Bits of SDCLK Frequency Select. + 6 + 2 + + + SDCLK_FREQ_SEL + SDCLK Frequency Select. + 8 + 8 + + + + + TO + Timeout Control. + 0x02E + 8 + + + DATA_COUNT_VALUE + Data Timeout Counter Value. + 0 + 3 + + + + + SW_RESET + Software Reset. + 0x02F + 8 + + + RESET_ALL + Software Reset For All. + 0 + 1 + + + RESET_CMD + Software Reset For CMD Line. + 1 + 1 + + + RESET_DAT + Software Reset For DAT Line. + 2 + 1 + + + + + INT_STAT + Normal Interrupt Status. + 0x030 + 16 + + + CMD_COMP + Command Complete. + 0 + 1 + + + TRANS_COMP + Transfer Complete. + 1 + 1 + + + BLK_GAP_EVENT + Block Gap Event. + 2 + 1 + + + DMA + DMA Interrupt. + 3 + 1 + + + BUFF_WR_READY + Buffer Write Ready. + 4 + 1 + + + BUFF_RD_READY + Buffer Read Ready. + 5 + 1 + + + CARD_INSERTION + Card Insertion. + 6 + 1 + + + CARD_REMOVAL + Card Removal. + 7 + 1 + + + CARD_INTR + Card Interrupt. + 8 + 1 + + + RETUNING + Re-Tuning Event. + 12 + 1 + + + ERR_INTR + Error Interrupt. + 15 + 1 + + + + + ER_INT_STAT + Error Interrupt Status. + 0x032 + 16 + + + CMD_TO + Command Timeout Error. + 0 + 1 + + + CMD_CRC + Command CRC Error. + 1 + 1 + + + CMD_END_BIT + Command End Bit Error. + 2 + 1 + + + CMD_IDX + Command Index Error. + 3 + 1 + + + DATA_TO + Data Timeout Error. + 4 + 1 + + + DATA_CRC + Data CRC Error. + 5 + 1 + + + DATA_END_BIT + Data End Bit Error. + 6 + 1 + + + CURRENT_LIMIT + Current Limit Error. + 7 + 1 + + + AUTO_CMD_12 + Auto CMD Error. + 8 + 1 + + + ADMA + ADMA Error. + 9 + 1 + + + DMA + DMA Error. + 12 + 1 + + + + + INT_EN + Normal Interrupt Status Enable. + 0x034 + 16 + + + CMD_COMP + Command Complete Status Enable. + 0 + 1 + + + TRANS_COMP + Transfer Complete Status Enable. + 1 + 1 + + + BLK_GAP + Block Gap Event Status Enable. + 2 + 1 + + + DMA + DMA Interrupt Status Enable. + 3 + 1 + + + BUFFER_WR + Buffer Write Ready Status Enable. + 4 + 1 + + + BUFFER_RD + Buffer Read Ready Status Enable. + 5 + 1 + + + CARD_INSERT + Card Insertion Status Enable. + 6 + 1 + + + CARD_REMOVAL + Card Removal Status Enable. + 7 + 1 + + + CARD_INT + Card Interrupt Status Enable. + 8 + 1 + + + RETUNING + Re-Tuning Event Status Enable. + 12 + 1 + + + + + ER_INT_EN + Error Interrupt Status Enable. + 0x36 + 16 + + + CMD_TO + Command Timeout Error Status Enable. + 0 + 1 + + + CMD_CRC + Command CRC Error Status Enable. + 1 + 1 + + + CMD_END_BIT + Command End Bit Error Status Enable. + 2 + 1 + + + CMD_IDX + Command Index Error Status Enable. + 3 + 1 + + + DATA_TO + Data Timeout Error Status Enable. + 4 + 1 + + + DATA_CRC + Data CRC Error Status Enable. + 5 + 1 + + + DATA_END_BIT + Data End Bit Error Status Enable. + 6 + 1 + + + AUTO_CMD + Auto CMD Error Status Enable. + 8 + 1 + + + ADMA + ADMA Error Status Enable. + 9 + 1 + + + TUNING + Tuning Error Status Enable. + 10 + 1 + + + VENDOR + Vendor Specific Error Status Enable. + 12 + 1 + + + + + INT_SIGNAL + Normal Interrupt Signal Enable. + 0x038 + 16 + + + CMD_COMP + Command Complete Signal Enable. + 0 + 1 + + + TRANS_COMP + Transfer Complete Signal Enable. + 1 + 1 + + + BLK_GAP + Block Gap Event Signal Enable. + 2 + 1 + + + DMA + DMA Interrupt Signal Enable. + 3 + 1 + + + BUFFER_WR + Buffer Write Ready Signal Enable. + 4 + 1 + + + BUFFER_RD + Buffer Read Ready Signal Enable. + 5 + 1 + + + CARD_INSERT + Card Insertion Signal Enable. + 6 + 1 + + + CARD_REMOVAL + Card Removal Signal Enable. + 7 + 1 + + + CARD_INT + Card Interrupt Signal Enable. + 8 + 1 + + + RETUNING + Re-Tuning Event Signal Enable. + 12 + 1 + + + + + ER_INT_SIGNAL + Error Interrupt Signal Enable. + 0x03A + 16 + + + CMD_TO + Command Timeout Error Signal Enable. + 0 + 1 + + + CMD_CRC + Command CRC Error Signal Enable. + 1 + 1 + + + CMD_END_BIT + Command End Bit Error Signal Enable. + 2 + 1 + + + CMD_IDX + Command Index Error Signal Enable. + 3 + 1 + + + DATA_TO + Data Timeout Error Signal Enable. + 4 + 1 + + + DATA_CRC + Data CRC Error Signal Enable. + 5 + 1 + + + DATA_END_BIT + Data End Bit Error Signal Enable. + 6 + 1 + + + CURR_LIM + Current Limit Error Signal Enable. + 7 + 1 + + + AUTO_CMD + Auto CMD Error Signal Enable. + 8 + 1 + + + ADMA + ADMA Error Signal Enable. + 9 + 1 + + + TUNING + Tuning Error Signal Enable. + 10 + 1 + + + TAR_RESP + Target Response Error Signal Enable. + 12 + 1 + + + + + AUTO_CMD_ER + Auto CMD Error Status. + 0x03C + 16 + + + NOT_EXCUTED + Auto CMD12 Not Executed. + 0 + 1 + + + TO + Auto CMD Timeout Error. + 1 + 1 + + + CRC + Auto CMD CRC Error. + 2 + 1 + + + END_BIT + Auto CMD End Bit Error. + 3 + 1 + + + INDEX + Auto CMD Index Error. + 4 + 1 + + + NOT_ISSUED + Command Not Issued By Auto CMD12 Error. + 7 + 1 + + + + + HOST_CN_2 + Host Control 2. + 0x03E + 16 + + + UHS + UHS Mode Select. + 0 + 2 + + + SIGNAL_V1_8 + 1.8V Signaling Enable. + 3 + 1 + + + DRIVER_STRENGTH + Driver Strength Select. + 4 + 2 + + + EXCUTE + Execute Tuning. + 6 + 1 + + + SAMPLING_CLK + Sampling Clock Select. + 7 + 1 + + + ASYNCH_INT + Asynchronous Interrupt Enable. + 14 + 1 + + + PRESET_VAL_EN + Preset Value Enable. + 15 + 1 + + + + + CFG_0 + Capabilities 0-31. + 0x040 + 32 + read-only + + + CLK_FREQ + Timeout Clock Frequency. + 0 + 6 + read-only + + + TO_CLK_UNIT + Timeout Clock Unit. + 7 + 1 + read-only + + + TO_CLK_FREQ + Base Clock Frequency For SD Clock. + 8 + 8 + read-only + + + MAX_BLK_LEN + Max Block Length. + 16 + 2 + read-only + + + BIT_8 + 8-bit Support for Embedded Device. + 18 + 1 + read-only + + + ADMA2 + ADMA2 Support. + 19 + 1 + read-only + + + HS + High Speed Support. + 21 + 1 + read-only + + + SDMA + SDMA Support. + 22 + 1 + read-only + + + SUSPEND + Suspend/Resume Support. + 23 + 1 + read-only + + + V3_3 + Voltage Support 3.3V. + 24 + 1 + read-only + + + V3_0 + Voltage Support 3.0V. + 25 + 1 + read-only + + + V1_8 + Voltage Support 1.8V. + 26 + 1 + read-only + + + BIT_64_SYS_BUS + 64-bit System Bus Support. + 28 + 1 + read-only + + + ASYNC_INT + Asynchronous Interrupt Support. + 29 + 1 + read-only + + + SLOT_TYPE + Slot Type. + 30 + 2 + read-only + + + + + CFG_1 + Capabilities 32-63. + 0x044 + 32 + read-only + + + SDR50 + SDR50 Support. + 0 + 1 + read-only + + + SDR104 + SDR104 Support. + 1 + 0 + read-only + + + DDR50 + DDR50 Support. + 2 + 1 + read-only + + + DRIVER_A + Driver Type A Support. + 4 + 1 + read-only + + + DRIVER_C + Driver Type C Support. + 5 + 1 + read-only + + + DRIVER_D + Driver Type D Support. + 6 + 1 + read-only + + + TIMER_CNT_TUNING + Timer Count for Re-Tuning. + 8 + 4 + read-only + + + TUNING_SDR50 + Use Tuning for SDR50. + 13 + 1 + read-only + + + RETUNING + Re-Tuning Modes. + 14 + 2 + read-only + + + CLK_MULTI + Clock Multiplier. + 16 + 8 + read-only + + + + + MAX_CURR_CFG + Maximum Current Capabilities. + 0x048 + 32 + read-only + + + V3_3 + Maximum Current for 3.3V. + 0 + 8 + read-only + + + V3_0 + Maximum Current for 3.0V. + 8 + 8 + read-only + + + V1_8 + Maximum Current for 1.8V. + 16 + 8 + read-only + + + + + FORCE_CMD + Force Event for Auto CMD Error Status. + 0x050 + 16 + write-only + + + NOT_EXCU + Force Event for Auto CMD12 Not Executed. + 0 + 1 + write-only + + + TO + Force Event for Auto CMD Timeout Error. + 1 + 1 + write-only + + + CRC + Force Event for Auto CMD CRC Error. + 2 + 1 + write-only + + + END_BIT + Force Event for Auto CMD End Bit Error. + 3 + 1 + write-only + + + INDEX + Force Event for Auto CMD Index Error. + 4 + 1 + write-only + + + NOT_ISSUED + Force Event for Command Not Issued By Auto CMD12 Error. + 7 + 1 + write-only + + + + + FORCE_EVENT_INT_STAT + Force Event for Error Interrupt Status. + 0x052 + 16 + + + CMD_TO + Force Event for Command Timeout Error. + 0 + 1 + read-only + + + CMD_CRC + Force Event for Command CRC Error. + 1 + 1 + read-only + + + CMD_END_BIT + Force Event for Command End Bit Error. + 2 + 1 + read-only + + + CMD_INDEX + Force Event for Command Index Error. + 3 + 1 + read-only + + + DATA_TO + Force Event for Data Timeout Error. + 4 + 1 + read-only + + + DATA_CRC + Force Event for Data CRC Error. + 5 + 1 + read-only + + + DATA_END_BIT + Force Event for Data End Bit Error. + 6 + 1 + read-only + + + CURR_LIMIT + Force Event for Current Limit Error. + 7 + 1 + read-only + + + AUTO_CMD + Force Event for Auto CMD Error. + 8 + 1 + read-only + + + ADMA + Force Event for ADMA Error. + 9 + 1 + + + VENDOR + Force Event for Vendor Specific Error Status. + 12 + 3 + write-only + + + + + ADMA_ER + ADMA Error Status. + 0x054 + 8 + + + STATE + ADMA Error State. + 0 + 2 + + + LEN_MISMATCH + ADMA Length Mismatch Error. + 2 + 1 + + + + + ADMA_ADDR_0 + ADMA System Address 0-31. + 0x058 + 32 + + + ADDR + ADMA System Address Part 1 (part 2 is ADMA_ADDR_1). + 0 + 32 + + + + + ADMA_ADDR_1 + ADMA System Address 32-63. + 0x05C + 32 + + + ADDR + ADMA System Address Part 1 (part 2 is ADMA_ADDR_1). + 0 + 32 + + + + + PRESET_0 + Preset Value for Initialization. + 0x060 + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_1 + Preset Value for Default Speed. + 0x062 + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_2 + Preset Value for High Speed. + 0x064 + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_3 + Preset Value for SDR12. + 0x066 + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_4 + Preset Value for SDR25. + 0x068 + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_5 + Preset Value for SDR50. + 0x06A + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_6 + Preset Value for SDR104. + 0x06C + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + PRESET_7 + Preset Value for DDR50. + 0x06E + 16 + read-only + + + SDCLK_FREQ + SDCLK Frequency Select Value. + 0 + 10 + read-only + + + CLK_GEN + Clock Generator Select Value. + 10 + 1 + read-only + + + DRIVER_STRENGTH + Driver Strength Select Value. + 14 + 2 + read-only + + + + + SLOT_INT + Slot Interrupt Status. + 0x0FC + 16 + read-only + + + INT_SIGNALS + Interrupt Signal For Each Slot. + 0 + 1 + read-only + + + + + HOST_CN_VER + Host Controller Version. + 0x0FE + 16 + + + SPEC_VER + Specification Version Number. + 0 + 8 + + + VEND_VER + Vendor Version Number. + 8 + 8 + + + + + + + + SEMA + The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. + The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software + architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be + + modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. + 0x4003E000 + + 0x00 + 0x1000 + registers + + + + 8 + 0x04 + SEMAPHORES[%s] + Read to test and set, returns prior value. Write 0 to clear semaphore. + 0x000 + 32 + + + sema + 0 + 1 + + + + + status + Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. + 0x100 + 32 + + + STATUS + 0 + 8 + + + + + + + + SIMO + Single Inductor Multiple Output Switching Converter + 0x40004400 + + 0x00 + 0x400 + registers + + + + VREGO_A + Buck Voltage Regulator A Control Register + 0x0004 + read-write + + + VSETA + Regulator Output Voltage Setting + 0 + 7 + + + RANGEA + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + VREGO_B + Buck Voltage Regulator B Control Register + 0x0008 + read-write + + + VSETB + Regulator Output Voltage Setting + 0 + 7 + + + RANGEB + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + VREGO_C + Buck Voltage Regulator C Control Register + 0x000C + read-write + + + VSETC + Regulator Output Voltage Setting + 0 + 7 + + + RANGEC + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + VREGO_D + Buck Voltage Regulator D Control Register + 0x0010 + read-write + + + VSETD + Regulator Output Voltage Setting + 0 + 7 + + + RANGED + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + IPKA + High Side FET Peak Current VREGO_A/VREGO_B Register + 0x0014 + read-write + + + IPKSETA + Voltage Regulator Peak Current Setting + 0 + 4 + + + IPKSETB + Voltage Regulator Peak Current Setting + 4 + 4 + + + + + IPKB + High Side FET Peak Current VREGO_C/VREGO_D Register + 0x0018 + read-write + + + IPKSETC + Voltage Regulator Peak Current Setting + 0 + 4 + + + IPKSETD + Voltage Regulator Peak Current Setting + 4 + 4 + + + + + MAXTON + Maximum High Side FET Time On Register + 0x001C + read-write + + + TONSET + Sets the maximum on time for the high side FET, each increment represents 500ns + 0 + 4 + + + + + ILOAD_A + Buck Cycle Count VREGO_A Register + 0x0020 + read-only + + + ILOADA + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + ILOAD_B + Buck Cycle Count VREGO_B Register + 0x0024 + read-only + + + ILOADB + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + ILOAD_C + Buck Cycle Count VREGO_C Register + 0x0028 + read-only + + + ILOADC + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + ILOAD_D + Buck Cycle Count VREGO_D Register + 0x002C + read-only + + + ILOADD + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + BUCK_ALERT_THR_A + Buck Cycle Count Alert VERGO_A Register + 0x0030 + read-write + + + BUCKTHRA + Threshold for ILOADA to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_ALERT_THR_B + Buck Cycle Count Alert VERGO_B Register + 0x0034 + read-write + + + BUCKTHRB + Threshold for ILOADB to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_ALERT_THR_C + Buck Cycle Count Alert VERGO_C Register + 0x0038 + read-write + + + BUCKTHRC + Threshold for ILOADC to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_ALERT_THR_D + Buck Cycle Count Alert VERGO_D Register + 0x003C + read-write + + + BUCKTHRD + Threshold for ILOADD to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_OUT_READY + Buck Regulator Output Ready Register + 0x0040 + read-only + + + BUCKOUTRDYA + When set, indicates that the output voltage has reached its regulated value + 0 + 1 + + + notrdy + Output voltage not in range + 0 + + + rdy + Output voltage in range + 1 + + + + + BUCKOUTRDYB + When set, indicates that the output voltage has reached its regulated value + 1 + 1 + + + BUCKOUTRDYC + When set, indicates that the output voltage has reached its regulated value + 2 + 1 + + + BUCKOUTRDYD + When set, indicates that the output voltage has reached its regulated value + 3 + 1 + + + + + ZERO_CROSS_CAL_A + Zero Cross Calibration VERGO_A Register + 0x0044 + read-only + + + ZXCALA + Zero Cross Calibrartion Value VREGO_A + 0 + 4 + + + + + ZERO_CROSS_CAL_B + Zero Cross Calibration VERGO_B Register + 0x0048 + read-only + + + ZXCALB + Zero Cross Calibrartion Value VREGO_B + 0 + 4 + + + + + ZERO_CROSS_CAL_C + Zero Cross Calibration VERGO_C Register + 0x004C + read-only + + + ZXCALC + Zero Cross Calibrartion Value VREGO_C + 0 + 4 + + + + + ZERO_CROSS_CAL_D + Zero Cross Calibration VERGO_D Register + 0x0050 + read-only + + + ZXCALD + Zero Cross Calibrartion Value VREGO_D + 0 + 4 + + + + + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x00 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ERRADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ERRADDR + 0 + 32 + + + + + FSTAT + funcstat register. + 0x100 + read-only + + + FPU + FPU Function. + 0 + 1 + + + no + 0 + + + yes + 1 + + + + + USB + USB Device. + 1 + 1 + + + no + 0 + + + yes + 1 + + + + + ADC + 10-bit Sigma Delta ADC. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + XIP + XiP function. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + PBM + PBM function. + 4 + 1 + + + no + 0 + + + yes + 1 + + + + + HBC + HBC function. + 5 + 1 + + + no + 0 + + + yes + 1 + + + + + SDHC + SDHC function. + 6 + 1 + + + no + 0 + + + yes + 1 + + + + + SMPHR + SMPHR function. + 7 + 1 + + + no + 0 + + + yes + 1 + + + + + SCACHE + System Cache function. + 8 + 1 + + + no + 0 + + + yes + 1 + + + + + + + SFSTAT + secfuncstat register. + 0x104 + read-only + + + TRNG + TRNG function. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + AES + AES function. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + SHA + SHA function. + 4 + 1 + + + no + 0 + + + yes + 1 + + + + + MAA + MAA function. + 5 + 1 + + + no + 0 + + + yes + 1 + + + + + + + + + + SMON + The Security Monitor block used to monitor system threat conditions. + 0x40004000 + + 0x00 + 0x400 + registers + + + + EXTSCN + External Sensor Control Register. + 0x00 + 0x3800FFC0 + + + EXTS_EN0 + External Sensor Enable for input/output pair 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN1 + External Sensor Enable for input/output pair 1. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN2 + External Sensor Enable for input/output pair 2. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN3 + External Sensor Enable for input/output pair 3. + 3 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN4 + External Sensor Enable for input/output pair 4. + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN5 + External Sensor Enable for input/output pair 5. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTCNT + External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. + 16 + 5 + + + EXTFRQ + External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair. + 21 + 3 + + + freq2000Hz + Div 4 (2000Hz). + 0 + + + freq1000Hz + Div 8 (1000Hz). + 1 + + + freq500Hz + Div 16 (500Hz). + 2 + + + freq250Hz + Div 32 (250Hz). + 3 + + + freq125Hz + Div 64 (125Hz). + 4 + + + freq63Hz + Div 128 (63Hz). + 5 + + + freq31Hz + Div 256 (31Hz). + 6 + + + RFU + Reserved. Do not use. + 7 + + + + + DIVCLK + Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: + If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor. + 24 + 3 + + + div1 + Divide by 1 (8000 Hz). + 0 + + + div2 + Divide by 2 (4000 Hz). + 1 + + + div4 + Divide by 4 (2000 Hz). + 2 + + + div8 + Divide by 8 (1000 Hz). + 3 + + + div16 + Divide by 16 (500 Hz). + 4 + + + div32 + Divide by 32 (250 Hz). + 5 + + + div64 + Divide by 64 (125 Hz). + 6 + + + + + BUSY + Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain. + 30 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Update in Progress. + 1 + + + + + LOCK + Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. + 31 + 1 + + + unlocked + Unlocked. + 0 + + + locked + Locked. + 1 + + + + + + + INTSCN + Internal Sensor Control Register. + 0x04 + 0x7F00FFF7 + + + SHIELD_EN + Die Shield Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TEMP_EN + Temperature Sensor Enable. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VBAT_EN + Battery Monitor Enable. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DFD_EN + Digital Fault Dector Enable + 3 + 1 + + + DFD_NMI + Digital Fault NMI Enable + 4 + 1 + + + DFD_STDBY + Digital Fault Dector Stand by Enable + 8 + 1 + + + PUF_TRIM_ERASE + Erase puf trim Enable + 10 + 1 + + + LOTEMP_SEL + Low Temperature Detection Select. + 16 + 1 + + + neg50C + -50 degrees C. + 0 + + + neg30C + -30 degrees C. + 1 + + + + + VCORELOEN + VCORE Undervoltage Detect Enable. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VCOREHIEN + VCORE Overvoltage Detect Enable. + 19 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VDDLOEN + VDD Undervoltage Detect Enable. + 20 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VDDHIEN + VDD Overvoltage Detect Enable. + 21 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VGLEN + Voltage Glitch Detection Enable. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LOCK + Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. + 31 + 1 + + + unlocked + Unlocked. + 0 + + + locked + Locked. + 1 + + + + + + + SECALM + Security Alarm Register. + 0x08 + 0x00000000 + 0x00000000 + + + DRS + Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + KEYWIPE + Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped. + 1 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SHIELDF + Die Shield Flag. + 2 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + LOTEMP + Low Temperature Detect. + 3 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + HITEMP + High Temperature Detect. + 4 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATLO + Battery Undervoltage Detect. + 5 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATHI + Battery Overvoltage Detect. + 6 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTF + External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. + 7 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VDDLO + VDD Undervoltage Detect Flag. + 8 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VCORELO + VCORE Undervoltage Detect Flag. + 9 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VCOREHI + VCORE Overvoltage Detect Flag. + 10 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VDDHI + VDD Overvoltage Flag. + 11 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VGL + Voltage Glitch Detection Flag. + 12 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT0 + External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 16 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT1 + External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 17 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT2 + External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 18 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT3 + External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 19 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT4 + External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 20 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT5 + External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 21 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN0 + External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 24 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN1 + External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 25 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN2 + External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 26 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN3 + External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 27 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN4 + External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 28 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN5 + External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 29 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + SECDIAG + Security Diagnostic Register. + 0x0C + read-only + 0x00000001 + 0xFFC0FE02 + + + BORF + Battery-On-Reset Flag. This bit is set once the back up battery is conneted. + 0 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + SHIELDF + Die Shield Flag. + 2 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + LOTEMP + Low Temperature Detect. + 3 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + HITEMP + High Temperature Detect. + 4 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATLO + Battery Undervoltage Detect. + 5 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATHI + Battery Overvoltage Detect. + 6 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + DYNF + Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. + 7 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + AESKT + AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR. + 8 + 1 + + + incomplete + Key has not been transferred. + 0 + + + complete + Key has been transferred. + 1 + + + + + EXTSTAT0 + External Sensor 0 Detect. + 16 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT1 + External Sensor 1 Detect. + 17 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT2 + External Sensor 2 Detect. + 18 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT3 + External Sensor 3 Detect. + 19 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT4 + External Sensor 4 Detect. + 20 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT5 + External Sensor 5 Detect. + 21 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + DLRTC + DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. + 0x10 + read-only + 0x00000000 + + + DLRTC + DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. + 0 + 32 + + + + + MEUCFG + MEU Configuration + 0x24 + 0x00000000 + + + MEUCFG + Configuration plain/encrypted area of the backed NVSRAM. + 0 + 7 + + + + + SECST + Security Monitor Status Register. + 0x34 + read-only + + + EXTSRS + External Sensor Control Register Status. + 0 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + INTSRS + Internal Sensor Control Register Status. + 1 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + SECALRS + Security Alarm Register Status. + 2 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + + + SDBE + Security Monitor Self Destruct Byte. + 0x38 + + + DBYTE + Self Destruct Byte + 0 + 8 + + + SBDEN + Self-Destruct Byte ENable. + 31 + 1 + + + + + + + + SPI + SPI peripheral. + 0x400BE000 + + 0x00 + 0x1000 + registers + + + SPI0 + 56 + + + + DATA32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + QSPIFIFO + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + DATA16[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 16 + read-write + + + QSPIFIFO + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + DATA8[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 8 + read-write + + + QSPIFIFO + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MASTER + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 3 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 0 + 16 bits per character. + 0 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SS_POL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 4 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + + + + + SS_TIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + PRE + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + POST + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + INACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLK_CFG + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + SCALE + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_FIFO_LEVEL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FIFO_CLEAR + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_FIFO_CNT + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_DMA_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FIFO_CLEAR + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_FIFO_CNT + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_DMA_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INT_FL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THRESH + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + M_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OVR + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UND + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OVR + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UND + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INT_EN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THRESH + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EMPTY + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + M_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OVR + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UND + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OVR + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UND + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WAKE_FL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WAKE_EN + Register for wake up enable. + 0x2C + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STAT + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + SPI1 + SPI peripheral. 1 + 0x40046000 + + SPI1 + SPI1 IRQ + 16 + + + + + SPI2 + SPI peripheral. 2 + 0x40047000 + + SPI2 + SPI2 IRQ + 17 + + + + + SPIXFC + SPI XiP Flash Configuration Controller + 0x40027000 + + 0 + 0x1000 + registers + + + SPIXFC + SPIXFC IRQ + 38 + + + + CONFIG + Configuration Register. + 0x00 + + + SSEL + Slaves Select. + 0 + 3 + + + Slave_0 + Slave 0 is selected. + 0 + + + Slave_1 + Slave 1 is selected. + 1 + + + + + MODE + Defines SPI Mode, Only valid values are 0 and 3. + 4 + 2 + + + SPIX_Mode_0 + SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. + 0 + + + SPIX_Mode_3 + SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. + 3 + + + + + PAGE_SIZE + Page Size. + 6 + 2 + + + 4_bytes + 4 bytes. + 0 + + + 8_bytes + 8 bytes. + 1 + + + 16_bytes + 16 bytes. + 2 + + + 32_bytes + 32 bytes. + 3 + + + + + HI_CLK + SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. + 8 + 4 + + + 16_SCLK + 16 system clocks. + 0 + + + + + LO_CLK + SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. + 12 + 4 + + + 16_SCLK + 16 system clocks. + 0 + + + + + SS_ACT + Slaves Select Activate Timing. + 16 + 2 + + + 0_CLKS + 0 sytem clocks. + 0 + + + 2_CLKS + 2 sytem clocks. + 1 + + + 4_CLKS + 4 sytem clocks. + 2 + + + 8_CLKS + 8 sytem clocks. + 3 + + + + + SS_INACT + Slaves Select Inactive Timing. + 18 + 2 + + + 4_CLKS + 4 sytem clocks. + 0 + + + 6_CLKS + 6 sytem clocks. + 1 + + + 8_CLKS + 8 sytem clocks. + 2 + + + 12_CLKS + 12 sytem clocks. + 3 + + + + + IOSMPL + Sample Delay. + 20 + 4 + + + + + SS_POL + SPIX Controller Slave Select Polarity Register. + 0x04 + + + SSPOL_0 + Slave Select Polarity. + 0 + 1 + + + lo + Active Low. + 0 + + + hi + Active High. + 1 + + + + + + + GEN_CTRL + SPIX Controller General Controller Register. + 0x08 + + + ENABLE + SPI Master enable. + 0 + 1 + + + dis + Disable SPI Master, putting a reset state. + 0 + + + en + Enable SPI Master for processing transactions. + 1 + + + + + TX_FIFO_EN + Transaction FIFO Enable. + 1 + 1 + + + dis_txfifo + Disable Transaction FIFO. + 0 + + + en_txfifo + Enable Transaction FIFO. + 1 + + + + + RX_FIFO_EN + Result FIFO Enable. + 2 + 1 + + + DIS_RXFIFO + Disable Result FIFO. + 0 + + + EN_RXFIFO + Enable Result FIFO. + 1 + + + + + BBMODE + Bit-Bang Mode. + 3 + 1 + + + dis + Disable Bit-Bang Mode. + 0 + + + en + Enable Bit-Bang Mode. + 1 + + + + + SSDR + This bits reflects the state of the currently selected slave select. + 4 + 1 + + + output0 + Selected Slave select output = 0. + 0 + + + output1 + Selected Slave select output = 1. + 1 + + + + + SCLK_DR + SSCLK Drive and State. + 6 + 1 + + + SCLK_0 + SCLK is 0. + 0 + + + SCLK_1 + SCLK is 1. + 1 + + + + + SDIO_DATA_IN + SDIO Input Data Value. + 8 + 4 + + + SDIO0 + SDIO[0] + 0 + + + SDIO1 + SDIO[1] + 1 + + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + + + + + BB_DATA + No description available. + 12 + 4 + + + SDIO0 + SDIO[0] + 0 + + + SDIO1 + SDIO[1] + 1 + + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + + + + + BB_DATA_OUT_EN + Bit Bang SDIO Output Enable. + 16 + 4 + + + SDIO0 + SDIO[0] + 0 + + + SDIO1 + SDIO[1] + 1 + + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + + + + + SIMPLE + Simple Mode Enable. + 20 + 1 + + + Dis + 0 + + + En + 1 + + + + + SIMPLERX + Simple Receive Enable. + 21 + 1 + + + Dis + 0 + + + En + 1 + + + + + SMPLSS + Simple Mode Slave Select. + 22 + 1 + + + Dis + 0 + + + En + 1 + + + + + SCLK_FB + Enable SCLK Feedback Mode. + 24 + 1 + + + Dis + 0 + + + En + 1 + + + + + SCKFBINV + SCK Inversion. + 25 + 1 + + + Dis + 0 + + + En + 1 + + + + + + + FIFO_CTRL + SPIX Controller FIFO Control and Status Register. + 0x0C + + + TX_FIFO_AE_LVL + Transaction FIFO Almost Empty Level. + 0 + 4 + + + TX_FIFO_CNT + Transaction FIFO Used. + 8 + 5 + + + RX_FIFO_AF_LVL + Results FIFO Almost Full Level. + 16 + 5 + + + RX_FIFO_CNT + Result FIFO Used. + 24 + 6 + + + + + SPCTRL + SPIX Controller Special Control Register. + 0x10 + + + SAMPL + SDIO Sample Mode Enable. + 0 + 1 + + + Dis + 0 + + + En + 1 + + + + + SDIOOUT + SDIO Output Value Sample Mode. + 4 + 4 + + + SDIO0 + SDIO[0] + 0 + + + SDIO1 + SDIO[1] + 1 + + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + + + + + SDIOOE + SDIO Output Enable Sample Mode. + 8 + 4 + + + SDIO0 + SDIO[0] + 0 + + + SDIO1 + SDIO[1] + 1 + + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + + + + + SCLKINH3 + SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. + 16 + 1 + + + EN + Allow trailing SCLK low pulse prior to Slave Select de-assertion. + 0 + + + DIS + Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. + 1 + + + + + + + INTFL + SPIX Controller Interrupt Status Register. + 0x14 + + + TX_STALLED + Transaction Stalled Interrupt Flag. + 0 + 1 + + + CLR + Normal FIFO Transaction. + 0 + + + SET + Stalled FIFO Transaction. + 1 + + + + + RX_STALLED + Results Stalled Interrupt Flag. + 1 + 1 + + + CLR + Normal FIFO Operation. + 0 + + + SET + Stalled FIFO. + 1 + + + + + TX_READY + Transaction Ready Interrupt Status. + 2 + 1 + + + CLR + FIFO Transaction not ready. + 0 + + + SET + FIFO Transaction ready. + 1 + + + + + RX_DONE + Results Done Interrupt Status. + 3 + 1 + + + CLR + Results FIFO ready. + 0 + + + SET + Results FIFO Not ready. + 1 + + + + + TX_FIFO_AE + Transaction FIFO Almost Empty Flag. + 4 + 1 + + + CLR + Transaction FIFO not Almost Empty. + 0 + + + SET + Transaction FIFO Almost Empty. + 1 + + + + + RX_FIFO_AF + Results FIFO Almost Full Flag. + 5 + 1 + + + CLR + Results FIFO level below the Almost Full level. + 0 + + + SET + Results FIFO level at Almost Full level. + 1 + + + + + + + INTEN + SPIX Controller Interrupt Enable Register. + 0x18 + + + TX_STALLED + Transaction Stalled Interrupt Enable. + 0 + 1 + + + EN + Disable Transaction Stalled Interrupt. + 0 + + + DIS + Enable Transaction Stalled Interrupt. + 1 + + + + + RX_STALLED + Results Stalled Interrupt Enable. + 1 + 1 + + + EN + Disable Results Stalled Interrupt. + 0 + + + DIS + Enable Results Stalled Interrupt. + 1 + + + + + TX_READY + Transaction Ready Interrupt Enable. + 2 + 1 + + + EN + Disable FIFO Transaction Ready Interrupt. + 0 + + + DIS + Enable FIFO Transaction Ready Interrupt. + 1 + + + + + RX_DONE + Results Done Interrupt Enable. + 3 + 1 + + + EN + Disable Results Done Interrupt. + 0 + + + DIS + Enable Results Done Interrupt. + 1 + + + + + TX_FIFO_AE + Transaction FIFO Almost Empty Interrupt Enable. + 4 + 1 + + + EN + Disable Transaction FIFO Almost Empty Interrupt. + 0 + + + DIS + Enable Transaction FIFO Almost Empty Interrupt. + 1 + + + + + RX_FIFO_AF + Results FIFO Almost Full Interrupt Enable. + 5 + 1 + + + EN + Disable Results FIFO Almost Full Interrupt. + 0 + + + DIS + Enable Results FIFO Almost Full Interrupt. + 1 + + + + + + + + + + SPIXFC_FIFO + SPI XiP Master Controller FIFO. + 0x400BC000 + + 0 + 0x1000 + registers + + + + TX_8 + SPI TX FIFO 8-Bit Write + 0x00 + 8 + uint8_t + + + TX_16 + SPI TX FIFO 16-Bit Write + TX_8 + 0x00 + 16 + uint16_t + + + TX_32 + SPI TX FIFO 32-Bit Write + TX_8 + 0x00 + 32 + uint32_t + + + RX_8 + SPI RX FIFO 8-Bit Access + 0x04 + 8 + uint8_t + + + RX_16 + SPI RX FIFO 16-Bit Access + RX_8 + 0x04 + 16 + uint16_t + + + RX_32 + SPI RX FIFO 32-Bit Access + RX_8 + 0x04 + 32 + uint32_t + + + + + + SPIXFM + SPIXF Master + 0x40026000 + + 0x00 + 0x1000 + registers + + + + CFG + SPIX Configuration Register. + 0x00 + + + MODE + Defines SPI Mode, Only valid values are 0 and 3. + 0 + 2 + + + SCLK_HI_SAMPLE_RISING + Description not available. + 0 + + + SCLK_LO_SAMPLE_FAILLING + Description not available. + 3 + + + + + SSPOL + Slave Select Polarity. + 2 + 1 + + + ACTIVE_HIGH + Slave Select is Active High. + 0 + + + ACTIVE_LOW + Slave Select is Active Low. + 1 + + + + + SSEL + Slave Select. Only valid value is zero. + 4 + 3 + + + LO_CLK + Number of system clocks that SCLK will be low when SCLK pulses are generated. + 8 + 4 + + + HI_CLK + Number of system clocks that SCLK will be high when SCLK pulses are generated. + 12 + 4 + + + SSACT + Slave Select Active Timing. + 16 + 2 + + + off + 0 system clocks. + 0 + + + for_2_mod_clk + 2 System clocks. + 1 + + + for_4_mod_clk + 4 System clocks. + 2 + + + for_8_mod_clk + 8 System clocks. + 3 + + + + + SSIACT + Slave Select Inactive Timing. + 18 + 2 + + + for_1_mod_clk + 1 system clocks. + 0 + + + for_3_mod_clk + 3 System clocks. + 1 + + + for_5_mod_clk + 5 System clocks. + 2 + + + for_9_mod_clk + 9 System clocks. + 3 + + + + + + + FETCH_CTRL + SPIX Fetch Control Register. + 0x04 + + + CMDVAL + Command Value sent to target to initiate fetching from SPI flash. + 0 + 8 + + + CMD_WIDTH + Command Width. Number of data I/O used to send commands. + 8 + 2 + + + Single + Single SDIO. + 0 + + + Dual_IO + Dual SDIO. + 1 + + + Quad_IO + Quad SDIO. + 2 + + + Invalid + Invalid. + 3 + + + + + ADDR_WIDTH + Address Width. Number of data I/O used to send address, and mode/dummy clocks. + 10 + 2 + + + Single + Single SDIO. + 0 + + + Dual_IO + Dual SDIO. + 1 + + + Quad_IO + Quad SDIO. + 2 + + + Invalid + Invalid. + 3 + + + + + DATA_WIDTH + Data Width. Number of data I/O used to receive data. + 12 + 2 + + + Single + Single SDIO. + 0 + + + Dual_IO + Dual SDIO. + 1 + + + Quad_IO + Quad SDIO. + 2 + + + Invalid + Invalid. + 3 + + + + + FOUR_BYTE_ADDR + Four Byte Address Mode. Enables 4-byte Flash Address Mode. + 16 + 1 + + + 3 + 3 Byte Address Mode. + 0 + + + 4 + 4 Byte Address Mode. + 1 + + + + + + + MODE_CTRL + SPIX Mode Control Register. + 0x08 + + + MDCLK + Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch. + 0 + 4 + + + NO_CMD_MODE + No Command Mode. + 8 + 1 + + + always + Send read command every time SPI transaction is initiated. + 0 + + + once + Send read command only once. NO read command in subsequent SPI transactions. + 1 + + + + + EXIT_NO_CMD_MODE + Exit no command mode. + 9 + 1 + + + + + MODE_DATA + SPIX Mode Data Register. + 0x0C + + + DATA + Mode Data. Specifies the data to send with the Dummy/Mode clocks. + 0 + 16 + + + OUT_EN + Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA. + 16 + 16 + + + + + SCLK_FB_CTRL + SPIX Feedback Control Register. + 0x10 + + + FB_EN + Enable SCLK feedback mode. + 0 + 1 + + + dis + Disable SCLK feedback mode. + 0 + + + en + Enable SCLK feedback mode. + 1 + + + + + INVERT_EN + Invert SCLK in feedback mode. + 1 + 1 + + + dis + Disable Invert SCLK feedback mode. + 0 + + + en + Enable Invert SCLK feedback mode. + 1 + + + + + + + IO_CTRL + SPIX IO Control Register. + 0x1C + + + SCLK_DS + SCLK drive Strength. This bit controls the drive strength on the SCLK pin. + 0 + 1 + + + Low + Low drive strength. + 0 + + + High + High drive strength. + 1 + + + + + SS_DS + Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin. + 1 + 1 + + + Low + Low drive strength. + 0 + + + High + High drive strength. + 1 + + + + + SDIO_DS + SDIO Drive Strength. This bit controls the drive strength of all SDIO pins. + 2 + 1 + + + Low + Low drive strength. + 0 + + + High + High drive strength. + 1 + + + + + PU_PD_CTRL + IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins. + 3 + 2 + + + tri_state + Tristate. + 0 + + + Pull_Up + Pull-Up. + 1 + + + Pull_down + Pull-Down. + 2 + + + + + + + MEMSECCN + SPIX Memory Security Control Register. + 0x20 + + + DECEN + Decryption Enable. + 0 + 1 + + + dis + Disable decryption of SPIX data. + 0 + + + en + Enable decryption of SPIX data. + 1 + + + + + AUTH_DISABLE + Integrity Enable. + 1 + 1 + + + dis + Integrity checking disabled. + 0 + + + en + Integrity checking enabled. + 1 + + + + + CNTOPTIEN + Enable counters optimization (when authentication is enabled) + 2 + 1 + + + dis + disable + 0 + + + en + enable + 1 + + + + + INTERLDIS + Disable authenticity interleaving (when authentication is enabled) + 3 + 1 + + + dis + disable + 1 + + + en + enable + 0 + + + + + AUTHERR + Authentication Error Flah Bit. + 4 + 1 + + + + + BUS_IDLE + SPIXF Bus Idle Detection. + 0x24 + + + BUSIDLE + Bus Idle Timer Limit. + 0 + 16 + + + + + + + + SPIXR + SPIXR peripheral. + 0x4003A000 + + 0x00 + 0x1000 + registers + + + + DATA32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + DATA16[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + DATA8[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x04 + read-write + + + SPIEN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MMEN + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + TIMER + Timer Enable. + 2 + 1 + + + dis + Timer is disabled. + 0 + + + en + Timer is enabled, only valid if SPIEN=0. + 1 + + + + + FL_EN + Flow Control Mode Enable. + 3 + 1 + + + dis + Flow Control mode is disabled. + 0 + + + en + Flow Control Mode is enabled. + 1 + + + + + SSIO + Slave Select 0, IO direction, to support Multi-Master mode, + Slave Select 0 can be input in Master mode. This bit has no + effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + TX_START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is + self clearing when transactions are done. If + a transaction completes, and the TX FIFO + is empty, the Master halts, if a transaction + completes, and the TX FIFO is not empty, + the Master initiates another transaction. + 1 + + + + + SS_CTRL + Slave Select Control. + 8 + 1 + + + deassert + SPI de-asserts Slave Select at the end of a transaction. + 0 + + + assert + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS + Slave Select, when in Master mode selects which Slave devices are + selected. More than one Slave device can be selected. + 16 + 8 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + SS4 + SS4 is selected. + 0x10 + + + SS5 + SS5 is selected. + 0x20 + + + SS6 + SS6 is selected. + 0x40 + + + SS7 + SS7 is selected. + 0x80 + + + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL3 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CPHA + Clock Phase. + 0 + 1 + + + CPOL + Clock Polarity. + 1 + 1 + + + SCLK_FB_INV + Invert SCLK Feedback in Master Mode. + 4 + 1 + + + NON_INV + SCLK is not inverted to Line Receiver. + 0 + + + INV + SCLK is inverted to Line Receiver. + 1 + + + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 0 + 16 bits per character. + 0 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SSPOL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 8 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 + + + SS4_high + SS4 active high. + 0x10 + + + SS5_high + SS5 active high. + 0x20 + + + SS6_high + SS6 active high. + 0x40 + + + SS7_high + SS7 active high. + 0x80 + + + + + + + CTRL4 + Register for controlling SPI peripheral. + 0x10 + read-write + + + SSACT1 + Slave Select Action delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + SSACT2 + Slave Select Action delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + SSINACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + BRG_CTRL + Register for controlling SPI clock rate. + 0x14 + read-write + + + LOW + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + SCALE + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_FIFO_LEVEL + Transmit FIFO level that will trigger a DMA request, also level for + threshold status. When TX FIFO has fewer than this many bytes, the + associated events and conditions are triggered. + 0 + 6 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FIFO_CLEAR + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_FIFO_CNT + Count of entries in TX FIFO. + 8 + 5 + + + TX_DMA_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO level that will trigger a DMA request, also level for + threshold status. When RX FIFO has more than this many bytes, the + associated events and conditions are triggered. + 16 + 6 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FIFO_CLEAR + Clear RX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFIO, clears any pending RX FIFO status. + 1 + + + + + RX_FIFO_CNT + Count of entries in RX FIFO. + 24 + 6 + + + RX_DMA_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + IRQ + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THRESH + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + M_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OVR + Transmit FIFO Overrun, set when the AMBA side attempts to write data + to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UND + Transmit FIFO Underrun, set when the SPI side attempts to read data + from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OVR + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UND + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + IRQE + Register for enabling interrupts. + 0x24 + read-write + + + TX_THRESH + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EMPTY + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + M_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OVR + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UND + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OVR + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UND + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WAKE + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WAKEE + Register for wake up enable. + 0x2C + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STAT + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, + cleared when last bit of last character is acted upon and Slave Select + de-assertion would occur. In Slave mode, set when Slave Select is + asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + XMEM_CTRL + Register to control external memory. + 0x34 + read-write + + + RD_CMD + Read command. + 0 + 8 + + + WR_CMD + Write command. + 8 + 8 + + + DUMMY_CLK + Dummy clocks. + 16 + 8 + + + XMEM_EN + XMEM enable. + 31 + 1 + + + + + + + + SRCC + External Memory Cache Controller Registers. + 0x40033000 + + 0x00 + 0x1000 + registers + + + + CACHE_ID + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + CCHID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + MEMCFG + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCHSZ + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEMSZ + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CACHE_CTRL + Cache Control and Status Register. + 0x0100 + + + CACHE_EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + WRITE_ALLOC + Write Allocate Enable. This bit only writable while the cache is disabled. + 1 + 1 + + + dis + Write-no-allocate. + 0 + + + en + Write-allocate enabled. + 1 + + + + + CWFST_DIS + Critical word first and streaming disable. This bit only writeable while the cache is disabled. + 2 + 1 + + + dis + Critical word first and streaming disabled. + 1 + + + en + Critical word first and streaming enabled. + 0 + + + + + CACHE_RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0. + 0x0700 + + + IA + Invalidate all cache contents. + 0 + 32 + + + + + + + + TMR0 + 32-bit reloadable timer that can be used for timing and event counting. + Timers + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR0 + TMR0 IRQ + 5 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + PWM + PWM. This register stores the value that is compared to the current timer count. + 0x08 + + + INTR + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IRQ + Clear Interrupt. + 0 + 1 + + + + + CN + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + pwm + PWM Mode. + 3 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + PWMSYNC + Timer PWM Synchronization Mode Enable. + 9 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLHPOL + Timer PWM output 0A polarity bit. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLLPOL + Timer PWM output 0A' polarity bit. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PWMCKBD + Timer PWM output 0A Mode Disable. + 12 + 1 + + + dis + Disable. + 1 + + + en + Enable. + 0 + + + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOLLCMP + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOLHCMP + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + + + + TMR1 + 32-bit reloadable timer that can be used for timing and event counting. 1 + 0x40011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + 32-bit reloadable timer that can be used for timing and event counting. 2 + 0x40012000 + + TMR2 + TMR2 IRQ + 7 + + + + + TMR3 + 32-bit reloadable timer that can be used for timing and event counting. 3 + 0x40013000 + + TMR3 + TMR3 IRQ + 8 + + + + + TMR4 + 32-bit reloadable timer that can be used for timing and event counting. 4 + 0x40014000 + + TMR4 + TMR4 IRQ + 9 + + + + + TMR5 + 32-bit reloadable timer that can be used for timing and event counting. 5 + 0x40015000 + + TMR5 + TMR5 IRQ + 10 + + + + + TPU + The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms. + 0x40001000 + + 0x00 + 0x1000 + registers + + + Crypto_Engine + Crypto Engine interrupt. + 27 + + + + CTRL + Crypto Control Register. + 0x00 + 0xC0000000 + + + RST + Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. + 0 + 1 + + reset_write + write + + reset + Starts reset operation. + 1 + + + + reset_read + read + + reset_done + Reset complete. + 0 + + + busy + Reset in progress. + 1 + + + + + INT + Interrupt Enable. Generates an interrupt when done or error set. + 1 + 1 + + + dis + Disable + 0 + + + en + Enable + 1 + + + + + SRC + Source Select. This bit selects the hash function and CRC generator input source. + 2 + 1 + + + inputFIFO + Input FIFO + 0 + + + outputFIFO + Output FIFO + 1 + + + + + BSO + Byte Swap Output. Note. No byte swap will occur if there is not a full word. + 4 + 1 + + + BSI + Byte Swap Input. Note. No byte swap will occur if there is not a full word. + 5 + 1 + + + WAIT_EN + Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. + 6 + 1 + + + WAIT_POL + Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. + 7 + 1 + + + activeLo + Active Low. + 0 + + + activeHi + Active High. + 1 + + + + + WRSRC + Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. + 8 + 2 + + + none + None. + 0 + + + cipherOutput + Cipher Output. + 1 + + + readFIFO + Read FIFO. + 2 + + + + + RDSRC + Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. + 10 + 2 + + + dmaDisabled + DMA Disable. + 0 + + + dmaOrApb + DMA Or APB. + 1 + + + rng + RNG. + 2 + + + + + FLAG_MODE + Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. + 14 + 1 + + + unres_wr + Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. + 0 + + + res_wr + Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. + 1 + + + + + DMADNE_MSK + DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. + 15 + 1 + + + not_used + DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. + 0 + + + used + DMA_DONE used in setting CRYPTO_CTRL.DONE bit. + 1 + + + + + DMA_DONE + DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. + 24 + 1 + + + notDone + Not Done. + 0 + + + done + Done. + 1 + + + + + GLS_DONE + Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. + 25 + 1 + + + HSH_DONE + Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. + 26 + 1 + + + CPH_DONE + Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. + 27 + 1 + + + MAA_DONE + MAA Done. MAA operation is complete. This bit must be cleared before starting a new MAA operation. This bit is read only while the MAA is in progress. This bit is negate of MAA_CTRL.STC. + 28 + 1 + + + ERR + AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. + 29 + 1 + read-only + + + noError + No Error. + 0 + + + error + Error. + 1 + + + + + RDY + Ready. Crypto block ready for more data. + 30 + 1 + read-only + + + busy + Busy. + 0 + + + ready + Ready. + 1 + + + + + DONE + Done. One or more cryptographic calculations complete (logical OR of done flags). + 31 + 1 + read-only + + + + + CIPHER_CTRL + Cipher Control Register. + 0x04 + + + ENC + Encrypt. Select encryption or decryption of input data. + 0 + 1 + + + encrypt + Encrypt. + 0 + + + decrypt + Decrypt. + 1 + + + + + KEY + Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. + 1 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SRC + Source of Random key. + 2 + 2 + + + cipherKey + User cipher key (0x4000_1060). + 0 + + + regFile + Key from battery-backed register file (0x4000_5000 to 0x4000_501F). + 2 + + + qspiKey_regFile + Key from battery-backed register file (0x4000_5020 to 0x4000_502F). + 3 + + + + + CIPHER + Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. + 4 + 3 + + + dis + Disabled. + 0 + + + aes128 + AES 128. + 1 + + + aes192 + AES 192. + 2 + + + aes256 + AES 256. + 3 + + + des + DES. + 4 + + + tdes + Triple DES. + 5 + + + + + MODE + Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. + 8 + 3 + + + ECB + ECB Mode. + 0 + + + CBC + CBC Mode. + 1 + + + CFB + CFB (AES only). + 2 + + + OFB + OFB (AES only). + 3 + + + CTR + CTR (AES only). + 4 + + + + + + + HASH_CTRL + HASH Control Register. + 0x08 + + + INIT + Initialize. Initializes hash registers with standard constants. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + XOR + XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + HASH + Hash function selection. + 2 + 3 + + + dis + Disabled. + 0 + + + sha1 + SHA-1. + 1 + + + sha224 + SHA 224. + 2 + + + sha256 + SHA 256. + 3 + + + sha384 + SHA 384. + 4 + + + sha512 + SHA 512. + 5 + + + + + LAST + Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. + 5 + 1 + + + noEffect + No Effect. + 0 + + + lastMsgData + Last Message Data. + 1 + + + + + + + CRC_CTRL + CRC Control Register. + 0x0C + + + CRC_EN + Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + MSB + MSB select. This bit selects the order of calculating CRC on data. + 1 + 1 + + + lsbFirst + LSB First. + 0 + + + msbFirst + MSB First. + 1 + + + + + PRNG + Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. + 2 + 1 + + + ENT + Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. + 3 + 1 + + + HAM + Hamming Code Enable. Enable hamming code calculation. + 4 + 1 + + + HRST + Hamming Reset. Reset Hamming code ECC generator for next block. + 5 + 1 + write-only + + write + + reset + Starts reset operation. + 1 + + + + + + + DMA_SRC + Crypto DMA Source Address. + 0x10 + + + SRC_ADDR + DMA Source Address. + 0 + 32 + + + + + DMA_DST + Crypto DMA Destination Address. + 0x14 + + + DST_ADDR + DMA Destination Address. + 0 + 32 + + + + + DMA_CNT + Crypto DMA Byte Count. + 0x18 + + + COUNT + DMA Byte Address. + 0 + 32 + + + + + MAA_CTRL + MAA Control Register. + 0x1C + + + STC + Start Calculation. This bit functions as both the control and the status of the MAA. If the size value in the MAWS register is invalid, the STC bit will be cleared by hardware immediately. Otherwise, the STC bit is automatically cleared following the completion of each calculation or detecting an error. Clearing the STC bit resets the controller to its default state. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CLC + Calculation Configuration. These bits select desired calculation. + 1 + 3 + + + exp + Exponentiation. + 0 + + + sq + Square operation. + 1 + + + mul + Multiplication. + 2 + + + sqMul + Square followed by a multiplication. + 3 + + + add + Addition. + 4 + + + sub + Subtraction. + 5 + + + + + OCALC + Optimized Calculation Control. For optimized calculation, unnecessary multiply operations after normalizing the exponent are skipped. + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + MAAER + MAA Error. The MAAER bit defaults to 0 and can only be set by hardware. Once set, it must be cleared by software otherwise no new operation can be initiated. Software writes 1 to this bit has no effect and MAAER will maintain its original state. + 7 + 1 + + + noError + No Error. + 0 + + + error + Error. + 1 + + + + + AMS + Multiplier A Memory Select. These bits select the starting position of the parameter 'a' within the logical segment specified by AMA. + 8 + 2 + + + BMS + Multiplicand B Memory Select. These bits select the starting position of the parameter 'b' within the logical segment specified by BMA. + 10 + 2 + + + EMS + Exponent Memory Select. These bits select the starting position of the parameter 'e' within the logical segment specified by EMA. + 12 + 2 + + + MMS + Modulus Memory Select. These bits select the starting position of the parameter 'm' within the logical segment 5. + 14 + 2 + + + AMA + Multiplier / Operand A Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'a'. + 16 + 4 + + + BMA + Multiplicand / Operand B Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'b'. + 20 + 4 + + + RMA + Result Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'r'. + 24 + 4 + + + TMA + Temporary Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 't'. + 28 + 4 + + + + + 4 + 4 + DATA_IN[%s] + Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. + 0x20 + write-only + + + DATA + Crypto Data Input. Input can be written to this register instead of using DMA. + 0 + 32 + + + + + 4 + 4 + DATA_OUT[%s] + Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. + 0x30 + read-only + + + DATA + Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. + 0 + 32 + + + + + CRC_POLY + CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + 0x40 + 0xEDB88320 + + + SRC_ADDR + CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + 0 + 32 + + + + + CRC_VAL + CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. + 0x44 + 0xFFFFFFFF + + + VAL + CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. + 0 + 32 + + + + + CRC_PRNG + Pseudo Random Value. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled. + 0x48 + read-only + + + PRNG + Pseudo Random Value. Output of the Galois Field Shift Register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled. + 0 + 32 + + + + + HAM_ECC + Hamming ECC Register. + 0x4C + + + ECC + Hamming ECC Value. These bits are the even parity of their corresponding bit groups. + 0 + 16 + + + PAR + Parity. This is the parity of the entire array. + 16 + 1 + + + even + Even. + 0 + + + odd + Odd. + 1 + + + + + + + 4 + 4 + CIPHER_INIT[%s] + Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + 0x50 + + + IVEC + Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + 0 + 32 + + + + + 8 + 4 + CIPHER_KEY[%s] + Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. + 0x60 + write-only + + + KEY + Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. + 0 + 32 + + + + + 16 + 4 + HASH_DIGEST[%s] + This register holds the calculated hash value. This register is affected by the endian swap bits. + 0x80 + + + HASH + This register holds the calculated hash value. This register is affected by the endian swap bits. + 0 + 32 + + + + + 4 + 4 + HASH_MSG_SZ[%s] + Message Size. This register holds the lowest 32-bit of message size in bytes. + 0xC0 + + + MSGSZ + Message Size. This register holds the lowest 32-bit of message size in bytes. + 0 + 32 + + + + + MAA_MAWS + MAA Word Size. This register defines the number of bits for a modular operation. This register must be set to a valid value prior to the MAA operation start. Valid values are from 1 to 2048. Invalid values are ignored and will not initiate a MAA operation. + 0xD0 + + + MSGSZ + MAA Word Size. + 0 + 12 + + + + + + + + TRNG + Random Number Generator. + 0x4004D000 + + 0x00 + 0x1000 + registers + + + TRNG + TRNG interrupt. + 4 + + + + CN + TRNG Control Register. + 0x00 + 0x00000003 + + + ODHT + Start On-Demand health test + 0 + 1 + + + RND_IRQ_EN + To enable IRQ generation when a new 32-bit Random number is ready. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + HEALTH_EN + To enable IRQ generation when a health test fails + 2 + 1 + read-only + + + disable + disable + 0 + + + enable + enable + 1 + + + + + AESKG_MEU + AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. + 3 + 1 + + + AESKG_MEMPROTE + AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. + 4 + 1 + + + AESKG_MEMPROTA + AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. + 5 + 1 + + + + + ST + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x04 + read-only + + + RND_RDY + 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. + 0 + 1 + + + Busy + TRNG Busy + 0 + + + Ready + 32 bit random data is ready + 1 + + + + + ODHTS + On-Demand health test status + 1 + 1 + + + Done + On demand health test done + 0 + + + Busy + On demand health test on going + 1 + + + + + HTS + Health test status. This bit shall be read when On-demand health test is completed (ODHTS=0) to check the result. This bit is also set when a continuous health test reports an error, IRQ is generated if HEALTH_EN=1. Write 1 to clear this bit. + 2 + 1 + + + Pass + Pass + 0 + + + Fail + Fail + 1 + + + + + SRCFAIL + Entropy source has failed. IRQ is generated if HEALTH_EN=1. Write 1 to clear this bit. + 3 + 1 + + + Works + Entopy source works correctly + 0 + + + Fail + Entropy Source has failed + 1 + + + + + AESKGD_MEU_S + Automatically AES transfer on going + 4 + 1 + + + + + DATA + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x08 + read-only + + + DATA + Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. + 0 + 32 + + + + + + + + TRIMSIR + Trim System Initilazation Registers + 0x40005400 + + 0x00 + 0x400 + registers + + + + RTC + System Init. Configuration Register 2. + 0x08 + + + RTCX1 + RTC X1 Trim. + 16 + 5 + + + RTCX2 + RTC X2 Trim. + 21 + 5 + + + LOCK + Lock. + 31 + 1 + + + + + SIR13 + System Init. Configuration Register 13. + 0x34 + + + SIMOCLKDIV + SIMO Clock Divide while in LP mode. + 0 + 2 + + + + + SIR17 + System Init. Configuration Register 17. + 0x44 + + + BUCKCLKSELLP + BUCK Clock Select Low Power Mode. + 6 + 2 + + + + + + + + UART0 + UART + 0x40042000 + + 0 + 0x1000 + registers + + + UART0 + UART0 IRQ + 14 + + + + CTRL + Control Register. + 0x00 + 32 + + + ENABLE + UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. + 0 + 1 + + + dis + UART disabled. FIFOs are flushed. Clock is gated off for power savings. + 0 + + + en + UART enabled. + 1 + + + + + PARITY_EN + Enable/disable Parity bit (9th character). + 1 + 1 + + + dis + No Parity + 0 + + + en + Parity enabled as 9th bit + 1 + + + + + PARITY + When PARITY_EN=1, selects odd, even, Mark or Space parity. + Mark parity = always 1; + + Space parity = always 0. + 2 + 2 + + + Even + Even parity selected. + 0 + + + ODD + Odd parity selected. + 1 + + + MARK + Mark parity selected. + 2 + + + SPACE + Space parity selected. + 3 + + + + + PARMD + Selects parity based on 1s or 0s count (when PARITY_EN=1). + 4 + 1 + + + 1 + Parity calculation is based on number of 1s in frame. + 0 + + + 0 + Parity calculation is based on number of 0s in frame. + 1 + + + + + TX_FLUSH + Flushes the TX FIFO buffer. + 5 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. + 6 + 1 + + + BITACC + If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. + 7 + 1 + + + FRAME + Frame accuracy. + 0 + + + BIT + Bit accuracy. + 1 + + + + + CHAR_SIZE + Selects UART character size. + 8 + 2 + + + 5 + 5 bits. + 0 + + + 6 + 6 bits. + 1 + + + 7 + 7 bits. + 2 + + + 8 + 8 bits. + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated. + 10 + 1 + + + 1 + 1 stop bit. + 0 + + + 1_5 + 1.5 stop bits. + 1 + + + + + FLOW_CTRL + Enables/disables hardware flow control. + 11 + 1 + + + en + HW Flow Control with RTS/CTS enabled + 1 + + + dis + HW Flow Control disabled + 0 + + + + + FLOW_POL + RTS/CTS polarity. + 12 + 1 + + + 0 + RTS/CTS asserted is logic 0. + 0 + + + 1 + RTS/CTS asserted is logic 1. + 1 + + + + + NULL_MODEM + NULL Modem Support (RTS/CTS and TXD/RXD swap). + 13 + 1 + + + DIS + Direct convention. + 0 + + + EN + Null Modem Mode. + 1 + + + + + BREAK + Break control bit. It causes a break condition to be transmitted to receiving UART. + 14 + 1 + + + DIS + Break characters are not generated. + 0 + + + EN + Break characters are sent (all the bits are at '0' including start/parity/stop). + 1 + + + + + CLKSEL + Baud Rate Clock Source Select. Selects the baud rate clock. + 15 + 1 + + + SYSTEM + System clock. + 0 + + + ALTERNATE + Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. + 1 + + + + + RX_TO + RX Time Out. RX time out interrupt will occur after RXTO Uart + characters if RX-FIFO is not empty and RX FIFO has not been read. + 16 + 8 + + + + + THRESH_CTRL + Threshold Control register. + 0x04 + 32 + + + RX_FIFO_THRESH + RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. + 0 + 6 + + + TX_FIFO_THRESH + TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. + 8 + 6 + + + RTS_FIFO_THRESH + RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. + 16 + 6 + + + + + STATUS + Status Register. + 0x08 + 32 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status. + 0 + 1 + read-only + + + RX_BUSY + Read-only flag indicating the UARTreceiver status. + 1 + 1 + read-only + + + PARITY + 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. + 2 + 1 + read-only + + + BREAK + Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). + 3 + 1 + read-only + + + RX_EMPTY + Read-only flag indicating the RX FIFO state. + 4 + 1 + read-only + + + RX_FULL + Read-only flag indicating the RX FIFO state. + 5 + 1 + read-only + + + TX_EMPTY + Read-only flag indicating the TX FIFO state. + 6 + 1 + read-only + + + TX_FULL + Read-only flag indicating the TX FIFO state. + 7 + 1 + read-only + + + RX_NUM + Indicates the number of bytes currently in the RX FIFO. + 8 + 6 + read-only + + + TX_FIFO_CNT + Indicates the number of bytes currently in the TX FIFO. + 16 + 6 + read-only + + + RX_TO + Receiver Timeout Status. Indicates if timeout has occurred. + 24 + 1 + read-only + + + + + INT_EN + Interrupt Enable Register. + 0x0C + 32 + + + RX_FRAME_ERROR + Enable for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + Enable for RX Parity Error interrupt. + 1 + 1 + + + CTS_CHANGE + Enable for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + Enable for RX FIFO OVerrun interrupt. + 3 + 1 + + + RX_FIFO_THRESH + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_ALMOST_EMPTY + Enable for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_THRESH + Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + Enable for received BREAK character interrupt. + 7 + 1 + + + RX_TIMEOUT + Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + Enable for Last break character interrupt. + 9 + 1 + + + + + INT_FL + Interrupt Status Flags. + 0x10 + 32 + oneToClear + + + RX_FRAME_ERROR + FLAG for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + FLAG for RX Parity Error interrupt. + 1 + 1 + + + CTS_CHANGE + FLAG for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + FLAG for RX FIFO Overrun interrupt. + 3 + 1 + + + RX_FIFO_THRESH + FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_ALMOST_EMPTY + FLAG for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_THRESH + FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + FLAG for received BREAK character interrupt. + 7 + 1 + + + RX_TIMEOUT + FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + FLAG for Last break character interrupt. + 9 + 1 + + + + + BAUD0 + Baud rate register. Integer portion. + 0x14 + 32 + + + IBAUD + Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). + 0 + 12 + + + FACTOR + FACTOR must be chosen to have IDIV> + 0. factor used in calculation = 128 > + > + FACTOR. + + 16 + 2 + + + 128 + Baud Factor 128 + 0 + + + 64 + Baud Factor 64 + 1 + + + 32 + Baud Factor 32 + 2 + + + 16 + Baud Factor 16 + 3 + + + + + + + BAUD1 + Baud rate register. Decimal Setting. + 0x18 + 32 + + + DBAUD + Decimal portion of baud rate divisor value. DIV = InputClock/ (factor*Baud Rate Frequency). DDIV= (DIV-IDIV) *128. + 0 + 12 + + + + + FIFO + FIFO Data buffer. + 0x1C + 32 + + + FIFO + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + + + DMA + DMA Configuration. + 0x20 + 32 + + + TXDMA_EN + TX DMA channel enable. + 0 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + RXDMA_EN + RX DMA channel enable. + 1 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + RXDMA_START + Receive DMA Start. + 3 + 1 + + + RXDMA_AUTO_TO + Receive DMA Timeout Start. + 5 + 1 + + + TXDMA_LEVEL + TX threshold for DMA transmission. + 8 + 6 + + + RXDMA_LEVEL + RX threshold for DMA transmission. + 16 + 6 + + + + + TX_FIFO + Transmit FIFO Status register. + 0x24 + 32 + + + DATA + Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). + 0 + 7 + + + + + + + + UART1 + UART 1 + 0x40043000 + + UART1 + UART1 IRQ + 15 + + + + + UART2 + UART 2 + 0x40044000 + + UART2 + UART2 IRQ + 34 + + + + + USBHS + USB 2.0 High-speed Controller. + 0x400B1000 + + 0 + 0x1000 + registers + + + USB + 2 + + + + FADDR + Function address register. + 0x00 + 8 + 0x00 + + + ADDR + Function address for this controller. + 0 + 7 + read-write + + + UPDATE + Set when ADDR is written, cleared when new address takes effect. + 7 + 1 + read-only + + + + + POWER + Power management register. + 0x01 + 8 + + + EN_SUSPENDM + Enable SUSPENDM signal. + 0 + 1 + read-write + + + SUSPEND + Suspend mode detected. + 1 + 1 + read-only + + + RESUME + Generate resume signaling. + 2 + 1 + read-write + + + RESET + Bus reset detected. + 3 + 1 + read-only + + + HS_MODE + High-speed mode detected. + 4 + 1 + read-only + + + HS_ENABLE + High-speed mode enable. + 5 + 1 + read-write + + + SOFTCONN + Softconn. + 6 + 1 + read-write + + + ISO_UPDATE + Wait for SOF during Isochronous xfers. + 7 + 1 + read-write + + + + + INTRIN + Interrupt register for EP0 and IN EP1-15. + 0x02 + 16 + + + EP15_IN_INT + Endpoint 15 interrupt. + 15 + 1 + read-only + + + EP14_IN_INT + Endpoint 14 interrupt. + 14 + 1 + read-only + + + EP13_IN_INT + Endpoint 13 interrupt. + 13 + 1 + read-only + + + EP12_IN_INT + Endpoint 12 interrupt. + 12 + 1 + read-only + + + EP11_IN_INT + Endpoint 11 interrupt. + 11 + 1 + read-only + + + EP10_IN_INT + Endpoint 10 interrupt. + 10 + 1 + read-only + + + EP9_IN_INT + Endpoint 9 interrupt. + 9 + 1 + read-only + + + EP8_IN_INT + Endpoint 8 interrupt. + 8 + 1 + read-only + + + EP7_IN_INT + Endpoint 7 interrupt. + 7 + 1 + read-only + + + EP6_IN_INT + Endpoint 6 interrupt. + 6 + 1 + read-only + + + EP5_IN_INT + Endpoint 5 interrupt. + 5 + 1 + read-only + + + EP4_IN_INT + Endpoint 4 interrupt. + 4 + 1 + read-only + + + EP3_IN_INT + Endpoint 3 interrupt. + 3 + 1 + read-only + + + EP2_IN_INT + Endpoint 2 interrupt. + 2 + 1 + read-only + + + EP1_IN_INT + Endpoint 1 interrupt. + 1 + 1 + read-only + + + EP0_IN_INT + Endpoint 0 interrupt. + 0 + 1 + read-only + + + + + INTROUT + Interrupt register for OUT EP 1-15. + 0x04 + 16 + + + EP15_OUT_INT + Endpoint 15 interrupt. + 15 + 1 + read-only + + + EP14_OUT_INT + Endpoint 14 interrupt. + 14 + 1 + read-only + + + EP13_OUT_INT + Endpoint 13 interrupt. + 13 + 1 + read-only + + + EP12_OUT_INT + Endpoint 12 interrupt. + 12 + 1 + read-only + + + EP11_OUT_INT + Endpoint 11 interrupt. + 11 + 1 + read-only + + + EP10_OUT_INT + Endpoint 10 interrupt. + 10 + 1 + read-only + + + EP9_OUT_INT + Endpoint 9 interrupt. + 9 + 1 + read-only + + + EP8_OUT_INT + Endpoint 8 interrupt. + 8 + 1 + read-only + + + EP7_OUT_INT + Endpoint 7 interrupt. + 7 + 1 + read-only + + + EP6_OUT_INT + Endpoint 6 interrupt. + 6 + 1 + read-only + + + EP5_OUT_INT + Endpoint 5 interrupt. + 5 + 1 + read-only + + + EP4_OUT_INT + Endpoint 4 interrupt. + 4 + 1 + read-only + + + EP3_OUT_INT + Endpoint 3 interrupt. + 3 + 1 + read-only + + + EP2_OUT_INT + Endpoint 2 interrupt. + 2 + 1 + read-only + + + EP1_OUT_INT + Endpoint 1 interrupt. + 1 + 1 + read-only + + + + + INTRINEN + Interrupt enable for EP 0 and IN EP 1-15. + 0x06 + 16 + + + EP15_IN_INT_EN + Endpoint 15 interrupt enable. + 15 + 1 + read-write + + + EP14_IN_INT_EN + Endpoint 14 interrupt enable. + 14 + 1 + read-write + + + EP13_IN_INT_EN + Endpoint 13 interrupt enable. + 13 + 1 + read-write + + + EP12_IN_INT_EN + Endpoint 12 interrupt enable. + 12 + 1 + read-write + + + EP11_IN_INT_EN + Endpoint 11 interrupt enable. + 11 + 1 + read-write + + + EP10_IN_INT_EN + Endpoint 10 interrupt enable. + 10 + 1 + read-write + + + EP9_IN_INT_EN + Endpoint 9 interrupt enable. + 9 + 1 + read-write + + + EP8_IN_INT_EN + Endpoint 8 interrupt enable. + 8 + 1 + read-write + + + EP7_IN_INT_EN + Endpoint 7 interrupt enable. + 7 + 1 + read-write + + + EP6_IN_INT_EN + Endpoint 6 interrupt enable. + 6 + 1 + read-write + + + EP5_IN_INT_EN + Endpoint 5 interrupt enable. + 5 + 1 + read-write + + + EP4_IN_INT_EN + Endpoint 4 interrupt enable. + 4 + 1 + read-write + + + EP3_IN_INT_EN + Endpoint 3 interrupt enable. + 3 + 1 + read-write + + + EP2_IN_INT_EN + Endpoint 2 interrupt enable. + 2 + 1 + read-write + + + EP1_IN_INT_EN + Endpoint 1 interrupt enable. + 1 + 1 + read-write + + + EP0_INT_EN + Endpoint 0 interrupt enable. + 0 + 1 + read-write + + + + + INTROUTEN + Interrupt enable for OUT EP 1-15. + 0x08 + 16 + + + EP15_OUT_INT_EN + Endpoint 15 interrupt. + 15 + 1 + read-write + + + EP14_OUT_INT_EN + Endpoint 14 interrupt. + 14 + 1 + read-write + + + EP13_OUT_INT_EN + Endpoint 13 interrupt. + 13 + 1 + read-write + + + EP12_OUT_INT_EN + Endpoint 12 interrupt. + 12 + 1 + read-write + + + EP11_OUT_INT_EN + Endpoint 11 interrupt. + 11 + 1 + read-write + + + EP10_OUT_INT_EN + Endpoint 10 interrupt. + 10 + 1 + read-write + + + EP9_OUT_INT_EN + Endpoint 9 interrupt. + 9 + 1 + read-write + + + EP8_OUT_INT_EN + Endpoint 8 interrupt. + 8 + 1 + read-write + + + EP7_OUT_INT_EN + Endpoint 7 interrupt. + 7 + 1 + read-write + + + EP6_OUT_INT_EN + Endpoint 6 interrupt. + 6 + 1 + read-write + + + EP5_OUT_INT_EN + Endpoint 5 interrupt. + 5 + 1 + read-write + + + EP4_OUT_INT_EN + Endpoint 4 interrupt. + 4 + 1 + read-write + + + EP3_OUT_INT_EN + Endpoint 3 interrupt. + 3 + 1 + read-write + + + EP2_OUT_INT_EN + Endpoint 2 interrupt. + 2 + 1 + read-write + + + EP1_OUT_INT_EN + Endpoint 1 interrupt. + 1 + 1 + read-write + + + + + INTRUSB + Interrupt register for common USB interrupts. + 0x0A + 8 + + + SOF_INT + Start of Frame. + 3 + 1 + read-only + + + RESET_INT + Bus reset detected. + 2 + 1 + read-only + + + RESUME_INT + Resume detected. + 1 + 1 + read-only + + + SUSPEND_INT + Suspend detected. + 0 + 1 + read-only + + + + + INTRUSBEN + Interrupt enable for common USB interrupts. + 0x0B + 8 + + + SOF_INT_EN + Start of Frame. + 3 + 1 + read-write + + + RESET_INT_EN + Bus reset detected. + 2 + 1 + read-write + + + RESUME_INT_EN + Resume detected. + 1 + 1 + read-write + + + SUSPEND_INT_EN + Suspend detected. + 0 + 1 + read-write + + + + + FRAME + Frame number. + 0x0C + 16 + + + FRAMENUM + Read the last received frame number, that is the 11-bit frame number received in the SOF packet. + 0 + 11 + read-only + + + + + INDEX + Index for banked registers. + 0x0E + 8 + + + INDEX + Index Register Access Selector. + 0 + 4 + read-write + + + + + TESTMODE + USB 2.0 test mode enable register. + 0x0F + 8 + + + FORCE_FS + Force USB to Full-speed after reset. + 5 + 1 + read-write + + + FORCE_HS + Force USB to High-speed after reset. + 4 + 1 + read-write + + + TEST_PKT + Transmit fixed test packet. + 3 + 1 + read-write + + + TEST_K + Force USB to continuous K state. + 2 + 1 + read-write + + + TEST_J + Force USB to continuous J state. + 1 + 1 + read-write + + + TEST_SE0_NAK + Respond to any valid IN token with NAK. + 0 + 1 + read-write + + + + + INMAXP + Maximum packet size for INx endpoint (x == INDEX). + 0x10 + 16 + + + MAXPACKETSIZE + Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9 + 0 + 11 + + + NUMPACKMINUS1 + Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. + 11 + 5 + + + + + CSR0 + Control status register for EP 0 (when INDEX == 0). + 0x12 + 8 + + + SERV_SETUP_END + Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set + 7 + 1 + read-write + + + SERV_OUTPKTRDY + Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set. + 6 + 1 + read-write + + + SEND_STALL + Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. + 5 + 1 + read-write + + + SETUP_END + Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear. + 4 + 1 + read-only + + + DATA_END + Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. + 3 + 1 + read-write + + + SENT_STALL + Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. + 2 + 1 + read-write + + + INPKTRDY + EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. + 1 + 1 + read-write + + + OUTPKTRDY + EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. + 0 + 1 + read-only + + + + + INCSRL + Control status lower register for INx endpoint (x == INDEX). + CSR0 + 0x12 + 8 + + + INCOMPTX + Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear. + 7 + 1 + read-write + + + CLRDATATOG + Write 1 to clear IN endpoint data-toggle to 0. + 6 + 1 + read-write + + + SENTSTALL + Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear. + 5 + 1 + read-write + + + SENDSTALL + Send STALL Handshake. + 4 + 1 + read-only + + + terminate + Terminate STALL handhsake + 0 + + + respond + Respond to an IN token with a STALL handshake + 1 + + + + + FLUSHFIFO + Flush Next Packet from IN FIFO. Write 1 to clear + 3 + 1 + read-write + + + UNDERRUN + Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear + 2 + 1 + read-write + + + FIFONOTEMPTY + Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. + 1 + 1 + read-write + + + INPKTRDY + IN Packet Ready. Write a 1 to clear + 0 + 1 + read-only + + + + + INCSRU + Control status upper register for INx endpoint (x == INDEX). + 0x13 + 8 + + + AUTOSET + Auto Set inpktrdy. + 7 + 1 + read-write + + + set + USBHS_INCSRL_inpktrdy must be set by firmware. + 0 + + + auto + USBHS_INCSRL_inpktrdy is automatically set. + 1 + + + + + ISO + Isochronous Transfer Enable + 6 + 1 + read-write + + + interrupt + Enable IN Bulk and IN interrupt transfers. + 0 + + + isochronous + Enable IN Isochronous transfers. + 1 + + + + + MODE + Endpoint Direction Mode. + 5 + 1 + read-write + + + out + Endpoint direction is OUT. + 0 + + + in + Endpoint direction is IN. + 1 + + + + + FRCDATATOG + Force In Data - Toggle + 3 + 1 + read-write + + + received + Toggle data-toglge only when an ACK is received. + 0 + + + dontcare + Toggle data-toggle regardless of ACK. + 1 + + + + + DPKTBUFDIS + Double Packet Buffering Disable + 1 + 1 + read-write + + + en + Enable Double packet buffering. + 0 + + + dis + Disable Double Packet Buffering. + 1 + + + + + + + OUTMAXP + Maximum packet size for OUTx endpoint (x == INDEX). + 0x14 + 16 + + + NUMPACKMINUS1 + Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. + 11 + 5 + + + MAXPACKETSIZE + Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9. + 0 + 11 + + + + + OUTCSRL + Control status lower register for OUTx endpoint (x == INDEX). + 0x16 + 8 + + + CLRDATATOG + 7 + 1 + read-write + + + SENTSTALL + 6 + 1 + read-write + + + SENDSTALL + 5 + 1 + read-write + + + FLUSHFIFO + 4 + 1 + read-write + + + DATAERROR + 3 + 1 + read-only + + + OVERRUN + 2 + 1 + read-write + + + FIFOFULL + 1 + 1 + read-only + + + OUTPKTRDY + 0 + 1 + read-write + + + + + OUTCSRU + Control status upper register for OUTx endpoint (x == INDEX). + 0x17 + 8 + + + AUTOCLEAR + 7 + 1 + read-write + + + ISO + 6 + 1 + read-write + + + DISNYET + 4 + 1 + read-write + + + DPKTBUFDIS + 1 + 1 + read-write + + + INCOMPRX + 0 + 1 + read-only + + + + + COUNT0 + Number of received bytes in EP 0 FIFO (INDEX == 0). + 0x18 + 16 + + + COUNT0 + Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 + 0 + 7 + read-only + + + + + OUTCOUNT + Number of received bytes in OUT EPx FIFO (x == INDEX). + COUNT0 + 0x18 + 16 + + + OUTCOUNT + Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. + 0 + 13 + read-only + + + + + FIFO0 + Read for OUT data FIFO, write for IN data FIFO. + 0x20 + + + USBHS_FIFO0 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO1 + Read for OUT data FIFO, write for IN data FIFO. + 0x24 + + + USBHS_FIFO1 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO2 + Read for OUT data FIFO, write for IN data FIFO. + 0x28 + + + USBHS_FIFO2 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO3 + Read for OUT data FIFO, write for IN data FIFO. + 0x2c + + + USBHS_FIFO3 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO4 + Read for OUT data FIFO, write for IN data FIFO. + 0x30 + + + USBHS_FIFO4 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO5 + Read for OUT data FIFO, write for IN data FIFO. + 0x34 + + + USBHS_FIFO5 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO6 + Read for OUT data FIFO, write for IN data FIFO. + 0x38 + + + USBHS_FIFO6 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO7 + Read for OUT data FIFO, write for IN data FIFO. + 0x3c + + + USBHS_FIFO7 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO8 + Read for OUT data FIFO, write for IN data FIFO. + 0x40 + + + USBHS_FIFO8 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO9 + Read for OUT data FIFO, write for IN data FIFO. + 0x44 + + + USBHS_FIFO9 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO10 + Read for OUT data FIFO, write for IN data FIFO. + 0x48 + + + USBHS_FIFO10 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO11 + Read for OUT data FIFO, write for IN data FIFO. + 0x4c + + + USBHS_FIFO11 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO12 + Read for OUT data FIFO, write for IN data FIFO. + 0x50 + + + USBHS_FIFO12 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO13 + Read for OUT data FIFO, write for IN data FIFO. + 0x54 + + + USBHS_FIFO13 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO14 + Read for OUT data FIFO, write for IN data FIFO. + 0x58 + + + USBHS_FIFO14 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + FIFO15 + Read for OUT data FIFO, write for IN data FIFO. + 0x5c + + + USBHS_FIFO15 + USBHS Endpoint FIFO Read/Write Register. + 0 + 32 + + + + + HWVERS + HWVERS + 0x6c + 16 + + + USBHS_HWVERS + USBHS Register. + 0 + 16 + + + + + EPINFO + Endpoint hardware information. + 0x78 + 8 + + + OUTENDPOINTS + 4 + 4 + read-only + + + INTENDPOINTS + 0 + 4 + read-only + + + + + RAMINFO + RAM width information. + 0x79 + 8 + + + RAMBITS + 0 + 4 + read-only + + + + + SOFTRESET + Software reset register. + 0x7A + 8 + + + RSTXS + 1 + 1 + read-write + + + RSTS + 0 + 1 + read-write + + + + + CTUCH + Chirp timeout timer setting. + 0x80 + 16 + + + C_T_UCH + HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. + 0 + 16 + + + + + CTHSRTN + Sets delay between HS resume to UTM normal operating mode. + 0x82 + 16 + + + C_T_HSTRN + High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation. + 0 + 16 + + + + + MXM_USB_REG_00 + MXM_USB_REG_00 + 0x400 + + + M31_PHY_UTMI_RESET + M31_PHY_UTMI_RESET + 0x404 + + + M31_PHY_UTMI_VCONTROL + M31_PHY_UTMI_VCONTROL + 0x408 + + + M31_PHY_CLK_EN + M31_PHY_CLK_EN + 0x40C + + + M31_PHY_PONRST + M31_PHY_PONRST + 0x410 + + + M31_PHY_NONCRY_RSTB + M31_PHY_NONCRY_RSTB + 0x414 + + + M31_PHY_NONCRY_EN + M31_PHY_NONCRY_EN + 0x418 + + + M31_PHY_U2_COMPLIANCE_EN + M31_PHY_U2_COMPLIANCE_EN + 0x420 + + + M31_PHY_U2_COMPLIANCE_DAC_ADJ + M31_PHY_U2_COMPLIANCE_DAC_ADJ + 0x424 + + + M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN + M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN + 0x428 + + + M31_PHY_CLK_RDY + M31_PHY_CLK_RDY + 0x42C + + + M31_PHY_PLL_EN + M31_PHY_PLL_EN + 0x430 + + + M31_PHY_BIST_OK + M31_PHY_BIST_OK + 0x434 + + + M31_PHY_DATA_OE + M31_PHY_DATA_OE + 0x438 + + + M31_PHY_OSCOUTEN + M31_PHY_OSCOUTEN + 0x43C + + + M31_PHY_LPM_ALIVE + M31_PHY_LPM_ALIVE + 0x440 + + + M31_PHY_HS_BIST_MODE + M31_PHY_HS_BIST_MODE + 0x444 + + + M31_PHY_CORECLKIN + M31_PHY_CORECLKIN + 0x448 + + + M31_PHY_XTLSEL + M31_PHY_XTLSEL + 0x44C + + + M31_PHY_LS_EN + M31_PHY_LS_EN + 0x450 + + + M31_PHY_DEBUG_SEL + M31_PHY_DEBUG_SEL + 0x454 + + + M31_PHY_DEBUG_OUT + M31_PHY_DEBUG_OUT + 0x458 + + + M31_PHY_OUTCLKSEL + M31_PHY_OUTCLKSEL + 0x45C + + + M31_PHY_XCFGI_31_0 + M31_PHY_XCFGI_31_0 + 0x460 + + + M31_PHY_XCFGI_63_32 + M31_PHY_XCFGI_63_32 + 0x464 + + + M31_PHY_XCFGI_95_64 + M31_PHY_XCFGI_95_64 + 0x468 + + + M31_PHY_XCFGI_127_96 + M31_PHY_XCFGI_127_96 + 0x46C + + + M31_PHY_XCFGI_137_128 + M31_PHY_XCFGI_137_128 + 0x470 + + + M31_PHY_XCFG_HS_COARSE_TUNE_NUM + M31_PHY_XCFG_HS_COARSE_TUNE_NUM + 0x474 + + + M31_PHY_XCFG_HS_FINE_TUNE_NUM + M31_PHY_XCFG_HS_FINE_TUNE_NUM + 0x478 + + + M31_PHY_XCFG_FS_COARSE_TUNE_NUM + M31_PHY_XCFG_FS_COARSE_TUNE_NUM + 0x47C + + + M31_PHY_XCFG_FS_FINE_TUNE_NUM + M31_PHY_XCFG_FS_FINE_TUNE_NUM + 0x480 + + + M31_PHY_XCFG_LOCK_RANGE_MAX + M31_PHY_XCFG_LOCK_RANGE_MAX + 0x484 + + + M31_PHY_XCFGI_LOCK_RANGE_MIN + M31_PHY_XCFGI_LOCK_RANGE_MIN + 0x488 + + + M31_PHY_XCFG_OB_RSEL + M31_PHY_XCFG_OB_RSEL + 0x48C + + + M31_PHY_XCFG_OC_RSEL + M31_PHY_XCFG_OC_RSEL + 0x490 + + + M31_PHY_XCFGO + M31_PHY_XCFGO + 0x494 + + + MXM_INT + USB Added Maxim Interrupt Flag Register. + 0x498 + + + VBUS + VBUS + 0 + 1 + + + NOVBUS + NOVBUS + 1 + 1 + + + + + MXM_INT_EN + USB Added Maxim Interrupt Enable Register. + 0x49C + + + VBUS + VBUS + 0 + 1 + + + NOVBUS + NOVBUS + 1 + 1 + + + + + MXM_SUSPEND + USB Added Maxim Suspend Register. + 0x4A0 + + + SEL + Suspend register + 0 + 1 + + + + + MXM_REG_A4 + USB Added Maxim Power Status Register + 0x4A4 + + + VRST_VDDB_N_A + VRST_VDDB_N_A + 0 + 1 + + + + + + + + WDT0 + Watchdog Timer 0 + 0x40003000 + + 0x00 + 0x0400 + registers + + + WDT0 + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + 0x7FFFF000 + + + INT_PERIOD + Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_PERIOD + Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + WDT_EN + Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_FLAG + Watchdog Timer Interrupt Flag. + 9 + 1 + oneToClear + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EN + Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_EN + Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_FLAG + Watchdog Timer Reset Flag. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Watchdog Timer Reset Register. + 0x04 + write-only + + + WDT_RST + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + + + + WDT1 + Watchdog Timer 0 1 + 0x40003400 + + WDT1 + WDT1 IRQ + 57 + + + + + WDT2 + Watchdog Timer 0 2 + 0x40003800 + + WDT2 + WDT2 IRQ + 81 + + + + + WUT + Wake Up Timer + 0x40006400 + + 0x00 + 0x0400 + registers + + + WUT + 53 + + + + CNT + Wakeup Timer Count Register + 0x0000 + read-write + + + COUNT + Timer Count Value. + 0 + 32 + + + + + CMP + Wakeup Timer Compare Register + 0x0004 + read-write + + + COMPARE + Timer Compare Value. + 0 + 32 + + + + + INTFL + Wakeup Timer Interrupt Register + 0x000C + read-write + + + IRQ_CLR + Timer Interrupt. + 0 + 1 + + + + + CTRL + Wakeup Timer Control Register + 0x0010 + read-write + + + TMODE + Timer Mode Select. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + pwm + PWM Mode. + 3 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Timer Prescaler Select. + 3 + 3 + + + DIV1 + 0 + + + DIV2 + 1 + + + DIV4 + 2 + + + DIV8 + 3 + + + DIV16 + 4 + + + DIV32 + 5 + + + DIV64 + 6 + + + DIV128 + 7 + + + DIV256 + 0 + + + DIV512 + 2 + + + DIV1024 + 3 + + + DIV2048 + 4 + + + DIV4096 + 5 + + + + + TPOL + Timer Polarity. + 6 + 1 + + + TEN + Timer Enable. + 7 + 1 + + + timer_dis + 0 + + + timer_en + 1 + + + + + PRES3 + Timer Prescaler Select. + 8 + 1 + + + pres3_1 + 0 + + + pres3_2 + 0 + + + pres3_4 + 0 + + + pres3_8 + 0 + + + pres3_16 + 0 + + + pres3_32 + 0 + + + pres3_64 + 0 + + + pres3_128 + 0 + + + pres3_256 + 1 + + + pres3_512 + 1 + + + pres3_1024 + 1 + + + pres3_2048 + 1 + + + pres3_4096 + 1 + + + + + + + NOLCMP + Non Overlaping Compare Register + 0x0014 + read-write + + + NOLLCMP + Non Overlaping Low Compare. + 0 + 8 + + + NOLHCMP + Non Overlaping High Compare. + 8 + 8 + + + + + PRESET + Preset register. + 0x0018 + + + PRESET + Preset Value. + 0 + 32 + + + + + RELOAD + Reload register. + 0x001C + + + RELOAD + Reload Value. + 0 + 32 + + + + + SNAPSHOT + Snapshot register. + 0x0020 + + + SNAPSHOT + Snapshot Value. + 0 + 32 + + + + + + + + diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 45382983f..5fc6e1c5b 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -75,6 +75,7 @@ from . import target_MAX32625 from . import target_MAX32630 from . import target_MAX32660 +from . import target_MAX32666 from . import target_MAX32670 from . import target_w7500 from . import target_s5js100 @@ -175,6 +176,7 @@ 'max32625': target_MAX32625.MAX32625, 'max32630': target_MAX32630.MAX32630, 'max32660': target_MAX32660.MAX32660, + 'max32666': target_MAX32666.MAX32666, 'max32670': target_MAX32670.MAX32670, 'mimxrt1010': target_MIMXRT1011xxxxx.MIMXRT1011xxxxx, 'mimxrt1015': target_MIMXRT1015xxxxx.MIMXRT1015xxxxx, diff --git a/pyocd/target/builtin/target_MAX32666.py b/pyocd/target/builtin/target_MAX32666.py new file mode 100644 index 000000000..a7dd625e6 --- /dev/null +++ b/pyocd/target/builtin/target_MAX32666.py @@ -0,0 +1,166 @@ +# pyOCD debugger +# Copyright (c) 2023 PyOCD Authors +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x0030ea4f, 0x00004770, + 0x0030ea4f, 0x00004770, 0x0030ea4f, 0x00004770, 0xf04fb538, 0x24004180, 0xf4206888, 0x608870e0, + 0xf4406888, 0x60882000, 0xf012688a, 0xd0fb6f00, 0xf4206888, 0xf4406060, 0x60886000, 0xf412688a, + 0xd0fb5f00, 0xf4206888, 0x60882080, 0xf8d0480f, 0xf0211100, 0xf8c00101, 0x46681100, 0xf840f000, + 0xbf0c2800, 0x20014620, 0x2000bd38, 0xb5104770, 0xf84df000, 0xbd102000, 0xf000b510, 0x2000f8c4, + 0xb510bd10, 0xfa0af000, 0xbd102000, 0x4002a000, 0x4280f04f, 0xf4006890, 0x48fa6160, 0x6f00f5b1, + 0x48f9bf08, 0xdc0bd017, 0xf5b1b1a9, 0xbf086f80, 0xd01048f6, 0x6fc0f5b1, 0xf44fbf08, 0xe00a50fa, + 0x6f20f5b1, 0xf44fbf08, 0xd00400e1, 0x6f40f5b1, 0xf44fbf08, 0x68914000, 0x1182f3c1, 0x477040c8, + 0xbc23f000, 0x4bea2100, 0xe00e4aea, 0x2901b169, 0x4610bf0c, 0x68802000, 0x0007f010, 0x4770bf18, + 0x29021c49, 0x4770bfa8, 0x4618e7f0, 0xe92de7f3, 0x4fde4df0, 0x4ddb2400, 0x4880f04f, 0xb374f8df, + 0xea4f4ed9, 0xe00c1a67, 0x2c01b15c, 0x4658bf0c, 0x68812000, 0x0f07f011, 0xf06fd005, 0xe8bd0005, + 0x48d38df0, 0xf8d8e7f5, 0xf4011008, 0xf5b16160, 0xbf086f00, 0xd01a4631, 0xb1b9dc0c, 0x6f80f5b1, + 0x4639bf08, 0xf5b1d013, 0xbf086fc0, 0x51faf44f, 0xe00bd00d, 0x6f20f5b1, 0xf44fbf08, 0xd00601e1, + 0x6f40f5b1, 0xf44fbf08, 0xd0004100, 0xf8d84629, 0xf3c22008, 0x40d11282, 0xf1fafbb1, 0x6a416041, + 0x0f02f011, 0x6a41d003, 0x0102f021, 0x68816241, 0x4170f021, 0x5100f041, 0x68816081, 0x417ff421, + 0x412af441, 0x68816081, 0x0102f041, 0x68816081, 0x0f07f011, 0x6881d1fb, 0x4170f021, 0x6a416081, + 0x0f02f011, 0x6a41d007, 0x0102f021, 0xf06f6241, 0xe8bd0006, 0xf0008df0, 0x1c64fb82, 0xdb932c02, + 0xe8bd2000, 0xb5108df0, 0xb0824604, 0x90002000, 0x46684621, 0xfb8bf000, 0xbf1c2800, 0xbd10b002, + 0x4620a901, 0xfba3f000, 0xbfbc2800, 0xbd10b002, 0xf0009800, 0x2800fad5, 0xb002bf1c, 0xf8ddbd10, + 0xf8dcc000, 0xf4200008, 0xf440407f, 0xf8cc40aa, 0x98010008, 0x0000f8cc, 0x0008f8dc, 0x0004f040, + 0x0008f8cc, 0x20004a8a, 0xe0204b8a, 0x2801b1f8, 0x4619bf0c, 0x68892100, 0x0f07f011, 0x1c40d1f3, + 0xdbf32802, 0x0008f8dc, 0x4070f020, 0x0008f8cc, 0x0024f8dc, 0x0f02f010, 0xf8dcd00b, 0xf0200024, + 0xf8cc0002, 0xb0020024, 0x0006f06f, 0x4611bd10, 0xf000e7e1, 0xb002fb24, 0xbd102000, 0xf3c0b570, + 0x1a84020c, 0x000cf3c1, 0x42ac1a0d, 0x4620d809, 0xff99f7ff, 0xbf182800, 0xf504bd70, 0x42ac5400, + 0x2000d9f5, 0xb530bd70, 0xb0834604, 0x460d2000, 0x0f0ff014, 0xbf1e9000, 0x0002f06f, 0xbd30b003, + 0x46684621, 0xfb13f000, 0xbf1c2800, 0xbd30b003, 0x4620a901, 0xfb2bf000, 0xbfbc2800, 0xbd30b003, + 0xf0009800, 0x2800fa5d, 0xb003bf1c, 0x9a00bd30, 0xf0206890, 0x60900010, 0x60109801, 0x63106828, + 0x63506868, 0x639068a8, 0x63d068e8, 0xf0406890, 0x60900001, 0xf0106890, 0xd1fb0f07, 0xf0206890, + 0x60904070, 0xf0106a50, 0xd0070f02, 0xf0206a50, 0x62500002, 0xf06fb003, 0xbd300086, 0xfabff000, + 0xf1042004, 0x42a10110, 0xeb04bf88, 0xd9030080, 0x1b04f854, 0xd8fb42a0, 0x2000b003, 0xe92dbd30, + 0xb08641f0, 0x460f2500, 0x9500493b, 0x95039502, 0x95059504, 0xf412680a, 0xbf076f00, 0xf4116809, + 0xf06f5f80, 0xb0060046, 0xe8bdbf18, 0xf01081f0, 0xbf1e0f03, 0x0002f06f, 0xe8bdb006, 0x220181f0, + 0x1d034601, 0xbf88428b, 0x0282eb00, 0xbf00d904, 0x3b04f851, 0xd8fb428a, 0x060ff020, 0x080ff000, + 0x46684631, 0xfa93f000, 0xbf1c2800, 0xe8bdb006, 0xa90181f0, 0xf0004630, 0x2800faaa, 0xb006bfbc, + 0x81f0e8bd, 0xf0009800, 0x2800f9db, 0xb006bf1c, 0x81f0e8bd, 0xf1064634, 0x42860010, 0xa902bf38, + 0xbf00d207, 0x2b04f854, 0x2025f841, 0x42841c6d, 0xe9ddd3f8, 0x60010100, 0x0f04f1b8, 0x9702bf38, + 0xf1b8d309, 0xbf380f08, 0xd3049703, 0x0f0cf1b8, 0x9704bf34, 0xa9029705, 0xf7ff4630, 0xb006ff34, + 0x81f0e8bd, 0x03938700, 0x05b8d800, 0x01e84800, 0x40029000, 0x40029400, 0x40006c00, 0x41f0e92d, + 0x4616b084, 0x4605460f, 0x0f03f010, 0xf025d029, 0xf0050003, 0xf1c80803, 0x68000404, 0xf1c49000, + 0x46690004, 0x46224408, 0xf0004631, 0xeba5fa85, 0x99000008, 0xff63f7ff, 0xbf1c2800, 0xe8bdb004, + 0x442581f0, 0x44261b3f, 0x4628e00b, 0xf7ff6831, 0x2800ff56, 0xb004bf1c, 0x81f0e8bd, 0x1d361d2d, + 0x2f041f3f, 0xf015d302, 0xd1ee0f0f, 0xbf282f10, 0x0800f04f, 0x462cd361, 0x0f0ff015, 0x8004f8cd, + 0xb004d004, 0x0002f06f, 0x81f0e8bd, 0xa8014629, 0xf9fdf000, 0xbf1c2800, 0xe8bdb004, 0xa90281f0, + 0xf0004620, 0x2800fa14, 0xb004bfbc, 0x81f0e8bd, 0xf0009801, 0x2800f945, 0xb004bf1c, 0x81f0e8bd, + 0x68889901, 0x0010f020, 0x98026088, 0x68306008, 0x68706308, 0x68b06348, 0x68f06388, 0x688863c8, + 0x0001f040, 0x68886088, 0x0f07f010, 0x6888d1fb, 0x4070f020, 0x6a486088, 0x0f02f010, 0x9801d009, + 0xf0206a40, 0x62480002, 0xf06fb004, 0xe8bd0086, 0xf00081f0, 0x2004f9a4, 0x0110f104, 0xbf8842a1, + 0x0080eb04, 0xbf00d904, 0x1b04f854, 0xd8fb42a0, 0x36103510, 0x2f103f10, 0x2f04d29d, 0x4628d30d, + 0xf7ff6831, 0x2800fedc, 0xb004bf1c, 0x81f0e8bd, 0x1d361d2d, 0x2f041f3f, 0xb17fd2f1, 0x90006828, + 0x4631463a, 0xf0004668, 0x4628fa2c, 0xf7ff9900, 0x2800fec6, 0xb004bf1c, 0x81f0e8bd, 0xb0042000, + 0x81f0e8bd, 0x47f0e92d, 0xf3c04688, 0x1a47010c, 0x040cf3c0, 0x000cf3c8, 0xeba84692, 0xf5c00500, + 0x42a35600, 0x42b3bf28, 0x42afd304, 0x19a0d128, 0xd9034298, 0x0002f06f, 0x87f0e8bd, 0x46394622, + 0xf0004650, 0xeb0af9b9, 0x46050084, 0x46414632, 0xf9b2f000, 0xf7ff4638, 0x2800fdc6, 0xe8bdbf18, + 0x465287f0, 0x46384621, 0xff08f7ff, 0xbf182800, 0x87f0e8bd, 0x4631462a, 0xe8bd4640, 0xe6fd47f0, + 0x46394622, 0xf0004650, 0x4638f997, 0xfdabf7ff, 0xbf182800, 0x87f0e8bd, 0x46214652, 0xf7ff4638, + 0x2800feed, 0xe8bdbf18, 0x463287f0, 0x46504641, 0xf982f000, 0xf7ff4628, 0x2800fd96, 0xe8bdbf18, + 0x465287f0, 0x46404631, 0xfed8f7ff, 0xbf182800, 0x87f0e8bd, 0x5100f507, 0x020cf3c1, 0x5000f5a5, + 0xf3c01a8c, 0x1a45010c, 0xd80a42ac, 0xf7ff4620, 0x2800fd7a, 0xe8bdbf18, 0xf50487f0, 0x42ac5400, + 0x2000d9f4, 0x87f0e8bd, 0x7040f410, 0xf06fbf04, 0x47700002, 0x6a4a494b, 0x62484310, 0x47702000, + 0x7040f410, 0xf06fbf04, 0x47700002, 0x6a4a4945, 0x0000ea22, 0x20006248, 0x48424770, 0xf0006a40, + 0x47700003, 0x0003f010, 0xf06fbf04, 0x47700002, 0x6a4a493c, 0x62484050, 0x47702000, 0x2100b508, + 0xf1a09100, 0xf5b15184, 0xbf244f00, 0x0002f06f, 0x4601bd08, 0xf0004668, 0x2800f8ca, 0xbd08bf18, + 0x98004931, 0x49316401, 0x49316401, 0x20006401, 0xb508bd08, 0x91002100, 0x5184f1a0, 0x4f00f5b1, + 0xf06fbf24, 0xbd080002, 0x46684601, 0xf8aff000, 0xbf182800, 0x4827bd08, 0x64089900, 0xbd082000, + 0xf0116881, 0xbf1c0f07, 0x0005f06f, 0xf04f4770, 0x68994380, 0x6260f401, 0xf5b2491f, 0xbf086f00, + 0xd017491e, 0xb1aadc0b, 0x6f80f5b2, 0x491cbf08, 0xf5b2d010, 0xbf086fc0, 0x51faf44f, 0xf5b2e00a, + 0xbf086f20, 0x01e1f44f, 0xf5b2d004, 0xbf086f40, 0x4100f44f, 0xf3c2689a, 0x40d11282, 0xfbb14a11, + 0x6041f1f2, 0xf0116a41, 0xd0030f02, 0xf0216a41, 0x62410102, 0xf0216881, 0xf0414170, 0x60815100, + 0x47702000, 0x40029000, 0x3a7f5ca3, 0xa1e34f20, 0x9608b2c1, 0xdeadbeef, 0x03938700, 0x05b8d800, + 0x01e84800, 0x000f4240, 0xf04f2101, 0x281f4280, 0x6c92d906, 0xfa013820, 0x4202f000, 0xe006d005, + 0xfa016a52, 0x4202f000, 0x2001d101, 0x20004770, 0x22014770, 0x4180f04f, 0xd906281f, 0x38206c8b, + 0xf000fa02, 0x64884318, 0x6a4b4770, 0xf000fa02, 0x62484318, 0x22014770, 0x4180f04f, 0xd907281f, + 0x38206c8b, 0xf000fa02, 0x0000ea23, 0x47706488, 0xfa026a4b, 0xea23f000, 0x62480000, 0x48324770, + 0xf8d0b081, 0xf0811100, 0xf8c00101, 0xf8d01100, 0xf0811100, 0xf8c00101, 0xf04f1100, 0x68005080, + 0x6800482a, 0xb0019000, 0x20004770, 0xf1a14770, 0x4a275380, 0x2f00f5b3, 0xf5a3d30a, 0x4b252c00, + 0x2f00f5bc, 0xf1a1d310, 0xf5bc5c84, 0xd2014f80, 0xe00a6002, 0x5184f1a1, 0x4180f5a1, 0x4f80f5b1, + 0xf06fbf24, 0x47700002, 0x20006003, 0xf1a04770, 0xf5b25280, 0xbf3c2f00, 0x0012f3c0, 0xd31f6008, + 0x5280f1a0, 0x2200f5a2, 0x2f00f5b2, 0xf5a0bf3c, 0xf3c02000, 0xd3120012, 0x5284f1a0, 0x4f80f5b2, + 0xf5a2d309, 0xf5b24280, 0xbf324f80, 0x4080f5a0, 0x0002f06f, 0xf3c04770, 0xf500000d, 0x60082000, + 0x47702000, 0x47702000, 0x4002a000, 0x10002000, 0x40029000, 0x40029400, 0xf2402a03, 0xf0108030, + 0xf0000c03, 0xf8118015, 0xf1bc3b01, 0x44620f02, 0xf811bf98, 0xf800cb01, 0xbf383b01, 0x3b01f811, + 0x0204f1a2, 0xf800bf98, 0xbf38cb01, 0x3b01f800, 0x0303f011, 0x8025f000, 0xf0c03a08, 0xf8518008, + 0x3a083b04, 0xcb04f851, 0x1008e8a0, 0x1d12e7f5, 0xf851bf5c, 0xf8403b04, 0xf3af3b04, 0x07d28000, + 0xf811bf24, 0xf8113b01, 0xbf48cb01, 0x2b01f811, 0xf800bf24, 0xf8003b01, 0xbf48cb01, 0x2b01f800, + 0xb5104770, 0xf0c03a20, 0xe8b1800b, 0x3a205018, 0x5018e8a0, 0x5018e8b1, 0x5018e8a0, 0xaff5f4bf, + 0x7c02ea5f, 0xe8b1bf24, 0xe8a05018, 0xbf445018, 0xc018c918, 0x4010e8bd, 0x7c82ea5f, 0xf851bf24, + 0xf8403b04, 0xbf083b04, 0x07d24770, 0xf831bf28, 0xbf483b02, 0x2b01f811, 0xf820bf28, 0xbf483b02, + 0x2b01f800, 0x00004770, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000035, + 'pc_unInit': 0x2000008f, + 'pc_program_page': 0x200000a7, + 'pc_erase_sector': 0x2000009d, + 'pc_eraseAll': 0x20000093, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000ae8, + 'begin_stack' : 0x200022f0, + 'end_stack' : 0x200012f0, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000af0, + 0x20000ef0 + ], + 'min_program_length' : 0x400, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0xae8, + 'rw_start': 0xaec, + 'rw_size': 0x4, + 'zi_start': 0xaf0, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x10000000, + 'flash_size': 0x100000, + 'sector_sizes': ( + (0x0, 0x2000), + ) +} + +class MAX32666(CoreSightTarget): + + VENDOR = "Maxim" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x10000000, length=0x100000, blocksize=0x2000, is_boot_memory=True, algo=FLASH_ALGO), + RamRegion( start=0x20000000, length=0x8C000), + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("max32665.svd") diff --git a/test/data/binaries/max32666fthr.bin b/test/data/binaries/max32666fthr.bin new file mode 100644 index 0000000000000000000000000000000000000000..77d971214ca0659144d7d27a88131bb478a22caf GIT binary patch literal 32776 zcmeFad3+Psy*GSjBw4a-KxT_E21c?0*=#Z)jUk&Po3SAf%#wt*v`BzqL;wo|iQ6=- zOi1c%jngcpZF*~Rn}+Td)Gajel}SiL(xjDG8nSSs^fvKAO2)!?Mv^VP-`_|ElG{G_ zd7sbc`Mm$U<};czXJ3Bjx1R&+G6_B%v)qek6rKV+6YxyJ!#?-7m}i!6XX8IaxF64B z`2PQ&|8M4i$-K(TEh%$bYY)rcTYZ1^&-*#!yNkI9FW;B?O)PixA9}{HaWXfiFqAB+ zk~v*r&A>Mp8-E{TmPMtZrV~xa5@%N#OGAzmj$_p!y_E0q*I?00SSg#%W>^;4Lruq$ z$YBpTj@5?pkUFiyDE}e;qaGb&vSFCXr&7~8r^@;<`JqoQngX9*%ndaA3RJ$BmCcWE z9j!fMEYX_I9#;1#N|fIEWKRxz!fguqYl=Lsqf=$e7)wOBwNMgdjum>$(b>K77>YH8 zX8*(TaIo&ZShxD@J9s86_>@Iko0!E?qK^tCeAH3G zqRx_MMftb-U+)onOx!7yeQ@-OF@GNO+L)Kdyyg^_h^xdei(_7!^5+WnQ!_iIuh@~x zPS#dTdyQtmCw_Wy{DT``^N8FMoqS{JsfkR;tqs&<9#-QBrIq1ys{6nHW2~TrSq!Dj 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zFGn8@Vo*%;y%RTO%Y#{lX3o~;Tp`&1yDa;^)0>yylSen^(ViTgbp{}x0GNHBLo5#L z$WIK6!3u2#&-Rc(+9bUbQIp7vnr-4JM{Q$=!zw~%*}>5GSZGw`xmlC4GcRm6uRLOQ z%`=QvY{If+t3G%up!Y*6+!7|p5WRKCDrOnSVVZXOCdS8M0k?b_P$s%HsaNT_fMIEZ{0XM;9}fgBHQ|S@?zxOx-tZMinRI;y|o;qq-HRDq&8X`qH%bf|J{#9z*l2i?77%}VABvp$)4u!)=p;ieL+BT>^;fOE-N;4Orf-h70X?1_cY(#sKAOr!jlywh|s0z?Ur z|6&}@1+ahJ89bLS$qY{t1gT`a0~qVno1i zN8spy)P>`R$ls2XmWTeougAk5Ys@55E(v%Ozyh!+FvSrE2DQjk2NwBKYyd!ISN(vE mP3vanx9Zvho_w;6DUXaY Date: Sun, 18 Jun 2023 15:23:00 -0500 Subject: [PATCH 03/25] board ids: add some missing ST and NXP board IDs (#1575) - Correct target type for NXP MIMXRT1160-EVK - Add NXP: MIMXRT1040-EVK, HANI-IOT (Arrow) - Add ST: 32F0308DISCOVERY, 32F072BDISCOVERY, 32F411EDISCOVERY, Avnet Silica ST Sensor Node, NUCLEO-L4A6ZG, 32F723EDISCOVERY, STM32H573I-DK, NUCLEO-H503RB, NUCLEO-WBA55CG, NUCLEO-U545RE-Q, NUCLEO-H755ZI-Q, NUCLEO-L412RB-P, NUCLEO-L412KB, STM32H745I-DISCO, STM32G071B-DISCO, STM32L562E-DK, STM32F7308-DK, STM32F7508-DK, DISCO-F750B, STM32H7B3I-DK, NUCLEO-H7A3ZI, NUCLEO-H7B3ZI, STM32L4P5G-DK, B-G474E-DPOW1, NUCLEO-L4P5ZG, NUCLEO-C031C6, STM32C0116-DK, STM32C0316-DK, NUCLEO-H723ZG, NUCLEO-G0B1RE, STM32H735G-DK, NUCLEO-U5A5ZJ-Q, NUCLEO-H563ZI, B-L462E-CELL1, STM32WL55C-DK, STM32WB5MM-DK, STM32U5A9J-DK, B-G473E-ZEST1S --- pyocd/board/board_ids.py | 45 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/pyocd/board/board_ids.py b/pyocd/board/board_ids.py index 30ce466ad..35b49b6f9 100644 --- a/pyocd/board/board_ids.py +++ b/pyocd/board/board_ids.py @@ -68,12 +68,13 @@ class BoardInfo(NamedTuple): "0243": BoardInfo( "MIMXRT1015-EVK", "mimxrt1015", "l1_mimxrt1015-evk.bin",), "0244": BoardInfo( "MIMXRT1170-EVK", "mimxrt1170_cm7", "l1_rt1170.bin", ), "0245": BoardInfo( "IBMEthernetKit", "k64f", "l1_k64f.bin" ), - "0246": BoardInfo( "MIMXRT1160-EVK", "mimxrt1166xxxxx", None, ), + "0246": BoardInfo( "MIMXRT1160-EVK", "mimxrt1166dvm6a", None, ), "0250": BoardInfo( "FRDM-KW24D512", "kw24d5", "l1_kw24d5.bin" ), "0251": BoardInfo( "FRDM-KW36", "kw36z4", "l1_kw36z.bin", ), "0252": BoardInfo( "FRDM-KW38", "kw38z4", None, ), "0253": BoardInfo( "USB-KW38", "kw38z4", None, ), "0254": BoardInfo( "KW38-ER-RD", "kw38z4", None, ), + "0255": BoardInfo( "MIMXRT1040-EVK", "mimxrt1042xjm5b", None, ), "0260": BoardInfo( "FRDM-KL26Z", "kl26z", "l1_kl26z.bin", ), "0261": BoardInfo( "FRDM-KL27Z", "kl27z4", "l1_kl27z.bin", ), "0262": BoardInfo( "FRDM-KL43Z", "kl43z4", "l1_kl26z.bin", ), @@ -95,6 +96,7 @@ class BoardInfo(NamedTuple): "0340": BoardInfo( "TWR-K80F150M", "mk80fn256vll15", None, ), "0341": BoardInfo( "FRDM-KV31F", "mkv31f512vll12", None, ), "0350": BoardInfo( "XDOT_L151CC", "stm32l151cctx", None ), + "0360": BoardInfo( "HANI-IOT", "lpc55s69", None ), "0400": BoardInfo( "MAXWSNENV", "max32600", "l1_maxwsnenv.bin", ), "0405": BoardInfo( "MAX32600MBED", "max32600", "l1_max32600mbed.bin", ), "0406": BoardInfo( "MAX32620MBED", "max32620", None ), @@ -121,10 +123,13 @@ class BoardInfo(NamedTuple): "0715": BoardInfo( "NUCLEO-L053R8", "stm32l053r8tx", "NUCLEO_L053R8.bin", ), "0720": BoardInfo( "NUCLEO-F401RE", "stm32f401retx", None, ), "0725": BoardInfo( "NUCLEO-F030R8", "stm32f030r8tx", None, ), + "0726": BoardInfo( "32F0308DISCOVERY", "stm32f030r8tx", None, ), "0729": BoardInfo( "NUCLEO-G071RB", "stm32g071rbtx", None, ), "0730": BoardInfo( "NUCLEO-F072RB", "stm32f072rbtx", "NUCLEO_F072RB.bin", ), + "0731": BoardInfo( "32F072BDISCOVERY", "stm32f072rbtx", None, ), "0735": BoardInfo( "NUCLEO-F334R8", "stm32f334r8tx", "NUCLEO_F334R8.bin", ), "0740": BoardInfo( "NUCLEO-F411RE", "stm32f411retx", "NUCLEO_F411RE.bin", ), + "0741": BoardInfo( "32F411EDISCOVERY", "stm32f411retx", None, ), "0742": BoardInfo( "NUCLEO-F413ZH", "stm32f413zhtx", None, ), "0743": BoardInfo( "DISCO-F413ZH", "stm32f413zhtx", None, ), "0744": BoardInfo( "NUCLEO-F410RB", "stm32f410rbtx", None, ), @@ -136,6 +141,7 @@ class BoardInfo(NamedTuple): "0760": BoardInfo( "NUCLEO-L073RZ", "stm32l073rztx", None, ), "0764": BoardInfo( "DISCO-L475VG-IOT01A", "stm32l475xg", "stm32l475vg_iot01a.bin",), "0765": BoardInfo( "NUCLEO-L476RG", "stm32l476rgtx", "NUCLEO_L476RG.bin", ), + "0766": BoardInfo( "Avnet Silica ST Sensor Node", "stm32f103cb", None, ), "0770": BoardInfo( "NUCLEO-L432KC", "stm32l432kcux", "NUCLEO_L432KC.bin", ), "0774": BoardInfo( "DISCO-L4R9I", "stm32l4r9aiix", None, ), "0775": BoardInfo( "NUCLEO-F303K8", "stm32f303k8tx", None, ), @@ -145,6 +151,7 @@ class BoardInfo(NamedTuple): "0779": BoardInfo( "NUCLEO-L433RC-P", "stm32l433rctx", None, ), "0780": BoardInfo( "NUCLEO-L011K4", "stm32l011k4tx", None, ), "0781": BoardInfo( "NUCLEO-L4R5ZI-P", "stm32l4r5zitx", None, ), + "0782": BoardInfo( "NUCLEO-L4A6ZG", "stm32l4a6zgtx", None, ), "0783": BoardInfo( "NUCLEO-L010RB", "stm32l010rbtx", None, ), "0785": BoardInfo( "NUCLEO-F042K6", "stm32f042k6tx", None, ), "0788": BoardInfo( "DISCO-F469NI", "stm32f469nihx", None, ), @@ -155,6 +162,7 @@ class BoardInfo(NamedTuple): "0797": BoardInfo( "NUCLEO-F439ZI", "stm32f439zitx", None, ), "0805": BoardInfo( "DISCO-L053C8", "stm32l053c8tx", None, ), "0810": BoardInfo( "DISCO-F334C8", "stm32f334c8tx", None, ), + "0811": BoardInfo( "32F723EDISCOVERY", "stm32f723iekx", None, ), "0812": BoardInfo( "NUCLEO-F722ZE", "stm32f722zetx", None, ), "0813": BoardInfo( "NUCLEO-H743ZI", "stm32h743zitx", None, ), "0814": BoardInfo( "DISCO-H747I", "stm32h747xihx", None, ), @@ -173,31 +181,60 @@ class BoardInfo(NamedTuple): "0828": BoardInfo( "NUCLEO-L496ZG-P", "stm32l496zgtx", None, ), "0829": BoardInfo( "NUCLEO-L452RE-P", "stm32l452retx", None, ), "0830": BoardInfo( "DISCO-F407VG", "stm32f407vgtx", None, ), + "0831": BoardInfo( "STM32H573I-DK", "stm32h573iitx", None, ), + "0832": BoardInfo( "NUCLEO-H503RB", "stm32h503rbt6", None, ), "0833": BoardInfo( "DISCO-L072CZ-LRWAN1", "stm32l072cztx", None, ), "0835": BoardInfo( "NUCLEO-F207ZG", "stm32f207zgtx", "NUCLEO_F207ZG.bin", ), "0836": BoardInfo( "NUCLEO-H743ZI2", "stm32h743zitx", None, ), + "0837": BoardInfo( "NUCLEO-WBA55CG", "stm32wba52cg", None, ), + "0838": BoardInfo( "NUCLEO-U545RE-Q", "stm32u545retxq", None, ), "0839": BoardInfo( "NUCLEO-WB55RG", "stm32wb55rgvx", None, ), "0840": BoardInfo( "B96B-F446VE", "stm32f446vetx", None, ), "0841": BoardInfo( "NUCLEO-G474RE", "stm32g474retx", None, ), "0842": BoardInfo( "NUCLEO-H753ZI", "stm32h753zitx", None, ), "0843": BoardInfo( "NUCLEO-H745ZI-Q", "stm32h745zitx", None, ), - "0847": BoardInfo( "DISCO-H745I", "stm32h745xihx", None, ), + "0844": BoardInfo( "NUCLEO-H755ZI-Q", "stm32h755zitx", None, ), + "0845": BoardInfo( "NUCLEO-L412RB-P", "stm32l412rbtxp", None, ), + "0846": BoardInfo( "NUCLEO-L412KB", "stm32l412kbtx", None, ), + "0847": BoardInfo( "STM32H745I-DISCO", "stm32h745xihx", None, ), + "0848": BoardInfo( "STM32G071B-DISCO", "stm32g071rbtx", None, ), "0849": BoardInfo( "NUCLEO-G070RB", "stm32g070rbtx", None, ), "0850": BoardInfo( "NUCLEO-G431RB", "stm32g431rbtx", None, ), "0851": BoardInfo( "NUCLEO-G431KB", "stm32g431kbtx", None, ), "0852": BoardInfo( "NUCLEO-G031K8", "stm32g031K8tx", None, ), "0853": BoardInfo( "NUCLEO-F301K8", "stm32f301k8tx", None, ), "0854": BoardInfo( "NUCLEO-L552ZE-Q", "stm32l552zetxq", None, ), - "0855": BoardInfo( "DISCO-L562QE", "stm32l562qeixq", None, ), + "0855": BoardInfo( "STM32L562E-DK", "stm32l562qeixq", None, ), + "0856": BoardInfo( "STM32F7308-DK", "stm32f730i8kx", None, ), + "0857": BoardInfo( "STM32F7508-DK", "stm32f750n8hx", None, ), + "0858": BoardInfo( "DISCO-F750B", "stm32f750n8hx", None, ), # not on st.com + "0859": BoardInfo( "STM32H7B3I-DK", "stm32h7b3lihxq", None, ), "0860": BoardInfo( "NUCLEO-H7A3ZI-Q", "stm32h7a3zitxq", None, ), + "0861": BoardInfo( "NUCLEO-H7A3ZI", "stm32h7a3zitx", None, ), + "0862": BoardInfo( "NUCLEO-H7B3ZI", "stm32h7b3zitx", None, ), + "0863": BoardInfo( "STM32L4P5G-DK", "stm32l4p5agix", None, ), + "0864": BoardInfo( "B-G474E-DPOW1", "stm32g474retx", None, ), + "0865": BoardInfo( "NUCLEO-L4P5ZG", "stm32l4p5zgtx", None, ), "0866": BoardInfo( "NUCLEO-WL55JC", "stm32wl55jcix", None, ), + "0867": BoardInfo( "NUCLEO-C031C6", "stm32c031c6tx", None, ), + "0868": BoardInfo( "STM32C0116-DK", "stm32c011f6ux", None, ), + "0869": BoardInfo( "STM32C0316-DK", "stm32c031c6tx", None, ), + "0871": BoardInfo( "NUCLEO-H723ZG", "stm32h723zgtx", None, ), + "0872": BoardInfo( "NUCLEO-G0B1RE", "stm32g0b1retx", None, ), + "0875": BoardInfo( "STM32H735G-DK", "stm32h735igtx", None, ), + "0877": BoardInfo( "NUCLEO-U5A5ZJ-Q", "stm32u5a5zjtxq", None, ), + "0878": BoardInfo( "NUCLEO-H563ZI", "stm32h563zitx", None, ), "0879": BoardInfo( "NUCLEO-F756ZG", "stm32f756zgtx", None, ), + "0880": BoardInfo( "B-L462E-CELL1", "stm32l462reyx", None, ), + "0881": BoardInfo( "STM32WL55C-DK", "stm32wl55ccux", None, ), "0882": BoardInfo( "NUCLEO-G491RE", "stm32g491retx", None, ), "0883": BoardInfo( "NUCLEO-WB15CC", "stm32wb15ccux", None, ), - "0884": BoardInfo( "DISCO-WB5MMG", "stm32wb5mmghx", None, ), + "0884": BoardInfo( "STM32WB5MM-DK", "stm32wb5mmghx", None, ), "0885": BoardInfo( "B-L4S5I-IOT01A", "stm32l4s5vitx", None, ), "0886": BoardInfo( "NUCLEO-U575ZI-Q", "stm32u575zitx", None, ), "0887": BoardInfo( "B-U585I-IOT02A", "stm32u585aiix", None, ), + "0888": BoardInfo( "STM32U5A9J-DK", "stm32u5a9njhxq", None, ), + "0889": BoardInfo( "B-G473E-ZEST1S", "stm32g473retx", None, ), # board not on st.com "1010": BoardInfo( "mbed NXP LPC1768", "lpc1768", "l1_lpc1768.bin", ), "1017": BoardInfo( "mbed HRM1017", "nrf51", "l1_nrf51.bin", ), "1018": BoardInfo( "Switch-Science-mbed-LPC824", "lpc824", "l1_lpc824.bin", ), From 56a299cf9a670d9166671e7d75b547f27f9c1bcf Mon Sep 17 00:00:00 2001 From: David van Rijn Date: Thu, 22 Jun 2023 18:33:38 +0200 Subject: [PATCH 04/25] targets: add stm32 h743 and h723 (#1567) * Added STM32H723 and STM32H743 builtin targets * Use shared minimal MEM-AP in STM32 targets when setting up targets during init. * gitignore for kdevelop --- .gitignore | 4 + pyocd/coresight/minimal_mem_ap.py | 44 +++ pyocd/target/builtin/__init__.py | 4 + pyocd/target/builtin/target_STM32F767xx.py | 29 +- pyocd/target/builtin/target_STM32H723xx.py | 272 +++++++++++++++++ pyocd/target/builtin/target_STM32H743xx.py | 326 +++++++++++++++++++++ 6 files changed, 651 insertions(+), 28 deletions(-) create mode 100644 pyocd/coresight/minimal_mem_ap.py create mode 100644 pyocd/target/builtin/target_STM32H723xx.py create mode 100644 pyocd/target/builtin/target_STM32H743xx.py diff --git a/.gitignore b/.gitignore index 5bea3323a..6be517cdd 100644 --- a/.gitignore +++ b/.gitignore @@ -92,3 +92,7 @@ pyocd_user.py # Mac .DS_Store +# kdevelop +.kdev4 +*.kdev4 +*.kate-swp diff --git a/pyocd/coresight/minimal_mem_ap.py b/pyocd/coresight/minimal_mem_ap.py new file mode 100644 index 000000000..6fe78f51f --- /dev/null +++ b/pyocd/coresight/minimal_mem_ap.py @@ -0,0 +1,44 @@ +# pyOCD debugger +# Copyright (c) 2023 David van Rijn +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +class MinimalMemAP: + """ + Minimalistic Access Port implementation. + This is used in some targets to access memory before the "real" AP's become available. + """ + AP0_CSW_ADDR = 0x00 + AP0_CSW_ADDR_VAL = 0x03000012 + AP0_TAR_ADDR = 0x04 + AP0_IDR_ADDR = 0xFC + AP0_DRW_ADDR = 0x0C + + def __init__(self, dp): + self.dp = dp + + def init(self): + # Init AP #0 + IDR = self.dp.read_ap(MinimalMemAP.AP0_IDR_ADDR) + # Check expected MEM-AP + assert IDR&0x0fffe00f == 0x04770001, f"Wrong IDR read from device: 0x{IDR:08x}" + self.dp.write_ap(MinimalMemAP.AP0_CSW_ADDR, MinimalMemAP.AP0_CSW_ADDR_VAL) + + def read32(self, addr): + self.dp.write_ap(MinimalMemAP.AP0_TAR_ADDR, addr) + return self.dp.read_ap(MinimalMemAP.AP0_DRW_ADDR) + + def write32(self, addr, val): + self.dp.write_ap(MinimalMemAP.AP0_TAR_ADDR, addr) + self.dp.write_ap(MinimalMemAP.AP0_DRW_ADDR, val) diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 5fc6e1c5b..90741c501 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -127,6 +127,8 @@ from . import target_ytm32b1le0 from . import target_ytm32b1me0 from . import target_ytm32b1md1 +from . import target_STM32H723xx +from . import target_STM32H743xx ## @brief Dictionary of all builtin targets. # @@ -209,6 +211,8 @@ 'stm32l475xe' : target_STM32L475xx.STM32L475xE, 'stm32l475xg' : target_STM32L475xx.STM32L475xG, 'stm32l031x6' : target_STM32L031x6.STM32L031x6, + 'stm32h723xx' : target_STM32H723xx.STM32H723xx, + 'stm32h743xx' : target_STM32H743xx.STM32H743xx, 'w7500': target_w7500.W7500, 's5js100': target_s5js100.S5JS100, 'lpc11xx_32': target_LPC1114FN28_102.LPC11XX_32, diff --git a/pyocd/target/builtin/target_STM32F767xx.py b/pyocd/target/builtin/target_STM32F767xx.py index 5ed532886..4e173d2ec 100644 --- a/pyocd/target/builtin/target_STM32F767xx.py +++ b/pyocd/target/builtin/target_STM32F767xx.py @@ -20,6 +20,7 @@ from ...coresight.coresight_target import CoreSightTarget from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) from ...coresight.cortex_m import CortexM +from ...coresight.minimal_mem_ap import MinimalMemAP as MiniAP LOG = logging.getLogger(__name__) @@ -27,34 +28,6 @@ class DBGMCU: CR = 0xE0042004 CR_VALUE = 0x7 # DBG_STANDBY | DBG_STOP | DBG_SLEEP - -class MiniAP(object): - """Minimalistic Access Port implementation.""" - AP0_CSW_ADDR = 0x00 - AP0_CSW_ADDR_VAL = 0x03000012 - AP0_TAR_ADDR = 0x04 - AP0_IDR_ADDR = 0xFC - AP0_DRW_ADDR = 0x0C - - def __init__(self, dp): - self.dp = dp - - def init(self): - # Init AP #0 - IDR = self.dp.read_ap(MiniAP.AP0_IDR_ADDR) - # Check expected MEM-AP - assert IDR == 0x74770001 - self.dp.write_ap(MiniAP.AP0_CSW_ADDR, MiniAP.AP0_CSW_ADDR_VAL) - - def read32(self, addr): - self.dp.write_ap(MiniAP.AP0_TAR_ADDR, addr) - return self.dp.read_ap(MiniAP.AP0_DRW_ADDR) - - def write32(self, addr, val): - self.dp.write_ap(MiniAP.AP0_TAR_ADDR, addr) - self.dp.write_ap(MiniAP.AP0_DRW_ADDR, val) - - FLASH_ALGO = { 'load_address' : 0x20000000, diff --git a/pyocd/target/builtin/target_STM32H723xx.py b/pyocd/target/builtin/target_STM32H723xx.py new file mode 100644 index 000000000..afcf6e874 --- /dev/null +++ b/pyocd/target/builtin/target_STM32H723xx.py @@ -0,0 +1,272 @@ +# pyOCD debugger +# Copyright (c) 2023 David van Rijn +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import time +import logging +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...coresight.cortex_m import CortexM +from ...coresight.minimal_mem_ap import MinimalMemAP as MiniAP + +LOG = logging.getLogger(__name__) + +class DBGMCU: + + # Via APB-ap (AP2) + #BASE = 0xe00e1000 + # via AHB-ap (AP0,1) + BASE = 0x5c001000 + + IDC = BASE + 0x000 + CR = BASE + 0x004 + CR_VALUE = (0x3f | # keep running in stop sleep and standby + 0x07 << 20 | # enable all debug components + 0x07 + ) + + ABP3 = BASE + 0x034 + +class FlashPeripheral: + def __init__(self): + self.flashaddr = 0x2000+0x12000000+0x40000000 + self.flash_keyr = self.flashaddr + 4 + self.flash_optkeyr = self.flashaddr + 8 + self.flash_optcr = self.flashaddr + 0x18 + self.flash_cr = self.flashaddr + 0xc + self.flash_sr = self.flashaddr + 0x10 + self.flash_optsr_cur = self.flashaddr + 0x1c + self.flash_optsr_prg = self.flashaddr + 0x20 + + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4603b510, 0x00def44f, 0x60e04c7f, 0x487ebf00, 0xf0006900, 0x28000004, 0x487cd1f9, 0x60604c7a, + 0x6060487b, 0xbd102000, 0x48774601, 0xf04068c0, 0x4a750001, 0x200060d0, 0xbf004770, 0x69004872, + 0x0001f000, 0xd1f92800, 0x486fbf00, 0xf0006900, 0x28000001, 0x486cd1f9, 0xf02068c0, 0x496a0030, + 0x460860c8, 0xf04068c0, 0x60c80008, 0x68c04608, 0x0080f040, 0xbf0060c8, 0x69004863, 0x0001f000, + 0xd1f92800, 0x68c04860, 0x0008f020, 0x60c8495e, 0x47702000, 0xf3c14601, 0xf1b14243, 0xd3376f00, + 0x6f01f1b1, 0xbf00d234, 0x69004857, 0x0004f000, 0xd1f92800, 0x68c04854, 0x60e0f420, 0x60d84b52, + 0x68c04618, 0x7330f647, 0x4b4f4398, 0x461860d8, 0x230468c0, 0x2302ea43, 0x4b4b4318, 0x461860d8, + 0xf04068c0, 0x60d80080, 0x4847bf00, 0xf0006900, 0x28000004, 0x4844d1f9, 0xf02068c0, 0x4b420004, + 0x461860d8, 0xf4006900, 0xb1080080, 0x47702001, 0xe7fc2000, 0x4603b5f0, 0x461c4616, 0x22004635, + 0x6f00f1b3, 0xf1b3d310, 0xd20d6f01, 0x4836bf00, 0xf0006900, 0x28000004, 0xbf00d1f9, 0x69004832, + 0x0001f000, 0xd1f92800, 0x00def44f, 0x60f84f2e, 0xf1b3e056, 0xd3536f00, 0x6f01f1b3, 0x482ad250, + 0xf64768c0, 0x43b87730, 0x60f84f27, 0x60f82002, 0xd30c2920, 0xe0062200, 0xf855686f, 0x60670b08, + 0x0b08f844, 0x2a041c52, 0x3920dbf6, 0x4620e017, 0x2200462f, 0xf817e004, 0xf800cb01, 0x1c52cb01, + 0xd3f8428a, 0xe0042200, 0x0cfff04f, 0xcb01f800, 0xf1c11c52, 0x45940c20, 0x2100d8f6, 0xbf00bf00, + 0x69004811, 0x0004f000, 0xd1f92800, 0x480ebf00, 0xf0006900, 0x28000001, 0x480bd1f9, 0xf4006900, + 0xb9683080, 0x6f00f1b3, 0xf1b3d308, 0xd2056f01, 0x68c04805, 0x0002f020, 0x60f84f03, 0xbdf02001, + 0xd1a62900, 0xe7fa2000, 0x52002000, 0x45670123, 0xcdef89ab, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x2000002d, + 'pc_program_page': 0x20000119, + 'pc_erase_sector': 0x20000099, + 'pc_eraseAll': 0x2000003f, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000214, + 'begin_stack' : 0x20001a20, + 'end_stack' : 0x20000a20, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000220, + 0x20000620 + ], + 'min_program_length' : 0x400, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x214, + 'rw_start': 0x218, + 'rw_size': 0x4, + 'zi_start': 0x21c, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x100000, + 'sector_sizes': ( + (0x0, 0x20000), + ) +} + + + +class STM32H723xx(CoreSightTarget): + + VENDOR = "STMicroelectronics" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x08000000, length=0x100000, sector_size=0x8000, + page_size=0x400, + is_boot_memory=True, + algo=FLASH_ALGO), + #ITCM + RamRegion( start=0x00000000, length=0x10000, + is_cachable=False, + access="rwx"), + #DTCM + RamRegion( start=0x20000000, length=0x20000, + is_cachable=False, + access="rw"), + #sram1 + RamRegion( start=0x30000000, length=0x4000, + is_powered_on_boot=False), + #sram2 + RamRegion( start=0x30004000, length=0x4000, + is_powered_on_boot=False), + #sram4 + RamRegion( start=0x38000000, length=0x4000), + ) + + + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + + def assert_reset_for_connect(self): + self.dp.assert_reset(1) + + def safe_reset_and_halt(self): + assert self.dp.is_reset_asserted() + + # At this point we can't access full AP as it is not initialized yet. + # Let's create a minimalistic AP and use it. + ap = MiniAP(self.dp) + ap.init() + + DEMCR_value = ap.read32(CortexM.DEMCR) + + # Halt on reset. + ap.write32(CortexM.DEMCR, + CortexM.DEMCR_VC_CORERESET | + CortexM.DEMCR_TRCENA + ) + ap.write32(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN) + + self.dp.assert_reset(0) + time.sleep(0.01) + + DEV_ID = ap.read32(DBGMCU.IDC) & 0xfff + assert DEV_ID == 0x483, f"IDC.DEV_ID 0x{DEV_ID:03x} did not match expected. 0x483" + ap.write32(DBGMCU.CR, DBGMCU.CR_VALUE) + + CR = ap.read32(DBGMCU.CR) + LOG.info("CR: 0x%08x", CR) + + # Restore DEMCR original value. + ap.write32(CortexM.DEMCR, DEMCR_value) + + def create_init_sequence(self): + # this was copied from target_STM32F767xx.py but seems to apply here as well + # + # STM32 under some low power/broken clock states doesn't allow AHP communication. + # Low power modes are quite popular on stm32 (including MBed OS defaults). + # 'attach' mode is broken by default, as STM32 can't be connected on low-power mode + # successfully without previous DBGMCU setup (It is not possible to write DBGMCU). + # It is also not possible to run full pyOCD discovery code under-reset. + # + # As a solution we can setup DBGMCU under reset, halt core and release reset. + # Unfortunately this code has to be executed _before_ discovery stage + # and without discovery stage we don't have access to AP/Core. + # As a solution we can create minimalistic AP implementation and use it + # to setup core halt. + # So the sequence for 'halt' connect mode will look like + # -> Assert reset + # -> Connect DebugPort + # -> Setup MiniAp + # -> Setup halt on reset + # -> Enable support for debugging in low-power modes + # -> Release reset + # -> [Core is halted and reset is released] + # -> Continue [discovery, create cores, etc] + seq = super().create_init_sequence() + if self.session.options.get('connect_mode') in ('halt', 'under-reset'): + seq.insert_before('dp_init', ('assert_reset_for_connect', self.assert_reset_for_connect)) + seq.insert_after('dp_init', ('safe_reset_and_halt', self.safe_reset_and_halt)) + + return seq + + def _unlock_flash_peripheral(self): + bank = FlashPeripheral() + LOG.info('unlocking flash peripheral') + self.reset_and_halt() + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + if self.read32(bank.flash_cr) & 1 != 0: + self.write32(bank.flash_keyr, 0x4567_0123) + self.write32(bank.flash_keyr, 0xCDEF_89AB) + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + if self.read32(bank.flash_optcr) & 1 != 0: + self.write32(bank.flash_optkeyr, 0x0819_2A3B) + self.write32(bank.flash_optkeyr, 0x4C5D_6E7F) + + + + def is_locked(self): + bank = FlashPeripheral() + optsr = self.read32(bank.flash_optsr_prg) + rdp = optsr & 0x0000_ff00 + if rdp == 0xaa: + return False; + if rdp == 0xcc: + LOG.warning("MCU permanently locked. No unlock possible") + return True + + def disable_read_protection(self): + bank = FlashPeripheral() + self._unlock_flash_peripheral() + + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + optsr = self.read32(bank.flash_optsr_prg) + self.write32(bank.flash_optsr_prg, optsr & 0xffff_00ff | 0x0000_aa00) + self.write32(bank.flash_optcr, 2) + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + self.reset_and_halt() + + def mass_erase(self): + bank = FlashPeripheral() + self._unlock_flash_peripheral() + + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + self.write32(bank.flash_cr, 1<<3 | 3<<4) + self.write32(bank.flash_cr, 1<<3 | 3<<4 | 1<<7) + LOG.info("mass_erase") + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + LOG.info("mass_erase done") + + + + + diff --git a/pyocd/target/builtin/target_STM32H743xx.py b/pyocd/target/builtin/target_STM32H743xx.py new file mode 100644 index 000000000..841c4c734 --- /dev/null +++ b/pyocd/target/builtin/target_STM32H743xx.py @@ -0,0 +1,326 @@ +# pyOCD debugger +# Copyright (c) 2023 David van Rijn +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import time +import logging +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...coresight.cortex_m import CortexM +from ...coresight.minimal_mem_ap import MinimalMemAP as MiniAP + +LOG = logging.getLogger(__name__) + +class DBGMCU: + + # Via APB-ap (AP2) + #BASE = 0xe00e1000 + # via AHB-ap (AP0,1) + BASE = 0x5c001000 + + IDC = BASE + 0x000 + CR = BASE + 0x004 + CR_VALUE = (0x3f | # keep running in stop sleep and standby + 0x07 << 20 | # enable all debug components + 0x07 + ) + + ABP3 = BASE + 0x034 + +class FlashPeripheral: + def __init__(self, bank=0): + assert bank < 2, "only two banks on this device" + + # only per-bank registers are offset + offset = 0x100 if bank == 1 else 0 + self.bank = bank + self.flashaddr = 0x2000+0x12000000+0x40000000 + self.flash_keyr = self.flashaddr + 0x04 + offset + self.flash_optkeyr = self.flashaddr + 0x08 + self.flash_optcr = self.flashaddr + 0x18 + self.flash_cr = self.flashaddr + 0x0c + offset + self.flash_sr = self.flashaddr + 0x10 + offset + self.flash_optsr_cur = self.flashaddr + 0x1c + offset + self.flash_optsr_prg = self.flashaddr + 0x20 + offset + + + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x8f4ff3bf, 0xf64a4770, 0x49fe20aa, 0x10406008, 0x20066008, 0x60081d09, 0x20aaf64a, 0x600849fa, + 0x60081040, 0x1d092006, 0xf2406008, 0x49f710ff, 0x207f6008, 0x60081f09, 0xb5104770, 0x460c4603, + 0xf44fb672, 0x49f27080, 0x20076008, 0x600849f1, 0x00def44f, 0xbf006148, 0x690048ee, 0x0004f000, + 0xd1f92800, 0x68c048eb, 0x0001f000, 0x48eab120, 0x604849e8, 0x604848e9, 0x00def44f, 0x600849e8, + 0x48e7bf00, 0x68001f00, 0x0004f000, 0xd1f82800, 0x380848e3, 0xf0006800, 0xb1380001, 0x49e048de, + 0x60083910, 0x49db48dd, 0x0104f8c1, 0xffabf7ff, 0x49d848dc, 0x49da6148, 0x20006008, 0x4601bd10, + 0x47702000, 0x49d348d8, 0xbf006148, 0x690048d1, 0x0004f000, 0xd1f92800, 0x49d148d3, 0xbf006008, + 0x1f0048cf, 0xf0006800, 0x28000004, 0xbf00d1f8, 0x690048c8, 0x0004f000, 0xd1f92800, 0x68c048c5, + 0x0030f020, 0x60c849c3, 0x68c04608, 0x0008f040, 0x460860c8, 0xf04068c0, 0x60c80080, 0x48bdbf00, + 0xf0006900, 0x28000004, 0x48bad1f9, 0xf02068c0, 0x49b80008, 0xbf0060c8, 0x1f0048b9, 0xf0006800, + 0x28000004, 0x48b6d1f8, 0x68003808, 0x0030f020, 0xf8c149b0, 0x4608010c, 0x010cf8d0, 0x0008f040, + 0x010cf8c1, 0xf8d04608, 0xf040010c, 0xf8c10080, 0xbf00010c, 0x1f0048aa, 0xf0006800, 0x28000004, + 0x48a7d1f8, 0x68003808, 0x0008f020, 0xf8c149a1, 0x2000010c, 0xb5704770, 0x461a4603, 0x3600f503, + 0xe0922400, 0x4543f3c2, 0x6f00f1b2, 0xf1b2d33f, 0xd23c6f01, 0x69404897, 0x310e499b, 0x49954308, + 0xe0016148, 0xff1ff7ff, 0x69004892, 0x0004f000, 0xd1f72800, 0x68c0488f, 0x7130f647, 0x498d4388, + 0xf04460c8, 0xea400004, 0xf0402005, 0x68c90030, 0x49884308, 0x460860c8, 0xf04068c0, 0x60c80080, + 0xf7ffe001, 0x4883ff00, 0xf0006900, 0x28000004, 0x4880d1f7, 0xf02068c0, 0x497e0004, 0x460860c8, + 0xf0006900, 0x28000001, 0x2001d04c, 0x487cbd70, 0x497d6800, 0x4308310e, 0xf8c14976, 0xe0010114, + 0xfee1f7ff, 0x1f004876, 0xf0006800, 0x28000004, 0x4873d1f6, 0x68003808, 0x7130f647, 0x496d4388, + 0x010cf8c1, 0x0104f044, 0x0008f1a5, 0x2000ea41, 0x0030f040, 0xf8d14967, 0x4308110c, 0xf8c14965, + 0x4608010c, 0x010cf8d0, 0x0080f040, 0x010cf8c1, 0xf7ffe001, 0x4862feb8, 0x68001f00, 0x0004f000, + 0xd1f62800, 0x3808485e, 0xf0206800, 0x49590004, 0x010cf8c1, 0x1f00485a, 0xf0006800, 0xb1080001, + 0xe7b32001, 0x3200f502, 0x42b2bf00, 0xaf6af67f, 0xe7ab2000, 0x4df7e92d, 0x46924605, 0x9c01462f, + 0x46d0463a, 0xf1b72300, 0xd30a6f00, 0x6f01f1b7, 0x4848d207, 0x494c6940, 0x4308310e, 0x61484945, + 0x4847e007, 0x49486800, 0x4308310e, 0xf8c14941, 0xe0ae0114, 0xfe77f7ff, 0x6f00f1b2, 0xf1b2d30a, + 0xd2076f01, 0x68c0483b, 0x7130f647, 0x49394388, 0xe00860c8, 0x3808483a, 0xf6476800, 0x43887130, + 0xf8c14934, 0xf1b2010c, 0xd3066f00, 0x6f01f1b2, 0x2032d203, 0x60c8492f, 0x2032e003, 0x39084930, + 0x2c206008, 0x2300d30f, 0xf8d8e009, 0xf8d81000, 0x60110004, 0xf1086050, 0x32080808, 0x2b041c5b, + 0x3c20dbf3, 0x4616e015, 0x230046c3, 0xf81be004, 0xf8060b01, 0x1c5b0b01, 0xd3f842a3, 0xe0032300, + 0xf80620ff, 0x1c5b0b01, 0x0020f1c4, 0xd8f74298, 0xf7ff2400, 0xf1b2fe25, 0xd30c6f00, 0x6f01f1b2, + 0xe001d209, 0xfe1ff7ff, 0x69004812, 0x0004f000, 0xd1f72800, 0xe001e009, 0xfe15f7ff, 0x1f004810, + 0xf0006800, 0x28000004, 0x480ad1f6, 0x20006900, 0xf1b2b358, 0xd31e6f00, 0x6f01f1b2, 0x4805d21b, + 0xe01368c0, 0x58004800, 0x58004c00, 0x40002c04, 0x580244d4, 0x52002000, 0x45670123, 0xcdef89ab, + 0x52002114, 0x0fee0000, 0x0fef0000, 0x0002f020, 0x60c84945, 0x4845e006, 0xf0206800, 0x49420002, + 0x010cf8c1, 0xe8bd2000, 0xf1b28dfe, 0xd3096f00, 0x6f01f1b2, 0x483cd206, 0xf02068c0, 0x493a0002, + 0xe00660c8, 0x68004839, 0x0002f020, 0xf8c14936, 0x2c00010c, 0xaf4ef47f, 0xe7e42000, 0x68004834, + 0x0001f040, 0x60084932, 0x30104831, 0x49316800, 0x492f4008, 0x60083110, 0x6800482d, 0x4008492e, + 0x6008492b, 0x68004608, 0x2080f420, 0x48286008, 0x68003010, 0x00fef420, 0x31104925, 0x20006008, + 0x31604923, 0x48226008, 0xf0206800, 0x49200018, 0x481f6008, 0x68003010, 0x3110491d, 0x46086008, + 0x60086800, 0x68004608, 0x7000f440, 0x05c86008, 0x6008491a, 0xb5004770, 0xf7ff2200, 0x4812fd84, + 0xe0016902, 0x69024810, 0x0001f002, 0xd1f92800, 0x1d00480e, 0xe0026802, 0x1d00480c, 0xf0026802, + 0x28000001, 0x4808d1f8, 0xe00168c2, 0x68c24806, 0x28002000, 0x4805d1fa, 0xe0016802, 0x68024803, + 0x28002000, 0xbd00d1fa, 0x52002000, 0x5200210c, 0x58024400, 0xf87fc00c, 0xfef6ffff, 0xe000ed08, + 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x2000003f, + 'pc_unInit': 0x200000c3, + 'pc_program_page': 0x200002d9, + 'pc_erase_sector': 0x2000019b, + 'pc_eraseAll': 0x200000c9, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000560, + 'begin_stack' : 0x20001d70, + 'end_stack' : 0x20000d70, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000570, + 0x20000970 + ], + 'min_program_length' : 0x400, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x560, + 'rw_start': 0x564, + 'rw_size': 0x4, + 'zi_start': 0x568, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x200000, + 'sector_sizes': ( + (0x0, 0x2000), + ) +} + + +class STM32H743xx(CoreSightTarget): + + VENDOR = "STMicroelectronics" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x0800_0000, length=0x10_0000, sector_size=0x8000, + page_size=0x400, + is_boot_memory=True, + algo=FLASH_ALGO), + + FlashRegion( start=0x0810_0000, length=0x10_0000, sector_size=0x8000, + page_size=0x400, + algo=FLASH_ALGO), + #ITCM + RamRegion( start=0x00000000, length=0x10000, + is_cachable=False, + access="rwx"), + #DTCM + RamRegion( start=0x20000000, length=0x20000, + is_cachable=False, + access="rw"), + #sram1 + RamRegion( start=0x30000000, length=0x20000, + is_powered_on_boot=False), + #sram2 + RamRegion( start=0x30020000, length=0x20000, + is_powered_on_boot=False), + + #sram3 + RamRegion( start=0x30040000, length=0x8000, + is_powered_on_boot=False), + #sram4 + RamRegion( start=0x38000000, length=0x10000), + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + + def assert_reset_for_connect(self): + self.dp.assert_reset(1) + + def safe_reset_and_halt(self): + assert self.dp.is_reset_asserted() + + # At this point we can't access full AP as it is not initialized yet. + # Let's create a minimalistic AP and use it. + ap = MiniAP(self.dp) + ap.init() + + DEMCR_value = ap.read32(CortexM.DEMCR) + + # Halt on reset. + ap.write32(CortexM.DEMCR, + CortexM.DEMCR_VC_CORERESET | + CortexM.DEMCR_TRCENA + ) + ap.write32(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN) + + self.dp.assert_reset(0) + time.sleep(0.01) + + DEV_ID = ap.read32(DBGMCU.IDC) & 0xfff + assert DEV_ID == 0x450, f"IDC.DEV_ID 0x{DEV_ID:03x} did not match expected. 0x450" + ap.write32(DBGMCU.CR, DBGMCU.CR_VALUE) + + CR = ap.read32(DBGMCU.CR) + LOG.info("CR: 0x%08x", CR) + + # Restore DEMCR original value. + ap.write32(CortexM.DEMCR, DEMCR_value) + + def create_init_sequence(self): + # this was copied from target_STM32F767xx.py but seems to apply here as well + # + # STM32 under some low power/broken clock states doesn't allow AHP communication. + # Low power modes are quite popular on stm32 (including MBed OS defaults). + # 'attach' mode is broken by default, as STM32 can't be connected on low-power mode + # successfully without previous DBGMCU setup (It is not possible to write DBGMCU). + # It is also not possible to run full pyOCD discovery code under-reset. + # + # As a solution we can setup DBGMCU under reset, halt core and release reset. + # Unfortunately this code has to be executed _before_ discovery stage + # and without discovery stage we don't have access to AP/Core. + # As a solution we can create minimalistic AP implementation and use it + # to setup core halt. + # So the sequence for 'halt' connect mode will look like + # -> Assert reset + # -> Connect DebugPort + # -> Setup MiniAp + # -> Setup halt on reset + # -> Enable support for debugging in low-power modes + # -> Release reset + # -> [Core is halted and reset is released] + # -> Continue [discovery, create cores, etc] + seq = super().create_init_sequence() + if self.session.options.get('connect_mode') in ('halt', 'under-reset'): + seq.insert_before('dp_init', ('assert_reset_for_connect', self.assert_reset_for_connect)) + seq.insert_after('dp_init', ('safe_reset_and_halt', self.safe_reset_and_halt)) + + return seq + + def _unlock_flash_peripheral(self, flash_banks=[0,1]): + + banks = [FlashPeripheral(n) for n in flash_banks] + + LOG.info('unlocking flash peripheral') + self.reset_and_halt() + + for bank in banks: + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + if self.read32(bank.flash_cr) & 1 != 0: + self.write32(bank.flash_keyr, 0x4567_0123) + self.write32(bank.flash_keyr, 0xCDEF_89AB) + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + # shared, so only once + if self.read32(bank.flash_optcr) & 1 != 0: + self.write32(bank.flash_optkeyr, 0x0819_2A3B) + self.write32(bank.flash_optkeyr, 0x4C5D_6E7F) + + + def is_locked(self, flash_banks=[0,1]): + banks = [FlashPeripheral(n) for n in flash_banks] + + # return true if either bank + for bank in banks: + optsr = self.read32(bank.flash_optsr_prg) + rdp = optsr & 0x0000_ff00 + if rdp == 0xcc: + LOG.warning(f"BANK {bank.bank} permanently locked. No unlock possible") + if rdp != 0xaa: + return True + return False + + def disable_read_protection(self, flash_banks=[0,1]): + self._unlock_flash_peripheral(flash_banks) + banks = [FlashPeripheral(n) for n in flash_banks] + + for bank in banks: + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + optsr = self.read32(bank.flash_optsr_prg) + self.write32(bank.flash_optsr_prg, optsr & 0xffff_00ff | 0x0000_aa00) + + # on trigger on both changes + self.write32(bank.flash_optcr, 2) + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + self.reset_and_halt() + + def mass_erase(self, flash_banks=[0,1]): + self._unlock_flash_peripheral(flash_banks) + banks = [FlashPeripheral(n) for n in flash_banks] + + for bank in banks: + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + + self.write32(bank.flash_cr, 1<<3 | 3<<4) + self.write32(bank.flash_cr, 1<<3 | 3<<4 | 1<<7) + LOG.info("mass_erase banks %i", bank.bank) + + # banks can be erased at the same time + # so start both, + # then wait for both + for bank in banks: + while self.read32(bank.flash_sr) & 1: + time.sleep(0.1) + LOG.info("mass_erase bank %i done", bank.bank) + + + From 327e22c3f48eb58b89295af860a3012d4837c370 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Thu, 13 Apr 2023 13:37:54 +0200 Subject: [PATCH 05/25] family: nRF91: fix unlock exception Signed-off-by: Maximilian Deubel --- pyocd/target/family/target_nRF91.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyocd/target/family/target_nRF91.py b/pyocd/target/family/target_nRF91.py index aa77fd22a..c170c6399 100644 --- a/pyocd/target/family/target_nRF91.py +++ b/pyocd/target/family/target_nRF91.py @@ -157,7 +157,7 @@ def check_flash_security(self): # Do the mass erase. if not self.mass_erase(): LOG.error("%s: mass erase failed", self.part_number) - raise exceptions.TargetErrors.TargetError("unable to unlock device") + raise exceptions.TargetError("unable to unlock device") # Target needs to be reset to clear protection status self.session.probe.reset() self.pre_connect() From 1fea6d5eb57f53ba42bdd8cb2074cc98a22c6fa9 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Fri, 21 Apr 2023 10:26:51 +0200 Subject: [PATCH 06/25] family: nRF91: add support for hardened APPROTECT --- pyocd/target/family/target_nRF91.py | 277 +++++++++++++++++++++++++++- 1 file changed, 267 insertions(+), 10 deletions(-) diff --git a/pyocd/target/family/target_nRF91.py b/pyocd/target/family/target_nRF91.py index c170c6399..e798371e0 100644 --- a/pyocd/target/family/target_nRF91.py +++ b/pyocd/target/family/target_nRF91.py @@ -79,6 +79,199 @@ IPC_PIPELINED_MAX_BUFFER_SIZE = 0xE000 IPC_MAX_BUFFER_SIZE = 0x10000 +CSW_DEVICEEN = 0x00000040 + +# just an empty program compiled with the Nordic MDK without ENABLE_APPROTECT set +nrf91_empty_image = [ + 0x00, 0xe0, 0x03, 0x20, 0xe1, 0x04, 0x00, 0x00, 0x09, 0x05, 0x00, 0x00, 0x0b, 0x05, 0x00, 0x00, \ + 0x0d, 0x05, 0x00, 0x00, 0x0f, 0x05, 0x00, 0x00, 0x11, 0x05, 0x00, 0x00, 0x13, 0x05, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x05, 0x00, 0x00, \ + 0x17, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x05, 0x00, 0x00, 0x1b, 0x05, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x1d, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x10, 0xb5, 0x05, 0x4c, 0x23, 0x78, 0x33, 0xb9, 0x04, 0x4b, 0x13, 0xb1, \ + 0x04, 0x48, 0x00, 0xe0, 0x00, 0xbf, 0x01, 0x23, 0x23, 0x70, 0x10, 0xbd, 0x3c, 0x04, 0x00, 0x20, \ + 0x00, 0x00, 0x00, 0x00, 0x44, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, 0x1b, 0xb1, 0x03, 0x49, \ + 0x03, 0x48, 0x00, 0xe0, 0x00, 0xbf, 0x08, 0xbd, 0x00, 0x00, 0x00, 0x00, 0x40, 0x04, 0x00, 0x20, \ + 0x44, 0x07, 0x00, 0x00, 0xa3, 0xf5, 0x80, 0x3a, 0x70, 0x47, 0x00, 0xbf, 0x17, 0x4b, 0x00, 0x2b, \ + 0x08, 0xbf, 0x13, 0x4b, 0x9d, 0x46, 0xff, 0xf7, 0xf5, 0xff, 0x00, 0x21, 0x8b, 0x46, 0x0f, 0x46, \ + 0x13, 0x48, 0x14, 0x4a, 0x12, 0x1a, 0x00, 0xf0, 0x5f, 0xf8, 0x0e, 0x4b, 0x00, 0x2b, 0x00, 0xd0, \ + 0x98, 0x47, 0x0d, 0x4b, 0x00, 0x2b, 0x00, 0xd0, 0x98, 0x47, 0x00, 0x20, 0x00, 0x21, 0x04, 0x00, \ + 0x0d, 0x00, 0x0d, 0x48, 0x00, 0x28, 0x02, 0xd0, 0x0c, 0x48, 0x00, 0xf0, 0x0d, 0xf9, 0x00, 0xf0, \ + 0x27, 0xf8, 0x20, 0x00, 0x29, 0x00, 0x00, 0xf0, 0x71, 0xf9, 0x00, 0xf0, 0x11, 0xf8, 0x00, 0xbf, \ + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x58, 0x04, 0x00, 0x20, 0x00, 0x90, 0xd0, 0x03, 0x1d, 0x03, 0x00, 0x00, 0x79, 0x01, 0x00, 0x00, \ + 0x55, 0x01, 0x00, 0x00 +] + LOG = logging.getLogger(__name__) @@ -116,6 +309,7 @@ class NRF91(CoreSightTarget): def __init__(self, session, memory_map=None): super(NRF91, self).__init__(session, memory_map) self.ctrl_ap = None + self.was_locked = False def create_init_sequence(self): seq = super(NRF91, self).create_init_sequence() @@ -128,7 +322,11 @@ def create_init_sequence(self): ('check_flash_security', self.check_flash_security), ) ) - + seq.wrap_task('discovery', + lambda seq: seq.insert_after('create_cores', + ('persist_unlock', self.persist_unlock), + ) + ) seq.insert_before('post_connect_hook', ('check_part_info', self.check_part_info)) @@ -141,6 +339,24 @@ def check_ctrl_ap_idr(self): if self.ctrl_ap.idr != CTRL_IDR_EXPECTED: LOG.error("%s: bad CTRL-AP IDR (is 0x%08x)", self.part_number, self.ctrl_ap.idr) + def ap_is_enabled(self): + csw = self.dp.read_ap(AHB_AP_NUM << 24) + return csw & CSW_DEVICEEN + + def persist_unlock(self): + if self.session.options.get('auto_unlock') and self.has_hardened_approtect: + # Write Unprotected to UICR.APPROTECT + self.write_uicr(0x00FF8000, 0x50FA50FA) + + # Write Unprotected to UICR.SECUREAPPROTECT + self.write_uicr(0x00FF802C, 0x50FA50FA) + + if self.session.options.get('auto_unlock') and self.has_hardened_approtect and self.was_locked: + # write unlock image + self.write_flash(0, nrf91_empty_image) + + self.reset() + def check_flash_security(self): """@brief Check security and unlock device. @@ -150,18 +366,40 @@ def check_flash_security(self): This init task runs *before* cores are created. """ + target_id = self.dp.read_dp(0x24) + if target_id & 0xFFF != 0x289: + LOG.error(f"This doesn't look like a Nordic Semiconductor device!") + if target_id & 0xF0000 != 0x90000: + LOG.error(f"This doesn't look like an nRF91 devcice!") + revision = target_id >> 28 + self.has_hardened_approtect = revision > 2 + if self.is_locked(): + self.was_locked = True if self.session.options.get('auto_unlock'): LOG.warning("%s APPROTECT enabled: will try to unlock via mass erase", self.part_number) - # Do the mass erase. - if not self.mass_erase(): - LOG.error("%s: mass erase failed", self.part_number) + unlock_successful = False + for _ in range(3): + # Do the mass erase. + if not self.mass_erase(): + continue + + if not self.has_hardened_approtect: + # pin reset is needed for older versions + self.session.probe.reset() + self.pre_connect() + self.dp.connect() + + # Check if AP was enabled + if self.ap_is_enabled(): + unlock_successful = True + break + else: + LOG.debug("unlock was not successful, retrying") + + if not unlock_successful: raise exceptions.TargetError("unable to unlock device") - # Target needs to be reset to clear protection status - self.session.probe.reset() - self.pre_connect() - self.dp.connect() self._discoverer._create_1_ap(AHB_AP_NUM) self._discoverer._create_1_ap(APB_AP_NUM) else: @@ -199,14 +437,15 @@ def mass_erase(self): status = self.ctrl_ap.read_reg(CTRL_AP_ERASEALLSTATUS) if status == CTRL_AP_ERASEALLSTATUS_READY: break - sleep(0.1) + sleep(0.5) else: # Timed out LOG.error("Mass erase timeout waiting for ERASEALLSTATUS") return False + sleep(0.01) self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_RESET) self.ctrl_ap.write_reg(CTRL_AP_RESET, CTRL_AP_RESET_NORESET) - self.ctrl_ap.write_reg(CTRL_AP_ERASEALL, CTRL_AP_ERASEALL_NOOPERATION) + sleep(0.2) return True def check_part_info(self): @@ -230,6 +469,16 @@ def write_uicr(self, addr: int, value: int): self.write32(0x50039504, 0) # NVMC.CONFIG = ReadOnly self._wait_nvmc_ready() + def write_flash(self, addr: int, bytes): + assert len(bytes) % 4 == 0, "only full words can be written" + self.write32(0x50039504, 1) # NVMC.CONFIG = WriteEnable + self._wait_nvmc_ready() + for off in range(0, len(bytes), 4): + self.write32(addr+off, bytes_to_word(bytes[off:off+4])) + self._wait_nvmc_readynext() + self.write32(0x50039504, 0) # NVMC.CONFIG = ReadOnly + self._wait_nvmc_ready() + def _wait_nvmc_ready(self): with Timeout(MASS_ERASE_TIMEOUT) as to: while to.check(): @@ -237,6 +486,14 @@ def _wait_nvmc_ready(self): break else: raise exceptions.TargetError("wait for NVMC timed out") + + def _wait_nvmc_readynext(self): + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + if self.read32(0x50039408) != 0x00000000: # NVMC.READYNEXT != BUSY + break + else: + raise exceptions.TargetError("wait for NVMC timed out") class ModemUpdater(object): """@brief Implements the nRF91 Modem Update procedure like described in nAN-41""" From ec3401025759155798523a61eaaea6539a909a14 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Mon, 24 Apr 2023 17:01:26 +0200 Subject: [PATCH 07/25] family: nRF91: add UICR flashing support and builtin algos Signed-off-by: Maximilian Deubel --- docs/builtin-targets.md | 5 + pyocd/core/memory_map.py | 1 + pyocd/debug/svd/data/nrf9160.svd | 35433 +++++++++++++++++++++++ pyocd/flash/builder.py | 36 +- pyocd/target/builtin/__init__.py | 2 + pyocd/target/builtin/target_nRF91xx.py | 225 + 6 files changed, 35686 insertions(+), 16 deletions(-) create mode 100644 pyocd/debug/svd/data/nrf9160.svd create mode 100644 pyocd/target/builtin/target_nRF91xx.py diff --git a/docs/builtin-targets.md b/docs/builtin-targets.md index 3e7515034..c18ce7dad 100644 --- a/docs/builtin-targets.md +++ b/docs/builtin-targets.md @@ -666,6 +666,11 @@ title: Built-in targets NRF52840 + nrf91 + Nordic Semiconductor + NRF9160 + + rp2040 Raspberry Pi RP2040Core0 diff --git a/pyocd/core/memory_map.py b/pyocd/core/memory_map.py index 7bc4a2258..d42d54c85 100644 --- a/pyocd/core/memory_map.py +++ b/pyocd/core/memory_map.py @@ -260,6 +260,7 @@ class MemoryRegion(MemoryRangeBase): 'is_readable': lambda r: 'r' in r.access, 'is_writable': lambda r: 'w' in r.access, 'is_executable': lambda r: 'x' in r.access, + 'is_erasable' : True, 'is_secure': lambda r: 's' in r.access, 'is_nonsecure': lambda r: not r.is_secure, } diff --git a/pyocd/debug/svd/data/nrf9160.svd b/pyocd/debug/svd/data/nrf9160.svd new file mode 100644 index 000000000..2195ec3d7 --- /dev/null +++ b/pyocd/debug/svd/data/nrf9160.svd @@ -0,0 +1,35433 @@ + + + + Nordic Semiconductor + Nordic + nrf9160 + nrf91 + 1 + nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller + +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 69 + 0 + + system_nrf91 + + 240 + + + + FICR_S + Factory Information Configuration Registers + 0x00FF0000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x140 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + + + PARTNO + 0 + 31 + + + 9160 + Device is an nRF9160 sip + 0x00009160 + + + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0x000000FF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0x000000FF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x200 + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + RAM + RAM variant + 0x018 + read-only + 0x00000100 + + + RAM + RAM variant + 0 + 31 + + + K256 + 256 kByte RAM + 0x100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x01C + read-only + 0x00000400 + + + FLASH + Flash variant + 0 + 31 + + + K1024 + 1 MByte FLASH + 0x400 + + + + + + + CODEPAGESIZE + Code memory page size + 0x020 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x024 + read-only + 0x00000100 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + DEVICETYPE + Device type + 0x028 + read-only + 0xFFFFFFFF + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x0000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + 256 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x300 + + ADDR + Description cluster: Address + 0x000 + read-only + 0xFFFFFFFF + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data + 0x004 + read-only + 0xFFFFFFFF + + + Data + Data + 0 + 31 + + + + + + TRNG90B + NIST800-90B RNG calibration data + FICR_TRNG90B + read-write + 0xC00 + + BYTES + Amount of bytes for the required entropy bits + 0x000 + read-only + 0xFFFFFFFF + + + BYTES + Amount of bytes for the required entropy bits + 0 + 31 + + + + + RCCUTOFF + Repetition counter cutoff + 0x004 + read-only + 0xFFFFFFFF + + + RCCUTOFF + Repetition counter cutoff + 0 + 31 + + + + + APCUTOFF + Adaptive proportion cutoff + 0x008 + read-only + 0xFFFFFFFF + + + APCUTOFF + Adaptive proportion cutoff + 0 + 31 + + + + + STARTUP + Amount of bytes for the startup tests + 0x00C + read-only + 0xFFFFFFFF + + + STARTUP + Amount of bytes for the startup tests + 0 + 31 + + + + + ROSC1 + Sample count for ring oscillator 1 + 0x010 + read-only + 0xFFFFFFFF + + + ROSC1 + Sample count for ring oscillator 1 + 0 + 31 + + + + + ROSC2 + Sample count for ring oscillator 2 + 0x014 + read-only + 0xFFFFFFFF + + + ROSC2 + Sample count for ring oscillator 2 + 0 + 31 + + + + + ROSC3 + Sample count for ring oscillator 3 + 0x018 + read-only + 0xFFFFFFFF + + + ROSC3 + Sample count for ring oscillator 3 + 0 + 31 + + + + + ROSC4 + Sample count for ring oscillator 4 + 0x01C + read-only + 0xFFFFFFFF + + + ROSC4 + Sample count for ring oscillator 4 + 0 + 31 + + + + + + + + UICR_S + User information configuration registers User information configuration registers + 0x00FF8000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + APPROTECT + Access port protection + 0x000 + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all CPU registers and + memory mapped addresses + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + XOSC32M + Oscillator control + 0x014 + read-write + 0xFFFFFFCF + + + CTRL + Pierce current DAC control signals + 0 + 5 + + + + + HFXOSRC + HFXO clock source selection + 0x01C + read-write + 0xFFFFFFFF + + + HFXOSRC + HFXO clock source selection + 0 + 0 + + + XTAL + 32 MHz crystal oscillator + 1 + + + TCXO + 32 MHz temperature compensated crystal oscillator (TCXO) + 0 + + + + + + + HFXOCNT + HFXO startup counter + 0x020 + read-write + 0xFFFFFFFF + + + HFXOCNT + HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us + 0 + 7 + + + MinDebounceTime + Min debounce time = (0*64 us + 0.5 us) + 0 + + + MaxDebounceTime + Max debounce time = (255*64 us + 0.5 us) + 255 + + + + + + + APPNVMCPOFGUARD + Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . + 0x024 + read-write + 0xFFFFFFFF + + + NVMCPOFGUARDEN + Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition + 0 + 0 + + + Disabled + NVM WRITE and NVM ERASE are not blocked in POFWARN condition + 0 + + + Enabled + NVM WRITE and NVM ERASE are blocked in POFWARN condition + 1 + + + + + + + SECUREAPPROTECT + Secure access port protection + 0x02C + read-write + 0x00000000 + + + PALL + Blocks debugger read/write access to all secure CPU registers and secure + memory mapped addresses + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + ERASEPROTECT + Erase protection + 0x030 + read-write + 0x00000000 + + + PALL + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality + 0 + 31 + + + Unprotected + Unprotected + 0xFFFFFFFF + + + Protected + Protected + 0x00000000 + + + + + + + 0xBE + 0x4 + OTP[%s] + Description collection: One time programmable memory + 0x108 + read-write + 0xFFFFFFFF + + + LOWER + Lower half word + 0 + 15 + read-writeonce + + + UPPER + Upper half word + 16 + 31 + read-writeonce + + + + + KEYSLOT + Unspecified + UICR_KEYSLOT + read-write + 0x400 + + 128 + 0x008 + CONFIG[%s] + Unspecified + UICR_KEYSLOT_CONFIG + read-write + 0x000 + + DEST + Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) + will be pushed by KMU. Note that this address must match that of a peripherals + APB mapped write-only key registers, else the KMU can push this key value into + an address range which the CPU can potentially read. + 0x000 + read-write + 0xFFFFFFFF + + + DEST + Secure APB destination address + 0 + 31 + + + + + PERM + Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. + 0x004 + read-write + 0xFFFFFFFF + + + WRITE + Write permission for key slot + 0 + 0 + + + Disabled + Disable write to the key value registers + 0 + + + Enabled + Enable write to the key value registers + 1 + + + + + READ + Read permission for key slot + 1 + 1 + + + Disabled + Disable read from key value registers + 0 + + + Enabled + Enable read from key value registers + 1 + + + + + PUSH + Push permission for key slot + 2 + 2 + + + Disabled + Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled + 0 + + + Enabled + Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! + 1 + + + + + STATE + Revocation state for the key slot + 16 + 16 + + + Revoked + Key value registers can no longer be read or pushed + 0 + + + Active + Key value registers are readable (if enabled) and can be pushed (if enabled) + 1 + + + + + + + + 128 + 0x010 + KEY[%s] + Unspecified + UICR_KEYSLOT_KEY + read-write + 0x400 + + 0x4 + 0x4 + VALUE[%s] + Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. + 0x000 + read-write + 0xFFFFFFFF + + + VALUE + Define bits [31+o*32:0+o*32] of value assigned to KMU key slot + 0 + 31 + + + + + + + + + TAD_S + Trace and debug control + 0xE0080000 + TAD + + + + 0 + 0x1000 + registers + + TAD + 0x20 + + + TASKS_CLOCKSTART + Start all trace and debug clocks. + 0x000 + write-only + + + TASKS_CLOCKSTART + Start all trace and debug clocks. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLOCKSTOP + Stop all trace and debug clocks. + 0x004 + write-only + + + TASKS_CLOCKSTOP + Stop all trace and debug clocks. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + ENABLE + Enable debug domain and aquire selected GPIOs + 0x500 + read-write + + + ENABLE + 0 + 0 + + + DISABLED + Disable debug domain and release selected GPIOs + 0 + + + ENABLED + Enable debug domain and aquire selected GPIOs + 1 + + + + + + + PSEL + Unspecified + TAD_PSEL + read-write + 0x504 + + TRACECLK + Pin configuration for TRACECLK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Traceclk + TRACECLK pin + 21 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA0 + Pin configuration for TRACEDATA[0] + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata0 + TRACEDATA0 pin + 22 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA1 + Pin configuration for TRACEDATA[1] + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata1 + TRACEDATA1 pin + 23 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA2 + Pin configuration for TRACEDATA[2] + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata2 + TRACEDATA2 pin + 24 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TRACEDATA3 + Pin configuration for TRACEDATA[3] + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + Tracedata3 + TRACEDATA3 pin + 25 + + + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + TRACEPORTSPEED + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components + 0x518 + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. + 0 + 1 + + + 32MHz + Trace Port clock is: 32MHz + 0 + + + 16MHz + Trace Port clock is: 16MHz + 1 + + + 8MHz + Trace Port clock is: 8MHz + 2 + + + 4MHz + Trace Port clock is: 4MHz + 3 + + + + + + + + + SPU_S + System protection unit + 0x50003000 + SPU + + + + 0 + 0x1000 + registers + + + SPU + 3 + + SPU + 0x20 + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0x100 + read-write + + + EVENTS_RAMACCERR + A security violation has been detected for the RAM memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0x104 + read-write + + + EVENTS_FLASHACCERR + A security violation has been detected for the flash memory space + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x108 + read-write + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RAMACCERR + Publish configuration for event RAMACCERR + 0x180 + read-write + + + CHIDX + DPPI channel that event RAMACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_FLASHACCERR + Publish configuration for event FLASHACCERR + 0x184 + read-write + + + CHIDX + DPPI channel that event FLASHACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PERIPHACCERR + Publish configuration for event PERIPHACCERR + 0x188 + read-write + + + CHIDX + DPPI channel that event PERIPHACCERR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RAMACCERR + Enable or disable interrupt for event RAMACCERR + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FLASHACCERR + Enable or disable interrupt for event FLASHACCERR + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RAMACCERR + Write '1' to enable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FLASHACCERR + Write '1' to enable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RAMACCERR + Write '1' to disable interrupt for event RAMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FLASHACCERR + Write '1' to disable interrupt for event FLASHACCERR + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CAP + Show implemented features for the current device + 0x400 + read-only + 0x00000001 + + + TZM + Show ARM TrustZone status + 0 + 0 + + + NotAvailable + ARM TrustZone support not available + 0 + + + Enabled + ARM TrustZone support is available + 1 + + + + + + + 1 + 0x004 + EXTDOMAIN[%s] + Unspecified + SPU_EXTDOMAIN + read-write + 0x440 + + PERM + Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n + 0x000 + read-write + 0x00000000 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + The bus access from this external domain always have the non-secure attribute set + 0 + + + Secure + The bus access from this external domain always have the secure attribute set + 1 + + + UserSelectable + Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + NonSecure + Bus accesses from this domain have the non-secure attribute set + 0 + + + Secure + Bus accesses from this domain have secure attribute set + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 1 + 0x008 + DPPI[%s] + Unspecified + SPU_DPPI + read-write + 0x480 + + PERM + Description cluster: Select between secure and non-secure attribute for the DPPI channels. + 0x000 + read-write + 0x0000FFFF + + + CHANNEL0 + Select secure attribute. + 0 + 0 + + + Secure + Channel0 has its secure attribute set + 1 + + + NonSecure + Channel0 has its non-secure attribute set + 0 + + + + + CHANNEL1 + Select secure attribute. + 1 + 1 + + + Secure + Channel1 has its secure attribute set + 1 + + + NonSecure + Channel1 has its non-secure attribute set + 0 + + + + + CHANNEL2 + Select secure attribute. + 2 + 2 + + + Secure + Channel2 has its secure attribute set + 1 + + + NonSecure + Channel2 has its non-secure attribute set + 0 + + + + + CHANNEL3 + Select secure attribute. + 3 + 3 + + + Secure + Channel3 has its secure attribute set + 1 + + + NonSecure + Channel3 has its non-secure attribute set + 0 + + + + + CHANNEL4 + Select secure attribute. + 4 + 4 + + + Secure + Channel4 has its secure attribute set + 1 + + + NonSecure + Channel4 has its non-secure attribute set + 0 + + + + + CHANNEL5 + Select secure attribute. + 5 + 5 + + + Secure + Channel5 has its secure attribute set + 1 + + + NonSecure + Channel5 has its non-secure attribute set + 0 + + + + + CHANNEL6 + Select secure attribute. + 6 + 6 + + + Secure + Channel6 has its secure attribute set + 1 + + + NonSecure + Channel6 has its non-secure attribute set + 0 + + + + + CHANNEL7 + Select secure attribute. + 7 + 7 + + + Secure + Channel7 has its secure attribute set + 1 + + + NonSecure + Channel7 has its non-secure attribute set + 0 + + + + + CHANNEL8 + Select secure attribute. + 8 + 8 + + + Secure + Channel8 has its secure attribute set + 1 + + + NonSecure + Channel8 has its non-secure attribute set + 0 + + + + + CHANNEL9 + Select secure attribute. + 9 + 9 + + + Secure + Channel9 has its secure attribute set + 1 + + + NonSecure + Channel9 has its non-secure attribute set + 0 + + + + + CHANNEL10 + Select secure attribute. + 10 + 10 + + + Secure + Channel10 has its secure attribute set + 1 + + + NonSecure + Channel10 has its non-secure attribute set + 0 + + + + + CHANNEL11 + Select secure attribute. + 11 + 11 + + + Secure + Channel11 has its secure attribute set + 1 + + + NonSecure + Channel11 has its non-secure attribute set + 0 + + + + + CHANNEL12 + Select secure attribute. + 12 + 12 + + + Secure + Channel12 has its secure attribute set + 1 + + + NonSecure + Channel12 has its non-secure attribute set + 0 + + + + + CHANNEL13 + Select secure attribute. + 13 + 13 + + + Secure + Channel13 has its secure attribute set + 1 + + + NonSecure + Channel13 has its non-secure attribute set + 0 + + + + + CHANNEL14 + Select secure attribute. + 14 + 14 + + + Secure + Channel14 has its secure attribute set + 1 + + + NonSecure + Channel14 has its non-secure attribute set + 0 + + + + + CHANNEL15 + Select secure attribute. + 15 + 15 + + + Secure + Channel15 has its secure attribute set + 1 + + + NonSecure + Channel15 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + DPPI[n].PERM register can't be changed until next reset + 1 + + + Unlocked + DPPI[n].PERM register content can be changed + 0 + + + + + + + + 1 + 0x008 + GPIOPORT[%s] + Unspecified + SPU_GPIOPORT + read-write + 0x4C0 + + PERM + Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. + 0x000 + read-write + 0xFFFFFFFF + + + PIN0 + Select secure attribute attribute for PIN 0. + 0 + 0 + + + Secure + Pin 0 has its secure attribute set + 1 + + + NonSecure + Pin 0 has its non-secure attribute set + 0 + + + + + PIN1 + Select secure attribute attribute for PIN 1. + 1 + 1 + + + Secure + Pin 1 has its secure attribute set + 1 + + + NonSecure + Pin 1 has its non-secure attribute set + 0 + + + + + PIN2 + Select secure attribute attribute for PIN 2. + 2 + 2 + + + Secure + Pin 2 has its secure attribute set + 1 + + + NonSecure + Pin 2 has its non-secure attribute set + 0 + + + + + PIN3 + Select secure attribute attribute for PIN 3. + 3 + 3 + + + Secure + Pin 3 has its secure attribute set + 1 + + + NonSecure + Pin 3 has its non-secure attribute set + 0 + + + + + PIN4 + Select secure attribute attribute for PIN 4. + 4 + 4 + + + Secure + Pin 4 has its secure attribute set + 1 + + + NonSecure + Pin 4 has its non-secure attribute set + 0 + + + + + PIN5 + Select secure attribute attribute for PIN 5. + 5 + 5 + + + Secure + Pin 5 has its secure attribute set + 1 + + + NonSecure + Pin 5 has its non-secure attribute set + 0 + + + + + PIN6 + Select secure attribute attribute for PIN 6. + 6 + 6 + + + Secure + Pin 6 has its secure attribute set + 1 + + + NonSecure + Pin 6 has its non-secure attribute set + 0 + + + + + PIN7 + Select secure attribute attribute for PIN 7. + 7 + 7 + + + Secure + Pin 7 has its secure attribute set + 1 + + + NonSecure + Pin 7 has its non-secure attribute set + 0 + + + + + PIN8 + Select secure attribute attribute for PIN 8. + 8 + 8 + + + Secure + Pin 8 has its secure attribute set + 1 + + + NonSecure + Pin 8 has its non-secure attribute set + 0 + + + + + PIN9 + Select secure attribute attribute for PIN 9. + 9 + 9 + + + Secure + Pin 9 has its secure attribute set + 1 + + + NonSecure + Pin 9 has its non-secure attribute set + 0 + + + + + PIN10 + Select secure attribute attribute for PIN 10. + 10 + 10 + + + Secure + Pin 10 has its secure attribute set + 1 + + + NonSecure + Pin 10 has its non-secure attribute set + 0 + + + + + PIN11 + Select secure attribute attribute for PIN 11. + 11 + 11 + + + Secure + Pin 11 has its secure attribute set + 1 + + + NonSecure + Pin 11 has its non-secure attribute set + 0 + + + + + PIN12 + Select secure attribute attribute for PIN 12. + 12 + 12 + + + Secure + Pin 12 has its secure attribute set + 1 + + + NonSecure + Pin 12 has its non-secure attribute set + 0 + + + + + PIN13 + Select secure attribute attribute for PIN 13. + 13 + 13 + + + Secure + Pin 13 has its secure attribute set + 1 + + + NonSecure + Pin 13 has its non-secure attribute set + 0 + + + + + PIN14 + Select secure attribute attribute for PIN 14. + 14 + 14 + + + Secure + Pin 14 has its secure attribute set + 1 + + + NonSecure + Pin 14 has its non-secure attribute set + 0 + + + + + PIN15 + Select secure attribute attribute for PIN 15. + 15 + 15 + + + Secure + Pin 15 has its secure attribute set + 1 + + + NonSecure + Pin 15 has its non-secure attribute set + 0 + + + + + PIN16 + Select secure attribute attribute for PIN 16. + 16 + 16 + + + Secure + Pin 16 has its secure attribute set + 1 + + + NonSecure + Pin 16 has its non-secure attribute set + 0 + + + + + PIN17 + Select secure attribute attribute for PIN 17. + 17 + 17 + + + Secure + Pin 17 has its secure attribute set + 1 + + + NonSecure + Pin 17 has its non-secure attribute set + 0 + + + + + PIN18 + Select secure attribute attribute for PIN 18. + 18 + 18 + + + Secure + Pin 18 has its secure attribute set + 1 + + + NonSecure + Pin 18 has its non-secure attribute set + 0 + + + + + PIN19 + Select secure attribute attribute for PIN 19. + 19 + 19 + + + Secure + Pin 19 has its secure attribute set + 1 + + + NonSecure + Pin 19 has its non-secure attribute set + 0 + + + + + PIN20 + Select secure attribute attribute for PIN 20. + 20 + 20 + + + Secure + Pin 20 has its secure attribute set + 1 + + + NonSecure + Pin 20 has its non-secure attribute set + 0 + + + + + PIN21 + Select secure attribute attribute for PIN 21. + 21 + 21 + + + Secure + Pin 21 has its secure attribute set + 1 + + + NonSecure + Pin 21 has its non-secure attribute set + 0 + + + + + PIN22 + Select secure attribute attribute for PIN 22. + 22 + 22 + + + Secure + Pin 22 has its secure attribute set + 1 + + + NonSecure + Pin 22 has its non-secure attribute set + 0 + + + + + PIN23 + Select secure attribute attribute for PIN 23. + 23 + 23 + + + Secure + Pin 23 has its secure attribute set + 1 + + + NonSecure + Pin 23 has its non-secure attribute set + 0 + + + + + PIN24 + Select secure attribute attribute for PIN 24. + 24 + 24 + + + Secure + Pin 24 has its secure attribute set + 1 + + + NonSecure + Pin 24 has its non-secure attribute set + 0 + + + + + PIN25 + Select secure attribute attribute for PIN 25. + 25 + 25 + + + Secure + Pin 25 has its secure attribute set + 1 + + + NonSecure + Pin 25 has its non-secure attribute set + 0 + + + + + PIN26 + Select secure attribute attribute for PIN 26. + 26 + 26 + + + Secure + Pin 26 has its secure attribute set + 1 + + + NonSecure + Pin 26 has its non-secure attribute set + 0 + + + + + PIN27 + Select secure attribute attribute for PIN 27. + 27 + 27 + + + Secure + Pin 27 has its secure attribute set + 1 + + + NonSecure + Pin 27 has its non-secure attribute set + 0 + + + + + PIN28 + Select secure attribute attribute for PIN 28. + 28 + 28 + + + Secure + Pin 28 has its secure attribute set + 1 + + + NonSecure + Pin 28 has its non-secure attribute set + 0 + + + + + PIN29 + Select secure attribute attribute for PIN 29. + 29 + 29 + + + Secure + Pin 29 has its secure attribute set + 1 + + + NonSecure + Pin 29 has its non-secure attribute set + 0 + + + + + PIN30 + Select secure attribute attribute for PIN 30. + 30 + 30 + + + Secure + Pin 30 has its secure attribute set + 1 + + + NonSecure + Pin 30 has its non-secure attribute set + 0 + + + + + PIN31 + Select secure attribute attribute for PIN 31. + 31 + 31 + + + Secure + Pin 31 has its secure attribute set + 1 + + + NonSecure + Pin 31 has its non-secure attribute set + 0 + + + + + + + LOCK + Description cluster: Prevent further modification of the corresponding PERM register + 0x004 + read-write + 0x00000000 + + + LOCK + 0 + 0 + + + Locked + GPIOPORT[n].PERM register can't be changed until next reset + 1 + + + Unlocked + GPIOPORT[n].PERM register content can be changed + 0 + + + + + + + + 2 + 0x008 + FLASHNSC[%s] + Unspecified + SPU_FLASHNSC + read-write + 0x500 + + REGION + Description cluster: Define which flash region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 4 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with a 32-byte size + 1 + + + 64 + The region n is defined as non-secure callable with a 64-byte size + 2 + + + 128 + The region n is defined as non-secure callable with a 128-byte size + 3 + + + 256 + The region n is defined as non-secure callable with a 256-byte size + 4 + + + 512 + The region n is defined as non-secure callable with a 512-byte size + 5 + + + 1024 + The region n is defined as non-secure callable with a 1024-byte size + 6 + + + 2048 + The region n is defined as non-secure callable with a 2048-byte size + 7 + + + 4096 + The region n is defined as non-secure callable with a 4096-byte size + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 2 + 0x008 + RAMNSC[%s] + Unspecified + SPU_RAMNSC + read-write + 0x540 + + REGION + Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n + 0x000 + read-write + 0x00000000 + + + REGION + Region number + 0 + 4 + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + SIZE + Description cluster: Define the size of the non-secure callable (NSC) region n + 0x004 + read-write + 0x00000000 + + + SIZE + Size of the non-secure callable (NSC) region n + 0 + 3 + + + Disabled + The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. + 0 + + + 32 + The region n is defined as non-secure callable with a 32-byte size + 1 + + + 64 + The region n is defined as non-secure callable with a 64-byte size + 2 + + + 128 + The region n is defined as non-secure callable with a 128-byte size + 3 + + + 256 + The region n is defined as non-secure callable with a 256-byte size + 4 + + + 512 + The region n is defined as non-secure callable with a 512-byte size + 5 + + + 1024 + The region n is defined as non-secure callable with a 1024-byte size + 6 + + + 2048 + The region n is defined as non-secure callable with a 2048-byte size + 7 + + + 4096 + The region n is defined as non-secure callable with a 4096-byte size + 8 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 32 + 0x004 + FLASHREGION[%s] + Unspecified + SPU_FLASHREGION + read-write + 0x600 + + PERM + Description cluster: Access permissions for flash region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from flash region n + 0 + 0 + + + Enable + Allow instruction fetches from flash region n + 1 + + + Disable + Block instruction fetches from flash region n + 0 + + + + + WRITE + Configure write permission for flash region n + 1 + 1 + + + Enable + Allow write operation to region n + 1 + + + Disable + Block write operation to region n + 0 + + + + + READ + Configure read permissions for flash region n + 2 + 2 + + + Enable + Allow read operation from flash region n + 1 + + + Disable + Block read operation from flash region n + 0 + + + + + SECATTR + Security attribute for flash region n + 4 + 4 + + + Non_Secure + Flash region n security attribute is non-secure + 0 + + + Secure + Flash region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 32 + 0x004 + RAMREGION[%s] + Unspecified + SPU_RAMREGION + read-write + 0x700 + + PERM + Description cluster: Access permissions for RAM region n + 0x000 + read-write + 0x00000017 + + + EXECUTE + Configure instruction fetch permissions from RAM region n + 0 + 0 + + + Enable + Allow instruction fetches from RAM region n + 1 + + + Disable + Block instruction fetches from RAM region n + 0 + + + + + WRITE + Configure write permission for RAM region n + 1 + 1 + + + Enable + Allow write operation to RAM region n + 1 + + + Disable + Block write operation to RAM region n + 0 + + + + + READ + Configure read permissions for RAM region n + 2 + 2 + + + Enable + Allow read operation from RAM region n + 1 + + + Disable + Block read operation from RAM region n + 0 + + + + + SECATTR + Security attribute for RAM region n + 4 + 4 + + + Non_Secure + RAM region n security attribute is non-secure + 0 + + + Secure + RAM region n security attribute is secure + 1 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + + + + 67 + 0x004 + PERIPHID[%s] + Unspecified + SPU_PERIPHID + read-write + 0x800 + + PERM + Description cluster: List capabilities and access permissions for the peripheral with ID n + 0x000 + read-write + 0x00000012 + + + SECUREMAPPING + Define configuration capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0 + + + Secure + This peripheral is always accessible as a secure peripheral + 1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register + 2 + + + Split + This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. + 3 + + + + + DMA + Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0 + + + + + LOCK + 8 + 8 + + + Unlocked + This register can be updated + 0 + + + Locked + The content of this register can't be changed until the next reset + 1 + + + + + PRESENT + Indicate if a peripheral is present with ID n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0 + + + IsPresent + Peripheral is present + 1 + + + + + + + + + + REGULATORS_NS + Voltage regulators control 0 + 0x40004000 + REGULATORS + + + + 0 + 0x1000 + registers + + REGULATORS + 0x20 + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enable + Enable System OFF mode + 1 + + + + + + + EXTPOFCON + External power failure warning configuration + 0x514 + read-write + + + POF + Enable or disable external power failure warning + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + DCDCEN + Enable DC/DC mode of the main voltage regulator. + 0x578 + read-write + + + DCDCEN + Enable DC/DC converter + 0 + 0 + + + Disabled + DC/DC mode is disabled + 0 + + + Enabled + DC/DC mode is enabled + 1 + + + + + + + + + REGULATORS_S + Voltage regulators control 1 + 0x50004000 + + + + + CLOCK_NS + Clock management 0 + 0x40005000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK source + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK source + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_HFCLKSTART + Subscribe configuration for task HFCLKSTART + 0x080 + read-write + + + CHIDX + DPPI channel that task HFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_HFCLKSTOP + Subscribe configuration for task HFCLKSTOP + 0x084 + read-write + + + CHIDX + DPPI channel that task HFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x088 + read-write + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x08C + read-write + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_HFCLKSTARTED + Publish configuration for event HFCLKSTARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event HFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x184 + read-write + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + HFCLKSTARTED + Enable or disable interrupt for event HFCLKSTARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + HFCLKSTARTED + Read pending status of interrupt for event HFCLKSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) + 0x40C + read-only + + + SRC + Active clock source + 0 + 0 + + + HFINT + HFINT - 64 MHz on-chip oscillator + 0 + + + HFXO + HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFXO has not been started or HFCLKSTOP task has been triggered + 0 + + + Running + HFXO has been started (HFCLKSTARTED event has been generated) + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) + 0x418 + read-only + + + SRC + Active clock source + 0 + 1 + + + RFU + Reserved for future use + 0 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + Requested LFCLK source has not been started or LFCLKSTOP task has been triggered + 0 + + + Running + Requested LFCLK source has been started (LFCLKSTARTED event has been generated) + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered + 0x41C + read-only + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + RFU + Reserved for future use + 0 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. + 0x518 + read-write + 0x00000001 + + + SRC + Clock source + 0 + 1 + + + RFU + Reserved for future use (equals selecting LFRC) + 0 + + + LFRC + 32.768 kHz RC oscillator + 1 + + + LFXO + 32.768 kHz crystal oscillator + 2 + + + + + + + + + POWER_NS + Power control 0 + 0x40005000 + CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 5 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable constant latency mode. + 0x78 + write-only + + + TASKS_CONSTLAT + Enable constant latency mode. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xF8 + read-write + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xFC + read-write + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x188 + read-write + + + CHIDX + DPPI channel that event POFWARN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x194 + read-write + + + CHIDX + DPPI channel that event SLEEPENTER will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x198 + read-write + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + POFWARN + Enable or disable interrupt for event POFWARN + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from global watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode + 4 + 4 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from AIRCR.SYSRESETREQ detected + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + CTRLAP + Reset triggered through CTRL-AP + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + POWERSTATUS + Modem domain power status + 0x440 + read-only + + + LTEMODEM + LTE modem domain status + 0 + 0 + + + OFF + LTE modem domain is powered off + 0 + + + ON + LTE modem domain is powered on + 1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + LTEMODEM + LTE Modem + POWER_LTEMODEM + read-write + 0x610 + + STARTN + Start LTE modem + 0x000 + read-write + 0x00000001 + + + STARTN + Start LTE modem + 0 + 0 + + + Start + Start LTE modem + 0 + + + Hold + Hold LTE modem disabled + 1 + + + + + + + FORCEOFF + Force off LTE modem + 0x004 + read-write + 0x00000000 + + + FORCEOFF + Force off LTE modem + 0 + 0 + + + Release + Release force off + 0 + + + Hold + Hold force off active + 1 + + + + + + + + + + CLOCK_S + Clock management 1 + 0x50005000 + + + + CLOCK_POWER + 5 + + + + POWER_S + Power control 1 + 0x50005000 + CLOCK_S + + + + CLOCK_POWER + 5 + + + + CTRL_AP_PERI_S + Control access port + 0x50006000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + CTRLAPPERI + 0x20 + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + + + RXDATA + Data received from debugger + 0 + 31 + + + + + RXSTATUS + This register shows a status that indicates if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + + + RXSTATUS + Status of data in register RXDATA + 0 + 0 + + + NoDataPending + No data pending in register RXDATA + 0 + + + DataPending + Data pending in register RXDATA + 1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + + + TXDATA + Data sent to debugger + 0 + 31 + + + + + TXSTATUS + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + + + TXSTATUS + Status of data in register TXDATA + 0 + 0 + + + NoDataPending + No data pending in register TXDATA + 0 + + + DataPending + Data pending in register TXDATA + 1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeonce + 0x00000000 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable + 0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only + 1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + read-write + 0x00000000 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + + + SPIM0_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x40008000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x090 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x198 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + ORC + Over-read character. Character clocked out in case an over-read of the TXD buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out in case an over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS0_NS + SPI Slave 0 + 0x40008000 + SPIM0_NS + SPIS + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x0A4 + read-write + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x0A8 + read-write + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x1A8 + read-write + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWIM0_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIM + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1C8 + read-write + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1DC + read-write + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1E0 + read-write + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40008000 + SPIM0_NS + TWIS + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x094 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x09C + read-write + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x0A0 + read-write + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0B0 + read-write + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0B4 + read-write + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1E4 + read-write + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1E8 + read-write + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Indication of which address in {ADDRESS} that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 12 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + UARTE0_NS + UART with EasyDMA 0 + 0x40008000 + SPIM0_NS + UARTE + + + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STARTRX + Subscribe configuration for task STARTRX + 0x080 + read-write + + + CHIDX + DPPI channel that task STARTRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPRX + Subscribe configuration for task STOPRX + 0x084 + read-write + + + CHIDX + DPPI channel that task STOPRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x088 + read-write + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x08C + read-write + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x0AC + read-write + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x188 + read-write + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x190 + read-write + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x19C + read-write + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1A0 + read-write + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x1A4 + read-write + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1C4 + read-write + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RXSTARTED + Publish configuration for event RXSTARTED + 0x1CC + read-write + + + CHIDX + DPPI channel that event RXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTARTED + Publish configuration for event TXSTARTED + 0x1D0 + read-write + + + CHIDX + DPPI channel that event TXSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1D8 + read-write + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source This register is read/write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 12 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 12 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + SPIM0_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x50008000 + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + SPIS0_S + SPI Slave 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + TWIM0_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + TWIS0_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + UARTE0_S + UART with EasyDMA 1 + 0x50008000 + SPIM0_S + + + + SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + 8 + + + + SPIM1_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x40009000 + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIS1_NS + SPI Slave 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIM1_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIS1_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + UARTE1_NS + UART with EasyDMA 2 + 0x40009000 + SPIM1_NS + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIM1_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x50009000 + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIS1_S + SPI Slave 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIM1_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + TWIS1_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + UARTE1_S + UART with EasyDMA 3 + 0x50009000 + SPIM1_S + + + + SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + 9 + + + + SPIM2_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4000A000 + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIS2_NS + SPI Slave 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIM2_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIS2_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + UARTE2_NS + UART with EasyDMA 4 + 0x4000A000 + SPIM2_NS + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIM2_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5000A000 + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIS2_S + SPI Slave 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIM2_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + TWIS2_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + UARTE2_S + UART with EasyDMA 5 + 0x5000A000 + SPIM2_S + + + + SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + 10 + + + + SPIM3_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4000B000 + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIS3_NS + SPI Slave 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIM3_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIS3_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + UARTE3_NS + UART with EasyDMA 6 + 0x4000B000 + SPIM3_NS + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIM3_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5000B000 + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + SPIS3_S + SPI Slave 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIM3_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + TWIS3_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + UARTE3_S + UART with EasyDMA 7 + 0x5000B000 + SPIM3_S + + + + SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + 11 + + + + GPIOTE0_S + GPIO Tasks and Events 0 + 0x5000D000 + GPIOTE + + + + 0 + 0x1000 + registers + + + GPIOTE0 + 13 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PORT + Publish configuration for event PORT + 0x1FC + read-write + + + CHIDX + DPPI channel that event PORT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC_NS + Analog to Digital Converter 0 + 0x4000E000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 14 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0 + + + Busy + ADC is busy. Single conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDDGPIO + VDD_GPIO + 9 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD_GPIO + VDD_GPIO + 9 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD_GPIO + 2 + + + VDD1_2 + Set input at VDD_GPIO/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD_GPIO + 2 + + + VDD1_2 + Set input at VDD_GPIO/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD_GPIO/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + SAADC_S + Analog to Digital Converter 1 + 0x5000E000 + + + + SAADC + 14 + + + + TIMER0_NS + Timer/Counter 0 + 0x4000F000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER0 + 15 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x6 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x514 + read-write + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0 + + + Enable + Enable one-shot operation + 1 + + + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER0_S + Timer/Counter 1 + 0x5000F000 + + + + TIMER0 + 15 + + + + TIMER1_NS + Timer/Counter 2 + 0x40010000 + + + + TIMER1 + 16 + + + + TIMER1_S + Timer/Counter 3 + 0x50010000 + + + + TIMER1 + 16 + + + + TIMER2_NS + Timer/Counter 4 + 0x40011000 + + + + TIMER2 + 17 + + + + TIMER2_S + Timer/Counter 5 + 0x50011000 + + + + TIMER2 + 17 + + + + RTC0_NS + Real-time counter 0 + 0x40014000 + RTC + + + + 0 + 0x1000 + registers + + + RTC0 + 20 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + RTC0_S + Real-time counter 1 + 0x50014000 + + + + RTC0 + 20 + + + + RTC1_NS + Real-time counter 2 + 0x40015000 + + + + RTC1 + 21 + + + + RTC1_S + Real-time counter 3 + 0x50015000 + + + + RTC1 + 21 + + + + DPPIC_NS + Distributed programmable peripheral interconnect controller 0 + 0x40017000 + DPPIC + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0 + + + Enabled + Read: Channel enabled + 1 + + + + write + + Clear + Write: Disable channel + 1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + + + DPPIC_S + Distributed programmable peripheral interconnect controller 1 + 0x50017000 + + + + + WDT_NS + Watchdog Timer 0 + 0x40018000 + WDT + + + + 0 + 0x1000 + registers + + + WDT + 24 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUSWDT + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT_S + Watchdog Timer 1 + 0x50018000 + + + + WDT + 24 + + + + EGU0_NS + Event generator unit 0 + 0x4001B000 + EGU + + + + 0 + 0x1000 + registers + + + EGU0 + 27 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + EGU0_S + Event generator unit 1 + 0x5001B000 + + + + EGU0 + 27 + + + + EGU1_NS + Event generator unit 2 + 0x4001C000 + + + + EGU1 + 28 + + + + EGU1_S + Event generator unit 3 + 0x5001C000 + + + + EGU1 + 28 + + + + EGU2_NS + Event generator unit 4 + 0x4001D000 + + + + EGU2 + 29 + + + + EGU2_S + Event generator unit 5 + 0x5001D000 + + + + EGU2 + 29 + + + + EGU3_NS + Event generator unit 6 + 0x4001E000 + + + + EGU3 + 30 + + + + EGU3_S + Event generator unit 7 + 0x5001E000 + + + + EGU3 + 30 + + + + EGU4_NS + Event generator unit 8 + 0x4001F000 + + + + EGU4 + 31 + + + + EGU4_S + Event generator unit 9 + 0x5001F000 + + + + EGU4 + 31 + + + + EGU5_NS + Event generator unit 10 + 0x40020000 + + + + EGU5 + 32 + + + + EGU5_S + Event generator unit 11 + 0x50020000 + + + + EGU5 + 32 + + + + PWM0_NS + Pulse width modulation unit 0 + 0x40021000 + PWM + + + + 0 + 0x1000 + registers + + + PWM0 + 33 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x2 + 0x4 + SUBSCRIBE_SEQSTART[%s] + Description collection: Subscribe configuration for task SEQSTART[n] + 0x088 + read-write + + + CHIDX + DPPI channel that task SEQSTART[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x090 + read-write + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PWM0_S + Pulse width modulation unit 1 + 0x50021000 + + + + PWM0 + 33 + + + + PWM1_NS + Pulse width modulation unit 2 + 0x40022000 + + + + PWM1 + 34 + + + + PWM1_S + Pulse width modulation unit 3 + 0x50022000 + + + + PWM1 + 34 + + + + PWM2_NS + Pulse width modulation unit 4 + 0x40023000 + + + + PWM2 + 35 + + + + PWM2_S + Pulse width modulation unit 5 + 0x50023000 + + + + PWM2 + 35 + + + + PWM3_NS + Pulse width modulation unit 6 + 0x40024000 + + + + PWM3 + 36 + + + + PWM3_S + Pulse width modulation unit 7 + 0x50024000 + + + + PWM3 + 36 + + + + PDM_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x40026000 + PDM + + + + 0 + 0x1000 + registers + + + PDM + 38 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency configuration. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + PDM_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x50026000 + + + + PDM + 38 + + + + I2S_NS + Inter-IC Sound 0 + 0x40028000 + I2S + + + + 0 + 0x1000 + registers + + + I2S + 40 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + I2S_S + Inter-IC Sound 1 + 0x50028000 + + + + I2S + 40 + + + + IPC_NS + Interprocessor communication 0 + 0x4002A000 + IPC + + + + 0 + 0x1000 + registers + + + IPC + 42 + + IPC + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] + 0x000 + write-only + + + TASKS_SEND + Trigger events on IPC channel enabled in SEND_CNF[n] + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0 + + + Enabled + Enable subscription + 1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0x100 + read-write + + + EVENTS_RECEIVE + Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + 0x8 + 0x4 + SEND_CNF[%s] + Description collection: Send event configuration for TASKS_SEND[n] + 0x510 + read-write + 0x00000000 + + + CHEN0 + Enable broadcasting on IPC channel 0 + 0 + 0 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN1 + Enable broadcasting on IPC channel 1 + 1 + 1 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN2 + Enable broadcasting on IPC channel 2 + 2 + 2 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN3 + Enable broadcasting on IPC channel 3 + 3 + 3 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN4 + Enable broadcasting on IPC channel 4 + 4 + 4 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN5 + Enable broadcasting on IPC channel 5 + 5 + 5 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN6 + Enable broadcasting on IPC channel 6 + 6 + 6 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + CHEN7 + Enable broadcasting on IPC channel 7 + 7 + 7 + + + Disable + Disable broadcast + 0 + + + Enable + Enable broadcast + 1 + + + + + + + 0x8 + 0x4 + RECEIVE_CNF[%s] + Description collection: Receive event configuration for EVENTS_RECEIVE[n] + 0x590 + read-write + 0x00000000 + + + CHEN0 + Enable subscription to IPC channel 0 + 0 + 0 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN1 + Enable subscription to IPC channel 1 + 1 + 1 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN2 + Enable subscription to IPC channel 2 + 2 + 2 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN3 + Enable subscription to IPC channel 3 + 3 + 3 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN4 + Enable subscription to IPC channel 4 + 4 + 4 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN5 + Enable subscription to IPC channel 5 + 5 + 5 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN6 + Enable subscription to IPC channel 6 + 6 + 6 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + CHEN7 + Enable subscription to IPC channel 7 + 7 + 7 + + + Disable + Disable events + 0 + + + Enable + Enable events + 1 + + + + + + + 0x4 + 0x4 + GPMEM[%s] + Description collection: General purpose memory + 0x610 + read-write + 0x00000000 + + + GPMEM + General purpose memory + 0 + 31 + + + + + + + IPC_S + Interprocessor communication 1 + 0x5002A000 + + + + IPC + 42 + + + + FPU_NS + FPU 0 + 0x4002C000 + FPU + + + + 0 + 0x1000 + registers + + + FPU + 44 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + FPU_S + FPU 1 + 0x5002C000 + + + + FPU + 44 + + + + GPIOTE1_NS + GPIO Tasks and Events 1 + 0x40031000 + + + + GPIOTE1 + 49 + + + + KMU_NS + Key management unit 0 + 0x40039000 + KMU + + + + 0 + 0x1000 + registers + + + KMU + 57 + + KMU + 0x20 + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0x0000 + write-only + + + TASKS_PUSH_KEYSLOT + Push a key slot over secure APB + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0x100 + read-write + + + EVENTS_KEYSLOT_PUSHED + Key slot successfully pushed over secure APB + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0x104 + read-write + + + EVENTS_KEYSLOT_REVOKED + Key slot has been revoked and cannot be tasked for selection + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0x108 + read-write + + + EVENTS_KEYSLOT_ERROR + No key slot selected, no destination address defined, or error during push operation + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + KEYSLOT_PUSHED + Enable or disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_REVOKED + Enable or disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + KEYSLOT_ERROR + Enable or disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + KEYSLOT_PUSHED + Write '1' to enable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to enable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + KEYSLOT_ERROR + Write '1' to enable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + KEYSLOT_PUSHED + Write '1' to disable interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_REVOKED + Write '1' to disable interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + KEYSLOT_ERROR + Write '1' to disable interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + + + KEYSLOT_PUSHED + Read pending status of interrupt for event KEYSLOT_PUSHED + 0 + 0 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_REVOKED + Read pending status of interrupt for event KEYSLOT_REVOKED + 1 + 1 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + KEYSLOT_ERROR + Read pending status of interrupt for event KEYSLOT_ERROR + 2 + 2 + + read + + NotPending + Read: Not pending + 0 + + + Pending + Read: Pending + 1 + + + + + + + STATUS + Status bits for KMU operation + 0x40C + read-only + 0x00000000 + + + SELECTED + Key slot ID successfully selected by the KMU + 0 + 0 + + + Disabled + No key slot ID selected by KMU + 0 + + + Enabled + Key slot ID successfully selected by KMU + 1 + + + + + BLOCKED + Violation status + 1 + 1 + + + Disabled + No access violation detected + 0 + + + Enabled + Access violation detected and blocked + 1 + + + + + + + SELECTKEYSLOT + Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started + 0x500 + read-write + 0x00000000 + + + ID + Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. + 0 + 7 + + + + + + + NVMC_NS + Non-volatile memory controller 0 + 0x40039000 + KMU_NS + NVMC + + + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 + read-only + 0x00000001 + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 2 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + PEen + Partial erase enabled + 4 + + + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register + 0x540 + read-write + 0x00000000 + + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter + 0x548 + read-write + + + + HITS + Number of cache hits Write zero to clear + 0 + 31 + + + + + IMISS + I-code cache miss counter + 0x54C + read-write + + + + MISSES + Number of cache misses Write zero to clear + 0 + 31 + + + + + CONFIGNS + Unspecified + 0x584 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + WRITEUICRNS + Non-secure APPROTECT enable register + 0x588 + write-only + + + SET + Allow non-secure code to set APPROTECT + 0 + 0 + + + Set + Set value + 1 + + + + + KEY + Key to write in order to validate the write operation + 4 + 31 + + + Keyvalid + Key value + 0xAFBE5A7 + + + + + + + + + KMU_S + Key management unit 1 + 0x50039000 + + + + KMU + 57 + + + + NVMC_S + Non-volatile memory controller 1 + 0x50039000 + KMU_S + + + + + VMC_NS + Volatile Memory controller 0 + 0x4003A000 + VMC + + + + 0 + 0x1000 + registers + + VMC + 0x20 + + + 8 + 0x010 + RAM[%s] + Unspecified + VMC_RAM + read-write + 0x600 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + Off + Off + 0 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + On + On + 1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + On + On + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAM n on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAM n on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S2POWER + Keep RAM section S2 of RAM n on or off in System ON mode + 2 + 2 + + + Off + Off + 1 + + + + + S3POWER + Keep RAM section S3 of RAM n on or off in System ON mode + 3 + 3 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 of RAM n when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 of RAM n when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + S2RETENTION + Keep retention on RAM section S2 of RAM n when RAM section is switched off + 18 + 18 + + + Off + Off + 1 + + + + + S3RETENTION + Keep retention on RAM section S3 of RAM n when RAM section is switched off + 19 + 19 + + + Off + Off + 1 + + + + + + + + + + VMC_S + Volatile Memory controller 1 + 0x5003A000 + + + + + CC_HOST_RGF_S + CRYPTOCELL HOST_RGF interface + 0x50840000 + CC_HOST_RGF + + + + 0 + 0x2000 + registers + + CC_HOST_RGF + 0x20 + + + HOST_CRYPTOKEY_SEL + AES hardware key select + 0x1A38 + read-write + 0x00000000 + + + HOST_CRYPTOKEY_SEL + Select the source of the HW key that is used by the AES engine + 0 + 1 + + + K_DR + Use device root key K_DR from CRYPTOCELL AO power domain + 0 + + + K_PRTL + Use hard-coded RTL key K_PRTL + 1 + + + Session + Use provided session key + 2 + + + + + + + HOST_IOT_KPRTL_LOCK + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A4C + read-write + 0x00000000 + + + HOST_IOT_KPRTL_LOCK + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + 0 + 0 + + + Disabled + K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL + 0 + + + Enabled + K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. + 1 + + + + + + + HOST_IOT_KDR0 + This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. + 0x1A50 + read-write + 0x00000000 + + + HOST_IOT_KDR0 + Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. + 0 + 31 + + + + + HOST_IOT_KDR1 + This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A54 + write-only + 0x00000000 + + + HOST_IOT_KDR1 + K_DR bits 63:32 + 0 + 31 + + + + + HOST_IOT_KDR2 + This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A58 + write-only + 0x00000000 + + + HOST_IOT_KDR2 + K_DR bits 95:64 + 0 + 31 + + + + + HOST_IOT_KDR3 + This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. + 0x1A5C + write-only + 0x00000000 + + + HOST_IOT_KDR3 + K_DR bits 127:96 + 0 + 31 + + + + + HOST_IOT_LCS + Controls lifecycle state (LCS) for CRYPTOCELL subsystem + 0x1A60 + read-write + 0x00000002 + + + LCS + Lifecycle state value. This field is write-once per reset. + 0 + 2 + + + Debug + CC310 operates in debug mode + 0 + + + Secure + CC310 operates in secure mode + 2 + + + + + LCS_IS_VALID + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. + 8 + 8 + + + Invalid + Valid LCS not yet retained in the CRYPTOCELL AO power domain + 0 + + + Valid + Valid LCS successfully retained in the CRYPTOCELL AO power domain + 1 + + + + + + + + + CRYPTOCELL_S + ARM TrustZone CryptoCell register interface + 0x50840000 + CC_HOST_RGF_S + CRYPTOCELL + + + + 0 + 0x2000 + registers + + + CRYPTOCELL + 64 + + CRYPTOCELL + 0x20 + + + ENABLE + Enable CRYPTOCELL subsystem + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable the CRYPTOCELL subsystem + 0 + 0 + + + Disabled + CRYPTOCELL subsystem disabled + 0 + + + Enabled + CRYPTOCELL subsystem enabled. + 1 + + + + + + + + + P0_NS + GPIO Port 0 + 0x40842500 + GPIO + + + + 0 + 0x300 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x004 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x008 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x00C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x010 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x014 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x018 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x01C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + + + PIN0 + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) + 0x024 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + DETECTMODE_SEC + Select between default DETECT signal behavior and LDETECT mode (For secure pin only) + 0x028 + read-write + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behavior + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x200 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0', standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0', disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + P0_S + GPIO Port 1 + 0x50842500 + + + + + \ No newline at end of file diff --git a/pyocd/flash/builder.py b/pyocd/flash/builder.py index 24ae46c25..c38900122 100644 --- a/pyocd/flash/builder.py +++ b/pyocd/flash/builder.py @@ -807,12 +807,14 @@ def _sector_erase_program(self, progress_cb=_stub_progress): for sector in self.sector_list: if sector.are_any_pages_not_same(): - # Erase the sector - self.flash.init(self.flash.Operation.ERASE) - self.flash.erase_sector(sector.addr) - self.flash.uninit() - actual_sector_erase_weight += sector.erase_weight + if self.region.is_erasable: + # Erase the sector + self.flash.init(self.flash.Operation.ERASE) + self.flash.erase_sector(sector.addr) + self.flash.uninit() + + actual_sector_erase_weight += sector.erase_weight # Update progress if self.sector_erase_weight > 0: @@ -907,18 +909,20 @@ def _sector_erase_program_double_buffer(self, progress_cb=_stub_progress): # to read from flash while simultaneously programming it. progress = self._scan_pages_for_same(progress_cb) - # Erase all sectors up front. - self.flash.init(self.flash.Operation.ERASE) - for sector in self.sector_list: - if sector.are_any_pages_not_same(): - # Erase the sector - self.flash.erase_sector(sector.addr) - # Update progress - progress += sector.erase_weight - if self.sector_erase_weight > 0: - progress_cb(float(progress) / float(self.sector_erase_weight)) - self.flash.uninit() + if self.region.is_erasable: + # Erase all sectors up front. + self.flash.init(self.flash.Operation.ERASE) + for sector in self.sector_list: + if sector.are_any_pages_not_same(): + # Erase the sector + self.flash.erase_sector(sector.addr) + + # Update progress + progress += sector.erase_weight + if self.sector_erase_weight > 0: + progress_cb(float(progress) / float(self.sector_erase_weight)) + self.flash.uninit() # Set up page and buffer info. current_buf = 0 diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 90741c501..0d421bfb6 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -61,6 +61,7 @@ from . import target_nRF52832_xxAA from . import target_nRF52833_xxAA from . import target_nRF52840_xxAA +from . import target_nRF91xx from . import target_STM32F103RC from . import target_STM32F051T8 from . import target_STM32F412xx @@ -197,6 +198,7 @@ 'nrf52832': target_nRF52832_xxAA.NRF52832, 'nrf52833': target_nRF52833_xxAA.NRF52833, 'nrf52840' : target_nRF52840_xxAA.NRF52840, + 'nrf91' : target_nRF91xx.NRF91XX, 'stm32f103rc': target_STM32F103RC.STM32F103RC, 'stm32f051': target_STM32F051T8.STM32F051, 'stm32f412xe' : target_STM32F412xx.STM32F412xE, diff --git a/pyocd/target/builtin/target_nRF91xx.py b/pyocd/target/builtin/target_nRF91xx.py new file mode 100644 index 000000000..6db86902e --- /dev/null +++ b/pyocd/target/builtin/target_nRF91xx.py @@ -0,0 +1,225 @@ +# Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of Nordic Semiconductor ASA nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +from ...core.memory_map import FlashRegion, RamRegion, MemoryMap +from ...debug.svd.loader import SVDFile +from ..family.target_nRF91 import NRF91 + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b5b0, 0xf2c00504, 0x20000500, 0x0105eb09, 0x0005f849, 0x0001e9c1, 0xb2d060c8, 0xf0004614, + 0xb120fa3d, 0x0105eb09, 0x0402e9c1, 0xeb09bdb0, 0x21010005, 0xf0006041, 0x2000fa2b, 0xbf00bdb0, + 0x4604b510, 0xf0002000, 0xb138fa29, 0x0104f240, 0x0100f2c0, 0xe9c14449, 0xbd100402, 0x0004f240, + 0x0000f2c0, 0x0100eb09, 0x29006889, 0x2000bf04, 0xf244bd10, 0xf2c20100, 0x22010100, 0xf859600a, + 0x44482000, 0x6842604a, 0x6882608a, 0x68c060ca, 0x20006108, 0xbf00bd10, 0x0004f240, 0x0000f2c0, + 0xf8492101, 0x44481000, 0xe9c02100, 0x60c11101, 0xba28f000, 0xf240b5b0, 0x46040504, 0x0500f2c0, + 0xf8492002, 0xeb090005, 0x21000005, 0x1101e9c0, 0xf00060c1, 0xfbb4f9a5, 0xfb01f1f0, 0xb1304010, + 0x0005eb09, 0xe9c02103, 0x20651402, 0xeb09bdb0, 0x21010005, 0xf0006041, 0x42a0f9ad, 0xf000d813, + 0x42a0f9ab, 0xeb09d90f, 0x21020005, 0x46206041, 0xf9c2f000, 0xbf1c2803, 0xbdb02067, 0xf0004620, + 0x2000f9e7, 0xeb09bdb0, 0x21040005, 0x1402e9c0, 0xbdb02066, 0x41f0e92d, 0x0704f240, 0xf2c04604, + 0x46150700, 0x2003460e, 0x0107eb09, 0x07a32200, 0x0007f849, 0x2201e9c1, 0xd00660ca, 0x0107eb09, + 0x0402e9c1, 0xe8bd2065, 0xeb0981f0, 0x21010007, 0xf0006041, 0x42a0f96f, 0xf000d815, 0x42a0f96d, + 0xeb09d911, 0x21030007, 0xeb066041, 0xf0000804, 0x4580f963, 0xeb09d90f, 0x21040007, 0x1802e9c0, + 0xe8bd2066, 0xeb0981f0, 0x21040007, 0x1402e9c0, 0xe8bd2066, 0xeb0981f0, 0x21040007, 0xf0006041, + 0xb130f969, 0x0007eb09, 0x60812102, 0xe8bd2067, 0xeb0981f0, 0x21050007, 0x46206041, 0xf95cf000, + 0xd2072802, 0x0007eb09, 0xe9c02102, 0x20671402, 0x81f0e8bd, 0x22ffd10f, 0x46314620, 0xf836f000, + 0x2003b148, 0x0007f849, 0x0007eb09, 0x60412105, 0xe8bd2067, 0x200381f0, 0x0007f849, 0xebb02000, + 0xeb090f96, 0xf04f0107, 0x604a0206, 0xe8bdbf08, 0xea4f81f0, 0x26000896, 0x0026f854, 0xd10c3001, + 0x0026f855, 0x0026f844, 0xf942f000, 0x45463601, 0x0000f04f, 0xe8bdd3f0, 0xeb0981f0, 0x21050007, + 0xe9c019a2, 0x20681202, 0x81f0e8bd, 0x41f0e92d, 0x0704f240, 0x4604460d, 0x0700f2c0, 0x46162005, + 0x0007f849, 0x0007eb09, 0x07aa2100, 0x1101e9c0, 0xd00760c1, 0x0007eb09, 0xe9c02103, 0x20651502, + 0x81f0e8bd, 0x0007eb09, 0x60412102, 0xf8d2f000, 0xd81542a0, 0xf8d0f000, 0xd91142a0, 0x0007eb09, + 0x60412103, 0x0804eb05, 0xf8c6f000, 0xd90f4580, 0x0007eb09, 0xe9c02104, 0x20661802, 0x81f0e8bd, + 0x0007eb09, 0xe9c02104, 0x20661402, 0x81f0e8bd, 0x0007eb09, 0x2d002104, 0xbf046041, 0xe8bd2000, + 0x210081f0, 0xbf00e007, 0x42a93101, 0x0000f04f, 0xe8bdbf28, 0x5c6081f0, 0xd0f542b0, 0xeb091860, + 0x22050107, 0x2002e9c1, 0xe8bd2001, 0xbf0081f0, 0x41f0e92d, 0x0504f240, 0xf2c04604, 0x20040500, + 0x460f4690, 0x0005f849, 0x0005eb09, 0x07a22100, 0x1101e9c0, 0xd00860c1, 0x0005eb09, 0x26652103, + 0x1402e9c0, 0xe8bd4630, 0xeb0981f0, 0x21010005, 0xf0006041, 0x42a0f86f, 0xf000d812, 0x42a0f86d, + 0xeb09d90e, 0x21030005, 0x193e6041, 0xf864f000, 0xd90e4286, 0x0005eb09, 0xe9c02104, 0xe0041602, + 0x0005eb09, 0xe9c02104, 0x26661402, 0xe8bd4630, 0x210081f0, 0x0f97ebb1, 0x0005eb09, 0x0104f04f, + 0xd00b6041, 0x210008b8, 0xf8586822, 0x429a3021, 0x3101d10b, 0xf1044281, 0xd3f50404, 0x0005eb09, + 0x60412105, 0xe8bd4630, 0xeb0981f0, 0x21060005, 0x1402e9c0, 0xe8bd4620, 0x000081f0, 0x1030f240, + 0x00fff2c0, 0x31016801, 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, 0xf3616849, 0x4770200b, + 0x2020f240, 0x00fff2c0, 0x31016801, 0x6800bf14, 0x5080f44f, 0xbf004770, 0x2024f240, 0x00fff2c0, + 0x31016801, 0x6800bf14, 0x7000f44f, 0xbf004770, 0x47702000, 0x47702000, 0xf7ffb510, 0x4604ffe1, + 0xffeaf7ff, 0xf004fb00, 0xbf00bd10, 0x42814401, 0x2001bf9c, 0xe0034770, 0xbf244288, 0x47702001, + 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf00e7f4, 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, + 0x47702069, 0xb240b580, 0xf851a105, 0xf2490020, 0xf2c55104, 0x60080103, 0xf80af000, 0xbd802000, + 0x00000000, 0x00000002, 0x00000001, 0x00000000, 0x4000f249, 0x0003f2c5, 0x29006801, 0x4770d0fc, + 0x500cf249, 0x0003f2c5, 0x60012101, 0xbf00e7f0, 0x9000b081, 0xf04f9800, 0x600131ff, 0xe7e7b001, + 0x47702069, 0xf7ffb5b0, 0x4604ffa7, 0x2500b140, 0xf7ff4628, 0xf7ffffed, 0x4405ff83, 0xd3f742a5, + 0xbdb02000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000045, + 'pc_program_page': 0x20000139, + 'pc_erase_sector': 0x200000b9, + 'pc_eraseAll': 0x2000009d, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000524, + 'begin_stack' : 0x20003540, + 'end_stack' : 0x20002540, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x1000, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000540, + 0x20001540 + ], + 'min_program_length' : 0x1000, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x524, + 'rw_start': 0x528, + 'rw_size': 0x4, + 'zi_start': 0x52c, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x200000, + 'sector_sizes': ( + (0x0, 0x1000), + ) +} + +FLASH_ALGO_UICR = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b570, 0xf2c00604, 0x25000600, 0x0006eb09, 0x5006f849, 0x5501e9c0, 0xb2d060c5, 0xf0004614, + 0x2800f9c9, 0xeb09bf1e, 0xe9c10106, 0x46050402, 0xbd704628, 0x4604b510, 0xf0002000, 0xf240f9bb, + 0x28000104, 0x0100f2c0, 0xeb09bf1c, 0xe9c20201, 0xeb090402, 0x68920201, 0xbf082a00, 0xf244bd10, + 0xf2c20200, 0x23010200, 0xf8596013, 0x44493001, 0x684b6053, 0x688b6093, 0x68c960d3, 0xbd106111, + 0xf240b580, 0xf2c00004, 0x21010000, 0x1000f849, 0x21004448, 0x1101e9c0, 0xf00060c1, 0x2000f9ad, + 0xbf00bd80, 0xf240b510, 0xf2c00004, 0x21020000, 0x1000f849, 0x24004448, 0x4401e9c0, 0xf00060c4, + 0x4601f93b, 0x0000f248, 0x00fff2c0, 0xf00022ff, 0xb138f80f, 0xf9a6f000, 0xd0052869, 0x28004604, + 0x2400bf08, 0xbd104620, 0x46202400, 0xbf00bd10, 0xf240b570, 0xf2c00c04, 0x23050c00, 0x300cf849, + 0x030ceb09, 0x0e00f04f, 0xe9c30784, 0xf8c3ee01, 0xd006e00c, 0x010ceb09, 0xe9c12203, 0x20652002, + 0xeb09bd70, 0xf04f030c, 0x078c0e01, 0xe004f8c3, 0xeb09d006, 0x2203000c, 0x2102e9c0, 0xbd702065, + 0x7efff648, 0x0efff2c0, 0x030ceb09, 0x45702402, 0xd906605c, 0x010ceb09, 0xe9c12204, 0x20662002, + 0x180bbd70, 0x0501f10e, 0x040ceb09, 0x42ab2603, 0xd9066066, 0x000ceb09, 0xe9c02104, 0x20661302, + 0x2900bd70, 0x2000bf04, 0xbf00bd70, 0x42937803, 0x3001d105, 0xf04f3901, 0xd1f70300, 0xeb09e005, + 0x2205010c, 0xe9c12301, 0x46182002, 0xbf00bd70, 0xf240b570, 0xf2c00304, 0xf04f0300, 0xeb090c03, + 0x24000503, 0xf849078e, 0xe9c5c003, 0x60ec4401, 0xeb09d005, 0xe9c00003, 0x2065c102, 0xf648bd70, + 0xf2c076ff, 0xeb0906ff, 0x24020503, 0x606c42b0, 0xeb09d906, 0x22040103, 0x2002e9c1, 0xbd702066, + 0x3601180d, 0x0403eb09, 0x0c03f04f, 0xf8c442b5, 0xd906c004, 0x0003eb09, 0xe9c02104, 0x20661502, + 0x2300bd70, 0x0f91ebb3, 0x088cd00b, 0x1f161f05, 0x0f04f856, 0x0f04f845, 0xf8d6f000, 0xd1f73c01, + 0x46182300, 0xbf00bd70, 0xf240b570, 0xf2c00c04, 0x23040c00, 0x300cf849, 0x030ceb09, 0x0e00f04f, + 0xe9c30784, 0xf8c3ee01, 0xd006e00c, 0x010ceb09, 0xe9c12203, 0x20652002, 0xeb09bd70, 0xf04f030c, + 0x078c0e01, 0xe004f8c3, 0xeb09d006, 0x2203000c, 0x2102e9c0, 0xbd702065, 0x7efff648, 0x0efff2c0, + 0x030ceb09, 0x45702402, 0xd906605c, 0x010ceb09, 0xe9c12204, 0x20662002, 0x180bbd70, 0x0501f10e, + 0x040ceb09, 0x42ab2603, 0xd9066066, 0x000ceb09, 0xe9c02104, 0x20661302, 0x2500bd70, 0x0f91ebb5, + 0x060ceb09, 0x0504f04f, 0xd0116075, 0xbf000889, 0x68156806, 0xd10542ae, 0x39013004, 0x0204f102, + 0xe005d1f6, 0x010ceb09, 0x46032206, 0x2002e9c1, 0xbd704618, 0x1030f240, 0x00fff2c0, 0x31016801, + 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, 0xf3616849, 0x4770200b, 0x2020f240, 0x00fff2c0, + 0x31016801, 0x6800bf14, 0x5080f44f, 0xbf004770, 0x2024f240, 0x00fff2c0, 0x31016801, 0x6800bf14, + 0x7000f44f, 0xbf004770, 0x47702000, 0x47702000, 0xf7ffb510, 0x4604ffe1, 0xffeaf7ff, 0xf004fb00, + 0xbf00bd10, 0x42814401, 0x2001bf9c, 0xbf004770, 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf244288, + 0x47702001, 0xbf00e7f4, 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, 0x47702069, 0xb240b580, + 0xf851a105, 0xf2490020, 0xf2c55104, 0x60080103, 0xf80af000, 0xbd802000, 0x00000000, 0x00000002, + 0x00000001, 0x00000000, 0x4000f249, 0x0003f2c5, 0x29006801, 0x4770d0fc, 0xf249b580, 0xf2c5500c, + 0x21010003, 0xf7ff6001, 0xbd80ffef, 0xb082b580, 0x98019001, 0x31fff04f, 0xf7ff6001, 0xb002ffe5, + 0xbf00bd80, 0x47702069, 0xf7ffb5b0, 0xb148ffa1, 0x25004604, 0xf7ff4628, 0xf7ffffe9, 0x4405ff7d, + 0xd3f742a5, 0xbdb02000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000039, + 'pc_program_page': 0x200001b5, + 'pc_erase_sector': 0x200000a9, + 'pc_eraseAll': 0x20000085, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000448, + 'begin_stack' : 0x20003460, + 'end_stack' : 0x20002460, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x1000, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000460, + 0x20001460 + ], + 'min_program_length' : 0x1000, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x448, + 'rw_start': 0x44c, + 'rw_size': 0x4, + 'zi_start': 0x450, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0xff8000, + 'flash_size': 0x1000, + 'sector_sizes': ( + (0x0, 0x1000), + ) +} + +class NRF91XX(NRF91): + MEMORY_MAP = MemoryMap( + FlashRegion( + start=0x0, + length=0x100000, + blocksize=0x1000, + is_boot_memory=True, + algo=FLASH_ALGO, + ), + # User Information Configation Registers (UICR) as a flash region + FlashRegion( + start=0x00ff8000, + length=0x1000, + blocksize=0x1000, + is_testable=False, + is_erasable=False, + algo=FLASH_ALGO_UICR, + ), + RamRegion(start=0x20000000, length=0x40000), + ) + + def __init__(self, session): + super(NRF91XX, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("nrf9160.svd") From 814a0b17132ad22b6d5637f42424cde8a6c57d47 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Mon, 10 Jul 2023 11:04:59 +0200 Subject: [PATCH 08/25] family: nRF91: add UICR region to pack based target Signed-off-by: Maximilian Deubel --- pyocd/target/builtin/target_nRF91xx.py | 82 +---------------------- pyocd/target/family/target_nRF91.py | 92 ++++++++++++++++++++++++++ 2 files changed, 93 insertions(+), 81 deletions(-) diff --git a/pyocd/target/builtin/target_nRF91xx.py b/pyocd/target/builtin/target_nRF91xx.py index 6db86902e..9926926e8 100644 --- a/pyocd/target/builtin/target_nRF91xx.py +++ b/pyocd/target/builtin/target_nRF91xx.py @@ -30,7 +30,7 @@ from ...core.memory_map import FlashRegion, RamRegion, MemoryMap from ...debug.svd.loader import SVDFile -from ..family.target_nRF91 import NRF91 +from ..family.target_nRF91 import NRF91, FLASH_ALGO_UICR FLASH_ALGO = { 'load_address' : 0x20000000, @@ -119,86 +119,6 @@ ) } -FLASH_ALGO_UICR = { - 'load_address' : 0x20000000, - - # Flash algorithm as a hex string - 'instructions': [ - 0xe7fdbe00, - 0xf240b570, 0xf2c00604, 0x25000600, 0x0006eb09, 0x5006f849, 0x5501e9c0, 0xb2d060c5, 0xf0004614, - 0x2800f9c9, 0xeb09bf1e, 0xe9c10106, 0x46050402, 0xbd704628, 0x4604b510, 0xf0002000, 0xf240f9bb, - 0x28000104, 0x0100f2c0, 0xeb09bf1c, 0xe9c20201, 0xeb090402, 0x68920201, 0xbf082a00, 0xf244bd10, - 0xf2c20200, 0x23010200, 0xf8596013, 0x44493001, 0x684b6053, 0x688b6093, 0x68c960d3, 0xbd106111, - 0xf240b580, 0xf2c00004, 0x21010000, 0x1000f849, 0x21004448, 0x1101e9c0, 0xf00060c1, 0x2000f9ad, - 0xbf00bd80, 0xf240b510, 0xf2c00004, 0x21020000, 0x1000f849, 0x24004448, 0x4401e9c0, 0xf00060c4, - 0x4601f93b, 0x0000f248, 0x00fff2c0, 0xf00022ff, 0xb138f80f, 0xf9a6f000, 0xd0052869, 0x28004604, - 0x2400bf08, 0xbd104620, 0x46202400, 0xbf00bd10, 0xf240b570, 0xf2c00c04, 0x23050c00, 0x300cf849, - 0x030ceb09, 0x0e00f04f, 0xe9c30784, 0xf8c3ee01, 0xd006e00c, 0x010ceb09, 0xe9c12203, 0x20652002, - 0xeb09bd70, 0xf04f030c, 0x078c0e01, 0xe004f8c3, 0xeb09d006, 0x2203000c, 0x2102e9c0, 0xbd702065, - 0x7efff648, 0x0efff2c0, 0x030ceb09, 0x45702402, 0xd906605c, 0x010ceb09, 0xe9c12204, 0x20662002, - 0x180bbd70, 0x0501f10e, 0x040ceb09, 0x42ab2603, 0xd9066066, 0x000ceb09, 0xe9c02104, 0x20661302, - 0x2900bd70, 0x2000bf04, 0xbf00bd70, 0x42937803, 0x3001d105, 0xf04f3901, 0xd1f70300, 0xeb09e005, - 0x2205010c, 0xe9c12301, 0x46182002, 0xbf00bd70, 0xf240b570, 0xf2c00304, 0xf04f0300, 0xeb090c03, - 0x24000503, 0xf849078e, 0xe9c5c003, 0x60ec4401, 0xeb09d005, 0xe9c00003, 0x2065c102, 0xf648bd70, - 0xf2c076ff, 0xeb0906ff, 0x24020503, 0x606c42b0, 0xeb09d906, 0x22040103, 0x2002e9c1, 0xbd702066, - 0x3601180d, 0x0403eb09, 0x0c03f04f, 0xf8c442b5, 0xd906c004, 0x0003eb09, 0xe9c02104, 0x20661502, - 0x2300bd70, 0x0f91ebb3, 0x088cd00b, 0x1f161f05, 0x0f04f856, 0x0f04f845, 0xf8d6f000, 0xd1f73c01, - 0x46182300, 0xbf00bd70, 0xf240b570, 0xf2c00c04, 0x23040c00, 0x300cf849, 0x030ceb09, 0x0e00f04f, - 0xe9c30784, 0xf8c3ee01, 0xd006e00c, 0x010ceb09, 0xe9c12203, 0x20652002, 0xeb09bd70, 0xf04f030c, - 0x078c0e01, 0xe004f8c3, 0xeb09d006, 0x2203000c, 0x2102e9c0, 0xbd702065, 0x7efff648, 0x0efff2c0, - 0x030ceb09, 0x45702402, 0xd906605c, 0x010ceb09, 0xe9c12204, 0x20662002, 0x180bbd70, 0x0501f10e, - 0x040ceb09, 0x42ab2603, 0xd9066066, 0x000ceb09, 0xe9c02104, 0x20661302, 0x2500bd70, 0x0f91ebb5, - 0x060ceb09, 0x0504f04f, 0xd0116075, 0xbf000889, 0x68156806, 0xd10542ae, 0x39013004, 0x0204f102, - 0xe005d1f6, 0x010ceb09, 0x46032206, 0x2002e9c1, 0xbd704618, 0x1030f240, 0x00fff2c0, 0x31016801, - 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, 0xf3616849, 0x4770200b, 0x2020f240, 0x00fff2c0, - 0x31016801, 0x6800bf14, 0x5080f44f, 0xbf004770, 0x2024f240, 0x00fff2c0, 0x31016801, 0x6800bf14, - 0x7000f44f, 0xbf004770, 0x47702000, 0x47702000, 0xf7ffb510, 0x4604ffe1, 0xffeaf7ff, 0xf004fb00, - 0xbf00bd10, 0x42814401, 0x2001bf9c, 0xbf004770, 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf244288, - 0x47702001, 0xbf00e7f4, 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, 0x47702069, 0xb240b580, - 0xf851a105, 0xf2490020, 0xf2c55104, 0x60080103, 0xf80af000, 0xbd802000, 0x00000000, 0x00000002, - 0x00000001, 0x00000000, 0x4000f249, 0x0003f2c5, 0x29006801, 0x4770d0fc, 0xf249b580, 0xf2c5500c, - 0x21010003, 0xf7ff6001, 0xbd80ffef, 0xb082b580, 0x98019001, 0x31fff04f, 0xf7ff6001, 0xb002ffe5, - 0xbf00bd80, 0x47702069, 0xf7ffb5b0, 0xb148ffa1, 0x25004604, 0xf7ff4628, 0xf7ffffe9, 0x4405ff7d, - 0xd3f742a5, 0xbdb02000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 - ], - - # Relative function addresses - 'pc_init': 0x20000005, - 'pc_unInit': 0x20000039, - 'pc_program_page': 0x200001b5, - 'pc_erase_sector': 0x200000a9, - 'pc_eraseAll': 0x20000085, - - 'static_base' : 0x20000000 + 0x00000004 + 0x00000448, - 'begin_stack' : 0x20003460, - 'end_stack' : 0x20002460, - 'begin_data' : 0x20000000 + 0x1000, - 'page_size' : 0x1000, - 'analyzer_supported' : False, - 'analyzer_address' : 0x00000000, - # Enable double buffering - 'page_buffers' : [ - 0x20000460, - 0x20001460 - ], - 'min_program_length' : 0x1000, - - # Relative region addresses and sizes - 'ro_start': 0x4, - 'ro_size': 0x448, - 'rw_start': 0x44c, - 'rw_size': 0x4, - 'zi_start': 0x450, - 'zi_size': 0x10, - - # Flash information - 'flash_start': 0xff8000, - 'flash_size': 0x1000, - 'sector_sizes': ( - (0x0, 0x1000), - ) -} - class NRF91XX(NRF91): MEMORY_MAP = MemoryMap( FlashRegion( diff --git a/pyocd/target/family/target_nRF91.py b/pyocd/target/family/target_nRF91.py index e798371e0..7080af17e 100644 --- a/pyocd/target/family/target_nRF91.py +++ b/pyocd/target/family/target_nRF91.py @@ -24,6 +24,7 @@ from intelhex import IntelHex from ...core import exceptions +from ...core.memory_map import FlashRegion from ...core.target import Target from ...coresight.coresight_target import CoreSightTarget from ...flash.eraser import FlashEraser @@ -301,6 +302,85 @@ def split_addr_range_into_chunks(range, chunk_size): break return chunks +FLASH_ALGO_UICR = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0xf240b570, 0xf2c00604, 0x25000600, 0x0006eb09, 0x5006f849, 0x5501e9c0, 0xb2d060c5, 0xf0004614, + 0x2800f9c9, 0xeb09bf1e, 0xe9c10106, 0x46050402, 0xbd704628, 0x4604b510, 0xf0002000, 0xf240f9bb, + 0x28000104, 0x0100f2c0, 0xeb09bf1c, 0xe9c20201, 0xeb090402, 0x68920201, 0xbf082a00, 0xf244bd10, + 0xf2c20200, 0x23010200, 0xf8596013, 0x44493001, 0x684b6053, 0x688b6093, 0x68c960d3, 0xbd106111, + 0xf240b580, 0xf2c00004, 0x21010000, 0x1000f849, 0x21004448, 0x1101e9c0, 0xf00060c1, 0x2000f9ad, + 0xbf00bd80, 0xf240b510, 0xf2c00004, 0x21020000, 0x1000f849, 0x24004448, 0x4401e9c0, 0xf00060c4, + 0x4601f93b, 0x0000f248, 0x00fff2c0, 0xf00022ff, 0xb138f80f, 0xf9a6f000, 0xd0052869, 0x28004604, + 0x2400bf08, 0xbd104620, 0x46202400, 0xbf00bd10, 0xf240b570, 0xf2c00c04, 0x23050c00, 0x300cf849, + 0x030ceb09, 0x0e00f04f, 0xe9c30784, 0xf8c3ee01, 0xd006e00c, 0x010ceb09, 0xe9c12203, 0x20652002, + 0xeb09bd70, 0xf04f030c, 0x078c0e01, 0xe004f8c3, 0xeb09d006, 0x2203000c, 0x2102e9c0, 0xbd702065, + 0x7efff648, 0x0efff2c0, 0x030ceb09, 0x45702402, 0xd906605c, 0x010ceb09, 0xe9c12204, 0x20662002, + 0x180bbd70, 0x0501f10e, 0x040ceb09, 0x42ab2603, 0xd9066066, 0x000ceb09, 0xe9c02104, 0x20661302, + 0x2900bd70, 0x2000bf04, 0xbf00bd70, 0x42937803, 0x3001d105, 0xf04f3901, 0xd1f70300, 0xeb09e005, + 0x2205010c, 0xe9c12301, 0x46182002, 0xbf00bd70, 0xf240b570, 0xf2c00304, 0xf04f0300, 0xeb090c03, + 0x24000503, 0xf849078e, 0xe9c5c003, 0x60ec4401, 0xeb09d005, 0xe9c00003, 0x2065c102, 0xf648bd70, + 0xf2c076ff, 0xeb0906ff, 0x24020503, 0x606c42b0, 0xeb09d906, 0x22040103, 0x2002e9c1, 0xbd702066, + 0x3601180d, 0x0403eb09, 0x0c03f04f, 0xf8c442b5, 0xd906c004, 0x0003eb09, 0xe9c02104, 0x20661502, + 0x2300bd70, 0x0f91ebb3, 0x088cd00b, 0x1f161f05, 0x0f04f856, 0x0f04f845, 0xf8d6f000, 0xd1f73c01, + 0x46182300, 0xbf00bd70, 0xf240b570, 0xf2c00c04, 0x23040c00, 0x300cf849, 0x030ceb09, 0x0e00f04f, + 0xe9c30784, 0xf8c3ee01, 0xd006e00c, 0x010ceb09, 0xe9c12203, 0x20652002, 0xeb09bd70, 0xf04f030c, + 0x078c0e01, 0xe004f8c3, 0xeb09d006, 0x2203000c, 0x2102e9c0, 0xbd702065, 0x7efff648, 0x0efff2c0, + 0x030ceb09, 0x45702402, 0xd906605c, 0x010ceb09, 0xe9c12204, 0x20662002, 0x180bbd70, 0x0501f10e, + 0x040ceb09, 0x42ab2603, 0xd9066066, 0x000ceb09, 0xe9c02104, 0x20661302, 0x2500bd70, 0x0f91ebb5, + 0x060ceb09, 0x0504f04f, 0xd0116075, 0xbf000889, 0x68156806, 0xd10542ae, 0x39013004, 0x0204f102, + 0xe005d1f6, 0x010ceb09, 0x46032206, 0x2002e9c1, 0xbd704618, 0x1030f240, 0x00fff2c0, 0x31016801, + 0x6800bf1c, 0xf6404770, 0xf2cf71e0, 0x78080100, 0xf3616849, 0x4770200b, 0x2020f240, 0x00fff2c0, + 0x31016801, 0x6800bf14, 0x5080f44f, 0xbf004770, 0x2024f240, 0x00fff2c0, 0x31016801, 0x6800bf14, + 0x7000f44f, 0xbf004770, 0x47702000, 0x47702000, 0xf7ffb510, 0x4604ffe1, 0xffeaf7ff, 0xf004fb00, + 0xbf00bd10, 0x42814401, 0x2001bf9c, 0xbf004770, 0x2b04f850, 0xbf1c3201, 0x47702000, 0xbf244288, + 0x47702001, 0xbf00e7f4, 0xbf004770, 0x47702000, 0x47702003, 0xbf842803, 0x47702069, 0xb240b580, + 0xf851a105, 0xf2490020, 0xf2c55104, 0x60080103, 0xf80af000, 0xbd802000, 0x00000000, 0x00000002, + 0x00000001, 0x00000000, 0x4000f249, 0x0003f2c5, 0x29006801, 0x4770d0fc, 0xf249b580, 0xf2c5500c, + 0x21010003, 0xf7ff6001, 0xbd80ffef, 0xb082b580, 0x98019001, 0x31fff04f, 0xf7ff6001, 0xb002ffe5, + 0xbf00bd80, 0x47702069, 0xf7ffb5b0, 0xb148ffa1, 0x25004604, 0xf7ff4628, 0xf7ffffe9, 0x4405ff7d, + 0xd3f742a5, 0xbdb02000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000039, + 'pc_program_page': 0x200001b5, + 'pc_erase_sector': 0x200000a9, + 'pc_eraseAll': 0x20000085, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000448, + 'begin_stack' : 0x20003460, + 'end_stack' : 0x20002460, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x1000, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000460, + 0x20001460 + ], + 'min_program_length' : 0x1000, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x448, + 'rw_start': 0x44c, + 'rw_size': 0x4, + 'zi_start': 0x450, + 'zi_size': 0x10, + + # Flash information + 'flash_start': 0xff8000, + 'flash_size': 0x1000, + 'sector_sizes': ( + (0x0, 0x1000), + ) +} class NRF91(CoreSightTarget): @@ -308,6 +388,18 @@ class NRF91(CoreSightTarget): def __init__(self, session, memory_map=None): super(NRF91, self).__init__(session, memory_map) + if memory_map.get_region_for_address(0x00ff8000) is None: + LOG.debug("Adding UICR region") + memory_map.add_region( + FlashRegion( + start=0x00ff8000, + length=0x1000, + blocksize=0x1000, + is_testable=False, + is_erasable=False, + algo=FLASH_ALGO_UICR, + ) + ) self.ctrl_ap = None self.was_locked = False From 08359a34c2a488467a94b995fcc88cf36c61e3f8 Mon Sep 17 00:00:00 2001 From: Maximilian Deubel Date: Wed, 12 Jul 2023 12:48:24 +0200 Subject: [PATCH 09/25] family: nRF91: add modem update command Signed-off-by: Maximilian Deubel --- pyocd/target/family/target_nRF91.py | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/pyocd/target/family/target_nRF91.py b/pyocd/target/family/target_nRF91.py index 7080af17e..72d947aad 100644 --- a/pyocd/target/family/target_nRF91.py +++ b/pyocd/target/family/target_nRF91.py @@ -31,6 +31,8 @@ from ...flash.file_programmer import FileProgrammer from ...utility.timeout import Timeout from ...utility.progress import print_progress +from ...commands.base import CommandBase +from ...commands.execution_context import CommandSet from typing import (Callable, Optional, TYPE_CHECKING, Union) ProgressCallback = Callable[[Union[int, float]], None] @@ -382,6 +384,40 @@ def split_addr_range_into_chunks(range, chunk_size): ) } +class nRF91ModemFirmwareUpdateCommand(CommandBase): + INFO = { + 'names': ['nrf91-update-modem-fw'], + 'group': 'nrf91', + 'category': 'nrf91', + 'nargs': '*', + 'usage': "[-f] mfw_nrf91xx_x.x.x.zip", + 'help': "Update modem firmware for an nRF91 target.", + 'extra_help': + "If -f is specified, modem firmware is written to the device, " + "even if the correct version is already present." + } + + file_path = "" + needs_update = False + + def parse(self, args): + if len(args) == 0 or not args[-1].endswith(".zip"): + raise exceptions.CommandError(f"invalid argument") + self.file_path = args[-1] + for a in args: + if a == '-f': + self.needs_update = True + + + def execute(self): + if not self.needs_update: + try: + ModemUpdater(self.context.session).verify(self.file_path) + except: + self.needs_update = True + if self.needs_update: + ModemUpdater(self.context.session).program_and_verify(self.file_path) + class NRF91(CoreSightTarget): VENDOR = "Nordic Semiconductor" @@ -571,6 +607,9 @@ def write_flash(self, addr: int, bytes): self.write32(0x50039504, 0) # NVMC.CONFIG = ReadOnly self._wait_nvmc_ready() + def add_target_command_groups(self, command_set: CommandSet) -> None: + command_set.add_command_group('nrf91') + def _wait_nvmc_ready(self): with Timeout(MASS_ERASE_TIMEOUT) as to: while to.check(): From 59d3b4206f15cffd627eada2f3ce4143f9b659e4 Mon Sep 17 00:00:00 2001 From: Giulio Girardi Date: Wed, 26 Jul 2023 23:46:40 +0200 Subject: [PATCH 10/25] coresight: add Trace Funnel component (#1592) * Add Trace Funnel Coresight component The Trace Funnel is automatically configured to enable all inputs. --- pyocd/coresight/component_ids.py | 5 ++- pyocd/coresight/funnel.py | 75 ++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 2 deletions(-) create mode 100644 pyocd/coresight/funnel.py diff --git a/pyocd/coresight/component_ids.py b/pyocd/coresight/component_ids.py index 6f03edb4b..8b8b8284b 100644 --- a/pyocd/coresight/component_ids.py +++ b/pyocd/coresight/component_ids.py @@ -26,6 +26,7 @@ from .tpiu import TPIU from .gpr import GPR from .sdc600 import SDC600 +from .funnel import TraceFunnel if TYPE_CHECKING: from .component import CoreSightComponent @@ -120,7 +121,7 @@ class CmpInfo(NamedTuple): (ARM_ID, CORESIGHT_CLASS, 0x193, 0x00, 0x0a57) : CmpInfo('TSGEN', 'CS-600', None ), (ARM_ID, CORESIGHT_CLASS, 0x906, 0x14, 0) : CmpInfo('CTI', 'CS-400', None ), (ARM_ID, CORESIGHT_CLASS, 0x907, 0x21, 0) : CmpInfo('ETB', 'CS-400', None ), - (ARM_ID, CORESIGHT_CLASS, 0x908, 0x12, 0) : CmpInfo('Trace Funnel', 'CS-400', None ), + (ARM_ID, CORESIGHT_CLASS, 0x908, 0x12, 0) : CmpInfo('Trace Funnel', 'CS-400', TraceFunnel.factory ), (ARM_ID, CORESIGHT_CLASS, 0x909, 0x22, 0) : CmpInfo('Trace Replicator',None, None ), (ARM_ID, CORESIGHT_CLASS, 0x912, 0x11, 0) : CmpInfo('TPIU', 'CS-400', TPIU.factory ), (ARM_ID, CORESIGHT_CLASS, 0x913, 0x43, 0) : CmpInfo('ITM', 'CS-400', None ), @@ -159,7 +160,7 @@ class CmpInfo(NamedTuple): (ARM_ID, CORESIGHT_CLASS, 0x9e8, 0x21, 0) : CmpInfo('ETR', 'CS-600', None ), (ARM_ID, CORESIGHT_CLASS, 0x9e9, 0x21, 0) : CmpInfo('ETB', 'CS-600', None ), (ARM_ID, CORESIGHT_CLASS, 0x9ea, 0x32, 0) : CmpInfo('ETF', 'CS-600', None ), - (ARM_ID, CORESIGHT_CLASS, 0x9eb, 0x12, 0) : CmpInfo('ATB Funnel', 'CS-600', None ), + (ARM_ID, CORESIGHT_CLASS, 0x9eb, 0x12, 0) : CmpInfo('ATB Funnel', 'CS-600', TraceFunnel.factory ), (ARM_ID, CORESIGHT_CLASS, 0x9ec, 0x22, 0) : CmpInfo('ATB Replicator', 'CS-600', None ), (ARM_ID, CORESIGHT_CLASS, 0x9ed, 0x14, 0x1a14) : CmpInfo('CTI', 'CS-600', None ), (ARM_ID, CORESIGHT_CLASS, 0x9ee, 0x00, 0) : CmpInfo('CATU', 'CS-600', None ), diff --git a/pyocd/coresight/funnel.py b/pyocd/coresight/funnel.py new file mode 100644 index 000000000..6c7495feb --- /dev/null +++ b/pyocd/coresight/funnel.py @@ -0,0 +1,75 @@ +# pyOCD debugger +# Copyright (c) 2023 Protech Engineering +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import logging + +from .component import CoreSightComponent + +LOG = logging.getLogger(__name__) + +class TraceFunnel(CoreSightComponent): + """@brief CoreSight Trace Funnel""" + + # Register definitions. + # + # The addresses are offsets from the base address. + CSTF = 0x00000000 + CSTF_ENSX_MASK = 0xFF + + DEVID = 0x00000FC8 + DEVID_PORTCOUNT_MASK = 0xF + + def __init__(self, ap, cmpid=None, addr=None): + """@brief Standard CoreSight component constructor.""" + super().__init__(ap, cmpid, addr) + self._available_channels = 2 + + @property + def available_channels(self) -> int: + """@brief Number of input ports connected to the funnel""" + return self._available_channels + + def init(self) -> None: + """@brief Reads Funnel connected channels and enables them all by default.""" + devid = self.ap.read32(self.address + TraceFunnel.DEVID) + self._available_channels = devid & TraceFunnel.DEVID_PORTCOUNT_MASK + self.enable() + + def set_enabled_channels(self, channels: int) -> bool: + """@brief Sets the enabled Trace Funnel channels. + + @param channels Word describing the desired state for the funnel channels. + Setting the n-th bit of this word high enables the corresponding n-th channel, setting it low disables it. + """ + valid_channels_mask = 2**self.available_channels-1 + if channels & ~valid_channels_mask: + LOG.warning(f"Trace Funnel: Trying to enable too many channels. Only {self.available_channels} channels are present") + return False + + cstf = self.ap.read32(self.address + TraceFunnel.CSTF) + cstf = cstf & ~TraceFunnel.CSTF_ENSX_MASK + cstf = cstf | channels + self.ap.write32(self.address + TraceFunnel.CSTF, cstf) + + return True + + def enable(self) -> None: + """@brief Enables all channels""" + self.set_enabled_channels(2**self.available_channels-1) + + def disable(self) -> None: + """@brief Disables all channels""" + self.set_enabled_channels(0x00) From 7e639623619b31267c43a15b56c248ad6066f58e Mon Sep 17 00:00:00 2001 From: lennvn Date: Sat, 29 Jul 2023 04:57:17 +0800 Subject: [PATCH 11/25] targets: added new HDSC target HC32F448 (#1599) Co-authored-by: wuze --- pyocd/debug/svd/data/HC32F448.svd | 60272 ++++++++++++++++++++++ pyocd/target/builtin/__init__.py | 5 + pyocd/target/builtin/target_HC32F448.py | 232 + 3 files changed, 60509 insertions(+) create mode 100644 pyocd/debug/svd/data/HC32F448.svd create mode 100644 pyocd/target/builtin/target_HC32F448.py diff --git a/pyocd/debug/svd/data/HC32F448.svd b/pyocd/debug/svd/data/HC32F448.svd new file mode 100644 index 000000000..211048d04 --- /dev/null +++ b/pyocd/debug/svd/data/HC32F448.svd @@ -0,0 +1,60272 @@ + + + HC32F448 + 1.0 + HC32F448 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + 0x0 + 0xFFFFFFFF + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xB1 + registers + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F7 + + + MS + desc MS + 2 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + CR2 + desc CR2 + 0x6 + 16 + read-write + 0x0 + 0x1F00 + + + OVSS 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INTMSK37 + desc INTMSK37 + 5 + 5 + read-write + + + INTMSK38 + desc INTMSK38 + 6 + 6 + read-write + + + INTMSK39 + desc INTMSK39 + 7 + 7 + read-write + + + INTMSK40 + desc INTMSK40 + 8 + 8 + read-write + + + INTMSK41 + desc INTMSK41 + 9 + 9 + read-write + + + INTMSK42 + desc INTMSK42 + 10 + 10 + read-write + + + INTMSK43 + desc INTMSK43 + 11 + 11 + read-write + + + INTMSK44 + desc INTMSK44 + 12 + 12 + read-write + + + INTMSK45 + desc INTMSK45 + 13 + 13 + read-write + + + INTMSK46 + desc INTMSK46 + 14 + 14 + read-write + + + INTMSK47 + desc INTMSK47 + 15 + 15 + read-write + + + INTMSK48 + desc INTMSK48 + 16 + 16 + read-write + + + INTMSK49 + desc INTMSK49 + 17 + 17 + read-write + + + INTMSK50 + desc INTMSK50 + 18 + 18 + read-write + + + INTMSK51 + desc INTMSK51 + 19 + 19 + read-write + + + INTMSK52 + desc INTMSK52 + 20 + 20 + read-write + + + INTMSK53 + desc INTMSK53 + 21 + 21 + read-write + + + INTMSK54 + desc INTMSK54 + 22 + 22 + read-write + + + INTMSK55 + desc INTMSK55 + 23 + 23 + read-write + + + INTMSK56 + desc INTMSK56 + 24 + 24 + read-write + + + INTMSK57 + desc INTMSK57 + 25 + 25 + read-write + + + INTMSK58 + desc INTMSK58 + 26 + 26 + read-write + + + INTMSK59 + desc INTMSK59 + 27 + 27 + read-write + + + INTMSK60 + desc INTMSK60 + 28 + 28 + read-write + + + INTMSK61 + desc INTMSK61 + 29 + 29 + read-write + + + INTMSK62 + desc INTMSK62 + 30 + 30 + read-write + + + INTMSK63 + desc INTMSK63 + 31 + 31 + read-write + + + + + INTMSK2 + desc INTMSK2 + 0xA4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + INTMSK64 + desc INTMSK64 + 0 + 0 + read-write + + + INTMSK65 + desc INTMSK65 + 1 + 1 + read-write + + + INTMSK66 + desc INTMSK66 + 2 + 2 + read-write + + + INTMSK67 + desc INTMSK67 + 3 + 3 + read-write + + + INTMSK68 + desc INTMSK68 + 4 + 4 + read-write + + + INTMSK69 + desc INTMSK69 + 5 + 5 + read-write + + + INTMSK70 + desc INTMSK70 + 6 + 6 + read-write + + + INTMSK71 + desc INTMSK71 + 7 + 7 + read-write + + + INTMSK72 + desc INTMSK72 + 8 + 8 + read-write + + + INTMSK73 + desc INTMSK73 + 9 + 9 + read-write + + + INTMSK74 + desc INTMSK74 + 10 + 10 + read-write + + + INTMSK75 + desc INTMSK75 + 11 + 11 + read-write + + + INTMSK76 + desc INTMSK76 + 12 + 12 + read-write + + + INTMSK77 + desc INTMSK77 + 13 + 13 + read-write + + + INTMSK78 + desc INTMSK78 + 14 + 14 + read-write + + + INTMSK79 + desc INTMSK79 + 15 + 15 + read-write + + + INTMSK80 + desc INTMSK80 + 16 + 16 + read-write + + + INTMSK81 + desc INTMSK81 + 17 + 17 + read-write + + + INTMSK82 + desc INTMSK82 + 18 + 18 + read-write + + + INTMSK83 + desc INTMSK83 + 19 + 19 + read-write + + + INTMSK84 + desc INTMSK84 + 20 + 20 + read-write + + + INTMSK85 + desc INTMSK85 + 21 + 21 + read-write + + + INTMSK86 + desc INTMSK86 + 22 + 22 + read-write + + + INTMSK87 + desc INTMSK87 + 23 + 23 + read-write + + + INTMSK88 + desc INTMSK88 + 24 + 24 + read-write + + + INTMSK89 + desc INTMSK89 + 25 + 25 + read-write + + + INTMSK90 + desc INTMSK90 + 26 + 26 + read-write + + + INTMSK91 + desc INTMSK91 + 27 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INTMSK126 + 30 + 30 + read-write + + + INTMSK127 + desc INTMSK127 + 31 + 31 + read-write + + + + + INTMSK4 + desc INTMSK4 + 0xAC + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + INTMSK128 + desc INTMSK128 + 0 + 0 + read-write + + + INTMSK129 + desc INTMSK129 + 1 + 1 + read-write + + + INTMSK130 + desc INTMSK130 + 2 + 2 + read-write + + + INTMSK131 + desc INTMSK131 + 3 + 3 + read-write + + + INTMSK132 + desc INTMSK132 + 4 + 4 + read-write + + + INTMSK133 + desc INTMSK133 + 5 + 5 + read-write + + + INTMSK134 + desc INTMSK134 + 6 + 6 + read-write + + + INTMSK135 + desc INTMSK135 + 7 + 7 + read-write + + + INTMSK136 + desc INTMSK136 + 8 + 8 + read-write + + + INTMSK137 + desc INTMSK137 + 9 + 9 + read-write + + + INTMSK138 + desc INTMSK138 + 10 + 10 + read-write + + + INTMSK139 + desc INTMSK139 + 11 + 11 + read-write + + + INTMSK140 + desc INTMSK140 + 12 + 12 + read-write + + + INTMSK141 + desc INTMSK141 + 13 + 13 + read-write + + + INTMSK142 + desc INTMSK142 + 14 + 14 + read-write + + + INTMSK143 + desc INTMSK143 + 15 + 15 + read-write + + + INTMSK144 + desc INTMSK144 + 16 + 16 + read-write + + + INTMSK145 + desc INTMSK145 + 17 + 17 + read-write + + + INTMSK146 + desc INTMSK146 + 18 + 18 + read-write + + + INTMSK147 + desc INTMSK147 + 19 + 19 + read-write + + + INTMSK148 + desc INTMSK148 + 20 + 20 + read-write + + + INTMSK149 + desc INTMSK149 + 21 + 21 + read-write + + + INTMSK150 + desc INTMSK150 + 22 + 22 + read-write + + + INTMSK151 + desc INTMSK151 + 23 + 23 + read-write + + + INTMSK152 + desc INTMSK152 + 24 + 24 + read-write + + + INTMSK153 + desc INTMSK153 + 25 + 25 + read-write + + + INTMSK154 + desc INTMSK154 + 26 + 26 + read-write + + + INTMSK155 + desc INTMSK155 + 27 + 27 + read-write + + + INTMSK156 + desc INTMSK156 + 28 + 28 + read-write + + + INTMSK157 + desc INTMSK157 + 29 + 29 + read-write + + + INTMSK158 + desc INTMSK158 + 30 + 30 + read-write + + + INTMSK159 + desc INTMSK159 + 31 + 31 + read-write + + + + + INTMSK5 + desc INTMSK5 + 0xB0 + 32 + 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INTMSK277 + 17 + 17 + read-write + + + INTMSK278 + desc INTMSK278 + 18 + 18 + read-write + + + INTMSK279 + desc INTMSK279 + 19 + 19 + read-write + + + INTMSK280 + desc INTMSK280 + 20 + 20 + read-write + + + INTMSK281 + desc INTMSK281 + 21 + 21 + read-write + + + INTMSK282 + desc INTMSK282 + 22 + 22 + read-write + + + INTMSK283 + desc INTMSK283 + 23 + 23 + read-write + + + INTMSK284 + desc INTMSK284 + 24 + 24 + read-write + + + INTMSK285 + desc INTMSK285 + 25 + 25 + read-write + + + INTMSK286 + desc INTMSK286 + 26 + 26 + read-write + + + INTMSK287 + desc INTMSK287 + 27 + 27 + read-write + + + INTMSK288 + desc INTMSK288 + 28 + 28 + read-write + + + INTMSK289 + desc INTMSK289 + 29 + 29 + read-write + + + INTMSK290 + desc INTMSK290 + 30 + 30 + read-write + + + INTMSK291 + desc INTMSK291 + 31 + 31 + read-write + + + + + INTMSK6 + desc INTMSK6 + 0xB4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + INTMSK192 + desc INTMSK192 + 0 + 0 + read-write + + + INTMSK193 + desc INTMSK193 + 1 + 1 + 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desc VD2WKE + 1 + 1 + read-write + + + RTCPRDWKE + desc RTCPRDWKE + 4 + 4 + read-write + + + RTCALMWKE + desc RTCALMWKE + 5 + 5 + read-write + + + WKTMWKE + desc WKTMWKE + 7 + 7 + read-write + + + + + PDWKES + desc PDWKES + 0x4C34 + 8 + read-write + 0x0 + 0x3F + + + WK0EGS + desc WK0EGS + 0 + 0 + read-write + + + WK1EGS + desc WK1EGS + 1 + 1 + read-write + + + WK2EGS + desc WK2EGS + 2 + 2 + read-write + + + WK3EGS + desc WK3EGS + 3 + 3 + read-write + + + VD1EGS + desc VD1EGS + 4 + 4 + read-write + + + VD2EGS + desc VD2EGS + 5 + 5 + read-write + + + + + PDWKF0 + desc PDWKF0 + 0x4C38 + 8 + read-write + 0x0 + 0x3F + + + PTWK0F + desc PTWK0F + 0 + 0 + read-write + + + PTWK1F + desc PTWK1F + 1 + 1 + read-write + + + PTWK2F + desc PTWK2F + 2 + 2 + read-write + + + PTWK3F + desc PTWK3F + 3 + 3 + read-write + + + VD1WKF + desc VD1WKF + 4 + 4 + read-write + + + VD2WKF + desc VD2WKF + 5 + 5 + read-write + + + + + PDWKF1 + desc PDWKF1 + 0x4C3C + 8 + read-write + 0x0 + 0xB8 + + + RXD0WKF + desc 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+ 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + CTEND + desc CTEND + 25 + 25 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x13 + + + PSC + desc PSC + 1 + 0 + read-write + + + ULBREN + desc ULBREN + 4 + 4 + read-write + + + + + + + USART6 + desc USART + 0x40021400 + + 0x0 + 0x20 + registers + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + registers + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 0d421bfb6..c75457099 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -111,6 +111,7 @@ from . import target_M460 from . import target_M480 from . import target_M2354 +from . import target_HC32F448 from . import target_HC32F45x from . import target_HC32F460 from . import target_HC32F4A0 @@ -262,14 +263,18 @@ 'm467hjhae' : target_M460.M467HJHAE, 'm487jidae' : target_M480.M487JIDAE, 'm2354kjfae' : target_M2354.M2354KJFAE, + 'hc32f448xa' : target_HC32F448.HC32F448xA, + 'hc32f448xc' : target_HC32F448.HC32F448xC, 'hc32f451xc' : target_HC32F45x.HC32F451xC, 'hc32f451xe' : target_HC32F45x.HC32F451xE, 'hc32f452xc' : target_HC32F45x.HC32F452xC, 'hc32f452xe' : target_HC32F45x.HC32F452xE, 'hc32f460xc' : target_HC32F460.HC32F460xC, 'hc32f460xe' : target_HC32F460.HC32F460xE, + 'hc32a460xe' : target_HC32F460.HC32F460xE, 'hc32f4a0xg' : target_HC32F4A0.HC32F4A0xG, 'hc32f4a0xi' : target_HC32F4A0.HC32F4A0xI, + 'hc32a4a0xi' : target_HC32F4A0.HC32F4A0xI, 'hc32m423xa' : target_HC32M423.HC32M423xA, 'hc32f120x6' : target_HC32x120.HC32F120x6TA, 'hc32f120x8' : target_HC32x120.HC32F120x8TA, diff --git a/pyocd/target/builtin/target_HC32F448.py b/pyocd/target/builtin/target_HC32F448.py new file mode 100644 index 000000000..1e54fd7fe --- /dev/null +++ b/pyocd/target/builtin/target_HC32F448.py @@ -0,0 +1,232 @@ +# pyOCD debugger +# Copyright (c) 2022 Huada Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + + +class DBGMCU: + STPCTL = 0xE0042020 + STPCTL_VALUE = 0x7FFFFF + + STPCTL1 = 0xE0042028 + STPCTL1_VALUE = 0xFFF + + TRACECTL = 0xE0042024 + TRACECTL_VALUE = 0x0 + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xE00ABE00, + 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x0030ea4f, 0x00004770, + 0x0030ea4f, 0x00004770, 0x0030ea4f, 0x00004770, 0x49052000, 0x49057008, 0x20016008, 0x39264902, + 0x002af881, 0x00004770, 0x40054026, 0x40010418, 0x6800480d, 0x0001f000, 0x480cb118, 0x6008490c, + 0x480ce002, 0x6008490a, 0x490b2003, 0x480b6008, 0x6208490b, 0x490a2000, 0x7008312a, 0x49082005, + 0x0026f881, 0x00004770, 0x40010684, 0x33306381, 0x40054100, 0x33304f81, 0x40010418, 0x00116310, + 0x40054000, 0xf000b510, 0xbd10f83f, 0x4604b510, 0xf0004620, 0xbd10f8a3, 0x49142000, 0xf44f6008, + 0x49133040, 0x20006008, 0x60081f09, 0x391c4910, 0x20016008, 0x7008490f, 0x490e480f, 0xf8c13926, + 0x20000100, 0x20016208, 0x1d09490a, 0x480b7008, 0x6008490b, 0x604812c0, 0x6108480a, 0x4025f44f, + 0x39264904, 0x03fef8a1, 0x00004770, 0x40010590, 0x4001041c, 0x40054026, 0x11101300, 0xfffffa0e, + 0x40048000, 0xa5a50000, 0xf000b570, 0xf240f989, 0x492e1005, 0x25006008, 0x2000148c, 0xe0076020, + 0x482b1c6d, 0xd3034285, 0xf97af000, 0xbd702001, 0x1d004826, 0xf4006800, 0xf5b07080, 0xd1ef7f80, + 0x4822e007, 0x68003008, 0x0010f040, 0x3108491f, 0x481e6008, 0x68001d00, 0x0010f000, 0xd1f02800, + 0x491a2004, 0x4c1b6008, 0x60202000, 0xf958f000, 0x4816e007, 0x68003008, 0x0010f040, 0x31084913, + 0x48126008, 0x68001d00, 0x0010f000, 0xd1f02800, 0x490e2004, 0x4c106008, 0x60202000, 0xf940f000, + 0x480ae007, 0x68003008, 0x0010f040, 0x31084907, 0x48066008, 0x68001d00, 0x0010f000, 0xd1f02800, + 0x60084902, 0xf92cf000, 0xe7b02000, 0x4001041c, 0x00061a80, 0x03002000, 0x03004000, 0x4604b570, + 0xf0002500, 0x2004f91d, 0x60084915, 0x60202000, 0x1c6de007, 0x42854813, 0xf000d303, 0x2001f911, + 0x480fbd70, 0x68001d00, 0x7080f400, 0x7f80f5b0, 0xe007d1ef, 0x3008480a, 0xf0406800, 0x49080010, + 0x60083108, 0x1d004806, 0xf0006800, 0x28000010, 0x4903d1f0, 0xf0006008, 0x2000f8f3, 0x0000e7e0, + 0x4001041c, 0x00061a80, 0xf000b510, 0xf240f8e9, 0x49101023, 0xf2436008, 0x60082010, 0x30fff04f, + 0x6008490d, 0x490b480d, 0x60081d09, 0x600843c0, 0x4908480b, 0x60083118, 0x1d0912c0, 0xf24a6008, + 0x49085001, 0xf7ff8008, 0xf7fffec3, 0xf000fed1, 0xbd10f8c7, 0x40010400, 0x40010590, 0x01234567, + 0x00080005, 0x400543fe, 0x43f8e92d, 0x460c4605, 0xf6494616, 0x90004040, 0xf24046b0, 0x492b1003, + 0x462f6008, 0x4040f649, 0xbf009000, 0xf8a8f000, 0x0000f8d8, 0x20006038, 0xe00c9000, 0x1c409800, + 0xf6499000, 0x98004140, 0xd3044288, 0xf898f000, 0xe8bd2001, 0x481d83f8, 0x68001d00, 0x0010f000, + 0xd1eb2810, 0x4819e007, 0x68003008, 0x0010f040, 0x31084916, 0x48156008, 0x68001d00, 0x0010f000, + 0xd0f02810, 0x0804f108, 0x1f241d3f, 0xd2cd2c04, 0x490e2000, 0x90006008, 0x9800e00b, 0x90001c40, + 0x4140f649, 0x42889800, 0xf000d303, 0x2001f869, 0x4806e7cf, 0x68001d00, 0x7080f400, 0x7f80f5b0, + 0xf000d1eb, 0x2000f85d, 0x0000e7c3, 0x4001041c, 0x4604b570, 0x4616460d, 0xff66f7ff, 0xbd702000, + 0x4604b570, 0x4616460d, 0x46294632, 0xf7ff4620, 0xbd70ff8b, 0x49034802, 0x48036008, 0x47706008, + 0xffff0123, 0x40049408, 0xffff3210, 0x4604b510, 0xfe72f7ff, 0xbd102000, 0x4604b5f0, 0x2300460d, + 0x27002600, 0x21004626, 0xf856e007, 0x6810cb04, 0xd0004584, 0x1d12e004, 0xebb11c49, 0xd3f40f95, + 0x4637bf00, 0xe0062300, 0xcb01f817, 0x45845cd0, 0xe004d000, 0xf0051c5b, 0x42980003, 0xbf00d8f4, + 0x0081eb04, 0xbdf04418, 0x49034802, 0x48036088, 0x47706088, 0xffff0123, 0x40049000, 0xffff3210, + 0x4807b500, 0xf4006800, 0xb9083080, 0xf854f000, 0x68004803, 0x0001f000, 0xf000b908, 0xbd00f809, + 0x40010680, 0x1e01bf00, 0x0001f1a0, 0x4770d1fb, 0x481fb510, 0xb2826800, 0x6800481e, 0x0481f3c0, + 0x6800481c, 0x2303f3c0, 0x1192b90c, 0x2c01e008, 0x1292d101, 0x2c02e004, 0x1312d101, 0x1392e000, + 0x2b0fb10b, 0xf7ffd102, 0xe020ff85, 0x0001f003, 0xb9e2b118, 0xff7ef7ff, 0xf003e019, 0x28020002, + 0x2a01d104, 0xf7ffd113, 0xe010ff75, 0x0004f003, 0xd1042804, 0xd10a2a02, 0xff6cf7ff, 0xf003e007, + 0x28080008, 0x2a03d103, 0xf7ffd101, 0xbd10ff63, 0x40049404, 0x40010680, 0x4823b510, 0xb2826840, + 0x68004822, 0x4481f3c0, 0x68004820, 0x6303f3c0, 0x1192b90c, 0x2c01e008, 0x1292d101, 0x2c02e004, + 0x1312d101, 0x1392e000, 0x2001b90b, 0x2000e000, 0xd1012b0f, 0xe0002101, 0x43082100, 0xf7ffb110, + 0xe020ff73, 0x0001f003, 0xb9e2b118, 0xff6cf7ff, 0xf003e019, 0x28020002, 0x2a01d104, 0xf7ffd113, + 0xe010ff63, 0x0004f003, 0xd1042804, 0xd10a2a02, 0xff5af7ff, 0xf003e007, 0x28080008, 0x2a03d103, + 0xf7ffd101, 0xbd10ff51, 0x40049000, 0x40010680, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000395, + 'pc_unInit': 0x200003d1, + 'pc_program_page': 0x200003a5, + 'pc_erase_sector': 0x200000b1, + 'pc_eraseAll': 0x200000a9, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000590, + 'begin_stack' : 0x20000800, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x200, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + 'page_buffers' : [0x20001000, 0x20001200], # Enable double buffering + 'min_program_length' : 0x200, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x40000, + 'sector_sizes': ( + (0x0, 0x2000), + ) +} + + +FLASH_ALGO_OTP = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xE00ABE00, + 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x0030ea4f, 0x00004770, + 0x0030ea4f, 0x00004770, 0x0030ea4f, 0x00004770, 0x49052000, 0x49057008, 0x20016008, 0x39264902, + 0x002af881, 0x00004770, 0x40054026, 0x40010418, 0x6800480d, 0x0001f000, 0x480cb118, 0x6008490c, + 0x480ce002, 0x6008490a, 0x490b2003, 0x480b6008, 0x6208490b, 0x490a2000, 0x7008312a, 0x49082005, + 0x0026f881, 0x00004770, 0x40010684, 0x33306381, 0x40054100, 0x33304f81, 0x40010418, 0x00116310, + 0x40054000, 0xf000b510, 0xbd10f83f, 0x4604b510, 0xf0004620, 0xbd10f83f, 0x49142000, 0xf44f6008, + 0x49133040, 0x20006008, 0x60081f09, 0x391c4910, 0x20016008, 0x7008490f, 0x490e480f, 0xf8c13926, + 0x20000100, 0x20016208, 0x1d09490a, 0x480b7008, 0x6008490b, 0x604812c0, 0x6108480a, 0x4025f44f, + 0x39264904, 0x03fef8a1, 0x00004770, 0x40010590, 0x4001041c, 0x40054026, 0x11101300, 0xfffffa0e, + 0x40048000, 0xa5a50000, 0xf000b510, 0x2000f925, 0x0000bd10, 0x4604b570, 0xf0002500, 0x2004f91d, + 0x60084915, 0x60202000, 0x1c6de007, 0x42854813, 0xf000d303, 0x2001f911, 0x480fbd70, 0x68001d00, + 0x7080f400, 0x7f80f5b0, 0xe007d1ef, 0x3008480a, 0xf0406800, 0x49080010, 0x60083108, 0x1d004806, + 0xf0006800, 0x28000010, 0x4903d1f0, 0xf0006008, 0x2000f8f3, 0x0000e7e0, 0x4001041c, 0x00061a80, + 0xf000b510, 0xf240f8e9, 0x49101023, 0xf2436008, 0x60082010, 0x30fff04f, 0x6008490d, 0x490b480d, + 0x60081d09, 0x600843c0, 0x4908480b, 0x60083118, 0x1d0912c0, 0xf24a6008, 0x49085001, 0xf7ff8008, + 0xf7ffff27, 0xf000ff35, 0xbd10f8c7, 0x40010400, 0x40010590, 0x01234567, 0x00080005, 0x400543fe, + 0x43f8e92d, 0x460c4605, 0xf6494616, 0x90004040, 0xf24046b0, 0x492b1003, 0x462f6008, 0x4040f649, + 0xbf009000, 0xf8a8f000, 0x0000f8d8, 0x20006038, 0xe00c9000, 0x1c409800, 0xf6499000, 0x98004140, + 0xd3044288, 0xf898f000, 0xe8bd2001, 0x481d83f8, 0x68001d00, 0x0010f000, 0xd1eb2810, 0x4819e007, + 0x68003008, 0x0010f040, 0x31084916, 0x48156008, 0x68001d00, 0x0010f000, 0xd0f02810, 0x0804f108, + 0x1f241d3f, 0xd2cd2c04, 0x490e2000, 0x90006008, 0x9800e00b, 0x90001c40, 0x4140f649, 0x42889800, + 0xf000d303, 0x2001f869, 0x4806e7cf, 0x68001d00, 0x7080f400, 0x7f80f5b0, 0xf000d1eb, 0x2000f85d, + 0x0000e7c3, 0x4001041c, 0x4604b570, 0x4616460d, 0xff66f7ff, 0xbd702000, 0x4604b570, 0x4616460d, + 0x46294632, 0xf7ff4620, 0xbd70ff8b, 0x49034802, 0x48036008, 0x47706008, 0xffff0123, 0x40049408, + 0xffff3210, 0x4604b510, 0xfed6f7ff, 0xbd102000, 0x4604b5f0, 0x2300460d, 0x27002600, 0x21004626, + 0xf856e007, 0x6810cb04, 0xd0004584, 0x1d12e004, 0xebb11c49, 0xd3f40f95, 0x4637bf00, 0xe0062300, + 0xcb01f817, 0x45845cd0, 0xe004d000, 0xf0051c5b, 0x42980003, 0xbf00d8f4, 0x0081eb04, 0xbdf04418, + 0x49034802, 0x48036088, 0x47706088, 0xffff0123, 0x40049000, 0xffff3210, 0x4807b500, 0xf4006800, + 0xb9083080, 0xf854f000, 0x68004803, 0x0001f000, 0xf000b908, 0xbd00f809, 0x40010680, 0x1e01bf00, + 0x0001f1a0, 0x4770d1fb, 0x481fb510, 0xb2826800, 0x6800481e, 0x0481f3c0, 0x6800481c, 0x2303f3c0, + 0x1192b90c, 0x2c01e008, 0x1292d101, 0x2c02e004, 0x1312d101, 0x1392e000, 0x2b0fb10b, 0xf7ffd102, + 0xe020ff85, 0x0001f003, 0xb9e2b118, 0xff7ef7ff, 0xf003e019, 0x28020002, 0x2a01d104, 0xf7ffd113, + 0xe010ff75, 0x0004f003, 0xd1042804, 0xd10a2a02, 0xff6cf7ff, 0xf003e007, 0x28080008, 0x2a03d103, + 0xf7ffd101, 0xbd10ff63, 0x40049404, 0x40010680, 0x4823b510, 0xb2826840, 0x68004822, 0x4481f3c0, + 0x68004820, 0x6303f3c0, 0x1192b90c, 0x2c01e008, 0x1292d101, 0x2c02e004, 0x1312d101, 0x1392e000, + 0x2001b90b, 0x2000e000, 0xd1012b0f, 0xe0002101, 0x43082100, 0xf7ffb110, 0xe020ff73, 0x0001f003, + 0xb9e2b118, 0xff6cf7ff, 0xf003e019, 0x28020002, 0x2a01d104, 0xf7ffd113, 0xe010ff63, 0x0004f003, + 0xd1042804, 0xd10a2a02, 0xff5af7ff, 0xf003e007, 0x28080008, 0x2a03d103, 0xf7ffd101, 0xbd10ff51, + 0x40049000, 0x40010680, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x200002cd, + 'pc_unInit': 0x20000309, + 'pc_program_page': 0x200002dd, + 'pc_erase_sector': 0x200000b1, + 'pc_eraseAll': 0x200000a9, + + 'static_base' : 0x20000000 + 0x00000004 + 0x000004c8, + 'begin_stack' : 0x20000700, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + 'page_buffers' : [0x20001000, 0x20001400], # Enable double buffering + 'min_program_length' : 0x400, + + # Flash information + 'flash_start': 0x3000c00, + 'flash_size': 0x400, + 'sector_sizes': ( + (0x0, 0x400), + ) +} + + +class HC32F448xA(CoreSightTarget): + + VENDOR = "HDSC" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x00000000, length=0x20000, page_size=0x200, sector_size=0x2000, + is_boot_memory=True, + algo=FLASH_ALGO), + FlashRegion( start=0x03000C00, length=0x400, page_size=0x400, sector_size=0x400, + is_boot_memory=False, + is_default=False, + algo=FLASH_ALGO_OTP), + RamRegion( start=0x1FFF8000, length=0x10000), + RamRegion( start=0x200F0000, length=0x1000) + ) + + def __init__(self, session): + super(HC32F448xA, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("HC32F448.svd") + + def post_connect_hook(self): + self.write32(DBGMCU.STPCTL, DBGMCU.STPCTL_VALUE) + self.write32(DBGMCU.STPCTL1, DBGMCU.STPCTL1_VALUE) + self.write32(DBGMCU.TRACECTL, DBGMCU.TRACECTL_VALUE) + + +class HC32F448xC(CoreSightTarget): + + VENDOR = "HDSC" + + MEMORY_MAP = MemoryMap( + FlashRegion( start=0x00000000, length=0x40000, page_size=0x200, sector_size=0x2000, + is_boot_memory=True, + algo=FLASH_ALGO), + FlashRegion( start=0x03000C00, length=0x400, page_size=0x400, sector_size=0x400, + is_boot_memory=False, + is_default=False, + algo=FLASH_ALGO_OTP), + RamRegion( start=0x1FFF8000, length=0x10000), + RamRegion( start=0x200F0000, length=0x1000) + ) + + def __init__(self, session): + super(HC32F448xC, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("HC32F448.svd") + + def post_connect_hook(self): + self.write32(DBGMCU.STPCTL, DBGMCU.STPCTL_VALUE) + self.write32(DBGMCU.STPCTL1, DBGMCU.STPCTL1_VALUE) + self.write32(DBGMCU.TRACECTL, DBGMCU.TRACECTL_VALUE) + From 8555b7b6b9300b850194f08ea8670061e48b0e3c Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 23 Jul 2023 17:08:30 -0500 Subject: [PATCH 12/25] coresight: adiv5 discovery: increment invalid AP count on exception (#1593) If an exception is raised when probing an AP, increment the invalid AP count. The scan loop is cleaned up a bit too. --- pyocd/coresight/discovery.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/pyocd/coresight/discovery.py b/pyocd/coresight/discovery.py index 923cb59b3..becb2533c 100644 --- a/pyocd/coresight/discovery.py +++ b/pyocd/coresight/discovery.py @@ -121,22 +121,24 @@ def _find_aps(self): return ap_list = [] - apsel = 0 invalid_count = 0 - while apsel < self.MAX_APSEL: + for apsel in range(self.MAX_APSEL): try: isValid = AccessPort.probe(self.dp, apsel) if isValid: ap_list.append(apsel) invalid_count = 0 - elif not self.session.options.get('scan_all_aps'): + else: invalid_count += 1 - if invalid_count == self.session.options.get('adi.v5.max_invalid_ap_count'): - break except exceptions.Error as e: LOG.error("Error probing AP#%d: %s", apsel, e, exc_info=self.session.log_tracebacks) - apsel += 1 + invalid_count += 1 + + # Stop scanning if we've seen a maximum number of invalid APs, unless `scan_all_aps` is set. + if not self.session.options.get('scan_all_aps') \ + and invalid_count >= self.session.options.get('adi.v5.max_invalid_ap_count'): + break # Update the AP list once we know it's complete. self.dp.valid_aps = ap_list From 28288ae11f11957678bbae3483f0a58ee12d80f8 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 23 Jul 2023 17:08:42 -0500 Subject: [PATCH 13/25] target: family: remove part number match for NXP MIMXRTxxxx series family (#1594) The IMXRT family class isn't needed for pack-based targets any more now that pyOCD supports the debug sequences present in the IMXRT packs. --- pyocd/target/family/__init__.py | 1 - 1 file changed, 1 deletion(-) diff --git a/pyocd/target/family/__init__.py b/pyocd/target/family/__init__.py index 8b650cfaf..7ef8bb893 100644 --- a/pyocd/target/family/__init__.py +++ b/pyocd/target/family/__init__.py @@ -39,7 +39,6 @@ class FamilyInfo(NamedTuple): # present), or the 'Dname' or 'Dvariant' part numbers. The comparisons are performed in order from # specific to general, starting with the part number. FAMILIES = [ - FamilyInfo("NXP", re.compile(r'MIMXRT[0-9]{4}.*'), target_imxrt.IMXRT ), FamilyInfo("NXP", re.compile(r'MK[LEVWS]?.*'), target_kinetis.Kinetis ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF52[0-9]+.*'), target_nRF52.NRF52 ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF91[0-9]+.*'), target_nRF91.NRF91 ), From f84cedad29799fe1c7e1a422fa3cacad1bc18059 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 9 Aug 2023 09:07:21 -0500 Subject: [PATCH 14/25] cleanup: annotations future (#1606) * target, soc_target: use annotations future * cortex_m: annotations future, use .read_core_register_raw() to fix a couple type errors * coresight: dap: annotations future * core: session: annotations future * probe: annotations future Use annotations future for CMSISDAPProbe, DebugProbe, and StlinkProbe. * coresight: ap: annotations future Also ignore some type errors that are not problems. --- pyocd/core/session.py | 76 +++++++++++++++++++++++----------- pyocd/core/soc_target.py | 26 ++++++------ pyocd/core/target.py | 34 ++++++++------- pyocd/coresight/ap.py | 51 +++++++++++++---------- pyocd/coresight/cortex_m.py | 50 ++++++++++++---------- pyocd/coresight/dap.py | 16 +++---- pyocd/probe/cmsis_dap_probe.py | 18 ++++---- pyocd/probe/debug_probe.py | 20 +++++---- pyocd/probe/stlink_probe.py | 12 +++--- 9 files changed, 176 insertions(+), 127 deletions(-) diff --git a/pyocd/core/session.py b/pyocd/core/session.py index 4618be9b6..babac8d59 100644 --- a/pyocd/core/session.py +++ b/pyocd/core/session.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,16 +15,20 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + from contextlib import contextmanager import logging import logging.config import yaml import os from pathlib import Path +import sys import weakref from inspect import (getfullargspec, signature) from types import SimpleNamespace from typing import (Any, Callable, Generator, Sequence, Union, cast, Dict, List, Mapping, Optional, TYPE_CHECKING) +from typing_extensions import Self from . import exceptions from .options_manager import OptionsManager @@ -38,6 +42,9 @@ from ..gdbserver.gdbserver import GDBServer from ..board.board import Board +# Check whether the eval_str parameter for inspect.signature is available. +HAS_SIGNATURE_EVAL_STR = (sys.version_info[:2] >= (3, 10)) + LOG = logging.getLogger(__name__) ## @brief Set of default config filenames to search for. @@ -95,7 +102,7 @@ class Session(Notifier): _current_session: Optional[weakref.ref] = None @classmethod - def get_current(cls) -> "Session": + def get_current(cls) -> Self: """@brief Return the most recently created Session instance or a default Session. By default this method will return the most recently created Session object that is @@ -111,11 +118,11 @@ def get_current(cls) -> "Session": if session is not None: return session - return Session(None) + return cls(None) def __init__( self, - probe: Optional["DebugProbe"], + probe: Optional[DebugProbe], auto_open: bool = True, options: Optional[Mapping[str, Any]] = None, option_defaults: Optional[Mapping[str, Any]] = None, @@ -159,8 +166,8 @@ def __init__( self._delegate: Optional[Any] = None self._auto_open = auto_open self._options = OptionsManager() - self._gdbservers: Dict[int, "GDBServer"] = {} - self._probeserver: Optional["DebugProbeServer"] = None + self._gdbservers: Dict[int, GDBServer] = {} + self._probeserver: Optional[DebugProbeServer] = None self._context_state = SimpleNamespace() # Set this session on the probe, if we were given a probe. @@ -314,17 +321,17 @@ def is_open(self) -> bool: return self._inited and not self._closed @property - def probe(self) -> Optional["DebugProbe"]: + def probe(self) -> Optional[DebugProbe]: """@brief The @ref pyocd.probe.debug_probe.DebugProbe "DebugProbe" instance.""" return self._probe @property - def board(self) -> Optional["Board"]: + def board(self) -> Optional[Board]: """@brief The @ref pyocd.board.board.Board "Board" object.""" return self._board @property - def target(self) -> Optional["SoCTarget"]: + def target(self) -> Optional[SoCTarget]: """@brief The @ref pyocd.core.target.soc_target "SoCTarget" object representing the SoC. This is the @ref pyocd.core.target.soc_target "SoCTarget" instance owned by the board. @@ -352,7 +359,7 @@ def delegate(self, new_delegate: Any) -> None: self._delegate = new_delegate @property - def user_script_proxy(self) -> "UserScriptDelegateProxy": + def user_script_proxy(self) -> UserScriptDelegateProxy: """@brief The UserScriptDelegateProxy object for a loaded user script.""" # Create a proxy if there isn't already one. This is a fallback in case there isn't a user script, # yet a Python $-command is executed and needs the user script namespace in which to run. @@ -363,21 +370,21 @@ def user_script_proxy(self) -> "UserScriptDelegateProxy": return self._user_script_proxy @property - def user_script_print_proxy(self) -> "PrintProxy": + def user_script_print_proxy(self) -> PrintProxy: return self._user_script_print_proxy @property - def gdbservers(self) -> Dict[int, "GDBServer"]: + def gdbservers(self) -> Dict[int, GDBServer]: """@brief Dictionary of core numbers to @ref pyocd.gdbserver.gdbserver.GDBServer "GDBServer" instances.""" return self._gdbservers @property - def probeserver(self) -> Optional["DebugProbeServer"]: + def probeserver(self) -> Optional[DebugProbeServer]: """@brief A @ref pyocd.probe.tcp_probe_server.DebugProbeServer "DebugProbeServer" instance.""" return self._probeserver @probeserver.setter - def probeserver(self, server: "DebugProbeServer") -> None: + def probeserver(self, server: DebugProbeServer) -> None: """@brief Setter for the `probeserver` property.""" self._probeserver = server @@ -405,7 +412,7 @@ def __enter__(self) -> "Session": raise return self - def __exit__(self, exc_type: type, value: Any, traceback: "TracebackType") -> bool: + def __exit__(self, exc_type: type, value: Any, traceback: TracebackType) -> bool: self.close() return False @@ -642,7 +649,10 @@ def _command_decorator(fn: Callable): classname = names_list[0].capitalize() + "Command" # Examine the command function's signature to extract arguments and their types. - sig = signature(fn) + if HAS_SIGNATURE_EVAL_STR: + sig = signature(fn, eval_str=True) + else: + sig = signature(fn) arg_converters = [] has_var_args = False usage_fields: List[str] = [] @@ -663,19 +673,35 @@ def _command_decorator(fn: Callable): if typ is parm.empty: LOG.error("user command function '%s' is missing type annotation for parameter '%s'", fn.__name__, parm.name) - return fn + return None + + # If we don't have Python 3.10 or later, then we must manually un-stringize the type. + # Using eval() to un-stringize won't work in all cases, but is sufficient for the types + # supported by pyocd's commands. + if not HAS_SIGNATURE_EVAL_STR: + try: + typ = eval(typ, fn.__globals__) + except Exception: + LOG.error("parameter '%s' of user command function '%s' has an unsupported type", + parm.name, fn.__name__) + return None # Otherwise add to param converter list. - if issubclass(typ, str): - arg_converters.append(lambda _, x: x) - elif issubclass(typ, float): - arg_converters.append(lambda _, x: float(x)) - elif issubclass(typ, int): - arg_converters.append(CommandBase._convert_value) - else: + try: + if issubclass(typ, str): + arg_converters.append(lambda _, x: x) + elif issubclass(typ, float): + arg_converters.append(lambda _, x: float(x)) + elif issubclass(typ, int): + arg_converters.append(CommandBase._convert_value) + else: + LOG.error("parameter '%s' of user command function '%s' has an unsupported type", + parm.name, fn.__name__) + return None + except TypeError: LOG.error("parameter '%s' of user command function '%s' has an unsupported type", parm.name, fn.__name__) - return fn + return None usage_fields.append(parm.name.upper()) # parse() method of the new command class. diff --git a/pyocd/core/soc_target.py b/pyocd/core/soc_target.py index 8aad90312..427611334 100644 --- a/pyocd/core/soc_target.py +++ b/pyocd/core/soc_target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,6 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging from typing import (Callable, Dict, List, Optional, overload, Sequence, Union, TYPE_CHECKING) from typing_extensions import Literal @@ -59,7 +61,7 @@ class SoCTarget(TargetGraphNode): VENDOR = "Generic" - def __init__(self, session: "Session", memory_map: Optional["MemoryMap"] = None) -> None: + def __init__(self, session: Session, memory_map: Optional[MemoryMap] = None) -> None: super().__init__(session, memory_map) self.vendor: str = self.VENDOR self.part_families: List[str] = getattr(self, 'PART_FAMILIES', []) @@ -133,7 +135,7 @@ def supported_security_states(self) -> Sequence[Target.SecurityState]: return self.selected_core_or_raise.supported_security_states @property - def core_registers(self) -> "CoreRegistersIndex": + def core_registers(self) -> CoreRegistersIndex: return self.selected_core_or_raise.core_registers def add_core(self, core: CoreTarget) -> None: @@ -241,25 +243,25 @@ def read_memory_block8(self, addr: int, size: int) -> Sequence[int]: def read_memory_block32(self, addr: int, size: int) -> Sequence[int]: return self.selected_core_or_raise.read_memory_block32(addr, size) - def read_core_register(self, id: "CoreRegisterNameOrNumberType") -> "CoreRegisterValueType": + def read_core_register(self, id: CoreRegisterNameOrNumberType) -> CoreRegisterValueType: return self.selected_core_or_raise.read_core_register(id) - def write_core_register(self, id: "CoreRegisterNameOrNumberType", data: "CoreRegisterValueType") -> None: + def write_core_register(self, id: CoreRegisterNameOrNumberType, data: CoreRegisterValueType) -> None: return self.selected_core_or_raise.write_core_register(id, data) - def read_core_register_raw(self, reg: "CoreRegisterNameOrNumberType") -> int: + def read_core_register_raw(self, reg: CoreRegisterNameOrNumberType) -> int: return self.selected_core_or_raise.read_core_register_raw(reg) - def read_core_registers_raw(self, reg_list: Sequence["CoreRegisterNameOrNumberType"]) -> List[int]: + def read_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberType]) -> List[int]: return self.selected_core_or_raise.read_core_registers_raw(reg_list) - def write_core_register_raw(self, reg: "CoreRegisterNameOrNumberType", data: int) -> None: + def write_core_register_raw(self, reg: CoreRegisterNameOrNumberType, data: int) -> None: self.selected_core_or_raise.write_core_register_raw(reg, data) - def write_core_registers_raw(self, reg_list: Sequence["CoreRegisterNameOrNumberType"], data_list: Sequence[int]) -> None: + def write_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberType], data_list: Sequence[int]) -> None: self.selected_core_or_raise.write_core_registers_raw(reg_list, data_list) - def find_breakpoint(self, addr: int) -> Optional["Breakpoint"]: + def find_breakpoint(self, addr: int) -> Optional[Breakpoint]: return self.selected_core_or_raise.find_breakpoint(addr) def set_breakpoint(self, addr: int, type: Target.BreakpointType = Target.BreakpointType.AUTO) -> bool: @@ -305,7 +307,7 @@ def set_vector_catch(self, enable_mask: int) -> None: def get_vector_catch(self) -> int: return self.selected_core_or_raise.get_vector_catch() - def get_target_context(self, core: Optional[int] = None) -> "DebugContext": + def get_target_context(self, core: Optional[int] = None) -> DebugContext: if core is not None: core_obj = self.cores[core] else: @@ -318,7 +320,7 @@ def trace_start(self): def trace_stop(self): self.call_delegate('trace_stop', target=self, mode=0) - def add_target_command_groups(self, command_set: "CommandSet"): + def add_target_command_groups(self, command_set: CommandSet): """@brief Hook for adding target-specific commands to a command set.""" self.call_delegate('add_target_command_groups', target=self, command_set=command_set) diff --git a/pyocd/core/target.py b/pyocd/core/target.py index 0b2331200..3899a246a 100644 --- a/pyocd/core/target.py +++ b/pyocd/core/target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2006-2019 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,8 +15,10 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + from enum import Enum -from typing import (Any, Callable, List, Optional, Sequence, TYPE_CHECKING, Set) +from typing import (Callable, List, Optional, Sequence, TYPE_CHECKING, Set) from .memory_interface import MemoryInterface from .memory_map import MemoryMap @@ -187,7 +189,7 @@ class HaltReason(Enum): ## PMU event. v8.1-M only. PMU = 7 - def __init__(self, session: "Session", memory_map: Optional[MemoryMap] = None) -> None: + def __init__(self, session: Session, memory_map: Optional[MemoryMap] = None) -> None: self._session = session # Make a target-specific copy of the memory map. This is safe to do without locking # because the memory map may not be mutated until target initialization. @@ -196,11 +198,11 @@ def __init__(self, session: "Session", memory_map: Optional[MemoryMap] = None) - self._svd_device: Optional[SVDDevice] = None @property - def session(self) -> "Session": + def session(self) -> Session: return self._session @property - def svd_device(self) -> Optional["SVDDevice"]: + def svd_device(self) -> Optional[SVDDevice]: return self._svd_device @property @@ -208,7 +210,7 @@ def supported_security_states(self) -> Sequence[SecurityState]: raise NotImplementedError() @property - def core_registers(self) -> "CoreRegistersIndex": + def core_registers(self) -> CoreRegistersIndex: raise NotImplementedError() @property @@ -219,7 +221,7 @@ def supported_reset_types(self) -> Set[ResetType]: def is_locked(self) -> bool: return False - def create_init_sequence(self) -> "CallSequence": + def create_init_sequence(self) -> CallSequence: raise NotImplementedError() def init(self) -> None: @@ -245,25 +247,25 @@ def resume(self) -> None: def mass_erase(self) -> None: raise NotImplementedError() - def read_core_register(self, id: "CoreRegisterNameOrNumberType") -> "CoreRegisterValueType": + def read_core_register(self, id: CoreRegisterNameOrNumberType) -> CoreRegisterValueType: raise NotImplementedError() - def write_core_register(self, id: "CoreRegisterNameOrNumberType", data: "CoreRegisterValueType") -> None: + def write_core_register(self, id: CoreRegisterNameOrNumberType, data: CoreRegisterValueType) -> None: raise NotImplementedError() - def read_core_register_raw(self, reg: "CoreRegisterNameOrNumberType") -> int: + def read_core_register_raw(self, reg: CoreRegisterNameOrNumberType) -> int: raise NotImplementedError() - def read_core_registers_raw(self, reg_list: Sequence["CoreRegisterNameOrNumberType"]) -> List[int]: + def read_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberType]) -> List[int]: raise NotImplementedError() - def write_core_register_raw(self, reg: "CoreRegisterNameOrNumberType", data: int) -> None: + def write_core_register_raw(self, reg: CoreRegisterNameOrNumberType, data: int) -> None: raise NotImplementedError() - def write_core_registers_raw(self, reg_list: Sequence["CoreRegisterNameOrNumberType"], data_list: Sequence[int]) -> None: + def write_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberType], data_list: Sequence[int]) -> None: raise NotImplementedError() - def find_breakpoint(self, addr: int) -> Optional["Breakpoint"]: + def find_breakpoint(self, addr: int) -> Optional[Breakpoint]: raise NotImplementedError() def set_breakpoint(self, addr: int, type: BreakpointType = BreakpointType.AUTO) -> bool: @@ -315,12 +317,12 @@ def set_vector_catch(self, enable_mask: int) -> None: def get_vector_catch(self) -> int: raise NotImplementedError() - def get_target_context(self, core: Optional[int] = None) -> "DebugContext": + def get_target_context(self, core: Optional[int] = None) -> DebugContext: raise NotImplementedError() class TargetGraphNode(Target, GraphNode): """@brief Abstract class for a target that is a graph node.""" - def __init__(self, session: "Session", memory_map: Optional[MemoryMap] = None) -> None: + def __init__(self, session: Session, memory_map: Optional[MemoryMap] = None) -> None: Target.__init__(self, session, memory_map) GraphNode.__init__(self) diff --git a/pyocd/coresight/ap.py b/pyocd/coresight/ap.py index 8a37ef064..b685e6c7a 100644 --- a/pyocd/coresight/ap.py +++ b/pyocd/coresight/ap.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,6 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging from contextlib import contextmanager from functools import total_ordering @@ -330,7 +332,7 @@ class AccessPort: """@brief Base class for a CoreSight Access Port (AP) instance.""" @staticmethod - def probe(dp: "DebugPort", ap_num: int) -> bool: + def probe(dp: DebugPort, ap_num: int) -> bool: """@brief Determine if an AP exists with the given AP number. Only applicable for ADIv5. @@ -344,9 +346,9 @@ def probe(dp: "DebugPort", ap_num: int) -> bool: @staticmethod def create( - dp: "DebugPort", + dp: DebugPort, ap_address: APAddressBase, - cmpid: Optional["CoreSightComponentID"] = None + cmpid: Optional[CoreSightComponentID] = None ) -> "AccessPort": """@brief Create a new AP object. @@ -393,12 +395,12 @@ def create( def __init__( self, - dp: "DebugPort", + dp: DebugPort, ap_address: APAddressBase, idr: Optional[int] = None, name: Optional[str] = None, flags: int = 0, - cmpid: Optional["CoreSightComponentID"] = None + cmpid: Optional[CoreSightComponentID] = None ) -> None: """@brief AP constructor. @param self @@ -421,12 +423,12 @@ def __init__( self.rom_addr = 0 self.has_rom_table = False self.rom_table = None - self.core: Optional["CoreTarget"] = None + self.core: Optional[CoreTarget] = None self._flags = flags self._cmpid = cmpid @property - def description(self): + def description(self) -> str: """ @brief The AP's type and version description. If the AP is an unknown proprietary type, then only the string "proprietary" is returned. @@ -438,7 +440,6 @@ def description(self): else: return "proprietary" - @property def short_description(self) -> str: """ @brief The AP's name and address.""" @@ -541,12 +542,12 @@ class MEM_AP(AccessPort, memory_interface.MemoryInterface): def __init__( self, - dp: "DebugPort", + dp: DebugPort, ap_address: APAddressBase, idr: Optional[int] = None, name: Optional[str] = None, flags: int = 0, - cmpid: Optional["CoreSightComponentID"] = None + cmpid: Optional[CoreSightComponentID] = None ) -> None: super().__init__(dp, ap_address, idr, name, flags, cmpid) @@ -899,14 +900,14 @@ class _MemAttrContext: The AP is locked during the lifetime of the context manager. This means that only the calling thread can perform memory transactions. """ - def __init__(self, ap: "MEM_AP", hprot: Optional[int] = None, hnonsec: Optional[int] = None): + def __init__(self, ap: MEM_AP, hprot: Optional[int] = None, hnonsec: Optional[int] = None): self._ap = ap self._hprot = hprot self._saved_hprot = None self._hnonsec = hnonsec self._saved_hnonsec = None - def __enter__(self) -> "MEM_AP._MemAttrContext": + def __enter__(self) -> MEM_AP._MemAttrContext: self._ap.lock() if self._hprot is not None: self._saved_hprot = self._ap.hprot @@ -916,7 +917,7 @@ def __enter__(self) -> "MEM_AP._MemAttrContext": self._ap.hnonsec = self._hnonsec return self - def __exit__(self, exc_type: type, value: Any, traceback: "TracebackType") -> None: + def __exit__(self, exc_type: type, value: Any, traceback: TracebackType) -> None: if self._saved_hprot is not None: self._ap.hprot = self._saved_hprot if self._saved_hnonsec is not None: @@ -991,7 +992,7 @@ def _invalidate_cache(self) -> None: """@brief Invalidate cached registers associated with this AP.""" self._cached_csw = -1 - def _reset_did_occur(self, notification: "Notification") -> None: + def _reset_did_occur(self, notification: Notification) -> None: """@brief Handles reset notifications to invalidate CSW cache.""" # We clear the cache on all resets just to be safe. self._invalidate_cache() @@ -1096,13 +1097,13 @@ def _read_memory(self, addr: int, transfer_size: int = 32, now: bool = True) -> def read_mem_cb() -> int: try: if transfer_size <= 32: - res = result_cb() + res = result_cb() # type: ignore # ignore possibly unbound result_cb if transfer_size == 8: res = (res >> ((addr & 0x03) << 3) & 0xff) elif transfer_size == 16: res = (res >> ((addr & 0x02) << 3) & 0xffff) else: - res_mw = result_cb_mw() + res_mw = result_cb_mw() # type: ignore # ignore possibly unbound result_cb_mw res = sum((w << (32 * i)) for i, w in enumerate(res_mw)) TRACE.debug("read_mem:%06d %s(ap=0x%x; addr=0x%08x, size=%d) -> 0x%08x }", num, "" if now else "...", self.address.nominal_address, addr, transfer_size, res) @@ -1212,6 +1213,10 @@ def _read_memory_block32(self, addr: int, size: int) -> Sequence[int]: addr += n return resp + # Note: the "type: ignore"s below are ok because the accelerated memory interface accepts + # attribute keyword args. The MemoryInterface class should be extended to accept attribute args + # too, but that changes a lot of places. So for now just ignore the type error. This will be + # addressed anyway when the memory API is refactored. @locked def _accelerated_write_memory(self, addr: int, data: int, transfer_size: int=32) -> None: """@brief Write one memory location using the probe's accelerated memory interface. @@ -1220,7 +1225,7 @@ def _accelerated_write_memory(self, addr: int, data: int, transfer_size: int=32) """ assert self._accelerated_memory_interface is not None self._accelerated_memory_interface.write_memory(addr, data, transfer_size, - csw=self._csw) + csw=self._csw) # type: ignore @locked def _accelerated_read_memory(self, addr: int, transfer_size: int=32, now: bool=True) \ @@ -1231,7 +1236,7 @@ def _accelerated_read_memory(self, addr: int, transfer_size: int=32, now: bool=T """ assert self._accelerated_memory_interface is not None return self._accelerated_memory_interface.read_memory(addr, transfer_size, now, - csw=self._csw) + csw=self._csw) # type: ignore @locked def _accelerated_write_memory_block32(self, addr: int, data: Sequence[int]) -> None: @@ -1241,7 +1246,7 @@ def _accelerated_write_memory_block32(self, addr: int, data: Sequence[int]) -> N """ assert self._accelerated_memory_interface is not None self._accelerated_memory_interface.write_memory_block32(addr, data, - csw=self._csw) + csw=self._csw) # type: ignore @locked def _accelerated_read_memory_block32(self, addr: int, size: int) -> Sequence[int]: @@ -1251,7 +1256,7 @@ def _accelerated_read_memory_block32(self, addr: int, size: int) -> Sequence[int """ assert self._accelerated_memory_interface is not None return self._accelerated_memory_interface.read_memory_block32(addr, size, - csw=self._csw) + csw=self._csw) # type: ignore @locked def _accelerated_write_memory_block8(self, addr: int, data: Sequence[int]) -> None: @@ -1261,7 +1266,7 @@ def _accelerated_write_memory_block8(self, addr: int, data: Sequence[int]) -> No """ assert self._accelerated_memory_interface is not None self._accelerated_memory_interface.write_memory_block8(addr, data, - csw=self._csw) + csw=self._csw) # type: ignore @locked def _accelerated_read_memory_block8(self, addr: int, size: int) -> Sequence[int]: @@ -1271,7 +1276,7 @@ def _accelerated_read_memory_block8(self, addr: int, size: int) -> Sequence[int] """ assert self._accelerated_memory_interface is not None return self._accelerated_memory_interface.read_memory_block8(addr, size, - csw=self._csw) + csw=self._csw) # type: ignore def _handle_error(self, error: Exception, num: int) -> None: self.dp._handle_error(error, num) diff --git a/pyocd/coresight/cortex_m.py b/pyocd/coresight/cortex_m.py index f779235c9..117c9ecff 100644 --- a/pyocd/coresight/cortex_m.py +++ b/pyocd/coresight/cortex_m.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2006-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,6 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging from time import sleep from typing import (Any, Callable, List, Optional, Set, overload, Sequence, TYPE_CHECKING, Union, cast) @@ -40,10 +42,14 @@ if TYPE_CHECKING: from .coresight_target import CoreSightTarget from .rom_table import CoreSightComponentID + from ..core.core_registers import ( + CoreRegistersIndex, + CoreRegisterNameOrNumberType, + CoreRegisterValueType, + ) from ..core.session import Session from ..core.memory_interface import MemoryInterface from ..core.memory_map import MemoryMap - from ..core.target_delegate import DelegateResult from ..debug.context import DebugContext from ..debug.elf.elf import ELFBinaryFile @@ -189,7 +195,7 @@ class CortexM(CoreTarget, CoreSightCoreComponent): # lgtm[py/multiple-calls-to-i _RESET_RECOVERY_SLEEP_INTERVAL = 0.01 # 10 ms @classmethod - def factory(cls, ap: "MemoryInterface", cmpid: "CoreSightComponentID", address: int) -> Any: + def factory(cls, ap: MemoryInterface, cmpid: CoreSightComponentID, address: int) -> Any: assert isinstance(ap, MEM_AP) # Create a new core instance. @@ -209,11 +215,11 @@ def factory(cls, ap: "MemoryInterface", cmpid: "CoreSightComponentID", address: return core def __init__(self, - session: "Session", + session: Session, ap: MEM_AP, - memory_map: Optional["MemoryMap"] = None, + memory_map: Optional[MemoryMap] = None, core_num: int = 0, - cmpid: Optional["CoreSightComponentID"] = None, + cmpid: Optional[CoreSightComponentID] = None, address: Optional[int] = None ) -> None: CoreTarget.__init__(self, session, memory_map) @@ -226,7 +232,7 @@ def __init__(self, self._core_number: int = core_num self._core_name: str = "Unknown" self._run_token: int = 0 - self._target_context: Optional["DebugContext"] = None + self._target_context: Optional[DebugContext] = None self._elf = None self.target_xml = None self._core_registers = CoreRegistersIndex() @@ -256,7 +262,7 @@ def __init__(self, self.bp_manager = BreakpointManager(self) self.bp_manager.add_provider(self.sw_bp) - def add_child(self, cmp: "CoreSightComponent") -> None: + def add_child(self, cmp: CoreSightComponent) -> None: """@brief Connect related CoreSight components.""" super().add_child(cmp) @@ -298,11 +304,11 @@ def supported_reset_types(self) -> Set[Target.ResetType]: return self._supported_reset_types @property - def elf(self) -> Optional["ELFBinaryFile"]: + def elf(self) -> Optional[ELFBinaryFile]: return self._elf @elf.setter - def elf(self, elffile: "ELFBinaryFile") -> None: + def elf(self, elffile: ELFBinaryFile) -> None: self._elf = elffile @property @@ -664,7 +670,7 @@ def step(self, disable_interrupts: bool = True, start: int = 0, end: int = 0, break # Read program counter and compare to [start, end) - program_counter = self.read_core_register('pc') + program_counter = self.read_core_register_raw('pc') if (program_counter < start) or (end <= program_counter): break @@ -1048,7 +1054,7 @@ def reset_and_halt(self, reset_type=None): # points to an invalid address. Only do this if the core is actually halted, otherwise we # can't access XPSR. if self.get_state() == Target.State.HALTED: - xpsr = self.read_core_register('xpsr') + xpsr = self.read_core_register_raw('xpsr') if xpsr & self.XPSR_THUMB == 0: self.write_core_register('xpsr', xpsr | self.XPSR_THUMB) @@ -1122,7 +1128,7 @@ def check_reg_list(self, reg_list): else: raise KeyError("register %s not available in this CPU", info.name) - def read_core_register(self, reg): + def read_core_register(self, reg: CoreRegisterNameOrNumberType) -> CoreRegisterValueType: """@brief Read one core register. The core must be halted or reads will fail. @@ -1140,7 +1146,7 @@ def read_core_register(self, reg): regValue = self.read_core_register_raw(reg_info.index) return reg_info.from_raw(regValue) - def read_core_register_raw(self, reg): + def read_core_register_raw(self, reg: CoreRegisterNameOrNumberType) -> int: """@brief Read a core register without type conversion. The core must be halted or reads will fail. @@ -1157,7 +1163,7 @@ def read_core_register_raw(self, reg): vals = self.read_core_registers_raw([reg]) return vals[0] - def read_core_registers_raw(self, reg_list): + def read_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberType]) -> List[int]: """@brief Read one or more core registers. The core must be halted or reads will fail. @@ -1177,7 +1183,7 @@ def read_core_registers_raw(self, reg_list): self.check_reg_list(reg_list) return self._base_read_core_registers_raw(reg_list) - def _base_read_core_registers_raw(self, reg_list): + def _base_read_core_registers_raw(self, reg_list: List[int]) -> List[int]: """@brief Private core register read routine. Items in the _reg_list_ must be pre-converted to index and only include valid @@ -1273,7 +1279,7 @@ def _base_read_core_registers_raw(self, reg_list): return reg_vals - def write_core_register(self, reg, data): + def write_core_register(self, reg: CoreRegisterNameOrNumberType, data: CoreRegisterValueType) -> None: """@brief Write a CPU register. The core must be halted or the write will fail. @@ -1289,7 +1295,7 @@ def write_core_register(self, reg, data): reg_info = CortexMCoreRegisterInfo.get(reg) self.write_core_register_raw(reg_info.index, reg_info.to_raw(data)) - def write_core_register_raw(self, reg, data): + def write_core_register_raw(self, reg: CoreRegisterNameOrNumberType, data: int) -> None: """@brief Write a CPU register without type conversion. The core must be halted or the write will fail. @@ -1304,7 +1310,7 @@ def write_core_register_raw(self, reg, data): """ self.write_core_registers_raw([reg], [data]) - def write_core_registers_raw(self, reg_list, data_list): + def write_core_registers_raw(self, reg_list: Sequence[CoreRegisterNameOrNumberType], data_list: Sequence[int]) -> None: """@brief Write one or more core registers. The core must be halted or writes will fail. @@ -1326,7 +1332,7 @@ def write_core_registers_raw(self, reg_list, data_list): self.check_reg_list(reg_list) self._base_write_core_registers_raw(reg_list, data_list) - def _base_write_core_registers_raw(self, reg_list, data_list): + def _base_write_core_registers_raw(self, reg_list: Sequence[int], data_list: Sequence[int]) -> None: """@brief Private core register write routine. Items in the _reg_list_ must be pre-converted to index and only include valid @@ -1573,5 +1579,5 @@ def exception_number_to_name(self, exc_num: int) -> Optional[str]: def in_thread_mode_on_main_stack(self) -> bool: if not self._target_context: return False - return (self._target_context.read_core_register('ipsr') == 0 and - (self._target_context.read_core_register('control') & CortexM.CONTROL_SPSEL) == 0) + return (self._target_context.read_core_register_raw('ipsr') == 0 and + (self._target_context.read_core_register_raw('control') & CortexM.CONTROL_SPSEL) == 0) diff --git a/pyocd/coresight/dap.py b/pyocd/coresight/dap.py index 4e86f6b74..995913270 100644 --- a/pyocd/coresight/dap.py +++ b/pyocd/coresight/dap.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # Copyright (c) 2022 Clay McClure # Copyright (c) 2022 Toshiba Electronic Devices & Storage Corporation # SPDX-License-Identifier: Apache-2.0 @@ -17,6 +17,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + import logging from enum import Enum from typing import (Callable, Dict, List, NamedTuple, Optional, Sequence, Tuple, TYPE_CHECKING, Union, overload) @@ -310,9 +312,9 @@ def __init__(self, probe: DebugProbe, target: Target) -> None: self.target = target assert target.session self._session = target.session - self.valid_aps: Optional[List["APAddressBase"]] = None + self.valid_aps: Optional[List[APAddressBase]] = None self.dpidr = DPIDR(0, 0, 0, 0, 0) - self.aps: Dict["APAddressBase", "AccessPort"] = {} + self.aps: Dict[APAddressBase, AccessPort] = {} self._access_number: int = 0 self._cached_dp_select: Optional[int] = None self._protocol: Optional[DebugProbe.Protocol] = None @@ -340,7 +342,7 @@ def probe(self) -> DebugProbe: return self._probe @property - def session(self) -> "Session": + def session(self) -> Session: return self._session @property @@ -353,7 +355,7 @@ def base_address(self) -> int: return self._base_addr @property - def apacc_memory_interface(self) -> "APAccessMemoryInterface": + def apacc_memory_interface(self) -> APAccessMemoryInterface: """@brief Memory interface for performing APACC transactions.""" if self._apacc_mem_interface is None: self._apacc_mem_interface = APAccessMemoryInterface(self) @@ -602,7 +604,7 @@ def _invalidate_cache(self) -> None: """@brief Invalidate cached DP registers.""" self._cached_dp_select = None - def _reset_did_occur(self, notification: "Notification") -> None: + def _reset_did_occur(self, notification: Notification) -> None: """@brief Handles reset notifications to invalidate register cache. The cache is cleared on all resets just to be safe. On most devices, warm resets do not reset @@ -1040,7 +1042,7 @@ class APAccessMemoryInterface(memory_interface.MemoryInterface): Only 32-bit transfers are supported. """ - def __init__(self, dp: DebugPort, ap_address: Optional["APAddressBase"] = None) -> None: + def __init__(self, dp: DebugPort, ap_address: Optional[APAddressBase] = None) -> None: """@brief Constructor. @param self diff --git a/pyocd/probe/cmsis_dap_probe.py b/pyocd/probe/cmsis_dap_probe.py index 42cbe46f6..45aa44966 100644 --- a/pyocd/probe/cmsis_dap_probe.py +++ b/pyocd/probe/cmsis_dap_probe.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,6 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + from time import sleep import logging from typing import (Callable, Collection, Dict, List, Optional, overload, Sequence, Set, TYPE_CHECKING, Tuple, Union) @@ -55,7 +57,7 @@ def __init__(self, device: _OpenableProtocol, suppress_exceptions: bool = True) self._suppress_exceptions = suppress_exceptions self._did_open_link: bool = False - def __enter__(self) -> "_TemporaryOpen": + def __enter__(self) -> _TemporaryOpen: try: # Temporarily open the device if not already opened. if not self._device.is_open: @@ -69,7 +71,7 @@ def __enter__(self) -> "_TemporaryOpen": return self - def __exit__(self, exc_type: Optional[type], exc_value: Optional[Exception], traceback: Optional["TracebackType"]) -> bool: + def __exit__(self, exc_type: Optional[type], exc_value: Optional[Exception], traceback: Optional[TracebackType]) -> bool: # Close the device if we had to open it. if self._did_open_link: self._device.close() @@ -134,14 +136,14 @@ def get_all_connected_probes( cls, unique_id: Optional[str] = None, is_explicit: bool = False - ) -> Sequence["DebugProbe"]: + ) -> Sequence[DebugProbe]: try: return [cls(dev) for dev in DAPAccess.get_connected_devices()] except DAPAccess.Error as exc: raise cls._convert_exception(exc) from exc @classmethod - def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optional["DebugProbe"]: + def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optional[DebugProbe]: try: dap_access = DAPAccess.get_device(unique_id) if dap_access is not None: @@ -208,7 +210,7 @@ def capabilities(self) -> Set[DebugProbe.Capability]: return self._caps @property - def associated_board_info(self) -> Optional["BoardInfo"]: + def associated_board_info(self) -> Optional[BoardInfo]: """@brief Info about the board associated with this probe, if known.""" # Get internal board info if available. if (self.board_id is not None) and (self.board_id in BOARD_ID_TO_INFO): @@ -242,7 +244,7 @@ def associated_board_info(self) -> Optional["BoardInfo"]: return info - def create_associated_board(self) -> Optional["Board"]: + def create_associated_board(self) -> Optional[Board]: assert self.session is not None board_info = self.associated_board_info @@ -659,7 +661,7 @@ def read_ap_repeat_callback(): if now: TRACE.debug("trace: read_ap_multi(addr=%#010x, count=%i) -> [%s]", addr, count, - ", ".join(["%#010x" % v for v in result])) + ", ".join(["%#010x" % v for v in result])) # type: ignore # result is always iterable if now is True return result else: return read_ap_repeat_callback diff --git a/pyocd/probe/debug_probe.py b/pyocd/probe/debug_probe.py index c478de2f6..42affa242 100644 --- a/pyocd/probe/debug_probe.py +++ b/pyocd/probe/debug_probe.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,6 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + from enum import (Enum, IntFlag) import threading from typing import (Callable, Collection, Optional, overload, Sequence, Set, TYPE_CHECKING, Tuple, Union) @@ -141,7 +143,7 @@ def get_all_connected_probes( cls, unique_id: Optional[str] = None, is_explicit: bool = False - ) -> Sequence["DebugProbe"]: + ) -> Sequence[DebugProbe]: """@brief Returns a list of DebugProbe instances. To filter the list of returned probes, the `unique_id` parameter may be set to a string with a full or @@ -160,7 +162,7 @@ def get_all_connected_probes( raise NotImplementedError() @classmethod - def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optional["DebugProbe"]: + def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optional[DebugProbe]: """@brief Returns a DebugProbe instance for a probe with the given unique ID. If no probe is connected with a fully matching unique ID, then None will be returned. @@ -174,16 +176,16 @@ def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optiona def __init__(self) -> None: """@brief Constructor.""" - self._session: Optional["Session"] = None + self._session: Optional[Session] = None self._lock = threading.RLock() @property - def session(self) -> Optional["Session"]: + def session(self) -> Optional[Session]: """@brief Session associated with this probe.""" return self._session @session.setter - def session(self, the_session: "Session") -> None: + def session(self, the_session: Session) -> None: self._session = the_session @property @@ -245,11 +247,11 @@ def capabilities(self) -> Set[Capability]: raise NotImplementedError() @property - def associated_board_info(self) -> Optional["BoardInfo"]: + def associated_board_info(self) -> Optional[BoardInfo]: """@brief Info about the board associated with this probe, if known.""" return None - def create_associated_board(self) -> Optional["Board"]: + def create_associated_board(self) -> Optional[Board]: """@brief Create a board instance representing the board of which the probe is a component. If the probe is part of a board, then this method will create a Board instance that @@ -503,7 +505,7 @@ def write_ap_multiple(self, addr: int, values) -> None: """@brief Write one AP register multiple times.""" raise NotImplementedError() - def get_memory_interface_for_ap(self, ap_address: "APAddressBase") -> Optional["MemoryInterface"]: + def get_memory_interface_for_ap(self, ap_address: APAddressBase) -> Optional[MemoryInterface]: """@brief Returns a @ref pyocd.core.memory_interface.MemoryInterface "MemoryInterface" for the specified AP. diff --git a/pyocd/probe/stlink_probe.py b/pyocd/probe/stlink_probe.py index eb025e378..34ca61c15 100644 --- a/pyocd/probe/stlink_probe.py +++ b/pyocd/probe/stlink_probe.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2018-2020,2022 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,6 +15,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import annotations + from time import sleep from typing import (Any, Callable, Dict, List, Optional, Sequence, Union, TYPE_CHECKING) @@ -44,11 +46,11 @@ class StlinkProbe(DebugProbe): @classmethod def get_all_connected_probes(cls, unique_id: Optional[str] = None, - is_explicit: bool = False) -> List["StlinkProbe"]: + is_explicit: bool = False) -> List[StlinkProbe]: return [cls(dev) for dev in STLinkUSBInterface.get_all_connected_devices()] @classmethod - def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optional["StlinkProbe"]: + def get_probe_with_id(cls, unique_id: str, is_explicit: bool = False) -> Optional[StlinkProbe]: for dev in STLinkUSBInterface.get_all_connected_devices(): if dev.serial_number == unique_id: return cls(dev) @@ -65,7 +67,7 @@ def __init__(self, device: STLinkUSBInterface) -> None: self._caps = set() @property - def board_id(self) -> str: + def board_id(self) -> Optional[str]: """@brief Lazily loaded 4-character board ID.""" if self._board_id is None: self._board_id = self._get_board_id() @@ -136,7 +138,7 @@ def capabilities(self): return self._caps @property - def associated_board_info(self) -> Optional["BoardInfo"]: + def associated_board_info(self) -> Optional[BoardInfo]: if (self.board_id is not None) and (self.board_id in BOARD_ID_TO_INFO): return BOARD_ID_TO_INFO[self.board_id] else: From 5e65c07da01fa3608b5b91525a9cfc3ca4c88f83 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 9 Aug 2023 09:07:37 -0500 Subject: [PATCH 15/25] coresight: cortex-m: CPU type detection improvements (#1605) - Use a common method to log the CPU description. It logs the arch version, extensions, and FPU type. This changes the logging of FPU type so it comes after CPU type. - Add .architecture_version property returning a tuple of major/minor version. - Use deferred reads when reading CPU ID registers. - Detect DSP, PMU, MPU, PACBTI, FP16, RAS, UDE extensions. - Add extensions for FPU v4/5. - Remove some extension enums for those that can be determined by arch version. --- pyocd/coresight/core_ids.py | 7 +- pyocd/coresight/cortex_m.py | 75 ++++++++++++++++++--- pyocd/coresight/cortex_m_v8m.py | 112 ++++++++++++++++++++++++++++---- 3 files changed, 169 insertions(+), 25 deletions(-) diff --git a/pyocd/coresight/core_ids.py b/pyocd/coresight/core_ids.py index 82fbf239f..7398325e6 100644 --- a/pyocd/coresight/core_ids.py +++ b/pyocd/coresight/core_ids.py @@ -73,6 +73,8 @@ class CortexMExtension(Enum): DSP = "DSP" # Digital Signal Processing instructions FPU_DP = "FPU_DP" # Double-Precision floating point FPU_HP = "FPU_HP" # Half-Precision floating point + FPU_V4 = "FPUv4" # FPv4, only present in Cortex-M4F + FPU_V5 = "FPUv5" # FPv5 single or double precision SEC = "SEC" # Security Extension SEC_V81 = "SEC_V81" # v8.1-M additions to the Security Extension MVE = "MVE" # M-profile Vector Extension, with integer support @@ -80,10 +82,5 @@ class CortexMExtension(Enum): UDE = "UDE" # Unprivileged Debug Extension RAS = "RAS" # Reliability, Serviceability, and Availability PMU = "PMU" # Performance Monitoring Unit - LOB = "LOB" # Low-Overhead loops and Branch Future - PXN = "PXN" # Privileged eXecute-Never - MAIN = "MAIN" # Main Extension MPU = "MPU" # Memory Protection Unit - DIT = "DIT" # Data-Independent Timing - FPCXT = "FPCXT" # Floating Point Context PACBTI = "PACBTI" # Pointer Authentication and Branch Target Identification diff --git a/pyocd/coresight/cortex_m.py b/pyocd/coresight/cortex_m.py index 117c9ecff..0b505a8ed 100644 --- a/pyocd/coresight/cortex_m.py +++ b/pyocd/coresight/cortex_m.py @@ -19,7 +19,7 @@ import logging from time import sleep -from typing import (Any, Callable, List, Optional, Set, overload, Sequence, TYPE_CHECKING, Union, cast) +from typing import (Any, Callable, List, Optional, Set, Tuple, overload, Sequence, TYPE_CHECKING, Union, cast) from typing_extensions import Literal from ..core.target import Target @@ -192,6 +192,17 @@ class CortexM(CoreTarget, CoreSightCoreComponent): # lgtm[py/multiple-calls-to-i MVFR2_VFP_MISC_SHIFT = 4 MVFR2_VFP_MISC_SUPPORTED = 4 + # Instruction Set Attribute Register 3 + ISAR3 = 0xE000ED6C + ISAR3_SIMD_MASK = 0x000000f0 + ISAR3_SIMD_SHIFT = 4 + ISAR3_SIMD__DSP = 0x3 # SIMD instructions from DSP extension are present + + # MPU Type register + MPU_TYPE = 0xE000ED90 + MPU_TYPE_DREGIONS_MASK = 0x0000ff00 + MPU_TYPE_DREGIONS_SHIFT = 8 + _RESET_RECOVERY_SLEEP_INTERVAL = 0.01 # 10 ms @classmethod @@ -226,6 +237,7 @@ def __init__(self, CoreSightCoreComponent.__init__(self, ap, cmpid, address) self._architecture: CoreArchitecture = CoreArchitecture.ARMv6M + self._arch_version: Tuple[int, int] = (0, 0) self._extensions: List[CortexMExtension] = [] self.core_type = 0 self.has_fpu: bool = False @@ -286,6 +298,11 @@ def architecture(self) -> CoreArchitecture: """@brief @ref pyocd.coresight.core_ids.CoreArchitecture "CoreArchitecture" for this core.""" return self._architecture + @property + def architecture_version(self) -> Tuple[int, int]: + """@brief Architecture major and minor version numbers.""" + return self._arch_version + @property def extensions(self) -> List[CortexMExtension]: """@brief List of extensions supported by this core.""" @@ -375,6 +392,7 @@ def init(self) -> None: self._check_for_fpu() self._init_reset_types() self._build_registers() + self._log_core_description() self.get_vector_catch() # Cache the current vector cache settings. self.sw_bp.init() @@ -438,24 +456,40 @@ def _build_registers(self) -> None: def _read_core_type(self) -> None: """@brief Read the CPUID register and determine core type and architecture.""" # Read CPUID register - cpuid = self.read32(CortexM.CPUID) + cpuid_cb = self.read32(CortexM.CPUID, now=False) + isar3_cb = self.read32(CortexM.ISAR3, now=False) + mpu_type_cb = self.read32(CortexM.MPU_TYPE, now=False) + # Check CPUID + cpuid = cpuid_cb() implementer = (cpuid & CortexM.CPUID_IMPLEMENTER_MASK) >> CortexM.CPUID_IMPLEMENTER_POS arch = (cpuid & CortexM.CPUID_ARCHITECTURE_MASK) >> CortexM.CPUID_ARCHITECTURE_POS self.core_type = (cpuid & CortexM.CPUID_PARTNO_MASK) >> CortexM.CPUID_PARTNO_POS self.cpu_revision = (cpuid & CortexM.CPUID_VARIANT_MASK) >> CortexM.CPUID_VARIANT_POS self.cpu_patch = (cpuid & CortexM.CPUID_REVISION_MASK) >> CortexM.CPUID_REVISION_POS + # Check for DSP extension + isar3 = isar3_cb() + isar3_simd = (isar3 & self.ISAR3_SIMD_MASK) >> self.ISAR3_SIMD_SHIFT + if isar3_simd == self.ISAR3_SIMD__DSP: + self._extensions.append(CortexMExtension.DSP) + + # Check for MPU extension + mpu_type = mpu_type_cb() + mpu_type_dregions = (mpu_type & self.MPU_TYPE_DREGIONS_MASK) >> self.MPU_TYPE_DREGIONS_SHIFT + if mpu_type_dregions > 0: + self._extensions.append(CortexMExtension.MPU) + # Set the arch version. if arch == CortexM.ARMv7M: self._architecture = CoreArchitecture.ARMv7M + self._arch_version = (7, 0) else: self._architecture = CoreArchitecture.ARMv6M + self._arch_version = (6, 0) self._core_name = CORE_TYPE_NAME.get((implementer, self.core_type), f"Unknown (CPUID={cpuid:#010x})") - LOG.info("CPU core #%d is %s r%dp%d", self.core_number, self._core_name, self.cpu_revision, self.cpu_patch) - def _check_for_fpu(self) -> None: """@brief Determine if a core has an FPU. @@ -473,7 +507,10 @@ def _check_for_fpu(self) -> None: # write to CPACR and checking the result. This test has the unfortunate property of not # working on certain cores when the core is held in reset, because CPACR is not accessible # under reset on all cores. Thus we use MVFR0. - mvfr0 = self.read32(CortexM.MVFR0) + mvfr0_cb = self.read32(CortexM.MVFR0, now=False) + mvfr2_cb = self.read32(CortexM.MVFR2, now=False) + + mvfr0 = mvfr0_cb() sp_val = (mvfr0 & CortexM.MVFR0_SINGLE_PRECISION_MASK) >> CortexM.MVFR0_SINGLE_PRECISION_SHIFT dp_val = (mvfr0 & CortexM.MVFR0_DOUBLE_PRECISION_MASK) >> CortexM.MVFR0_DOUBLE_PRECISION_SHIFT self.has_fpu = ((sp_val == self.MVFR0_SINGLE_PRECISION_SUPPORTED) or @@ -485,20 +522,40 @@ def _check_for_fpu(self) -> None: # Now check the VFP version by looking for support for the misc FP instructions added in # FPv5 (VMINNM, VMAXNM, etc). - mvfr2 = self.read32(CortexM.MVFR2) + mvfr2 = mvfr2_cb() vfp_misc_val = (mvfr2 & CortexM.MVFR2_VFP_MISC_MASK) >> CortexM.MVFR2_VFP_MISC_SHIFT if dp_val == self.MVFR0_DOUBLE_PRECISION_SUPPORTED: # FPv5 with double-precision - fpu_type = "FPv5-D16-M" self._extensions.append(CortexMExtension.FPU_DP) + self._extensions.append(CortexMExtension.FPU_V5) elif vfp_misc_val == self.MVFR2_VFP_MISC_SUPPORTED: # FPv5 with only single-precision - fpu_type = "FPv5-SP-D16-M" + self._extensions.append(CortexMExtension.FPU_V5) + else: + # FPv4 has only single-precision, only present on the CM4F. + self._extensions.append(CortexMExtension.FPU_V4) + + def _log_core_description(self) -> None: + core_desc = f"CPU core #{self.core_number}: {self._core_name} r{self.cpu_revision}p{self.cpu_patch}, v{self.architecture_version[0]}.{self.architecture_version[1]}-M architecture" + LOG.info(core_desc) + + if self._extensions: + exts_desc = f" Extensions: [{', '.join(sorted(x.name for x in self._extensions))}]" + LOG.info(exts_desc) + + if self.has_fpu: + if CortexMExtension.FPU_V5 in self._extensions: + if CortexMExtension.FPU_DP in self._extensions: + # FPv5 with double-precision + fpu_type = "FPv5-D16-M" + else: + # FPv5 with only single-precision + fpu_type = "FPv5-SP-D16-M" else: # FPv4 has only single-precision, only present on the CM4F. fpu_type = "FPv4-SP-D16-M" - LOG.info("FPU present: " + fpu_type) + LOG.info(" FPU present: " + fpu_type) def _init_reset_types(self) -> None: """@brief Adjust supported reset types based on the architecture.""" diff --git a/pyocd/coresight/cortex_m_v8m.py b/pyocd/coresight/cortex_m_v8m.py index 27f77ed34..9d265b32d 100644 --- a/pyocd/coresight/cortex_m_v8m.py +++ b/pyocd/coresight/cortex_m_v8m.py @@ -39,6 +39,12 @@ class CortexM_v8M(CortexM): DSCSR_SBRSEL = 0x00000002 DSCSR_SBRSELEN = 0x00000001 + # Processor Feature Register 0 + PFR0 = 0xE000ED40 + PFR0_RAS_MASK = 0xf0000000 + PFR0_RAS_SHIFT = 28 + PFR0_RAS_VERSION_1 = 2 + # Processor Feature Register 1 PFR1 = 0xE000ED44 PFR1_SECURITY_MASK = 0x000000f0 @@ -47,12 +53,37 @@ class CortexM_v8M(CortexM): PFR1_SECURITY_EXT_V8_0 = 0x1 # Base security extension. PFR1_SECURITY_EXT_V8_1 = 0x3 # v8.1-M adds several instructions. + # Debug Feature Register 0 + DFR0 = 0xE000ED48 + DFR0_UDE_MASK = 0xf0000000 + DFR0_UDE_SHIFT = 28 + DFR0_UDE_SUPPORTED = 1 + # Media and FP Feature Register 1 MVFR1 = 0xE000EF44 MVFR1_MVE_MASK = 0x00000f00 MVFR1_MVE_SHIFT = 8 MVFR1_MVE__INTEGER = 0x1 MVFR1_MVE__FLOAT = 0x2 + MVFR1_FP16_MASK = 0x00f00000 + MVFR1_FP16_SHIFT = 20 + MVFR1_FP16__SUPPORTED = 0x1 # FP16 format support is present. + + # Instruction Set Attribute Register 0 + ISAR0 = 0xE000ED60 + ISAR0_CMPBRANCH_MASK = 0x0000f000 + ISAR0_CMPBRANCH_SHIFT = 12 + ISAR0_CMPBRANCH__LOB = 0x3 # LOB instructions from v8.1-M are present. + + # Instruction Set Attribute Register 5 + ISAR5 = 0xE000ED74 + ISAR5_PACBTI_MASK = 0x00f00000 + ISAR5_PACBTI_SHIFT = 20 + ISAR5_PACBTI__NONE = 0x0 # PACBTI is not present. + + # PMU Type register + PMU_TYPE = 0xE0003E00 + PMU_TYPE_N_MASK = 0x0000000f def __init__(self, rootTarget, ap, memory_map=None, core_num=0, cmpid=None, address=None): super().__init__(rootTarget, ap, memory_map, core_num, cmpid, address) @@ -71,51 +102,110 @@ def supported_security_states(self): def _read_core_type(self): """@brief Read the CPUID register and determine core type and architecture.""" - # Read CPUID register - cpuid = self.read32(CortexM.CPUID) + # Schedule deferred reads. + cpuid_cb = self.read32(self.CPUID, now=False) + pfr0_cb = self.read32(self.PFR0, now=False) + pfr1_cb = self.read32(self.PFR1, now=False) + dfr0_cb = self.read32(self.DFR0, now=False) + isar0_cb = self.read32(self.ISAR0, now=False) + isar3_cb = self.read32(self.ISAR3, now=False) + isar5_cb = self.read32(self.ISAR5, now=False) + pmu_type_cb = self.read32(self.PMU_TYPE, now=False) + mpu_type_cb = self.read32(self.MPU_TYPE, now=False) + # Read CPUID register + cpuid = cpuid_cb() implementer = (cpuid & CortexM.CPUID_IMPLEMENTER_MASK) >> CortexM.CPUID_IMPLEMENTER_POS arch = (cpuid & CortexM.CPUID_ARCHITECTURE_MASK) >> CortexM.CPUID_ARCHITECTURE_POS self.core_type = (cpuid & CortexM.CPUID_PARTNO_MASK) >> CortexM.CPUID_PARTNO_POS self.cpu_revision = (cpuid & CortexM.CPUID_VARIANT_MASK) >> CortexM.CPUID_VARIANT_POS self.cpu_patch = (cpuid & CortexM.CPUID_REVISION_MASK) >> CortexM.CPUID_REVISION_POS - pfr1 = self.read32(self.PFR1) - pfr1_sec = ((pfr1 & self.PFR1_SECURITY_MASK) >> self.PFR1_SECURITY_SHIFT) + # Check for DSP extension + isar3 = isar3_cb() + isar3_simd = (isar3 & self.ISAR3_SIMD_MASK) >> self.ISAR3_SIMD_SHIFT + if isar3_simd == self.ISAR3_SIMD__DSP: + self._extensions.append(CortexMExtension.DSP) + + # Check for RAS extension. + pfr0 = pfr0_cb() + pfr0_ras = (pfr0 & self.PFR0_RAS_MASK) >> self.PFR0_RAS_SHIFT + if pfr0_ras == self.PFR0_RAS_VERSION_1: + self._extensions.append(CortexMExtension.RAS) + + # Check for the security extension. + pfr1 = pfr1_cb() + pfr1_sec = (pfr1 & self.PFR1_SECURITY_MASK) >> self.PFR1_SECURITY_SHIFT self.has_security_extension = pfr1_sec in (self.PFR1_SECURITY_EXT_V8_0, self.PFR1_SECURITY_EXT_V8_1) if self.has_security_extension: self._extensions.append(CortexMExtension.SEC) if pfr1_sec == self.PFR1_SECURITY_EXT_V8_1: self._extensions.append(CortexMExtension.SEC_V81) + # Check for UDE extension. + dfr0 = dfr0_cb() + dfr0_ude = (dfr0 & self.DFR0_UDE_MASK) >> self.DFR0_UDE_SHIFT + if dfr0_ude == self.DFR0_UDE_SUPPORTED: + self._extensions.append(CortexMExtension.UDE) + + # Check for PACBTI extension. + isar5 = isar5_cb() + isar5_pacbti = (isar5 & self.ISAR5_PACBTI_MASK) >> self.ISAR5_PACBTI_SHIFT + if isar5_pacbti != self.ISAR5_PACBTI__NONE: + self._extensions.append(CortexMExtension.PACBTI) + + # Check for PMU extension. + pmu_type = pmu_type_cb() + pmu_type_n = pmu_type & self.PMU_TYPE_N_MASK + if pmu_type_n > 0: + self._extensions.append(CortexMExtension.PMU) + + # Check for MPU extension + mpu_type = mpu_type_cb() + mpu_type_dregions = (mpu_type & self.MPU_TYPE_DREGIONS_MASK) >> self.MPU_TYPE_DREGIONS_SHIFT + if mpu_type_dregions > 0: + self._extensions.append(CortexMExtension.MPU) + + # Determine the base/main variant. if arch == self.ARMv8M_BASE: self._architecture = CoreArchitecture.ARMv8M_BASE else: self._architecture = CoreArchitecture.ARMv8M_MAIN - self._core_name = CORE_TYPE_NAME.get((implementer, self.core_type), f"Unknown (CPUID={cpuid:#010x})") - - if self.has_security_extension: - LOG.info("CPU core #%d is %s r%dp%d (security ext present)", - self.core_number, self._core_name, self.cpu_revision, self.cpu_patch) + # Determine the architecture major/minor version. + # The presence of low-overhead loop and branch instructions is used to distinguish v8.1-M from v8.0-M. + isar0 = isar0_cb() + isar0_cmpbranch = (isar0 & self.ISAR0_CMPBRANCH_MASK) >> self.ISAR0_CMPBRANCH_SHIFT + if isar0_cmpbranch == self.ISAR0_CMPBRANCH__LOB: + self._arch_version = (8, 1) else: - LOG.info("CPU core #%d is %s r%dp%d", self.core_number, self._core_name, self.cpu_revision, self.cpu_patch) + self._arch_version = (8, 0) + + self._core_name = CORE_TYPE_NAME.get((implementer, self.core_type), f"Unknown (CPUID={cpuid:#010x})") def _check_for_fpu(self): """@brief Determine if a core has an FPU. In addition to the tests performed by CortexM, this method tests for the MVE extension. """ + # Schedule this deferred read before calling the super implementation. + mvfr1_cb = self.read32(self.MVFR1, now=False) + super()._check_for_fpu() # Check for MVE. - mvfr1 = self.read32(self.MVFR1) + mvfr1 = mvfr1_cb() mve = (mvfr1 & self.MVFR1_MVE_MASK) >> self.MVFR1_MVE_SHIFT if mve == self.MVFR1_MVE__INTEGER: self._extensions.append(CortexMExtension.MVE) elif mve == self.MVFR1_MVE__FLOAT: self._extensions += [CortexMExtension.MVE, CortexMExtension.MVE_FP] + # Check for half-precision FP. + fp16 = (mvfr1 & self.MVFR1_FP16_MASK) >> self.MVFR1_FP16_SHIFT + if fp16 == self.MVFR1_FP16__SUPPORTED: + self._extensions.append(CortexMExtension.FPU_HP) + def _build_registers(self): super()._build_registers() From 419a8941639e45e64c1963de043cfb565ffe3480 Mon Sep 17 00:00:00 2001 From: Kai <60053077+kaidegit@users.noreply.github.com> Date: Mon, 14 Aug 2023 03:40:46 +0800 Subject: [PATCH 16/25] target: add support for airm2m air001 target (#1612) --- pyocd/debug/svd/data/AIR001.svd | 11580 ++++++++++++++++++++++++ pyocd/target/builtin/__init__.py | 2 + pyocd/target/builtin/target_Air001.py | 85 + 3 files changed, 11667 insertions(+) create mode 100644 pyocd/debug/svd/data/AIR001.svd create mode 100644 pyocd/target/builtin/target_Air001.py diff --git a/pyocd/debug/svd/data/AIR001.svd b/pyocd/debug/svd/data/AIR001.svd new file mode 100644 index 000000000..f49b11603 --- /dev/null +++ b/pyocd/debug/svd/data/AIR001.svd @@ -0,0 +1,11580 @@ + + + + AIR001_DFP + + AIR001 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + + CM0+ + r0p1 + little + false + false + 4 + false + + + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + ADC analog watchdog flag + 7 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOSEQ + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + ADC analog watchdog + interrupt + 7 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSEQIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC group regular conversion + calibration + 31 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR1 + CFGR1 + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + ADC analog watchdog monitored channel + selection + 26 + 4 + + + AWDEN + ADC analog watchdog enable on scope + ADC group regular + 23 + 1 + + + AWDSGL + ADC analog watchdog monitoring a + single channel or all channels + 22 + 1 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + WAIT + Wait conversion mode + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 6 + 3 + + + ALIGN + ADC data alignement + 5 + 1 + + + RESSEL + ADC data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + DMACFG + ADC DMA transfer + configuration + 1 + 1 + + + DMAEN + ADC DMA transfer enable + 0 + 1 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CKMODE + ADC clock mode + 28 + 4 + + + + + SMPR + SMPR + ADC sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP + Sampling time selection + 0 + 3 + + + + + TR + TR + ADC analog watchdog 1 threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT + ADC analog watchdog threshold + high + 16 + 12 + + + LT + ADC analog watchdog threshold + low + 0 + 12 + + + + + CHSELR + CHSELR + ADC group regular sequencer register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + CHSEL12 + Channel-12 selection + 12 + 1 + + + CHSEL11 + Channel-11 selection + 11 + 1 + + + CHSEL9 + Channel-9 selection + 9 + 1 + + + CHSEL8 + Channel-8 selection + 8 + 1 + + + CHSEL7 + Channel-7 selection + 7 + 1 + + + CHSEL6 + Channel-6 selection + 6 + 1 + + + CHSEL5 + Channel-5 selection + 5 + 1 + + + CHSEL4 + Channel-4 selection + 4 + 1 + + + CHSEL3 + Channel-3 selection + 3 + 1 + + + CHSEL2 + Channel-2 selection + 2 + 1 + + + CHSEL1 + Channel-1 selection + 1 + 1 + + + CHSEL0 + Channel-0 selection + 0 + 1 + + + + + DR + DR + ADC group regular data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + ADC group regular conversion + data + 0 + 16 + + + + + CCSR + CCSR + ADC calibration configuration and status register + 0x44 + 0x20 + read-write + 0x00000000 + + + CALON + Calibration flag + 31 + 1 + read-only + + + CALFAIL + Calibration fail flag + 30 + 1 + + + CALSET + Calibration factor selection + 15 + 1 + + + CALSMP + Calibration sample time selection + 12 + 2 + + + CALSEL + Calibration contents selection + 11 + 1 + + + + + CALRR1 + CALRR1 + ADC calibration result register 1 + 0x48 + 0x20 + read-only + 0x00000000 + + + CALBOUT + offset result + 16 + 7 + + + CALC5OUT + C5 result + 8 + 8 + + + CALC4OUT + C4 result + 0 + 8 + + + + + CALRR2 + CALRR2 + ADC calibration result register 2 + 0x4C + 0x20 + read-only + 0x00000000 + + + CALC3OUT + C3 result + 24 + 8 + + + CALC2OUT + C2 result + 16 + 8 + + + CALC1OUT + C1 result + 8 + 8 + + + CALC0OUT + C0 result + 0 + 8 + + + + + CALFIR1 + CALFIR1 + ADC calibration factor input register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CALBIO + Calibration offset factor input + 16 + 7 + + + CALC5IO + Calibration C5 factor input + 8 + 8 + + + CALC4IO + Calibration C4 factor input + 0 + 8 + + + + + CALFIR2 + CALFIR2 + ADC calibration factor input register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + CALC3IO + Calibration C3 factor input + 24 + 8 + + + CALC2IO + Calibration C2 factor input + 16 + 8 + + + CALC1IO + Calibration C1 factor input + 8 + 8 + + + CALC0IO + Calibration C0 factor input + 0 + 8 + + + + + CCR + CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + VREFINT enable + 22 + 1 + + + + + + + COMP1 + Comparator + COMP + 0x40010200 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + HYST + Comparator hysteresis enable + selector + 16 + 1 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + SCALER_EN + SCALER enable bit + 1 + 1 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + COMP2 + Comparator + COMP + 0x40010210 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator 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+ + WWDGEN + WWDG clock enable + 11 + 1 + + + RTCAPBEN + RTC APB clock enable + 10 + 1 + + + TIM3EN + TIM3 timer clock enable + 1 + 1 + + + + + APBENR2 + APBENR2 + APB peripheral clock enable register + 2 + 0x40 + 0x20 + read-write + 0x00000000 + + + LEDEN + LED clock enable + 23 + 1 + + + COMP2EN + COMP2 clock enable + 22 + 1 + + + COMP1EN + COMP1 clock enable + 21 + 1 + + + ADCEN + ADC clock enable + 20 + 1 + + + TIM17EN + TIM16 timer clock enable + 18 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM14EN + TIM14 timer clock enable + 15 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock + enable + 0 + 1 + + + + + CCIPR + CCIPR + Peripherals independent clock configuration + register + 0x54 + 0x20 + read-write + 0x00000000 + + + LPTIM1SEL + LPTIM1 clock source + selection + 18 + 2 + + + COMP2SEL + COMP2 clock source + selection + 9 + 1 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Pin reset flag + 26 + 1 + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + + + RMVF + Remove reset flags + 23 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + LSION + LSI oscillator enable + 0 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00030000 + + + HSION_CTRL + HSI open time control + 19 + 1 + + + SRAM_RETV + SRAM retention voltage control + 16 + 3 + + + LPR + Low-power run + 14 + 1 + + + FLS_SLPTIME + Flash wait time after wakeup from the stop mode + 12 + 2 + + + MRRDY_TIME + Time selection wakeup from LP to VR + 10 + 2 + + + VOS + Voltage scaling range + selection + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + BIAS_CR_SEL + MR Bias current selection + 4 + 1 + + + BIAS_CR + MR Bias current + 0 + 4 + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x20 + read-write + 0x00000500 + + + FLT_TIME + Digital filter time configuration + 9 + 3 + + + FLTEN + Digital filter enable + 8 + 1 + + + PVDT + Power voltage detector threshold + selection + 4 + 3 + + + SRCSEL + Power voltage detector volatage + selection + 2 + 1 + + + PVDE + Power voltage detector + enable + 0 + 1 + + + + + SR + SR + Power status register + 0x14 + 0x20 + read-only + 0x00000000 + + + PVDO + PVD output + 11 + 1 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xEBFFFFFF + + + MODE15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODE14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODE13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODE12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODE11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODE10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODE9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODE8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODE7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODE6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODE5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODE4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODE3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODE2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODE1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODE0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEED14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEED13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEED12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEED11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEED10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEED9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEED8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEED7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEED6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEED5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEED4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEED3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEED2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEED1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEED0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + Port input data (y = + 0..15) + 15 + 1 + + + ID14 + Port input data (y = + 0..15) + 14 + 1 + + + ID13 + Port input data (y = + 0..15) + 13 + 1 + + + ID12 + Port input data (y = + 0..15) + 12 + 1 + + + ID11 + Port input data (y = + 0..15) + 11 + 1 + + + ID10 + Port input data (y = + 0..15) + 10 + 1 + + + ID9 + Port input data (y = + 0..15) + 9 + 1 + + + ID8 + Port input data (y = + 0..15) + 8 + 1 + + + ID7 + Port input data (y = + 0..15) + 7 + 1 + + + ID6 + Port input data (y = + 0..15) + 6 + 1 + + + ID5 + Port input data (y = + 0..15) + 5 + 1 + + + ID4 + Port input data (y = + 0..15) + 4 + 1 + + + ID3 + Port input data (y = + 0..15) + 3 + 1 + + + ID2 + Port input data (y = + 0..15) + 2 + 1 + + + ID1 + Port input data (y = + 0..15) + 1 + 1 + + + ID0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + Port output data (y = + 0..15) + 15 + 1 + + + OD14 + Port output data (y = + 0..15) + 14 + 1 + + + OD13 + Port output data (y = + 0..15) + 13 + 1 + + + OD12 + Port output data (y = + 0..15) + 12 + 1 + + + OD11 + Port output data (y = + 0..15) + 11 + 1 + + + OD10 + Port output data (y = + 0..15) + 10 + 1 + + + OD9 + Port output data (y = + 0..15) + 9 + 1 + + + OD8 + Port output data (y = + 0..15) + 8 + 1 + + + OD7 + Port output data (y = + 0..15) + 7 + 1 + + + OD6 + Port output data (y = + 0..15) + 6 + 1 + + + OD5 + Port output data (y = + 0..15) + 5 + 1 + + + OD4 + Port output data (y = + 0..15) + 4 + 1 + + + OD3 + Port output data (y = + 0..15) + 3 + 1 + + + OD2 + Port output data (y = + 0..15) + 2 + 1 + + + OD1 + Port output data (y = + 0..15) + 1 + 1 + + + OD0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + Port Reset bit + 15 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR0 + Port Reset bit + 0 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x50000400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODE8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODE7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + 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0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEED8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEED7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEED6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEED5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEED4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEED3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEED2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEED1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEED0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID8 + Port input data (y = + 0..15) + 8 + 1 + + + ID7 + Port input data (y = + 0..15) + 7 + 1 + + + ID6 + Port input data (y = + 0..15) + 6 + 1 + + + ID5 + Port input data (y = + 0..15) + 5 + 1 + + + ID4 + Port input data (y = + 0..15) + 4 + 1 + + + ID3 + Port input data (y = + 0..15) + 3 + 1 + + + ID2 + Port input data (y = + 0..15) + 2 + 1 + + + ID1 + Port input data (y = + 0..15) + 1 + 1 + + + ID0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD8 + Port output data (y = + 0..15) + 8 + 1 + + + OD7 + Port output data (y = + 0..15) + 7 + 1 + + + OD6 + Port output data (y = + 0..15) + 6 + 1 + + + OD5 + Port output data (y = + 0..15) + 5 + 1 + + + OD4 + Port output data (y = + 0..15) + 4 + 1 + + + OD3 + Port output data (y = + 0..15) + 3 + 1 + + + OD2 + Port output data (y = + 0..15) + 2 + 1 + + + OD1 + Port output data (y = + 0..15) + 1 + 1 + + + OD0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR8 + Port Reset bit + 8 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR0 + Port Reset bit + 0 + 1 + + + + + + + GPIOF + 0x50001400 + + + EXTI + External interrupt/event + controller + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + PVD + PVD Interrupt through EXTI Lines 16 + 1 + + + EXTI0_1 + EXTI Line 0 and 1 Interrupt + 5 + + + EXTI2_3 + EXTI Line 2 and 3 Interrupt + 6 + + + EXTI4_15 + EXTI Line 4 to 15 Interrupt + 7 + + + + RTSR + RTSR + EXTI rising trigger selection + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RT18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + RT17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + RT16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + RT15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + RT14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + RT13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + RT12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + RT11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + RT10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + RT9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + RT8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + RT7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + RT6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + RT5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + RT4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + RT3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + RT2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + RT1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + RT0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + FTSR + FTSR + EXTI falling trigger selection + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FT18 + Falling trigger event configuration bit + of Configurable Event input + 18 + 1 + + + FT17 + Falling trigger event configuration bit + of Configurable Event input + 17 + 1 + + + FT16 + Falling trigger event configuration bit + of Configurable Event input + 16 + 1 + + + FT15 + Falling trigger event configuration bit + of Configurable Event input + 15 + 1 + + + FT14 + Falling trigger event configuration bit + of Configurable Event input + 14 + 1 + + + FT13 + Falling trigger event configuration bit + of Configurable Event input + 13 + 1 + + + FT12 + Falling trigger event configuration bit + of Configurable Event input + 12 + 1 + + + FT11 + Falling trigger event configuration bit + of Configurable Event input + 11 + 1 + + + FT10 + Falling trigger event configuration bit + of Configurable Event input + 10 + 1 + + + FT9 + Falling trigger event configuration bit + of Configurable Event input + 9 + 1 + + + FT8 + Falling trigger event configuration bit + of Configurable Event input + 8 + 1 + + + FT7 + Falling trigger event configuration bit + of Configurable Event input + 7 + 1 + + + FT6 + Falling trigger event configuration bit + of Configurable Event input + 6 + 1 + + + FT5 + Falling trigger event configuration bit + of Configurable Event input + 5 + 1 + + + FT4 + Falling trigger event configuration bit + of Configurable Event input + 4 + 1 + + + FT3 + Falling trigger event configuration bit + of Configurable Event input + 3 + 1 + + + FT2 + Falling trigger event configuration bit + of Configurable Event input + 2 + 1 + + + FT1 + Falling trigger event configuration bit + of Configurable Event input + 1 + 1 + + + FT0 + Falling trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + SWIER + SWIER + EXTI software interrupt event + register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWI18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + SWI17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + SWI16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + SWI15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + SWI14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + SWI13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + SWI12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + SWI11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + SWI10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + SWI9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + SWI8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + SWI7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + SWI6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + SWI5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + SWI4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + SWI3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + SWI2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + SWI1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + SWI0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + PR + PR + EXTI pending + register + 0xC + 0x20 + read-write + 0x00000000 + + + PR18 + configurable event inputs x rising edge + Pending bit. + 18 + 1 + + + PR17 + configurable event inputs x rising edge + Pending bit. + 17 + 1 + + + PR16 + configurable event inputs x rising edge + Pending bit. + 16 + 1 + + + PR15 + configurable event inputs x rising edge + Pending bit. + 15 + 1 + + + PR14 + configurable event inputs x rising edge + Pending bit. + 14 + 1 + + + PR13 + configurable event inputs x rising edge + Pending bit + 13 + 1 + + + PR12 + configurable event inputs x rising edge + Pending bit. + 12 + 1 + + + PR11 + configurable event inputs x rising edge + Pending bit. + 11 + 1 + + + PR10 + configurable event inputs x rising edge + Pending bit. + 10 + 1 + + + PR9 + configurable event inputs x rising edge + Pending bit. + 9 + 1 + + + PR8 + configurable event inputs x rising edge + Pending bit. + 8 + 1 + + + PR7 + configurable event inputs x rising edge + Pending bit. + 7 + 1 + + + PR6 + configurable event inputs x rising edge + Pending bit. + 6 + 1 + + + PR5 + configurable event inputs x rising edge + Pending bit. + 5 + 1 + + + PR4 + configurable event inputs x rising edge + Pending bit. + 4 + 1 + + + PR3 + configurable event inputs x rising edge + Pending bit. + 3 + 1 + + + PR2 + configurable event inputs x rising edge + Pending bit. + 2 + 1 + + + PR1 + configurable event inputs x rising edge + Pending bit. + 1 + 1 + + + PR0 + configurable event inputs x rising edge + Pending bit. + 0 + 1 + + + + + EXTICR1 + EXTICR1 + EXTI external interrupt selection + register + 0x60 + 0x20 + read-write + 0x00000000 + + + EXTI3 + GPIO port selection + 24 + 2 + + + EXTI2 + GPIO port selection + 16 + 2 + + + EXTI1 + GPIO port selection + 8 + 2 + + + EXTI0 + GPIO port selection + 0 + 2 + + + + + EXTICR2 + EXTICR2 + EXTI external interrupt selection + register + 0x64 + 0x20 + read-write + 0x00000000 + + + EXTI7 + GPIO port selection + 24 + 1 + + + EXTI6 + GPIO port selection + 16 + 1 + + + EXTI5 + GPIO port selection + 8 + 1 + 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11 + 1 + + + IM10 + CPU wakeup with interrupt mask on event + input + 10 + 1 + + + IM9 + CPU wakeup with interrupt mask on event + input + 9 + 1 + + + IM8 + CPU wakeup with interrupt mask on event + input + 8 + 1 + + + IM7 + CPU wakeup with interrupt mask on event + input + 7 + 1 + + + IM6 + CPU wakeup with interrupt mask on event + input + 6 + 1 + + + IM5 + CPU wakeup with interrupt mask on event + input + 5 + 1 + + + IM4 + CPU wakeup with interrupt mask on event + input + 4 + 1 + + + IM3 + CPU wakeup with interrupt mask on event + input + 3 + 1 + + + IM2 + CPU wakeup with interrupt mask on event + input + 2 + 1 + + + IM1 + CPU wakeup with interrupt mask on event + input + 1 + 1 + + + IM0 + CPU wakeup with interrupt mask on event + input + 0 + 1 + + + + + EMR + EMR + EXTI CPU wakeup with event mask + register + 0x84 + 0x20 + read-write + 0x00000000 + + + EM29 + CPU wakeup with event mask on event + input + 29 + 1 + + + EM19 + CPU wakeup with event mask on event + input + 19 + 1 + + + EM18 + CPU wakeup with event mask on event + input + 18 + 1 + + + EM17 + CPU wakeup with event mask on event + input + 17 + 1 + + + EM16 + CPU wakeup with event mask on event + input + 16 + 1 + + + EM15 + CPU wakeup with event mask on event + input + 15 + 1 + + + EM14 + CPU wakeup with event mask on event + input + 14 + 1 + + + EM13 + CPU wakeup with event mask on event + input + 13 + 1 + + + EM12 + CPU wakeup with event mask on event + input + 12 + 1 + + + EM11 + CPU wakeup with event mask on event + input + 11 + 1 + + + EM10 + CPU wakeup with event mask on event + input + 10 + 1 + + + EM9 + CPU wakeup with event mask on event + input + 9 + 1 + + + EM8 + CPU wakeup with event mask on event + input + 8 + 1 + + + EM7 + CPU wakeup with event mask on event + input + 7 + 1 + + + EM6 + CPU wakeup with event mask on event + input + 6 + 1 + + + EM5 + CPU wakeup with event mask on event + input + 5 + 1 + + + EM4 + CPU wakeup with event mask on event + input + 4 + 1 + + + EM3 + CPU wakeup with event mask on event + input + 3 + 1 + + + EM2 + CPU wakeup with event mask on event + input + 2 + 1 + + + EM1 + CPU wakeup with event mask on event + input + 1 + 1 + + + EM0 + CPU wakeup with event mask on event + input + 0 + 1 + + + + + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + ARRM + Autoreload match + 1 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + PRELOAD + Registers update mode + 22 + 1 + + + PRESC + Clock prescaler + 9 + 3 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after 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+ 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 32 + + + + + + + TIM14 + General purpose timer + TIM + 0x40002000 + + 0x00 + 0x400 + registers + + + TIM14 + TIM14 global Interrupt + 19 + + + + CR1 + CR1 + TIM14 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Compare/ + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Compare/capture 1 flag + 9 + 1 + + + CC1IF + Compare/capture 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Compare/capture1 event + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + OR + OR + Option register + 0x50 + 0x20 + read-write + 0x00000000 + + + TI1_RMP + TIM14 channel1 input remap + 0 + 2 + + + + + + + TIM16 + General purpose timer + TIM + 0x40014400 + + 0x00 + 0x400 + registers + + + TIM16 + TIM16 global Interrupt + 21 + + + + CR1 + CR1 + TIM16 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1DE + Compare/capture DMA requeset enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + Com interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Update interrupt flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + Com interrupt flag + 5 + 1 + + + CC1IF + Capture/Compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break event generation + 7 + 1 + + + COMG + COM evnet generation + 5 + 1 + + + CC1G + Capture/Compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global Interrupt + 22 + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x30 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + I2C_PF1_ANF + Analog filter enable control driving capability + activation bits PF1 + 30 + 1 + + + I2C_PF0_ANF + Analog filter enable control driving capability + activation bits PF0 + 29 + 1 + + + I2C_PB8_ANF + Analog filter enable control driving capability + activation bits PB8 + 28 + 1 + + + I2C_PB7_ANF + Analog filter enable control driving capability + activation bits PB7 + 27 + 1 + + I2C_PB6_ANF + Analog filter enable control driving capability + activation bits PB6 + 26 + 1 + + + I2C_PA12_ANF + Analog filter enable control driving capability + activation bits PA12 + 25 + 1 + + + I2C_PA11_ANF + Analog filter enable control driving capability + activation bits PA11 + 24 + 1 + + + I2C_PA10_ANF + Analog filter enable control driving capability + activation bits PA10 + 23 + 1 + + + I2C_PA9_ANF + Analog filter enable control driving capability + activation bits PA9 + 22 + 1 + + + I2C_PA8_ANF + Analog filter enable control driving capability + activation bits PA8 + 21 + 1 + + + I2C_PA7_ANF + Analog filter enable control driving capability + activation bits PA7 + 20 + 1 + + + I2C_PA3_ANF + Analog filter enable control driving capability + activation bits PA3 + 19 + 1 + + + I2C_PA2_ANF + Analog filter enable control driving capability + activation bits PA2 + 18 + 1 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + ETR_SRC_TIM1 + TIM1 ETR source selection + 9 + 2 + + + COMP2_BRK_TIM17 + COMP2 is enable to input of TIM17 break + 8 + 1 + + + COMP1_BRK_TIM17 + COMP1 is enable to input of TIM17 break + 7 + 1 + + + COMP2_BRK_TIM16 + COMP2 is enable to input of TIM16 break + 6 + 1 + + + COMP1_BRK_TIM16 + COMP1 is enable to input of TIM16 break + 5 + 1 + + + COMP2_BRK_TIM1 + COMP2 is enable to input of TIM1 break + 4 + 1 + + + COMP1_BRK_TIM1 + COMP1 is enable to input of TIM1 break + 3 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + LOCKUP_LOCK + Cortex-M0+ LOCKUP bit enable + bit + 0 + 1 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + DMA3_MAP + DMA channel3 requeset selection + 16 + 5 + + + DMA2_MAP + DMA channel2 requeset selection + 8 + 5 + + + DMA1_MAP + DMA channel1 requeset selection + 0 + 5 + + + + + + + DMA + Direct memory access + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_Channel1 + DMA Channel 1 Interrupt + 9 + + + DMA_Channel2_3 + DMA Channel 2 and Channel 3 Interrupt + 10 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEY + Flash key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY + Busy + 16 + 1 + + + OPTVERR + Option and Engineering bits loading + validity error + 15 + 1 + + + WRPERR + Write protected error + 4 + 1 + + + EOP + End of operation + 0 + 1 + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + OBL_LAUNCH + Force the option byte + loading + 27 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + PGTSTRT + Flash main memory program start + 19 + 1 + + + OPTSTRT + Option byte program start + 17 + 1 + + + SER + Sector erase + 11 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x4F55B0AA + + + nBOOT1 + Boot configuration + 15 + 1 + + + NRST_MODE + NRST_MODE + 14 + 1 + + + WWDG_SW + Window watchdog selection + 13 + 1 + + + IDWG_SW + Independent watchdog + selection + 12 + 1 + + + BORF_LEV + These bits contain the VDD supply level + threshold that activates the reset + 9 + 3 + + + BOREN + BOR reset Level + 8 + 1 + + + RDP + Read Protection + 0 + 8 + + + + + SDKR + SDKR + Flash SDK address + register + 0x24 + 0x20 + read-write + 0xFFE0001F + + + SDK_END + SDK area end address + 8 + 5 + + + SDK_STRT + SDK area start address + 0 + 5 + + + + + WRPR + WRPR + Flash WRP address + register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + WRP + WRP address + 0 + 16 + + + + + STCR + STCR + Flash sleep time config + register + 0x90 + 0x20 + read-write + 0x00006400 + + + SLEEP_TIME + FLash sleep time configuration(counter based on HSI_10M) + 8 + 8 + + + SLEEP_EN + FLash sleep enable + 0 + 1 + + + + + TS0 + TS0 + Flash TS0 + register + 0x100 + 0x20 + read-write + 0x000000B4 + + + TS0 + FLash TS0 register + 0 + 8 + + + + + TS1 + TS1 + Flash TS1 + register + 0x104 + 0x20 + read-write + 0x000001B0 + + + TS1 + FLash TS1 register + 0 + 9 + + + + + TS2P + TS2P + Flash TS2P + register + 0x108 + 0x20 + read-write + 0x000000B4 + + + TS2P + FLash TS2P register + 0 + 8 + + + + + TPS3 + TPS3 + Flash TPS3 + register + 0x10C + 0x20 + read-write + 0x000006C0 + + + TPS3 + FLash TPS3 register + 0 + 11 + + + + + TS3 + TS3 + Flash TS3 + register + 0x110 + 0x20 + read-write + 0x000000B4 + + + TS3 + FLash TS3 register + 0 + 8 + + + + + PERTPE + PERTPE + Flash PERTPE + register + 0x114 + 0x20 + read-write + 0x0000EA60 + + + PERTPE + FLash PERTPE register + 0 + 17 + + + + + SMERTPE + SMERTPE + Flash SMERTPE + register + 0x118 + 0x20 + read-write + 0x0000FD20 + + + SMERTPE + FLash SMERTPE register + 0 + 17 + + + + + PRGTPE + PRGTPE + Flash PRGTPE + register + 0x11C + 0x20 + read-write + 0x00008CA0 + + + PRGTPE + FLash PRGTPE register + 0 + 16 + + + + + PRETPE + PRETPE + Flash PRETPE + register + 0x120 + 0x20 + read-write + 0x000012C0 + + + PRETPE + FLash PRETPE register + 0 + 13 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave selection + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + SLVFM + Slave fast mode enable + 15 + 1 + + + LDMA_TX + Last DAM Transmit(TX) + 14 + 1 + + + LDMA_RX + Last DAM Transmit(RX) + 13 + 1 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + DS + Data length + + 11 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global Interrupt + 26 + + + + I2C + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADD + Interface address + 1 + 7 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + LED + LED CONTROLLER + LED + 0x40002400 + + 0x0 + 0x400 + registers + + + LED + LED global Interrupt + 30 + + + + CR + LED_CR + Control register + 0x0 + 0x20 + read-write + 0x0000 + + + EHS + Light control + 12 + 2 + + + IE + LED interrupt enable + 3 + 1 + + + LED_COM_SEL + LED COM Selection + 1 + 2 + + + LEDON + LED enable + 0 + 1 + + + + + PR + LED_PR + Prescaler register + 0x4 + 0x20 + read-write + 0x0000 + + + PR + Prescaler control + 0 + 8 + + + + + TR + LED_TR + Time register + 0x8 + 0x20 + read-write + 0x0000 + + + T2 + Switch time + 8 + 8 + + + T1 + Light on time + 0 + 8 + + + + + DR0 + LED_DR0 + Data0 register + 0x0C + 0x20 + read-write + 0x0000 + + + DATA0_DP + 8-bit data register + 7 + 1 + + + DATA0_G + 8-bit data register + 6 + 1 + + + DATA0_F + 8-bit data register + 5 + 1 + + + DATA0_E + 8-bit data register + 4 + 1 + + + DATA0_D + 8-bit data register + 3 + 1 + + + DATA0_C + 8-bit data register + 2 + 1 + + + DATA0_B + 8-bit data register + 1 + 1 + + + DATA0_A + 8-bit data register + 0 + 1 + + + + + DR1 + LED_DR1 + Data1 register + 0x10 + 0x20 + read-write + 0x0000 + + + DATA1_DP + 8-bit data register + 7 + 1 + + + DATA1_G + 8-bit data register + 6 + 1 + + + DATA1_F + 8-bit data register + 5 + 1 + + + DATA1_E + 8-bit data register + 4 + 1 + + + DATA1_D + 8-bit data register + 3 + 1 + + + DATA1_C + 8-bit data register + 2 + 1 + + + DATA1_B + 8-bit data register + 1 + 1 + + + DATA1_A + 8-bit data register + 0 + 1 + + + + + DR2 + LED_DR2 + Data2 register + 0x14 + 0x20 + read-write + 0x0000 + + + DATA2_DP + 8-bit data register + 7 + 1 + + + DATA2_G + 8-bit data register + 6 + 1 + + + DATA2_F + 8-bit data register + 5 + 1 + + + DATA2_E + 8-bit data register + 4 + 1 + + + DATA2_D + 8-bit data register + 3 + 1 + + + DATA2_C + 8-bit data register + 2 + 1 + + + DATA2_B + 8-bit data register + 1 + 1 + + + DATA2_A + 8-bit data register + 0 + 1 + + + + + DR3 + LED_DR3 + Data3 register + 0x18 + 0x20 + read-write + 0x0000 + + + DATA3_DP + 8-bit data register + 7 + 1 + + + DATA3_G + 8-bit data register + 6 + 1 + + + DATA3_F + 8-bit data register + 5 + 1 + + + DATA3_E + 8-bit data register + 4 + 1 + + + DATA3_D + 8-bit data register + 3 + 1 + + + DATA3_C + 8-bit data register + 2 + 1 + + + DATA3_B + 8-bit data register + 1 + 1 + + + DATA3_A + 8-bit data register + 0 + 1 + + + + + IR + LED_IR + Interrupt register 1 + 0x1C + 0x20 + 0x0000 + + + FLAG + interrupt flag + 0 + 1 + read-write + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER3_STOP + Debug Timer 3 stopped when Core is + halted + 1 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core is + halted + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core is + halted + 11 + 1 + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is + halted + 15 + 1 + + + DBG_TIMER16_STOP + Debug Timer 16 stopped when Core is + halted + 17 + 1 + + + DBG_TIMER17_STOP + Debug Timer 17 stopped when Core is + halted + 18 + 1 + + + + + + + diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index c75457099..7c81d81ce 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -131,6 +131,7 @@ from . import target_ytm32b1md1 from . import target_STM32H723xx from . import target_STM32H743xx +from . import target_Air001 ## @brief Dictionary of all builtin targets. # @@ -302,4 +303,5 @@ 'ytm32b1le0': target_ytm32b1le0.YTM32B1LE0, 'ytm32b1me0': target_ytm32b1me0.YTM32B1ME0, 'ytm32b1md1': target_ytm32b1md1.YTM32B1MD1, + 'air001': target_Air001.Air001 } diff --git a/pyocd/target/builtin/target_Air001.py b/pyocd/target/builtin/target_Air001.py new file mode 100644 index 000000000..ffd1ce687 --- /dev/null +++ b/pyocd/target/builtin/target_Air001.py @@ -0,0 +1,85 @@ +# pyOCD debugger +# Copyright (c) 2023 AirM2M +# Copyright (c) 2023 yekai +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x6842488d, 0x4b8d2107, 0x400a0349, 0x601a444b, 0x438a6842, 0x03c92101, 0x60411851, 0x4a886841, + 0x69120b49, 0x04d20349, 0x43110cd2, 0x68016041, 0xd5fc0549, 0x30404882, 0xb2ca6ac1, 0x600a4981, + 0x04126ac2, 0x610a0e12, 0x01d26ac2, 0x604a0dd2, 0xb2d26b02, 0x6b02608a, 0x0d520152, 0x6b4260ca, + 0x0bd203d2, 0x6b82614a, 0x0bd203d2, 0x6bc2618a, 0x61cab292, 0x0c006bc0, 0x47706208, 0x4c73b510, + 0x60a04871, 0x60a04872, 0xffbaf7ff, 0x60202000, 0x21016920, 0x61204308, 0x04c06a20, 0x486ed406, + 0x6001496c, 0x60412106, 0x6081496c, 0xbd102000, 0x68424861, 0x03492107, 0x4960438a, 0x68094449, + 0x6042430a, 0x035b2301, 0x495d1aca, 0x1ad2d018, 0x1ad2d011, 0x429ad00a, 0xd1036842, 0x03520b52, + 0xe0116909, 0x03520b52, 0xe00d6809, 0x68c96842, 0x03520b52, 0x6842e008, 0x0b526889, 0xe0030352, + 0x68496842, 0x03520b52, 0x0cc904c9, 0x6042430a, 0x05496801, 0x4770d5fc, 0xf7ffb500, 0x484bffc9, + 0x04826941, 0x61414311, 0xbd002000, 0x4a47b570, 0x23016910, 0x61104318, 0x24046950, 0x61504320, + 0x061d6950, 0x61504328, 0x06d920ff, 0xf3bf6008, 0x48438f4f, 0xe0004940, 0x69166008, 0xd4fb03f6, + 0x43a06950, 0x69506150, 0x615043a8, 0x07c06910, 0x2000d001, 0x6910bd70, 0x61104318, 0xbd702001, + 0x4932b530, 0x2301690a, 0x610a431a, 0x14cc694a, 0x614a4322, 0x061d694a, 0x614a432a, 0x600222ff, + 0x8f4ff3bf, 0x4a2c482e, 0x6010e000, 0x03db690b, 0x6948d4fb, 0x614843a0, 0x43a86948, 0x20006148, + 0x2001bd30, 0xb5f04770, 0x317f4d20, 0x692b09c9, 0x240101c9, 0x612b4323, 0xe0280626, 0x2401696b, + 0x616b4323, 0x4333696b, 0x2300616b, 0x5917009c, 0x2b1e5107, 0x696cd104, 0x04ff2701, 0x616c433c, + 0xb2db1c5b, 0xd3f12b20, 0x8f4ff3bf, 0x4c124b14, 0x6023e000, 0x03ff692f, 0x696bd4fb, 0x005b085b, + 0x696b616b, 0x616b43b3, 0x39803080, 0x29003280, 0x2000d1d4, 0x0000bdf0, 0x40021000, 0x00000004, + 0x1fff0f00, 0x40022100, 0x45670123, 0x40022000, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, + 0x0000aaaa, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000081, + 'pc_unInit': 0x2000011d, + 'pc_program_page': 0x200001cb, + 'pc_erase_sector': 0x20000185, + 'pc_eraseAll': 0x20000131, + + 'static_base' : 0x20000000 + 0x00000004 + 0x00000264, + 'begin_stack' : 0x20001000, + 'end_stack' : 0x20000370, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x80, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000270, + 0x200002f0 + ], + 'min_program_length' : 0x80, +} + +class Air001(CoreSightTarget): + + VENDOR = "AirM2M" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0800_0000, length=0x8000, + page_size=0x80, sector_size=0x1000, + is_boot_memory=True, algo=FLASH_ALGO), + RamRegion(start=0x2000_0000, length=0x1000) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("AIR001.svd") From bb5aaf015eb4395033b5f9197dde6244152173a8 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 13 Aug 2023 14:42:28 -0500 Subject: [PATCH 17/25] debug: sequences: support pname on DebugPort* sequences (#1607) --- docs/open_cmsis_pack_support.md | 10 ++++++++-- pyocd/coresight/coresight_target.py | 8 ++++---- pyocd/coresight/dap.py | 25 ++++++++++++------------- 3 files changed, 24 insertions(+), 19 deletions(-) diff --git a/docs/open_cmsis_pack_support.md b/docs/open_cmsis_pack_support.md index 202917c06..76eaa3c48 100644 --- a/docs/open_cmsis_pack_support.md +++ b/docs/open_cmsis_pack_support.md @@ -105,9 +105,15 @@ Only top-level sequences can be disabled individually. If a debug sequence is ca This section documents details of the debug sequence engine provided by pyOCD, supported features, and any notable differences with other debuggers (primarily Keil MDK, which provided the first implementation and against which Packs are generally most thoroughly tested by their authors). -### CPU-specific DebugPort sequences +### Core-specific sequences -Like all other debug sequences, `DebugPortSetup`, `DebugPortStart`, and `DebugPortStop` can be customised per CPU core. If a DFP has multiple CPU-specific instances of these sequences, they may behave differently in pyOCD than other debuggers. Many debuggers only "connect" to a single CPU chosen by the user when debugging or running a project. PyOCD is somewhat different in that it connects to the device as a whole, and then debugs a chosen core after the connection is established (which more closely reflects the hardware situation). +The DFP debug sequence architecture is currently based on the fact that most debuggers only "connect" to a single CPU core chosen by the user when debugging or running a project. All debug sequences can be customised per core, and there can be separate sequences for each core. + +PyOCD is somewhat different in that it connects to the device as a whole, and then debugs one or more cores after the connection is established. This more closely reflects the hardware situation. + +This primarily impacts the `DebugPortSetup`, `DebugPortStart`, `DebugPortStop`, and `DebugDeviceUnlock` debug sequences that affect the entire SoC. These relate to the connect procedure for the Arm ADI DP (Debug Port) used for SWD/JTAG communications. While most sequences can be run separately for each core, these are run only once per target connection. The core-specific variant that is selected can affect the rest of the debugging session. (Technically, this is also true for debuggers that are presented as debugging a single core, in cases where a second instance of that debugger can be started to debug another core. But, the way it's presented to the user is different.) + +The `primary_core` session option is used to select which core-specific version of the `DebugPort*`/`DebugDeviceUnlock` sequences is run during the target connection process. For all other sequences, the core-specific version that is run depends on which core is performing the action. ### Custom default reset sequences diff --git a/pyocd/coresight/coresight_target.py b/pyocd/coresight/coresight_target.py index a98eeeb60..49887d6f9 100644 --- a/pyocd/coresight/coresight_target.py +++ b/pyocd/coresight/coresight_target.py @@ -1,6 +1,6 @@ # pyOCD debugger # Copyright (c) 2015-2020 Arm Limited -# Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2021-2023 Chris Reed # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -163,7 +163,7 @@ def primary_core_pname(self) -> str: raise exceptions.Error(f"invalid 'primary_core' session option '{primary_core}' " f"(valid values are {', '.join(str(i) for i, _ in enumerate(ap_map.values()))})") - def _call_pre_discovery_debug_sequence(self, sequence: str) -> bool: + def call_pre_discovery_debug_sequence(self, sequence: str) -> bool: """@brief Run a debug sequence before discovery has been performed. The primary core's pname cannot be looked up via the `node_name` property of the core @@ -192,7 +192,7 @@ def unlock_device(self) -> None: if self.delegate_implements('unlock_device'): self.call_delegate('unlock_device') else: - self._call_pre_discovery_debug_sequence('DebugDeviceUnlock') + self.call_pre_discovery_debug_sequence('DebugDeviceUnlock') def create_discoverer(self) -> None: """@brief Init task to create the discovery object. @@ -215,7 +215,7 @@ def pre_connect(self) -> None: # Set the state variable indicating we're running ResetHardware for pre-reset, used # by the debug sequence delegate's get_connection_type() method. self.session.context_state.is_performing_pre_reset = True - if not self._call_pre_discovery_debug_sequence('ResetHardware'): + if not self.call_pre_discovery_debug_sequence('ResetHardware'): self.dp.reset() finally: self.session.context_state.is_performing_pre_reset = False diff --git a/pyocd/coresight/dap.py b/pyocd/coresight/dap.py index 995913270..741c72b49 100644 --- a/pyocd/coresight/dap.py +++ b/pyocd/coresight/dap.py @@ -21,7 +21,7 @@ import logging from enum import Enum -from typing import (Callable, Dict, List, NamedTuple, Optional, Sequence, Tuple, TYPE_CHECKING, Union, overload) +from typing import (cast, Callable, Dict, List, NamedTuple, Optional, Sequence, Tuple, TYPE_CHECKING, Union, overload) from typing_extensions import Literal from ..core import (exceptions, memory_interface) @@ -439,23 +439,22 @@ def _get_probe_capabilities(self) -> None: self._probe_supports_apv2_addresses = (DebugProbe.Capability.APv2_ADDRESSES in caps) self._have_probe_capabilities = True + # Usually when we call a debug sequence, we first check if the sequence exists. For the below + # methods, we rely on .call_pre_discovery_debug_sequence() to do this for us. def connect_debug_port_hook(self) -> Optional[bool]: - if self.has_debug_sequence('DebugPortSetup'): - assert self.debug_sequence_delegate - self.debug_sequence_delegate.run_sequence('DebugPortSetup') - return True + from .coresight_target import CoreSightTarget + cst = cast(CoreSightTarget, self.session.target) + return cst.call_pre_discovery_debug_sequence('DebugPortSetup') def enable_debug_port_hook(self) -> Optional[bool]: - if self.has_debug_sequence('DebugPortStart'): - assert self.debug_sequence_delegate - self.debug_sequence_delegate.run_sequence('DebugPortStart') - return True + from .coresight_target import CoreSightTarget + cst = cast(CoreSightTarget, self.session.target) + return cst.call_pre_discovery_debug_sequence('DebugPortStart') def disable_debug_port_hook(self) -> Optional[bool]: - if self.has_debug_sequence('DebugPortStop'): - assert self.debug_sequence_delegate - self.debug_sequence_delegate.run_sequence('DebugPortStop') - return True + from .coresight_target import CoreSightTarget + cst = cast(CoreSightTarget, self.session.target) + return cst.call_pre_discovery_debug_sequence('DebugPortStop') def _connect(self) -> None: # Connect the probe. From d64bfab1b5f833ac5ef34afe6986544fe844b1be Mon Sep 17 00:00:00 2001 From: Brian Pugh Date: Mon, 21 Aug 2023 13:13:39 -0700 Subject: [PATCH 18/25] flash: allow FlashBuilder to work when program page size is larger than sector erase size (#1608) * Allow programming of devices where sector_size < program_size (e.g. STM32H7B0) * fix sector iterator --- pyocd/flash/builder.py | 51 ++++++++++++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/pyocd/flash/builder.py b/pyocd/flash/builder.py index c38900122..3b6ff45d5 100644 --- a/pyocd/flash/builder.py +++ b/pyocd/flash/builder.py @@ -1,6 +1,7 @@ # pyOCD debugger # Copyright (c) 2015-2019 Arm Limited # Copyright (c) 2021 Chris Reed +# Copyright (c) 2023 Brian Pugh # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -94,12 +95,22 @@ def _stub_progress(percent): class _FlashSector: """@brief Info about an erase sector and all pages to be programmed within it.""" - def __init__(self, sector_info): + def __init__(self, sector_info, n_subsectors: int = 1): self.addr: int = sector_info.base_addr - self.size: int = sector_info.size + self._subsector_size: int = sector_info.size self.max_page_count: int = 0 self.page_list: List[_FlashPage] = [] self.erase_weight: float = sector_info.erase_weight + self.n_subsectors = n_subsectors + + @property + def size(self): + return self.n_subsectors * self._subsector_size + + @property + def addrs(self): + for i in range(self.n_subsectors): + yield self.addr + (i * self._subsector_size) def add_page(self, page): # The first time a page is added, compute the page count for this sector. This @@ -122,8 +133,8 @@ def mark_all_pages_not_same(self): page.same = False def __repr__(self): - return "<_FlashSector@%x addr=%x size=%x wgt=%g pages=%s>" % ( - id(self), self.addr, self.size, self.erase_weight, self.page_list) + return "<_FlashSector@%x addr=%x size=%x wgt=%g pages=%s, subsectors=%d>" % ( + id(self), self.addr, self.size, self.erase_weight, self.page_list, self.n_subsectors) class _FlashPage: """@brief A page to be programmed and its data.""" @@ -187,8 +198,8 @@ def __init__(self, flash): self.flash = flash self.flash_start = flash.region.start self.flash_operation_list = [] - self.sector_list = [] - self.page_list = [] + self.sector_list: List[_FlashSector] = [] + self.page_list: List[_FlashPage] = [] self.perf = ProgrammingInfo() self.enable_double_buffering = True self.log_performance = True @@ -285,11 +296,23 @@ def _build_sectors_and_pages(self, keep_unwritten): if page_info is None: raise FlashFailure("attempt to program invalid flash address", address=flash_addr) - current_sector = _FlashSector(sector_info) - self.sector_list.append(current_sector) + def create_flash_sector(sector_info, page_info): + if page_info.size > sector_info.size: + assert page_info.size % sector_info.size == 0, \ + f"Sector ({sector_info.size} bytes) do not fit evenly into page ({page_info.size} bytes)" + n_subsectors = page_info.size // sector_info.size + else: + n_subsectors = 1 + + return _FlashSector(sector_info, n_subsectors=n_subsectors) + current_page = _FlashPage(page_info) - current_sector.add_page(current_page) + current_sector = create_flash_sector(sector_info, page_info) + self.page_list.append(current_page) + self.sector_list.append(current_sector) + + current_sector.add_page(current_page) def fill_end_of_page_gap(): # Fill the gap at the end of the soon to be previous page if there is one @@ -314,7 +337,7 @@ def fill_end_of_page_gap(): sector_info = self.flash.get_sector_info(flash_addr) if sector_info is None: raise FlashFailure("attempt to program invalid flash address", address=flash_addr) - current_sector = _FlashSector(sector_info) + current_sector = create_flash_sector(sector_info, page_info) self.sector_list.append(current_sector) # Check if operation is in a different page @@ -807,11 +830,11 @@ def _sector_erase_program(self, progress_cb=_stub_progress): for sector in self.sector_list: if sector.are_any_pages_not_same(): - if self.region.is_erasable: # Erase the sector self.flash.init(self.flash.Operation.ERASE) - self.flash.erase_sector(sector.addr) + for addr in sector.addrs: + self.flash.erase_sector(addr) self.flash.uninit() actual_sector_erase_weight += sector.erase_weight @@ -909,14 +932,14 @@ def _sector_erase_program_double_buffer(self, progress_cb=_stub_progress): # to read from flash while simultaneously programming it. progress = self._scan_pages_for_same(progress_cb) - if self.region.is_erasable: # Erase all sectors up front. self.flash.init(self.flash.Operation.ERASE) for sector in self.sector_list: if sector.are_any_pages_not_same(): # Erase the sector - self.flash.erase_sector(sector.addr) + for addr in sector.addrs: + self.flash.erase_sector(addr) # Update progress progress += sector.erase_weight From c947c04837dde3af1e8f3434616b6b9a866e27f0 Mon Sep 17 00:00:00 2001 From: Brian Pugh Date: Tue, 29 Aug 2023 09:21:10 -0700 Subject: [PATCH 19/25] target: add STM32H7B0 Target (#1610) Add STM32H7B0 target with 'stm32h7b0xx' target type name. --- pyocd/target/builtin/__init__.py | 2 + pyocd/target/builtin/target_STM32H7B0xx.py | 189 +++++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 pyocd/target/builtin/target_STM32H7B0xx.py diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 7c81d81ce..4b21f8983 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -131,6 +131,7 @@ from . import target_ytm32b1md1 from . import target_STM32H723xx from . import target_STM32H743xx +from . import target_STM32H7B0xx from . import target_Air001 ## @brief Dictionary of all builtin targets. @@ -217,6 +218,7 @@ 'stm32l031x6' : target_STM32L031x6.STM32L031x6, 'stm32h723xx' : target_STM32H723xx.STM32H723xx, 'stm32h743xx' : target_STM32H743xx.STM32H743xx, + 'stm32h7b0xx' : target_STM32H7B0xx.STM32H7B0xx, 'w7500': target_w7500.W7500, 's5js100': target_s5js100.S5JS100, 'lpc11xx_32': target_LPC1114FN28_102.LPC11XX_32, diff --git a/pyocd/target/builtin/target_STM32H7B0xx.py b/pyocd/target/builtin/target_STM32H7B0xx.py new file mode 100644 index 000000000..3cb45c30b --- /dev/null +++ b/pyocd/target/builtin/target_STM32H7B0xx.py @@ -0,0 +1,189 @@ +# pyOCD debugger +# Copyright (c) 2023 Brian Pugh +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import time +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...coresight.cortex_m import CortexM +from ...coresight.minimal_mem_ap import MinimalMemAP as MiniAP + + +class DBGMCU: + CR = 0xE00E1004 + CR_VALUE = 0x7 # DBG_STANDBY | DBG_STOP | DBG_SLEEP + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4770ba40, 0x4770bac0, 0x0030ea4f, 0x00004770, 0x8f4ff3bf, 0xb5104770, 0x48ea4603, 0x61604cea, + 0x48e9bf00, 0xf0006900, 0x28000001, 0x48e7d1f9, 0x60604ce5, 0x606048e6, 0x4ce648e2, 0xbf006020, + 0x1f0048e4, 0xf0006800, 0x28000001, 0x48dfd1f8, 0x3c104ce0, 0x48de6020, 0xf8c44cdb, 0x46200104, + 0x200069c0, 0x4601bd10, 0x68c048d7, 0x0001f040, 0x60d04ad5, 0x380848d7, 0xf0406800, 0xf8c20001, + 0x2000010c, 0xbf004770, 0x690048cf, 0x0001f000, 0xd1f92800, 0x49cc48cb, 0x46086148, 0xf02068c0, + 0x60c80001, 0x68c04608, 0x0008f040, 0x460860c8, 0xf04068c0, 0x60c80020, 0x48c3bf00, 0xf0006900, + 0x28000001, 0x48c0d1f9, 0xf02068c0, 0x49be0008, 0xbf0060c8, 0x1f0048bf, 0xf0006800, 0x28000001, + 0x48b8d1f8, 0x600849bb, 0xf8d048b7, 0xf020010c, 0x49b50001, 0x010cf8c1, 0xf8d04608, 0xf040010c, + 0xf8c10008, 0x4608010c, 0x010cf8d0, 0x0020f040, 0x390849b0, 0xbf006008, 0x1f0048ae, 0xf0006800, + 0x28000001, 0x48abd1f8, 0x68003808, 0x0008f020, 0xf8c149a5, 0x2000010c, 0xb5104770, 0xf3c14601, + 0xf1b13247, 0xd3366f00, 0x6f01f1b1, 0x489ed233, 0x4ba16940, 0x4b9c4318, 0xbf006158, 0x6900489a, + 0x0004f000, 0xd1f92800, 0x68c04897, 0x50fef420, 0x60d84b95, 0x68c04618, 0xea432304, 0x43181382, + 0x60d84b91, 0x68c04618, 0x0020f040, 0xbf0060d8, 0x6900488d, 0x0004f000, 0xd1f92800, 0x68c0488a, + 0x0004f020, 0x60d84b88, 0x69004618, 0x0001f000, 0x2001b3f0, 0x4887bd10, 0x4b876800, 0x4b824318, + 0x0114f8c3, 0x4883bf00, 0x68001f00, 0x0004f000, 0xd1f82800, 0x3808487f, 0xf4206800, 0x4b7a50fe, + 0x010cf8c3, 0x3808487b, 0xf1a26800, 0x24040380, 0x1383ea44, 0x4b744318, 0x010cf8c3, 0xf8d04618, + 0xf040010c, 0xf8c30020, 0xbf00010c, 0x1f004871, 0xf0006800, 0x28000004, 0x486ed1f8, 0x68003808, + 0x0004f020, 0xf8c34b68, 0x486a010c, 0xe0001f00, 0x6800e005, 0x0001f000, 0x2001b108, 0xf7ffe7ba, + 0x2000fee7, 0xb5f0e7b6, 0x46164603, 0x4635461a, 0xbf002400, 0x6900485c, 0x0001f000, 0xd1f92800, + 0x4f594858, 0xbf006178, 0x1f00485a, 0xf0006800, 0x28000001, 0x4853d1f8, 0x60384f56, 0x4852e09c, + 0xf02068c0, 0x4f500001, 0x463860f8, 0xf04068c0, 0x60f80002, 0x3808484f, 0xf0206800, 0xf8c70001, + 0x4638010c, 0x010cf8d0, 0x0002f040, 0x010cf8c7, 0xd30c2910, 0xe0062400, 0x6868682f, 0x60506017, + 0x32083508, 0x2c021c64, 0x3910dbf6, 0x2400e028, 0xf815e004, 0xf8020b01, 0x1c640b01, 0xd3f8428c, + 0xe0032400, 0xf80220ff, 0x1c640b01, 0x0010f1c1, 0xd8f742a0, 0x6f00f1b3, 0xf1b3d309, 0xd2066f01, + 0x68c04831, 0x0040f040, 0x60f84f2f, 0x4831e007, 0x68003808, 0x0040f040, 0xf8c74f2b, 0x2100010c, + 0xfe76f7ff, 0x6f00f1b3, 0xf1b3d30a, 0xd2076f01, 0x4825bf00, 0xf0006900, 0x28000001, 0xe007d1f9, + 0x4824bf00, 0x68001f00, 0x0001f000, 0xd1f82800, 0x6900481d, 0x4f1f2000, 0x683f1f3f, 0xb1b04300, + 0x6f00f1b3, 0xf1b3d309, 0xd2066f01, 0x68c04816, 0x0002f020, 0x60f84f14, 0x4816e007, 0x68003808, + 0x0002f020, 0xf8c74f10, 0x2001010c, 0xf1b3bdf0, 0xd3096f00, 0x6f01f1b3, 0x480bd206, 0xf02068c0, + 0x4f090002, 0xe00760f8, 0x3808480a, 0xf0206800, 0x4f050002, 0x010cf8c7, 0xf47f2900, 0x2000af60, + 0x0000e7e4, 0x0faf0000, 0x52002000, 0x45670123, 0xcdef89ab, 0x52002114, 0x0fef0000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x2000001b, + 'pc_unInit': 0x2000006b, + 'pc_program_page': 0x2000024b, + 'pc_erase_sector': 0x2000013f, + 'pc_eraseAll': 0x2000008b, + + 'static_base' : 0x20000000 + 0x00000004 + 0x000003dc, + 'begin_stack' : 0x200113f0, + 'end_stack' : 0x200103f0, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x8000, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x200003f0, + 0x200083f0 + ], + 'min_program_length' : 0x8000, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x3dc, + 'rw_start': 0x3e0, + 'rw_size': 0x4, + 'zi_start': 0x3e4, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x40000, + 'sector_sizes': ( + (0x0, 0x2000), + ) +} + +class STM32H7B0xx(CoreSightTarget): + + VENDOR = "STMicroelectronics" + + MEMORY_MAP = MemoryMap( + # Datasheet says there's 128KB, but there's actually 256KB + FlashRegion( start=0x08000000, length=0x40000, sector_size=0x2000, + page_size=0x8000, + is_boot_memory=True, + algo=FLASH_ALGO, + name="bank_1"), + # Datasheet does not reference a flash bank 2, + # but there's an additional 256KB here, as well. + FlashRegion( start=0x08100000, length=0x40000, sector_size=0x2000, + page_size=0x8000, + algo=FLASH_ALGO, + name="bank_2"), + RamRegion( start=0x20000000, length=0x20000, name="dtcm"), + RamRegion( start=0x24000000, length=0x40000, name="axi_sram_1"), + RamRegion( start=0x24040000, length=0x60000, name="axi_sram_2"), + RamRegion( start=0x240A0000, length=0x60000, name="axi_sram_3"), + RamRegion( start=0x30000000, length=0x10000, name="ahb_sram_1"), + RamRegion( start=0x30010000, length=0x10000, name="ahb_sram_2"), + RamRegion( start=0x38000000, length=0x8000, name="sdr_sram"), + RamRegion( start=0x38800000, length=0x1000, name="backup_sram"), + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + + def assert_reset_for_connect(self): + self.dp.assert_reset(1) + + def safe_reset_and_halt(self): + assert self.dp.is_reset_asserted() + + # At this point we can't access full AP as it is not initialized yet. + # Let's create a minimalistic AP and use it. + ap = MiniAP(self.dp) + ap.init() + + DEMCR_value = ap.read32(CortexM.DEMCR) + + # Halt on reset. + ap.write32(CortexM.DEMCR, CortexM.DEMCR_VC_CORERESET) + ap.write32(CortexM.DHCSR, CortexM.DBGKEY | CortexM.C_DEBUGEN) + + # Prevent disabling bus clock/power in low power modes. + ap.write32(DBGMCU.CR, DBGMCU.CR_VALUE) + + self.dp.assert_reset(0) + time.sleep(0.01) + + # Restore DEMCR original value. + ap.write32(CortexM.DEMCR, DEMCR_value) + + def create_init_sequence(self): + # STM32 under some low power/broken clock states doesn't allow AHP communication. + # Low power modes are quite popular on stm32 (including MBed OS defaults). + # 'attach' mode is broken by default, as STM32 can't be connected on low-power mode + # successfully without previous DBGMCU setup (It is not possible to write DBGMCU). + # It is also not possible to run full pyOCD discovery code under-reset. + # + # As a solution we can setup DBGMCU under reset, halt core and release reset. + # Unfortunately this code has to be executed _before_ discovery stage + # and without discovery stage we don't have access to AP/Core. + # As a solution we can create minimalistic AP implementation and use it + # to setup core halt. + # So the sequence for 'halt' connect mode will look like + # -> Assert reset + # -> Connect DebugPort + # -> Setup MiniAp + # -> Setup halt on reset + # -> Enable support for debugging in low-power modes + # -> Release reset + # -> [Core is halted and reset is released] + # -> Continue [discovery, create cores, etc] + seq = super().create_init_sequence() + if self.session.options.get('connect_mode') in ('halt', 'under-reset'): + seq.insert_before('dp_init', ('assert_reset_for_connect', self.assert_reset_for_connect)) + seq.insert_after('dp_init', ('safe_reset_and_halt', self.safe_reset_and_halt)) + + return seq + + def post_connect_hook(self): + self.write32(DBGMCU.CR, DBGMCU.CR_VALUE) From 6d42caaeb563a65d8f19c7cfb9e516cb01fbed03 Mon Sep 17 00:00:00 2001 From: marian-m12l <50991156+marian-m12l@users.noreply.github.com> Date: Wed, 30 Aug 2023 17:57:09 +0200 Subject: [PATCH 20/25] probe: jlink: add accelerated memory interface for jlink AP 0 (#1618) * add memory interface for jlink ap 0 --------- Co-authored-by: marian --- pyocd/probe/jlink_probe.py | 124 ++++++++++++++++++++++++++++++++++++- 1 file changed, 123 insertions(+), 1 deletion(-) diff --git a/pyocd/probe/jlink_probe.py b/pyocd/probe/jlink_probe.py index 341487940..b844ddf64 100644 --- a/pyocd/probe/jlink_probe.py +++ b/pyocd/probe/jlink_probe.py @@ -1,6 +1,7 @@ # pyOCD debugger # Copyright (c) 2020 Arm Limited # Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2023 Marian Muller Rebeyrol # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,12 +22,14 @@ import pylink from pylink.enums import JLinkInterfaces from pylink.errors import (JLinkException, JLinkWriteException, JLinkReadException) -from typing import (TYPE_CHECKING, Optional, Tuple) +from typing import (TYPE_CHECKING, Optional, Tuple, Any, Sequence, Union, Callable) from .debug_probe import DebugProbe +from ..core.memory_interface import MemoryInterface from ..core import exceptions from ..core.plugin import Plugin from ..core.options import OptionInfo +from ..utility import conversion if TYPE_CHECKING: from pylink.structs import JLinkHardwareStatus @@ -126,6 +129,7 @@ def __init__(self, serial_number): self._default_protocol = None self._is_open = False self._product_name = six.ensure_str(info.acProduct) + self._memory_interfaces = {} @property def description(self): @@ -211,6 +215,7 @@ def close(self): try: self._link.close() self._is_open = False + self._memory_interfaces = {} except JLinkException as exc: raise self._convert_exception(exc) from exc @@ -450,6 +455,19 @@ def write_ap_multiple(self, addr, values): for v in values: self.write_ap(addr, v) + def get_memory_interface_for_ap(self, ap_address): + assert self._is_open + # JLink memory access commands only support AP 0 + if ap_address.apsel != 0: + return None + # JLink memory access commands require to be conneected to the target + if not self._link.target_connected(): + return None + apsel = ap_address.apsel + if apsel not in self._memory_interfaces: + self._memory_interfaces[apsel] = JLinkMemoryInterface(self._link, apsel) + return self._memory_interfaces[apsel] + def swo_start(self, baudrate): try: self._link.swo_start(int(baudrate)) @@ -483,6 +501,110 @@ def _convert_exception(exc): else: return exc +class JLinkMemoryInterface(MemoryInterface): + """@brief Concrete memory interface for a single AP.""" + + def __init__(self, link, apsel): + self._link = link + self._apsel = apsel + + def write_memory(self, addr: int, data: int, transfer_size: int=32, **attrs: Any) -> None: + """@brief Write a single memory location. + + By default the transfer size is a word. + """ + assert transfer_size in (8, 16, 32) + addr &= 0xffffffff + if transfer_size == 32: + self._link.memory_write32(addr, [data]) + elif transfer_size == 16: + self._link.memory_write16(addr, [data]) + elif transfer_size == 8: + self._link.memory_write8(addr, [data]) + + def read_memory(self, addr: int, transfer_size: int=32, now: bool=True, **attrs: Any) \ + -> Union[int, Callable[[], int]]: + """@brief Read a memory location. + + By default, a word will be read. + """ + assert transfer_size in (8, 16, 32) + addr &= 0xffffffff + if transfer_size == 32: + result = self._link.memory_read32(addr, 1)[0] + elif transfer_size == 16: + result = self._link.memory_read16(addr, 1)[0] + elif transfer_size == 8: + result = self._link.memory_read8(addr, 1)[0] + + def read_callback(): + return result + return result if now else read_callback + + def write_memory_block32(self, addr: int, data: Sequence[int], **attrs: Any) -> None: + addr &= 0xffffffff + self._link.memory_write32(addr, data) + + def read_memory_block32(self, addr: int, size: int, **attrs: Any) -> Sequence[int]: + addr &= 0xffffffff + return self._link.memory_read32(addr, size) + + def read_memory_block8(self, addr: int, size: int, **attrs: Any) -> Sequence[int]: + addr &= 0xffffffff + res = [] + + # Transfers are handled in 3 phases: + # 1. read 8-bit chunks until the first aligned address is reached, + # 2. read 32-bit chunks from all aligned addresses, + # 3. read 8-bit chunks from the remaining unaligned addresses. + # If the requested size is so small that phase-1 would not even reach + # aligned address, go straight to phase-3. + + # 1. read leading unaligned bytes + unaligned_count = 3 & (4 - addr) + if (size > unaligned_count > 0): + res += self._link.memory_read8(addr, unaligned_count) + size -= unaligned_count + addr += unaligned_count + + # 2. read aligned block of 32 bits + if (size >= 4): + aligned_size = size & ~3 + res += conversion.u32le_list_to_byte_list(self._link.memory_read32(addr, aligned_size//4)) + size -= aligned_size + addr += aligned_size + + # 3. read trailing unaligned bytes + if (size > 0): + res += self._link.memory_read8(addr, size) + + return res + + def write_memory_block8(self, addr: int, data: Sequence[int], **attrs: Any) -> None: + addr &= 0xffffffff + size = len(data) + idx = 0 + + # write leading unaligned bytes + unaligned_count = 3 & (4 - addr) + if (size > unaligned_count > 0): + self._link.memory_write8(addr, data[:unaligned_count]) + size -= unaligned_count + addr += unaligned_count + idx += unaligned_count + + # write aligned block of 32 bits + if (size >= 4): + aligned_size = size & ~3 + self._link.memory_write32(addr, conversion.byte_list_to_u32le_list(data[idx:idx + aligned_size])) + size -= aligned_size + addr += aligned_size + idx += aligned_size + + # write trailing unaligned bytes + if (size > 0): + self._link.memory_write8(addr, data[idx:]) + class JLinkProbePlugin(Plugin): """@brief Plugin class for JLinkProbe.""" From d532e452c54eea42edd9d434df59cf70483cc9b8 Mon Sep 17 00:00:00 2001 From: Hardy Griech Date: Wed, 30 Aug 2023 18:07:36 +0200 Subject: [PATCH 21/25] probe: cmsis-dap: very basic implementation to get a "connect" LED status display (#1620) --- pyocd/probe/pydapaccess/dap_access_cmsis_dap.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py b/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py index 1934fe332..23fc03fe9 100644 --- a/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py +++ b/pyocd/probe/pydapaccess/dap_access_cmsis_dap.py @@ -60,6 +60,10 @@ class SWOStatus: RUNNING = 3 ERROR = 4 +class DAP_LED: + DAP_DEBUGGER_CONNECTED = 0 + DAP_TARGET_RUNNING = 1 + LOG = logging.getLogger(__name__) TRACE = LOG.getChild("trace") @@ -922,6 +926,9 @@ def connect(self, port=DAPAccessIntf.PORT.DEFAULT): elif self._dap_port == DAPAccessIntf.PORT.JTAG: self.configure_jtag() + self._protocol.set_led(DAP_LED.DAP_DEBUGGER_CONNECTED, 1) + self._protocol.set_led(DAP_LED.DAP_TARGET_RUNNING, 0) + @locked def configure_swd(self, turnaround=1, always_send_data_phase=False): self.flush() @@ -950,6 +957,8 @@ def jtag_sequence(self, cycles, tms, read_tdo, tdi): @locked def disconnect(self): self.flush() + self._protocol.set_led(DAP_LED.DAP_DEBUGGER_CONNECTED, 0) + self._protocol.set_led(DAP_LED.DAP_TARGET_RUNNING, 0) self._protocol.disconnect() def has_swo(self): From 5f02a94b2c58650e8c14a529520197d445e8ba20 Mon Sep 17 00:00:00 2001 From: HalfSweet <60973476+HalfSweet@users.noreply.github.com> Date: Thu, 31 Aug 2023 00:09:36 +0800 Subject: [PATCH 22/25] target: add support for airm2m air32f103 target (#1615) * add: support Air32F103xB * add: support Air32F103xC * add: combine and support Air32F103xc/xg/xe --- pyocd/debug/svd/data/AIR32F103xx.svd | 24923 +++++++++++++++++++ pyocd/target/builtin/__init__.py | 8 +- pyocd/target/builtin/target_Air32F103xx.py | 275 + 3 files changed, 25205 insertions(+), 1 deletion(-) create mode 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MODE3 + Port n.3 mode bits + 12 + 2 + + + CNF3 + Port n.3 configuration + bits + 14 + 2 + + + MODE4 + Port n.4 mode bits + 16 + 2 + + + CNF4 + Port n.4 configuration + bits + 18 + 2 + + + MODE5 + Port n.5 mode bits + 20 + 2 + + + CNF5 + Port n.5 configuration + bits + 22 + 2 + + + MODE6 + Port n.6 mode bits + 24 + 2 + + + CNF6 + Port n.6 configuration + bits + 26 + 2 + + + MODE7 + Port n.7 mode bits + 28 + 2 + + + CNF7 + Port n.7 configuration + bits + 30 + 2 + + + + + CRH + CRH + Port configuration register high + (GPIOn_CRL) + 0x4 + 0x20 + read-write + 0x44444444 + + + MODE8 + Port n.8 mode bits + 0 + 2 + + + CNF8 + Port n.8 configuration + bits + 2 + 2 + + + MODE9 + Port n.9 mode bits + 4 + 2 + + + CNF9 + Port n.9 configuration + bits + 6 + 2 + + + MODE10 + Port n.10 mode bits + 8 + 2 + + + CNF10 + Port n.10 configuration + bits + 10 + 2 + + + MODE11 + Port n.11 mode bits + 12 + 2 + + + CNF11 + Port n.11 configuration + bits + 14 + 2 + + + MODE12 + Port n.12 mode bits + 16 + 2 + + + CNF12 + Port n.12 configuration + bits + 18 + 2 + + + MODE13 + Port n.13 mode bits + 20 + 2 + + + CNF13 + Port n.13 configuration + bits + 22 + 2 + + + MODE14 + Port n.14 mode bits + 24 + 2 + + + CNF14 + Port n.14 configuration + bits + 26 + 2 + + + MODE15 + Port n.15 mode bits + 28 + 2 + + + CNF15 + Port n.15 configuration + bits + 30 + 2 + + + + + IDR + IDR + Port input data register + (GPIOn_IDR) + 0x8 + 0x20 + read-only + 0x00000000 + + + IDR0 + Port input data + 0 + 1 + + + IDR1 + Port input data + 1 + 1 + + + IDR2 + Port input data + 2 + 1 + + + IDR3 + Port input data + 3 + 1 + + + IDR4 + Port input data + 4 + 1 + + + IDR5 + Port input data + 5 + 1 + + + IDR6 + Port input data + 6 + 1 + + + IDR7 + Port input data + 7 + 1 + + + IDR8 + Port input data + 8 + 1 + + + IDR9 + Port input data + 9 + 1 + + + IDR10 + Port input data + 10 + 1 + + + IDR11 + Port input data + 11 + 1 + + + IDR12 + Port input data + 12 + 1 + + + IDR13 + Port input data + 13 + 1 + + + IDR14 + Port input data + 14 + 1 + + + IDR15 + Port input data + 15 + 1 + + + + + ODR + ODR + Port output data register + (GPIOn_ODR) + 0xC + 0x20 + read-write + 0x00000000 + + + ODR0 + Port output data + 0 + 1 + + + ODR1 + Port output data + 1 + 1 + + + ODR2 + Port output data + 2 + 1 + + + ODR3 + Port output data + 3 + 1 + + + ODR4 + Port output data + 4 + 1 + + + ODR5 + Port output data + 5 + 1 + + + ODR6 + Port output data + 6 + 1 + + + ODR7 + Port output data + 7 + 1 + + + ODR8 + Port output data + 8 + 1 + + + ODR9 + Port output data + 9 + 1 + + + ODR10 + Port output data + 10 + 1 + + + ODR11 + Port output data + 11 + 1 + + + ODR12 + Port output data + 12 + 1 + + + ODR13 + Port output data + 13 + 1 + + + ODR14 + Port output data + 14 + 1 + + + ODR15 + Port output data + 15 + 1 + + + + + BSRR + BSRR + Port bit set/reset register + (GPIOn_BSRR) + 0x10 + 0x20 + write-only + 0x00000000 + + + BS0 + Set bit 0 + 0 + 1 + + + BS1 + Set bit 1 + 1 + 1 + + + BS2 + Set bit 1 + 2 + 1 + + + BS3 + Set bit 3 + 3 + 1 + + + BS4 + Set bit 4 + 4 + 1 + + + BS5 + Set bit 5 + 5 + 1 + + + BS6 + Set bit 6 + 6 + 1 + + + BS7 + Set bit 7 + 7 + 1 + + + BS8 + Set bit 8 + 8 + 1 + + + BS9 + Set bit 9 + 9 + 1 + + + BS10 + Set bit 10 + 10 + 1 + + + BS11 + Set bit 11 + 11 + 1 + + + BS12 + Set bit 12 + 12 + 1 + + + BS13 + Set bit 13 + 13 + 1 + + + BS14 + Set bit 14 + 14 + 1 + + + BS15 + Set bit 15 + 15 + 1 + + + BR0 + Reset bit 0 + 16 + 1 + + + BR1 + Reset bit 1 + 17 + 1 + + + BR2 + Reset bit 2 + 18 + 1 + + + BR3 + Reset bit 3 + 19 + 1 + + + BR4 + Reset bit 4 + 20 + 1 + + + BR5 + Reset bit 5 + 21 + 1 + + + BR6 + Reset bit 6 + 22 + 1 + + + BR7 + Reset bit 7 + 23 + 1 + + + BR8 + Reset bit 8 + 24 + 1 + + + BR9 + Reset bit 9 + 25 + 1 + + + BR10 + Reset bit 10 + 26 + 1 + + + BR11 + Reset bit 11 + 27 + 1 + + + BR12 + Reset bit 12 + 28 + 1 + + + BR13 + Reset bit 13 + 29 + 1 + + + BR14 + Reset bit 14 + 30 + 1 + + + BR15 + Reset bit 15 + 31 + 1 + + + + + BRR + BRR + Port bit reset register + (GPIOn_BRR) + 0x14 + 0x20 + write-only + 0x00000000 + + + BR0 + Reset bit 0 + 0 + 1 + + + BR1 + Reset bit 1 + 1 + 1 + + + BR2 + Reset bit 1 + 2 + 1 + + + BR3 + Reset bit 3 + 3 + 1 + + + BR4 + Reset bit 4 + 4 + 1 + + + BR5 + Reset bit 5 + 5 + 1 + + + BR6 + Reset bit 6 + 6 + 1 + + + BR7 + Reset bit 7 + 7 + 1 + + + BR8 + Reset bit 8 + 8 + 1 + + + BR9 + Reset bit 9 + 9 + 1 + + + BR10 + Reset bit 10 + 10 + 1 + + + BR11 + Reset bit 11 + 11 + 1 + + + BR12 + Reset bit 12 + 12 + 1 + + + BR13 + Reset bit 13 + 13 + 1 + + + BR14 + Reset bit 14 + 14 + 1 + + + BR15 + Reset bit 15 + 15 + 1 + + + + + LCKR + LCKR + Port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LCK0 + Port A Lock bit 0 + 0 + 1 + + + LCK1 + Port A Lock bit 1 + 1 + 1 + + + LCK2 + Port A Lock bit 2 + 2 + 1 + + + LCK3 + Port A Lock bit 3 + 3 + 1 + + + LCK4 + Port A Lock bit 4 + 4 + 1 + + + LCK5 + Port A Lock bit 5 + 5 + 1 + + + LCK6 + Port A Lock bit 6 + 6 + 1 + + + LCK7 + Port A Lock bit 7 + 7 + 1 + + + LCK8 + Port A Lock bit 8 + 8 + 1 + + + LCK9 + Port A Lock bit 9 + 9 + 1 + + + LCK10 + Port A Lock bit 10 + 10 + 1 + + + LCK11 + Port A Lock bit 11 + 11 + 1 + + + LCK12 + Port A Lock bit 12 + 12 + 1 + + + LCK13 + Port A Lock bit 13 + 13 + 1 + + + LCK14 + Port A Lock bit 14 + 14 + 1 + + + LCK15 + Port A Lock bit 15 + 15 + 1 + + + LCKK + Lock key + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + GPIOF + 0x40011C00 + + + GPIOG + 0x40012000 + + + AFIO + Alternate function I/O + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVCR + EVCR + Event Control Register + (AFIO_EVCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + PIN + Pin selection + 0 + 4 + + + PORT + Port selection + 4 + 3 + + + EVOE + Event Output Enable + 7 + 1 + + + + + MAPR + MAPR + AF remap and debug I/O configuration + register (AFIO_MAPR) + 0x4 + 0x20 + 0x00000000 + + + SPI1_REMAP + SPI1 remapping + 0 + 1 + read-write + + + I2C1_REMAP + I2C1 remapping + 1 + 1 + read-write + + + USART1_REMAP + USART1 remapping + 2 + 1 + read-write + + + USART2_REMAP + USART2 remapping + 3 + 1 + read-write + + + USART3_REMAP + USART3 remapping + 4 + 2 + read-write + + + TIM1_REMAP + TIM1 remapping + 6 + 2 + read-write + + + TIM2_REMAP + TIM2 remapping + 8 + 2 + read-write + + + TIM3_REMAP + TIM3 remapping + 10 + 2 + read-write + + + TIM4_REMAP + TIM4 remapping + 12 + 1 + read-write + + + CAN_REMAP + CAN1 remapping + 13 + 2 + read-write + + + PD01_REMAP + Port D0/Port D1 mapping on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TIM5CH4_IREMAP + Set and cleared by + software + 16 + 1 + read-write + + + ADC1_ETRGINJ_REMAP + ADC 1 External trigger injected + conversion remapping + 17 + 1 + read-write + + + ADC1_ETRGREG_REMAP + ADC 1 external trigger regular + conversion remapping + 18 + 1 + read-write + + + ADC2_ETRGINJ_REMAP + ADC 2 external trigger injected + conversion remapping + 19 + 1 + read-write + + + ADC2_ETRGREG_REMAP + ADC 2 external trigger regular + conversion remapping + 20 + 1 + read-write + + + SWJ_CFG + Serial wire JTAG + configuration + 24 + 3 + write-only + + + + + EXTICR1 + EXTICR1 + External interrupt configuration register 1 + (AFIO_EXTICR1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 configuration + 0 + 4 + + + EXTI1 + EXTI1 configuration + 4 + 4 + + + EXTI2 + EXTI2 configuration + 8 + 4 + + + EXTI3 + EXTI3 configuration + 12 + 4 + + + + + EXTICR2 + EXTICR2 + External interrupt configuration register 2 + (AFIO_EXTICR2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI4 + EXTI4 configuration + 0 + 4 + + + EXTI5 + EXTI5 configuration + 4 + 4 + + + EXTI6 + EXTI6 configuration + 8 + 4 + + + EXTI7 + EXTI7 configuration + 12 + 4 + + + + + EXTICR3 + EXTICR3 + External interrupt configuration register 3 + (AFIO_EXTICR3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI8 + EXTI8 configuration + 0 + 4 + + + EXTI9 + EXTI9 configuration + 4 + 4 + + + EXTI10 + EXTI10 configuration + 8 + 4 + + + EXTI11 + EXTI11 configuration + 12 + 4 + + + + + EXTICR4 + EXTICR4 + External interrupt configuration register 4 + (AFIO_EXTICR4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI12 + EXTI12 configuration + 0 + 4 + + + EXTI13 + EXTI13 configuration + 4 + 4 + + + EXTI14 + EXTI14 configuration + 8 + 4 + + + EXTI15 + EXTI15 configuration + 12 + 4 + + + + + MAPR2 + MAPR2 + AF remap and debug I/O configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM9_REMAP + TIM9 remapping + 5 + 1 + + + TIM10_REMAP + TIM10 remapping + 6 + 1 + + + TIM11_REMAP + TIM11 remapping + 7 + 1 + + + TIM13_REMAP + TIM13 remapping + 8 + 1 + + + TIM14_REMAP + TIM14 remapping + 9 + 1 + + + FSMC_NADV + NADV connect/disconnect + 10 + 1 + + + + + + + EXTI + EXTI + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + DMA channel configuration register + (DMA_CCR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + DMA channel configuration register + (DMA_CCR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + DMA channel configuration register + (DMA_CCR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + DMA channel configuration register + (DMA_CCR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + (SDIO_CLKCR) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock divide factor + 0 + 8 + + + CLKEN + Clock enable bit + 8 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + + + ARG + ARG + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + SDIO command register + (SDIO_CMD) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + CMDINDEX + 0 + 6 + + + WAITRESP + WAITRESP + 6 + 2 + + + WAITINT + WAITINT + 8 + 1 + + + WAITPEND + WAITPEND + 9 + 1 + + + CPSMEN + CPSMEN + 10 + 1 + + + SDIOSuspend + SDIOSuspend + 11 + 1 + + + ENCMDcompl + ENCMDcompl + 12 + 1 + + + nIEN + nIEN + 13 + 1 + + + CE_ATACMD + CE_ATACMD + 14 + 1 + + + + + RESPCMD + RESPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + RESPCMD + 0 + 6 + + + + + RESPI1 + RESPI1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + CARDSTATUS1 + 0 + 32 + + + + + RESP2 + RESP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + CARDSTATUS2 + 0 + 32 + + + + + RESP3 + RESP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + CARDSTATUS3 + 0 + 32 + + + + + RESP4 + RESP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + CARDSTATUS4 + 0 + 32 + + + + + DTIMER + DTIMER + Bits 31:0 = DATATIME: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + DTEN + 0 + 1 + + + DTDIR + DTDIR + 1 + 1 + + + DTMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + DBLOCKSIZE + DBLOCKSIZE + 4 + 4 + + + PWSTART + PWSTART + 8 + 1 + + + PWSTOP + PWSTOP + 9 + 1 + + + RWMOD + RWMOD + 10 + 1 + + + SDIOEN + SDIOEN + 11 + 1 + + + + + DCOUNT + DCOUNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + CCRCFAIL + 0 + 1 + + + DCRCFAIL + DCRCFAIL + 1 + 1 + + + CTIMEOUT + CTIMEOUT + 2 + 1 + + + DTIMEOUT + DTIMEOUT + 3 + 1 + + + TXUNDERR + TXUNDERR + 4 + 1 + + + RXOVERR + RXOVERR + 5 + 1 + + + CMDREND + CMDREND + 6 + 1 + + + CMDSENT + CMDSENT + 7 + 1 + + + DATAEND + DATAEND + 8 + 1 + + + STBITERR + STBITERR + 9 + 1 + + + DBCKEND + DBCKEND + 10 + 1 + + + CMDACT + CMDACT + 11 + 1 + + + TXACT + TXACT + 12 + 1 + + + RXACT + RXACT + 13 + 1 + + + TXFIFOHE + TXFIFOHE + 14 + 1 + + + RXFIFOHF + RXFIFOHF + 15 + 1 + + + TXFIFOF + TXFIFOF + 16 + 1 + + + RXFIFOF + RXFIFOF + 17 + 1 + + + TXFIFOE + TXFIFOE + 18 + 1 + + + RXFIFOE + RXFIFOE + 19 + 1 + + + TXDAVL + TXDAVL + 20 + 1 + + + RXDAVL + RXDAVL + 21 + 1 + + + SDIOIT + SDIOIT + 22 + 1 + + + CEATAEND + CEATAEND + 23 + 1 + + + + + ICR + ICR + SDIO interrupt clear register + (SDIO_ICR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAILC + 0 + 1 + + + DCRCFAILC + DCRCFAILC + 1 + 1 + + + CTIMEOUTC + CTIMEOUTC + 2 + 1 + + + DTIMEOUTC + DTIMEOUTC + 3 + 1 + + + TXUNDERRC + TXUNDERRC + 4 + 1 + + + RXOVERRC + RXOVERRC + 5 + 1 + + + CMDRENDC + CMDRENDC + 6 + 1 + + + CMDSENTC + CMDSENTC + 7 + 1 + + + DATAENDC + DATAENDC + 8 + 1 + + + STBITERRC + STBITERRC + 9 + 1 + + + DBCKENDC + DBCKENDC + 10 + 1 + + + SDIOITC + SDIOITC + 22 + 1 + + + CEATAENDC + CEATAENDC + 23 + 1 + + + + + MASK + MASK + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + CCRCFAILIE + 0 + 1 + + + DCRCFAILIE + DCRCFAILIE + 1 + 1 + + + CTIMEOUTIE + CTIMEOUTIE + 2 + 1 + + + DTIMEOUTIE + DTIMEOUTIE + 3 + 1 + + + TXUNDERRIE + TXUNDERRIE + 4 + 1 + + + RXOVERRIE + RXOVERRIE + 5 + 1 + + + CMDRENDIE + CMDRENDIE + 6 + 1 + + + CMDSENTIE + CMDSENTIE + 7 + 1 + + + DATAENDIE + DATAENDIE + 8 + 1 + + + STBITERRIE + STBITERRIE + 9 + 1 + + + DBACKENDIE + DBACKENDIE + 10 + 1 + + + CMDACTIE + CMDACTIE + 11 + 1 + + + TXACTIE + TXACTIE + 12 + 1 + + + RXACTIE + RXACTIE + 13 + 1 + + + TXFIFOHEIE + TXFIFOHEIE + 14 + 1 + + + RXFIFOHFIE + RXFIFOHFIE + 15 + 1 + + + TXFIFOFIE + TXFIFOFIE + 16 + 1 + + + RXFIFOFIE + RXFIFOFIE + 17 + 1 + + + TXFIFOEIE + TXFIFOEIE + 18 + 1 + + + RXFIFOEIE + RXFIFOEIE + 19 + 1 + + + TXDAVLIE + TXDAVLIE + 20 + 1 + + + RXDAVLIE + RXDAVLIE + 21 + 1 + + + SDIOITIE + SDIOITIE + 22 + 1 + + + CEATENDIE + CEATENDIE + 23 + 1 + + + + + FIFOCNT + FIFOCNT + Bits 23:0 = FIFOCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + FIF0COUNT + FIF0COUNT + 0 + 24 + + + + + FIFO + FIFO + bits 31:0 = FIFOData: Receive and transmit + FIFO data + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + FIFOData + 0 + 32 + + + + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + RTCAlarm + RTC Alarms through EXTI line + interrupt + 41 + + + + CRH + CRH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + SECIE + Second interrupt Enable + 0 + 1 + + + ALRIE + Alarm interrupt Enable + 1 + 1 + + + OWIE + Overflow interrupt Enable + 2 + 1 + + + + + CRL + CRL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + SECF + Second Flag + 0 + 1 + read-write + + + ALRF + Alarm Flag + 1 + 1 + read-write + + + OWF + Overflow Flag + 2 + 1 + read-write + + + RSF + Registers Synchronized + Flag + 3 + 1 + read-write + + + CNF + Configuration Flag + 4 + 1 + read-write + + + RTOFF + RTC operation OFF + 5 + 1 + read-only + + + + + PRLH + PRLH + RTC Prescaler Load Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + PRLH + RTC Prescaler Load Register + High + 0 + 4 + + + + + PRLL + PRLL + RTC Prescaler Load Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + PRLL + RTC Prescaler Divider Register + Low + 0 + 16 + + + + + DIVH + DIVH + RTC Prescaler Divider Register + High + 0x10 + 0x20 + read-only + 0x00000000 + + + DIVH + RTC prescaler divider register + high + 0 + 4 + + + + + DIVL + DIVL + RTC Prescaler Divider Register + Low + 0x14 + 0x20 + read-only + 0x8000 + + + DIVL + RTC prescaler divider register + Low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNTH + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNTL + RTC counter register Low + 0 + 16 + + + + + ALRH + ALRH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + ALRH + RTC alarm register high + 0 + 16 + + + + + ALRL + ALRL + RTC Alarm Register Low + 0x24 + 0x20 + write-only + 0xFFFF + + + ALRL + RTC alarm register low + 0 + 16 + + + + + + + BKP + Backup registers + BKP + 0x40006C04 + + 0x0 + 0x400 + registers + + + + DR1 + DR1 + Backup data register (BKP_DR) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1 + Backup data + 0 + 16 + + + + + DR2 + DR2 + Backup data register (BKP_DR) + 0x4 + 0x20 + read-write + 0x00000000 + + + D2 + Backup data + 0 + 16 + + + + + DR3 + DR3 + Backup data register (BKP_DR) + 0x8 + 0x20 + read-write + 0x00000000 + + + D3 + Backup data + 0 + 16 + + + + + DR4 + DR4 + Backup data register (BKP_DR) + 0xC + 0x20 + read-write + 0x00000000 + + + D4 + Backup data + 0 + 16 + + + + + DR5 + DR5 + Backup data register (BKP_DR) + 0x10 + 0x20 + read-write + 0x00000000 + + + D5 + Backup data + 0 + 16 + + + + + DR6 + DR6 + Backup data register (BKP_DR) + 0x14 + 0x20 + read-write + 0x00000000 + + + D6 + Backup data + 0 + 16 + + + + + DR7 + DR7 + Backup data register (BKP_DR) + 0x18 + 0x20 + read-write + 0x00000000 + + + D7 + Backup data + 0 + 16 + + + + + DR8 + DR8 + Backup data register (BKP_DR) + 0x1C + 0x20 + read-write + 0x00000000 + + + D8 + Backup data + 0 + 16 + + + + + DR9 + DR9 + Backup data register (BKP_DR) + 0x20 + 0x20 + read-write + 0x00000000 + + + D9 + Backup data + 0 + 16 + + + + + DR10 + DR10 + Backup data register (BKP_DR) + 0x24 + 0x20 + read-write + 0x00000000 + + + D10 + Backup data + 0 + 16 + + + + + DR11 + DR11 + Backup data register (BKP_DR) + 0x3C + 0x20 + read-write + 0x00000000 + + + DR11 + Backup data + 0 + 16 + + + + + DR12 + DR12 + Backup data register (BKP_DR) + 0x40 + 0x20 + read-write + 0x00000000 + + + DR12 + Backup data + 0 + 16 + + + + + DR13 + DR13 + Backup data register (BKP_DR) + 0x44 + 0x20 + read-write + 0x00000000 + + + DR13 + Backup data + 0 + 16 + + + + + DR14 + DR14 + Backup data register (BKP_DR) + 0x48 + 0x20 + read-write + 0x00000000 + + + D14 + Backup data + 0 + 16 + + + + + DR15 + DR15 + Backup data register (BKP_DR) + 0x4C + 0x20 + read-write + 0x00000000 + + + D15 + Backup data + 0 + 16 + + + + + DR16 + DR16 + Backup data register (BKP_DR) + 0x50 + 0x20 + read-write + 0x00000000 + + + D16 + Backup data + 0 + 16 + + + + + DR17 + DR17 + Backup data register (BKP_DR) + 0x54 + 0x20 + read-write + 0x00000000 + + + D17 + Backup data + 0 + 16 + + + + + DR18 + DR18 + Backup data register (BKP_DR) + 0x58 + 0x20 + read-write + 0x00000000 + + + D18 + Backup data + 0 + 16 + + + + + DR19 + DR19 + Backup data register (BKP_DR) + 0x5C + 0x20 + read-write + 0x00000000 + + + D19 + Backup data + 0 + 16 + + + + + DR20 + DR20 + Backup data register (BKP_DR) + 0x60 + 0x20 + read-write + 0x00000000 + + + D20 + Backup data + 0 + 16 + + + + + DR21 + DR21 + Backup data register (BKP_DR) + 0x64 + 0x20 + read-write + 0x00000000 + + + D21 + Backup data + 0 + 16 + + + + + DR22 + DR22 + Backup data register (BKP_DR) + 0x68 + 0x20 + read-write + 0x00000000 + + + D22 + Backup data + 0 + 16 + + + + + DR23 + DR23 + Backup data register (BKP_DR) + 0x6C + 0x20 + read-write + 0x00000000 + + + D23 + Backup data + 0 + 16 + + + + + DR24 + DR24 + Backup data register (BKP_DR) + 0x70 + 0x20 + read-write + 0x00000000 + + + D24 + Backup data + 0 + 16 + + + + + DR25 + DR25 + Backup data register (BKP_DR) + 0x74 + 0x20 + read-write + 0x00000000 + + + D25 + Backup data + 0 + 16 + + + + + DR26 + DR26 + Backup data register (BKP_DR) + 0x78 + 0x20 + read-write + 0x00000000 + + + D26 + Backup data + 0 + 16 + + + + + DR27 + DR27 + Backup data register (BKP_DR) + 0x7C + 0x20 + read-write + 0x00000000 + + + D27 + Backup data + 0 + 16 + + + + + DR28 + DR28 + Backup data register (BKP_DR) + 0x80 + 0x20 + read-write + 0x00000000 + + + D28 + Backup data + 0 + 16 + + + + + DR29 + DR29 + Backup data register (BKP_DR) + 0x84 + 0x20 + read-write + 0x00000000 + + + D29 + Backup data + 0 + 16 + + + + + DR30 + DR30 + Backup data register (BKP_DR) + 0x88 + 0x20 + read-write + 0x00000000 + + + D30 + Backup data + 0 + 16 + + + + + DR31 + DR31 + Backup data register (BKP_DR) + 0x8C + 0x20 + read-write + 0x00000000 + + + D31 + Backup data + 0 + 16 + + + + + DR32 + DR32 + Backup data register (BKP_DR) + 0x90 + 0x20 + read-write + 0x00000000 + + + D32 + Backup data + 0 + 16 + + + + + DR33 + DR33 + Backup data register (BKP_DR) + 0x94 + 0x20 + read-write + 0x00000000 + + + D33 + Backup data + 0 + 16 + + + + + DR34 + DR34 + Backup data register (BKP_DR) + 0x98 + 0x20 + read-write + 0x00000000 + + + D34 + Backup data + 0 + 16 + + + + + DR35 + DR35 + Backup data register (BKP_DR) + 0x9C + 0x20 + read-write + 0x00000000 + + + D35 + Backup data + 0 + 16 + + + + + DR36 + DR36 + Backup data register (BKP_DR) + 0xA0 + 0x20 + read-write + 0x00000000 + + + D36 + Backup data + 0 + 16 + + + + + DR37 + DR37 + Backup data register (BKP_DR) + 0xA4 + 0x20 + read-write + 0x00000000 + + + D37 + Backup data + 0 + 16 + + + + + DR38 + DR38 + Backup data register (BKP_DR) + 0xA8 + 0x20 + read-write + 0x00000000 + + + D38 + Backup data + 0 + 16 + + + + + DR39 + DR39 + Backup data register (BKP_DR) + 0xAC + 0x20 + read-write + 0x00000000 + + + D39 + Backup data + 0 + 16 + + + + + DR40 + DR40 + Backup data register (BKP_DR) + 0xB0 + 0x20 + read-write + 0x00000000 + + + D40 + Backup data + 0 + 16 + + + + + DR41 + DR41 + Backup data register (BKP_DR) + 0xB4 + 0x20 + read-write + 0x00000000 + + + D41 + Backup data + 0 + 16 + + + + + DR42 + DR42 + Backup data register (BKP_DR) + 0xB8 + 0x20 + read-write + 0x00000000 + + + D42 + Backup data + 0 + 16 + + + + + RTCCR + RTCCR + RTC clock calibration register + (BKP_RTCCR) + 0x28 + 0x20 + read-write + 0x00000000 + + + CAL + Calibration value + 0 + 7 + + + CCO + Calibration Clock Output + 7 + 1 + + + ASOE + Alarm or second output + enable + 8 + 1 + + + ASOS + Alarm or second output + selection + 9 + 1 + + + + + CR + CR + Backup control register + (BKP_CR) + 0x2C + 0x20 + read-write + 0x00000000 + + + TPE + Tamper pin enable + 0 + 1 + + + TPAL + Tamper pin active level + 1 + 1 + + + + + CSR + CSR + BKP_CSR control/status register + (BKP_CSR) + 0x30 + 0x20 + 0x00000000 + + + CTE + Clear Tamper event + 0 + 1 + write-only + + + CTI + Clear Tamper Interrupt + 1 + 1 + write-only + + + TPIE + Tamper Pin interrupt + enable + 2 + 1 + read-write + + + TEF + Tamper Event Flag + 8 + 1 + read-only + + + TIF + Tamper Interrupt Flag + 9 + 1 + read-only + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + WDGA + Activation bit + 7 + 1 + + + + + CFR + CFR + Configuration register + (WWDG_CFR) + 0x4 + 0x20 + read-write + 0x0000007F + + + W + 7-bit window value + 0 + 7 + + + WDGTB + Timer Base + 7 + 2 + + + EWI + Early Wakeup Interrupt + 9 + 1 + + + + + SR + SR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EWI + Early Wakeup Interrupt + 0 + 1 + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + 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Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + + + TIM8 + 0x40013400 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare interrupt + 46 + + + + TIM2 + General purpose timer + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output 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2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global interrupt + 50 + + + + TIM9 + General purpose timer + TIM + 0x40014C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + 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DAC channel2 mask/amplitude + selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + + + SWTRIGR + SWTRIGR + DAC software trigger register + (DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + + DHR12R1 + DHR12R1 + DAC channel1 12-bit right-aligned data + holding register(DAC_DHR12R1) + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + DAC channel1 12-bit left aligned data + holding register (DAC_DHR12L1) + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + DAC channel1 8-bit right aligned data + holding register (DAC_DHR8R1) + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + DAC channel2 12-bit right aligned data + holding register (DAC_DHR12R2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + DAC channel2 12-bit left aligned data + holding register (DAC_DHR12L2) + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + DAC channel2 8-bit right-aligned data + holding register (DAC_DHR8R2) + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 + Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 + Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register (DAC_DHR8RD), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output register + (DAC_DOR1) + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output register + (DAC_DOR2) + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + DBG + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DBGMCU_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + CR + CR + DBGMCU_CR + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + DBG_IWDG_STOP + DBG_IWDG_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 9 + 1 + + + DBG_TIM1_STOP + DBG_TIM1_STOP + 10 + 1 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 11 + 1 + + + DBG_TIM3_STOP + DBG_TIM3_STOP + 12 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 13 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 14 + 1 + + + DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT + 15 + 1 + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + 16 + 1 + + + DBG_TIM8_STOP + DBG_TIM8_STOP + 17 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 18 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 19 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 20 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 21 + 1 + + + + + + + UART4 + Universal asynchronous receiver + transmitter + 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enable receiver + 6 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + + + + + UART5 + Universal asynchronous receiver + transmitter + USART + 0x40005000 + + 0x0 + 0x400 + registers + + + UART5 + UART5 global interrupt + 53 + + + + SR + SR + UART4_SR + 0x0 + 0x20 + 0x0 + + + PE + PE + 0 + 1 + read-only + + + FE + FE + 1 + 1 + read-only + + + NE + NE + 2 + 1 + read-only + + + ORE + ORE + 3 + 1 + read-only + + + IDLE + IDLE + 4 + 1 + read-only + + + RXNE + RXNE + 5 + 1 + read-write + + + TC + TC + 6 + 1 + read-write + + + TXE + TXE + 7 + 1 + read-only + + + LBD + LBD + 8 + 1 + read-write + + + + + DR + DR + UART4_DR + 0x4 + 0x20 + read-write + 0x0 + + + DR + DR + 0 + 9 + + + + + BRR + BRR + UART4_BRR + 0x8 + 0x20 + read-write + 0x0 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + + + CR1 + CR1 + UART4_CR1 + 0xC + 0x20 + read-write + 0x0 + + + SBK + SBK + 0 + 1 + + + RWU + RWU + 1 + 1 + + + RE + RE + 2 + 1 + + + TE + TE + 3 + 1 + + + IDLEIE + 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IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + FLASH + FLASH + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000030 + + + LATENCY + Latency + 0 + 3 + read-write + + + HLFCYA + Flash half cycle access + enable + 3 + 1 + read-write + + + PRFTBE + Prefetch buffer enable + 4 + 1 + read-write + + + PRFTBS + Prefetch buffer status + 5 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRTERR + Write protection error + 4 + 1 + read-write + + + PGERR + Programming error + 2 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + PG + Programming + 0 + 1 + + + PER + Page Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + OPTPG + Option byte programming + 4 + 1 + + + OPTER + Option byte erase + 5 + 1 + + + STRT + Start + 6 + 1 + + + LOCK + Lock + 7 + 1 + + + OPTWRE + Option bytes write enable + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + + + AR + AR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash Address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + OPTERR + Option byte error + 0 + 1 + + + RDPRT + Read protection + 1 + 1 + + + WDG_SW + WDG_SW + 2 + 1 + + + nRST_STOP + nRST_STOP + 3 + 1 + + + nRST_STDBY + nRST_STDBY + 4 + 1 + + + Data0 + Data0 + 10 + 8 + + + Data1 + Data1 + 18 + 8 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB + Universal serial bus full-speed device + interface + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + USB_FS_WKUP + USB Device FS Wakeup through EXTI line + interrupt + 42 + + + + EP0R + EP0R + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP1R + EP1R + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP2R + EP2R + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP3R + EP3R + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP4R + EP4R + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP5R + EP5R + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP6R + EP6R + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP7R + EP7R + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + CNTR + USB_CNTR + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + ESOFM + Expected start of frame interrupt + mask + 8 + 1 + + + SOFM + Start of frame interrupt + mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt + mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun + interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt + mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EP_ID + Endpoint Identifier + 0 + 4 + + + DIR + Direction of transaction + 4 + 1 + + + ESOF + Expected start frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RESET + reset request + 10 + 1 + + + SUSP + Suspend mode request + 11 + 1 + + + WKUP + Wakeup + 12 + 1 + + + ERR + Error + 13 + 1 + + + PMAOVR + Packet memory area over / + underrun + 14 + 1 + + + CTR + Correct transfer + 15 + 1 + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADD + Device address + 0 + 7 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + + + diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 4b21f8983..c6e0a00a2 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -133,6 +133,7 @@ from . import target_STM32H743xx from . import target_STM32H7B0xx from . import target_Air001 +from . import target_Air32F103xx ## @brief Dictionary of all builtin targets. # @@ -305,5 +306,10 @@ 'ytm32b1le0': target_ytm32b1le0.YTM32B1LE0, 'ytm32b1me0': target_ytm32b1me0.YTM32B1ME0, 'ytm32b1md1': target_ytm32b1md1.YTM32B1MD1, - 'air001': target_Air001.Air001 + 'air001': target_Air001.Air001, + 'air32f103xb': target_Air32F103xx.Air32F103xB, + 'air32f103xc': target_Air32F103xx.Air32F103xC, + 'air32f103xp': target_Air32F103xx.Air32F103xP, + 'air32f103xe': target_Air32F103xx.Air32F103xE, + 'air32f103xg': target_Air32F103xx.Air32F103xG, } diff --git a/pyocd/target/builtin/target_Air32F103xx.py b/pyocd/target/builtin/target_Air32F103xx.py new file mode 100644 index 000000000..1b88f1e83 --- /dev/null +++ b/pyocd/target/builtin/target_Air32F103xx.py @@ -0,0 +1,275 @@ +# pyOCD debugger +# Copyright (c) 2023 AirM2M +# Copyright (c) 2023 HalfSweet +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...coresight.coresight_target import CoreSightTarget +from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap) +from ...debug.svd.loader import SVDFile + +FLASH_128k_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4603b510, 0x04c00cd8, 0x444c4c47, 0x20006020, 0x60204c46, 0x60604846, 0x60604846, 0x69c04620, + 0x0004f000, 0xf245b940, 0x4c435055, 0x20066020, 0xf6406060, 0x60a070ff, 0xbd102000, 0x483b4601, + 0xf0406900, 0x4a390080, 0x20006110, 0x48374770, 0xf0406900, 0x49350004, 0x46086108, 0xf0406900, + 0x61080040, 0xf64ae003, 0x493320aa, 0x482f6008, 0xf00068c0, 0x28000001, 0x482cd1f5, 0xf0206900, + 0x492a0004, 0x20006108, 0x46014770, 0x69004827, 0x0002f040, 0x61104a25, 0x61414610, 0xf0406900, + 0x61100040, 0xf64ae003, 0x4a2320aa, 0x481f6010, 0xf00068c0, 0x28000001, 0x481cd1f5, 0xf0206900, + 0x4a1a0002, 0x20006110, 0xb5104770, 0x1c484603, 0x0101f020, 0x4815e023, 0xf0406900, 0x4c130001, + 0x88106120, 0xbf008018, 0x68c04810, 0x0001f000, 0xd1f92800, 0x6900480d, 0x0001f020, 0x61204c0b, + 0x68c04620, 0x0014f000, 0x4620b130, 0xf04068c0, 0x60e00014, 0xbd102001, 0x1c921c9b, 0x29001e89, + 0x2000d1d9, 0x0000e7f7, 0x00000004, 0x40022000, 0x45670123, 0xcdef89ab, 0x40003000, 0x00000000, + 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000041, + 'pc_program_page': 0x200000cf, + 'pc_erase_sector': 0x2000008f, + 'pc_eraseAll': 0x20000053, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000013c, + 'begin_stack' : 0x20001950, + 'end_stack' : 0x20000950, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000150, + 0x20000550 + ], + 'min_program_length' : 0x400, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x13c, + 'rw_start': 0x140, + 'rw_size': 0x8, + 'zi_start': 0x148, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x20000, + 'sector_sizes': ( + (0x0, 0x400), + ) +} + +FLASH_512k_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4603b510, 0x04c00cd8, 0x444c4c47, 0x20006020, 0x60204c46, 0x60604846, 0x60604846, 0x69c04620, + 0x0004f000, 0xf245b940, 0x4c435055, 0x20066020, 0xf6406060, 0x60a070ff, 0xbd102000, 0x483b4601, + 0xf0406900, 0x4a390080, 0x20006110, 0x48374770, 0xf0406900, 0x49350004, 0x46086108, 0xf0406900, + 0x61080040, 0xf64ae003, 0x493320aa, 0x482f6008, 0xf00068c0, 0x28000001, 0x482cd1f5, 0xf0206900, + 0x492a0004, 0x20006108, 0x46014770, 0x69004827, 0x0002f040, 0x61104a25, 0x61414610, 0xf0406900, + 0x61100040, 0xf64ae003, 0x4a2320aa, 0x481f6010, 0xf00068c0, 0x28000001, 0x481cd1f5, 0xf0206900, + 0x4a1a0002, 0x20006110, 0xb5104770, 0x1c484603, 0x0101f020, 0x4815e023, 0xf0406900, 0x4c130001, + 0x88106120, 0xbf008018, 0x68c04810, 0x0001f000, 0xd1f92800, 0x6900480d, 0x0001f020, 0x61204c0b, + 0x68c04620, 0x0014f000, 0x4620b130, 0xf04068c0, 0x60e00014, 0xbd102001, 0x1c921c9b, 0x29001e89, + 0x2000d1d9, 0x0000e7f7, 0x00000004, 0x40022000, 0x45670123, 0xcdef89ab, 0x40003000, 0x00000000, + 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000041, + 'pc_program_page': 0x200000cf, + 'pc_erase_sector': 0x2000008f, + 'pc_eraseAll': 0x20000053, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000013c, + 'begin_stack' : 0x20001950, + 'end_stack' : 0x20000950, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000150, + 0x20000550 + ], + 'min_program_length' : 0x400, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x13c, + 'rw_start': 0x140, + 'rw_size': 0x8, + 'zi_start': 0x148, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x80000, + 'sector_sizes': ( + (0x0, 0x800), + ) +} + +FLASH_1024k_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xe7fdbe00, + 0x4603b510, 0x04c00cd8, 0x444c4c83, 0x20006020, 0x60204c82, 0x60604882, 0x60604882, 0x64604880, + 0x64604880, 0x69c04620, 0x0004f000, 0xf245b940, 0x4c7d5055, 0x20066020, 0xf6406060, 0x60a070ff, + 0xbd102000, 0x48754601, 0xf0406900, 0x4a730080, 0x46106110, 0xf0406d00, 0x65100080, 0x47702000, + 0x6900486e, 0x0004f040, 0x6108496c, 0x69004608, 0x0040f040, 0xe0036108, 0x20aaf64a, 0x6008496a, + 0x68c04866, 0x0001f000, 0xd1f52800, 0x69004863, 0x0004f020, 0x61084961, 0x6d004608, 0x0004f040, + 0x46086508, 0xf0406d00, 0x65080040, 0xf64ae003, 0x495d20aa, 0x48596008, 0xf0006cc0, 0x28000001, + 0x4856d1f5, 0xf0206d00, 0x49540004, 0x20006508, 0x46014770, 0x44484850, 0xf5006800, 0x42812000, + 0x484ed21d, 0xf0406900, 0x4a4c0002, 0x46106110, 0x69006141, 0x0040f040, 0xe0036110, 0x20aaf64a, + 0x60104a49, 0x68c04845, 0x0001f000, 0xd1f52800, 0x69004842, 0x0002f020, 0x61104a40, 0x483fe01c, + 0xf0406d00, 0x4a3d0002, 0x46106510, 0x6d006541, 0x0040f040, 0xe0036510, 0x20aaf64a, 0x60104a3a, + 0x6cc04836, 0x0001f000, 0xd1f52800, 0x6d004833, 0x0002f020, 0x65104a31, 0x47702000, 0x4603b510, + 0xf0201c48, 0x482c0101, 0x68004448, 0x2000f500, 0xd2274283, 0x4829e023, 0xf0406900, 0x4c270001, + 0x88106120, 0xbf008018, 0x68c04824, 0x0001f000, 0xd1f92800, 0x69004821, 0x0001f020, 0x61204c1f, + 0x68c04620, 0x0014f000, 0x4620b130, 0xf04068c0, 0x60e00014, 0xbd102001, 0x1c921c9b, 0x29001e89, + 0xe026d1d9, 0x4815e023, 0xf0406d00, 0x4c130001, 0x88106520, 0xbf008018, 0x6cc04810, 0x0001f000, + 0xd1f92800, 0x6d00480d, 0x0001f020, 0x65204c0b, 0x6cc04620, 0x0014f000, 0x4620b130, 0xf0406cc0, + 0x64e00014, 0xe7d62001, 0x1c921c9b, 0x29001e89, 0x2000d1d9, 0x0000e7cf, 0x00000004, 0x40022000, + 0x45670123, 0xcdef89ab, 0x40003000, 0x00000000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000005, + 'pc_unInit': 0x20000049, + 'pc_program_page': 0x20000161, + 'pc_erase_sector': 0x200000d7, + 'pc_eraseAll': 0x20000065, + + 'static_base' : 0x20000000 + 0x00000004 + 0x0000022c, + 'begin_stack' : 0x20001a40, + 'end_stack' : 0x20000a40, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x400, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + # Enable double buffering + 'page_buffers' : [ + 0x20000240, + 0x20000640 + ], + 'min_program_length' : 0x400, + + # Relative region addresses and sizes + 'ro_start': 0x4, + 'ro_size': 0x22c, + 'rw_start': 0x230, + 'rw_size': 0x8, + 'zi_start': 0x238, + 'zi_size': 0x0, + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x100000, + 'sector_sizes': ( + (0x0, 0x1000), + ) +} + +class Air32F103xB(CoreSightTarget): + + VENDOR = "AirM2M" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0800_0000, length=0x20000, + blocksize=0x400, is_boot_memory=True, + algo=FLASH_128k_ALGO), + RamRegion(start=0x2000_0000, length=0x18000 + ) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("AIR32F103xx.svd") + +class Air32F103xC(CoreSightTarget): + + VENDOR = "AirM2M" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0800_0000, length=0x40000, + blocksize=0x400, is_boot_memory=True, + algo=FLASH_512k_ALGO), + RamRegion(start=0x2000_0000, length=0x18000 + ) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("AIR32F103xx.svd") + +class Air32F103xP(CoreSightTarget): + + VENDOR = "AirM2M" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0800_0000, length=0x80000, + blocksize=0x400, is_boot_memory=True, + algo=FLASH_512k_ALGO), + RamRegion(start=0x2000_0000, length=0x18000 + ) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("AIR32F103xx.svd") + +class Air32F103xE(CoreSightTarget): + + VENDOR = "AirM2M" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0800_0000, length=0x80000, + blocksize=0x400, is_boot_memory=True, + algo=FLASH_512k_ALGO), + RamRegion(start=0x2000_0000, length=0x18000 + ) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("AIR32F103xx.svd") + +class Air32F103xG(CoreSightTarget): + + VENDOR = "AirM2M" + + MEMORY_MAP = MemoryMap( + FlashRegion(start=0x0800_0000, length=0x100000, + blocksize=0x1000, is_boot_memory=True, + algo=FLASH_1024k_ALGO), + RamRegion(start=0x2000_0000, length=0x18000 + ) + ) + + def __init__(self, session): + super().__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("AIR32F103xx.svd") From ef74216c6ddf722b7800ebd1eef71c133b423810 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 25 Sep 2023 11:45:24 -0500 Subject: [PATCH 23/25] coresight: cortex-m: always evaluate deferred read of MVFR2 (#1613) A deferred read of MVFR2 is queued, but the value isn't used unless an FPU is detected. This fix always evaluates the deferred read of this register to prevent the CMSIS-DAP read queue from getting stuck. --- pyocd/coresight/cortex_m.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/pyocd/coresight/cortex_m.py b/pyocd/coresight/cortex_m.py index 0b505a8ed..72d900eaf 100644 --- a/pyocd/coresight/cortex_m.py +++ b/pyocd/coresight/cortex_m.py @@ -516,13 +516,15 @@ def _check_for_fpu(self) -> None: self.has_fpu = ((sp_val == self.MVFR0_SINGLE_PRECISION_SUPPORTED) or (dp_val == self.MVFR0_DOUBLE_PRECISION_SUPPORTED)) + # Deferred reads must always be evaluated, to prevent the read queue getting stuck, so read + # this outside the 'if' below even if we don't use it. + mvfr2 = mvfr2_cb() + if self.has_fpu: self._extensions.append(CortexMExtension.FPU) # Now check the VFP version by looking for support for the misc FP instructions added in # FPv5 (VMINNM, VMAXNM, etc). - - mvfr2 = mvfr2_cb() vfp_misc_val = (mvfr2 & CortexM.MVFR2_VFP_MISC_MASK) >> CortexM.MVFR2_VFP_MISC_SHIFT if dp_val == self.MVFR0_DOUBLE_PRECISION_SUPPORTED: From 48887960154aada6c33f861d91707f39676cb6f9 Mon Sep 17 00:00:00 2001 From: Sadik Ozer <46590392+ozersa@users.noreply.github.com> Date: Mon, 25 Sep 2023 19:45:52 +0300 Subject: [PATCH 24/25] Update copyright section (#1621) Signed-off-by: Sadik.Ozer --- pyocd/target/builtin/target_MAX32660.py | 2 +- pyocd/target/builtin/target_MAX32666.py | 2 +- pyocd/target/builtin/target_MAX32670.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pyocd/target/builtin/target_MAX32660.py b/pyocd/target/builtin/target_MAX32660.py index 60585b456..8cdc1750a 100644 --- a/pyocd/target/builtin/target_MAX32660.py +++ b/pyocd/target/builtin/target_MAX32660.py @@ -1,5 +1,5 @@ # pyOCD debugger -# Copyright (c) 2017-2021 Maxim Integrated (Part of Analog Devices) +# Copyright (c) 2021 Maxim Integrated (now owned by Analog Devices, Inc.) # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pyocd/target/builtin/target_MAX32666.py b/pyocd/target/builtin/target_MAX32666.py index a7dd625e6..82d6c057c 100644 --- a/pyocd/target/builtin/target_MAX32666.py +++ b/pyocd/target/builtin/target_MAX32666.py @@ -1,5 +1,5 @@ # pyOCD debugger -# Copyright (c) 2023 PyOCD Authors +# Copyright (c) 2023 Analog Devices, Inc. # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pyocd/target/builtin/target_MAX32670.py b/pyocd/target/builtin/target_MAX32670.py index 4873dd191..8b4a08d73 100644 --- a/pyocd/target/builtin/target_MAX32670.py +++ b/pyocd/target/builtin/target_MAX32670.py @@ -1,5 +1,5 @@ # pyOCD debugger -# Copyright (c) 2017-2022 Analog Devices Inc +# Copyright (c) 2022 Analog Devices, Inc. # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); From c684bdf3b6d471bb881071ece1755b5094c8cd86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20S=C3=B8lberg?= Date: Tue, 26 Sep 2023 20:04:06 +0200 Subject: [PATCH 25/25] board: remove extra space in generic cortex-m warning message (#1625) --- pyocd/board/board.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pyocd/board/board.py b/pyocd/board/board.py index 9754f3b48..20c29b843 100644 --- a/pyocd/board/board.py +++ b/pyocd/board/board.py @@ -1,6 +1,7 @@ # pyOCD debugger # Copyright (c) 2006-2013,2018 Arm Limited # Copyright (c) 2021-2022 Chris Reed +# Copyright (c) 2023 Benjamin Sølberg # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -77,7 +78,7 @@ def __init__(self, if session.options.get('warning.cortex_m_default'): LOG.warning("Generic 'cortex_m' target type is selected by default; is this " "intentional? You will be able to debug most devices, but not program " - " flash. To set the target type use the '--target' argument or " + "flash. To set the target type use the '--target' argument or " "'target_override' option. Use 'pyocd list --targets' to see available " "targets types.")