Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Rev.1.0.20 DDR initialize fails on salvator-x #5

Open
fisaksen opened this issue May 24, 2018 · 9 comments
Open

Rev.1.0.20 DDR initialize fails on salvator-x #5

fisaksen opened this issue May 24, 2018 · 9 comments

Comments

@fisaksen
Copy link

I just built the latest version
(Rev.1.0.20) fromhttps://github.com/renesas-rcar/arm-trusted-firmware.git

and initializing DDR fails:

[ 0.000283] NOTICE: BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.20
[ 0.005843] NOTICE: BL2: PRR is R-Car H3 Ver1.1
[ 0.010426] NOTICE: BL2: Board is Salvator-X Rev1.0
[ 0.015368] NOTICE: BL2: Boot device is HyperFlash(80MHz)
[ 0.020793] NOTICE: BL2: LCM state is CM
[ 0.024838] NOTICE: BL2: AVS setting succeeded. DVFS_SetVID=0x53
[ 0.030887] NOTICE: BL2: DDR2400(rev.0.31)NOTICE: [COLD_BOOT]NOTICE: ..1
[ 0.162859] NOTICE: BL2: Failed to DRAM initialize (-1).

Using Rev.1.0.19 (commit: 3f4912a) is working.

@hosoya
Copy link
Contributor

hosoya commented May 30, 2018

Hello,

Thank you for report.

Using Rev.1.0.19 (commit: 3f4912a) is working.

We found R-Car H3 Ver.1.1 DDR setting bug in Rev.1.0.20(commit: 1eee0ad).
It was fixed in Rev 1.0.21(commit: c71e1be).

Regards,

@mozoko
Copy link

mozoko commented Jun 7, 2018

I got same error using rev 1.0.20 (commit: 0340c68) and later.
1.0.19 rev2 (commit: 3f4912a) works fine.
The board is Salvator-XS with R-Car H3 ver2.0.

[    0.000062] INFO:    ARM GICv2 driver initialized
[    0.003345] NOTICE:  BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.20
[    0.010292] NOTICE:  BL2: PRR is R-Car H3 Ver2.0
[    0.015032] NOTICE:  BL2: Board is Salvator-XS Rev1.0
[    0.019892] NOTICE:  BL2: Boot device is HyperFlash(80MHz)
[    0.025323] NOTICE:  BL2: LCM state is CM
[    0.029357] NOTICE:  BL2: AVS setting succeeded. DVFS_SetVID=0x53
[    0.035376] NOTICE:  BL2: DDR1600(rev.0.31rc02)NOTICE:  [COLD_BOOT]NOTICE:  ..1
[    0.057088] NOTICE:  BL2: Failed to DRAM initialize (-1).

@hosoya
Copy link
Contributor

hosoya commented Jun 27, 2018

Hello,

[ 0.010292] NOTICE: BL2: PRR is R-Car H3 Ver2.0
[ 0.035376] NOTICE: BL2: DDR1600(rev.0.31rc02)NOTICE: [COLD_BOOT]NOTICE: ..1

DDR 3200 mode is expected for Salvator-XS with R-Car H3 ver2.0.
Could you check Salvator-XS DDR clock frequency (SW10:MD19 and MD17)?

Regards,

@fisaksen
Copy link
Author

I only have the Salavtor-X with ver 1.1. Is DDR 3200 supposed to work with that as well ?

@mozoko
Copy link

mozoko commented Jun 29, 2018

Hi, hosoya

On your advice, I changed PIN 3, 4 to ON from OFF in SW10 and succeeded to boot kernel.
Thanks!!

@hosoya
Copy link
Contributor

hosoya commented Jul 6, 2018

Hello,

[ 0.005843] NOTICE: BL2: PRR is R-Car H3 Ver1.1

I only have the Salavtor-X with ver 1.1. Is DDR 3200 supposed to work with that as well ?

R-Car H3 Ver1.1 supports to DDR2400.

regards,

omihalac added a commit to omihalac/arm-trusted-firmware that referenced this issue Feb 4, 2019
…OMIHALAC/arm-trusted-firmware:xilinx_generic_updates to master

* commit 'e94603c4e51bc600aaa4ec9a8115a6b5aee85690':
  plat: zynqmp: Add support for CG/EG/EV device detection
  cadence: Change logic in uart driver
@tianming1992
Copy link

I got same error using rev 1.0.20 (commit: 0340c68) and later.
1.0.19 rev2 (commit: 3f4912a) works fine.
The board is Salvator-XS with R-Car H3 ver2.0.

[    0.000062] INFO:    ARM GICv2 driver initialized
[    0.003345] NOTICE:  BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.20
[    0.010292] NOTICE:  BL2: PRR is R-Car H3 Ver2.0
[    0.015032] NOTICE:  BL2: Board is Salvator-XS Rev1.0
[    0.019892] NOTICE:  BL2: Boot device is HyperFlash(80MHz)
[    0.025323] NOTICE:  BL2: LCM state is CM
[    0.029357] NOTICE:  BL2: AVS setting succeeded. DVFS_SetVID=0x53
[    0.035376] NOTICE:  BL2: DDR1600(rev.0.31rc02)NOTICE:  [COLD_BOOT]NOTICE:  ..1
[    0.057088] NOTICE:  BL2: Failed to DRAM initialize (-1).

hi, I've got a similar error on salavtor-xs as following print info, any body have ideas about this?
0.000163] NOTICE: BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.20
[ 0.005736] NOTICE: BL2: PRR is R-Car H3 Ver3.0
[ 0.010326] NOTICE: BL2: Board is Salvator-XS Rev1.0
[ 0.015361] NOTICE: BL2: Boot device is HyperFlash(160MHz)
[ 0.020883] NOTICE: BL2: LCM state is CM
[ 0.024928] NOTICE: BL2: AVS setting succeeded. DVFS_SetVID=0x53
[ 0.030913] NOTICE: BL2: CH0: 0x400000000 - 0x440000000, 1 GiB
[ 0.036784] NOTICE: BL2: CH1: 0x500000000 - 0x540000000, 1 GiB
[ 0.042668] NOTICE: BL2: CH2: 0x600000000 - 0x640000000, 1 GiB
[ 0.048553] NOTICE: BL2: CH3: 0x700000000 - 0x740000000, 1 GiB
[ 0.054478] NOTICE: BL2: DDR3200(rev.0.31)NOTICE: [WARM_BOOT]ERROR:
Warm booting...
The potential of BKUP_TRG did not switch to Low.
If you expect the operation of cold boot,
check the board configuration (ex, Dip-SW) and/or the H/W failure.
[ 0.087737] NOTICE: [BOOT_STATUS_UPDATE_ERROR]NOTICE: ..1
[ 0.093277] NOTICE: BL2: Failed to DRAM initialize (-1).
[ 5.007798] ERROR:
[ 5.008592] ERROR: BL2: System WDT overflow, occured address is 0xe6312c78

@truongtx1982
Copy link

I got same error using rev 1.0.20 (commit: 0340c68) and later.
1.0.19 rev2 (commit: 3f4912a) works fine.
The board is Salvator-XS with R-Car H3 ver2.0.

[    0.000062] INFO:    ARM GICv2 driver initialized
[    0.003345] NOTICE:  BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.20
[    0.010292] NOTICE:  BL2: PRR is R-Car H3 Ver2.0
[    0.015032] NOTICE:  BL2: Board is Salvator-XS Rev1.0
[    0.019892] NOTICE:  BL2: Boot device is HyperFlash(80MHz)
[    0.025323] NOTICE:  BL2: LCM state is CM
[    0.029357] NOTICE:  BL2: AVS setting succeeded. DVFS_SetVID=0x53
[    0.035376] NOTICE:  BL2: DDR1600(rev.0.31rc02)NOTICE:  [COLD_BOOT]NOTICE:  ..1
[    0.057088] NOTICE:  BL2: Failed to DRAM initialize (-1).

Hi

You can try to re-build it with option as below, so It may related to DDR size on the board, this command to build for H3 Salvator 4G DDR,
make PLAT=rcar LSI=H3 RCAR_SYSTEM_SUSPEND=0 RCAR_DRAM_LPDDR4_MEMCONF=0

Regards,
Truong

@tianming1992
Copy link

I got same error using rev 1.0.20 (commit: 0340c68) and later.
1.0.19 rev2 (commit: 3f4912a) works fine.
The board is Salvator-XS with R-Car H3 ver2.0.

[    0.000062] INFO:    ARM GICv2 driver initialized
[    0.003345] NOTICE:  BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.20
[    0.010292] NOTICE:  BL2: PRR is R-Car H3 Ver2.0
[    0.015032] NOTICE:  BL2: Board is Salvator-XS Rev1.0
[    0.019892] NOTICE:  BL2: Boot device is HyperFlash(80MHz)
[    0.025323] NOTICE:  BL2: LCM state is CM
[    0.029357] NOTICE:  BL2: AVS setting succeeded. DVFS_SetVID=0x53
[    0.035376] NOTICE:  BL2: DDR1600(rev.0.31rc02)NOTICE:  [COLD_BOOT]NOTICE:  ..1
[    0.057088] NOTICE:  BL2: Failed to DRAM initialize (-1).

Hi

You can try to re-build it with option as below, so It may related to DDR size on the board, this command to build for H3 Salvator 4G DDR,
make PLAT=rcar LSI=H3 RCAR_SYSTEM_SUSPEND=0 RCAR_DRAM_LPDDR4_MEMCONF=0

Regards,
Truong

That's OK! Thanks!!!

takeshikihara pushed a commit that referenced this issue Oct 25, 2023
 - Cite crash reports as an example of sensitive
   information. Previously, it might have sounded like this was the
   focus of the threat.

 - Warn about logging high-precision timing information, as well as
   conditionally logging (potentially nonsensitive) information
   depending on sensitive information.

Change-Id: I33232dcb1e4b5c81efd4cd621b24ab5ac7b58685
Signed-off-by: Sandrine Bailleux <[email protected]>
takeshikihara pushed a commit that referenced this issue Oct 25, 2023
* changes:
  docs(threat-model): broaden the scope of threat #5
  docs(threat-model): emphasize whether mitigations are implemented
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

5 participants