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richjyoung/vscode-modern-vhdl
Initialization of record type signals is not colored uniformely when using | operator

Hello, The issue is the following: I have a package with this record declared type myRecord_t is record a : std_logic; b : std_logic_vector(7 downto 0); c : std_logic_vector(7 downto 0); end ...
  • jacopobelli
  • 1
  • Opened 
    on Jun 21, 2021
  • #40

richjyoung/vscode-modern-vhdl
wrong functionality in shortcut for the brackets

hi. while shortcut for the brackets is enabled, and You press “ [ “ Open Square Brackets, In order to replace by “ ( “ Open Round brackets, The shortcut is working but both: “ ( “ and “ [ “ are writing... ...
  • MohammadNiknam17
  • Opened 
    on May 16, 2021
  • #39

richjyoung/vscode-modern-vhdl
Code highlight error on entity instantiation with name ending with ***is followed by brackets

image image
  • ghost
  • 1
  • Opened 
    on Feb 9, 2021
  • #36

richjyoung/vscode-modern-vhdl
Process inside architecture block incorrectly indented

architecture A of x is signal sig : std_logic; begin process(sig) begin -- -- When finished typing begin, it jumps to a 0 indentation level. -- ... end A;
  • benjaminmordaunt
  • 1
  • Opened 
    on Feb 2, 2021
  • #35

richjyoung/vscode-modern-vhdl
Respect letter case in code completion hints

Hello for the third time! :smile: The current letter case of code completion hints does not always match with the letter case of actually applied hints. In other words, the code completion hints do not ...
  • dominiksalvet
  • 4
  • Opened 
    on Jun 22, 2020
  • #32

richjyoung/vscode-modern-vhdl
Improve library snippet generation

Hello, The current library generation based on ieee prefix is pretty weak and inflexible. It would be great if it could respect either vhdl.suggestLibraryCase settings or current typing case - e.g., writing ...
  • dominiksalvet
  • 7
  • Opened 
    on Jun 22, 2020
  • #31

richjyoung/vscode-modern-vhdl
Add support for std_ulogic_vector snippets

Hello @richjyoung! :wave: First, thank you for developing this vscode extension! :heart: It seems to be the best vscode VHDL extension to date! :+1: Now, I would really appreciate adding the support ...
  • dominiksalvet
  • 1
  • Opened 
    on Jun 22, 2020
  • #30

richjyoung/vscode-modern-vhdl
Process definition without 'is' does not indent correctly

Something similar happens during process definition. If i write a statement like ProcessName: process(Clk) If I write begin after newline, the indent is automatically decreased by one. Originally posted ...
help wanted
language-config
  • richjyoung
  • 3
  • Opened 
    on Feb 2, 2020
  • #28

richjyoung/vscode-modern-vhdl
[Bug] Character literals are not valid enumeration literals

bug_problems_with_character_literals_in_enumeration Again, the github grammar is not much better here, although it is less visible due to the poor contrast (look closely at the Y ): architecture arch ...
  • pvanschendel
  • 1
  • Opened 
    on Feb 2, 2020
  • #26

richjyoung/vscode-modern-vhdl
[Bug] Names starting with process are interpreted as begin of process block

The signal name not displayed properly, but also, the process block is never terminated, resulting in follow up errors: bug_names_with_process_begin_process_block The textmate grammar used by Github ...
  • pvanschendel
  • 1
  • Opened 
    on Feb 2, 2020
  • #25
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