diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index b33603f8648..79ecee518eb 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -53,7 +53,9 @@ jobs: - "synwit/swm341" - "beaglebone" - "zynqmp-r5-axu4ev" + - "at32/at32f402-start" - "at32/at32f403a-start" + - "at32/at32f405-start" - "at32/at32f407-start" - "at32/at32f413-start" - "at32/at32f415-start" diff --git a/bsp/at32/at32f402-start/.config b/bsp/at32/at32f402-start/.config new file mode 100644 index 00000000000..ca815c2c50e --- /dev/null +++ b/bsp/at32/at32f402-start/.config @@ -0,0 +1,489 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_DFS_V1 is not set +# CONFIG_RT_USING_DFS_V2 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# CONFIG__RT_USB_DEVICE_NONE is not set +# CONFIG__RT_USB_DEVICE_CDC is not set +# CONFIG__RT_USB_DEVICE_MSTORAGE is not set +# CONFIG__RT_USB_DEVICE_HID is not set +# CONFIG__RT_USB_DEVICE_WINUSB is not set +# CONFIG__RT_USB_DEVICE_AUDIO is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_MQTTCLIENT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_FAMILY_AT32=y +CONFIG_SOC_SERIES_AT32F402=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_AT32F402RCT7=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_SERIAL=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_USBOTG is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_RTC_USING_LEXT is not set +# CONFIG_BSP_RTC_USING_LICK is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CAN is not set diff --git a/bsp/at32/at32f402-start/Kconfig b/bsp/at32/at32f402-start/Kconfig new file mode 100644 index 00000000000..79b160b8567 --- /dev/null +++ b/bsp/at32/at32f402-start/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/at32/at32f402-start/README.md b/bsp/at32/at32f402-start/README.md new file mode 100644 index 00000000000..0d45c5a80a6 --- /dev/null +++ b/bsp/at32/at32f402-start/README.md @@ -0,0 +1,139 @@ +# AT32F402 AT-START 开发板 BSP 说明 + +## 简介 + +AT32F402 AT-START是雅特力推出的一款AT32F402系列的评估板，其搭载的MCU主要资源参数如下： + +| 硬件 | 描述 | +| --------- | ------------- | +| 芯片型号 | AT32F402RCT7 | +| CPU | ARM Cortex M4 | +| 主频 | 216M | +| 片内SRAM | 96K | +| 片内FLASH | 256K | + +## 编译说明 + +AT32F402-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| MDK4 | MDK4.74 | +| MDK5 | MDK531 | +| IAR | IAR8.20 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 板载资源 + +- MCU：AT32F402RCT7，主频 216MHz，256KB FLASH，96KB RAM +- 常用外设 + - LED：3个，（红色PF4、黄色PF5、绿色PF6） + - 按键：1个，KEY_USER（兼具唤醒功能，PA0) +- 常用接口：插针串口J8 +- 调试接口，板载的 AT-LINK SWD 下载 + +## 外设支持 + +本 BSP 目前对外设驱动的支持情况如下： + +| 驱动 | 支持情况 | 备注 | +| --------- | -------- | :------------------------: | +| UART | 支持 | USART1/2/3 | +| GPIO | 支持 | PA0...PF7 | +| IIC | 支持 | GPIO模拟I2C | +| SPI | 支持 | SPI1/2 | +| ADC | 支持 | ADC1 | +| PWM | 支持 | TMR1/2 | +| HWTIMER | 支持 | TMR3/4 | +| CAN | 支持 | CAN1 | +| QSPI | 支持 | QSPI1/2 | +| WDT | 支持 | | +| RTC | 支持 | | +| FLASH | 支持 | | +| USBFS | 支持 | OTG1 | + +### IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| ---- | -------------- | +| PF4 | LED2 | +| PF5 | LED3 | +| PF6 | LED4 | +| PA9 | USART1_TX | +| PA10 | USART1_RX | +| PA2 | USART2_TX | +| PA3 | USART2_RX | +| PB10 | USART3_TX | +| PB11 | USART3_RX | +| PA4 | SPI1_NSS | +| PA5 | SPI1_SCK | +| PA6 | SPI1_MISO | +| PA7 | SPI1_MOSI | +| PF1 | SPI2_NSS | +| PC7 | SPI2_SCK | +| PC2 | SPI2_MISO | +| PC3 | SPI2_MOSI | +| PB6 | I2C1_SCL | +| PB7 | I2C1_SDA | +| PA8 | PWM_TMR1_CH1 | +| PA11 | PWM_TMR1_CH4 | +| PA0 | PWM_TMR2_CH1 | +| PA1 | PWM_TMR2_CH2 | +| PC0 | ADC1/2_IN10 | +| PC1 | ADC1/2_IN11 | +| PC2 | ADC1/2_IN12 | +| PC3 | ADC1/2_IN13 | +| PC4 | ADC1/2_IN14 | +| PC5 | ADC1/2_IN15 | +| PB8 | CAN1_RX | +| PB9 | CAN1_TX | +| PC9 | QSPI1_IO0 | +| PB7 | QSPI1_IO1 | +| PC8 | QSPI1_IO2 | +| PC5 | QSPI1_IO3 | +| PB2 | QSPI1_SCK | +| PC11 | QSPI1_CS | +| PA11 | USB_DM | +| PA12 | USB_DP | + +## 使用说明 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用AT-LINK SWD下载程序，在通过AT-LINK SWD连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED2/3/4 会周期性闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，在串口上可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Mar 23 2022 + 2006 - 2022 Copyright by RT-Thread team +msh /> +``` + +## 注意事项 + +可在雅特力官方网站进行所需资料下载，如Keil_v5/Keil_v4/IAR等pack安装包和AT-START开发板原理图等（www.arterytek.com） + +## 联系人信息 + +维护人: + +- [sheltonyu] \ No newline at end of file diff --git a/bsp/at32/at32f402-start/SConscript b/bsp/at32/at32f402-start/SConscript new file mode 100644 index 00000000000..d7ad2b45f81 --- /dev/null +++ b/bsp/at32/at32f402-start/SConscript @@ -0,0 +1,14 @@ +# for module compiling +from building import * +import os + +cwd = GetCurrentDir() +objs = [] + +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/at32/at32f402-start/SConstruct b/bsp/at32/at32f402-start/SConstruct new file mode 100644 index 00000000000..d7a999a8a46 --- /dev/null +++ b/bsp/at32/at32f402-start/SConstruct @@ -0,0 +1,62 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +at32_library = 'AT32F402_405_Firmware_Library' +rtconfig.BSP_LIBRARY_TYPE = at32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, at32_library, 'SConscript'))) + +# include usb libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'usbotg_library', 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'rt_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/at32/at32f402-start/applications/SConscript b/bsp/at32/at32f402-start/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/at32/at32f402-start/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/at32/at32f402-start/applications/main.c b/bsp/at32/at32f402-start/applications/main.c new file mode 100644 index 00000000000..f32a2f6e38f --- /dev/null +++ b/bsp/at32/at32f402-start/applications/main.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-10-18 shelton first version + */ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +/* defined the led2 pin: pf4 */ +#define LED2_PIN GET_PIN(F, 4) +/* defined the led3 pin: pf5 */ +#define LED3_PIN GET_PIN(F, 5) +/* defined the led4 pin: pf6 */ +#define LED4_PIN GET_PIN(F, 6) + +int main(void) +{ + rt_uint32_t speed = 200; + /* set led2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + /* set led3 pin mode to output */ + rt_pin_mode(LED3_PIN, PIN_MODE_OUTPUT); + /* set led4 pin mode to output */ + rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(speed); + rt_pin_write(LED3_PIN, PIN_LOW); + rt_thread_mdelay(speed); + rt_pin_write(LED4_PIN, PIN_LOW); + rt_thread_mdelay(speed); + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED3_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED4_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + } +} diff --git a/bsp/at32/at32f402-start/board/Kconfig b/bsp/at32/at32f402-start/board/Kconfig new file mode 100644 index 00000000000..30446e35a03 --- /dev/null +++ b/bsp/at32/at32f402-start/board/Kconfig @@ -0,0 +1,312 @@ +menu "Hardware Drivers Config" + +config SOC_AT32F402RCT7 + bool + select SOC_SERIES_AT32F402 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SERIAL + bool "Enable USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_USBOTG + bool "Enable USB BUS" + default n + if BSP_USING_USBOTG + menuconfig BSP_USING_USBOTG1 + bool "Enable USB BUS1" + default n + if BSP_USING_USBOTG1 + config BSP_USING_DEVICE_USBOTG1 + bool "Enable USB1 Deivce" + select RT_USING_USB_DEVICE + default n + + config BSP_USING_HOST_USBOTG1 + bool "Enable USB1 Host" + select RT_USING_USB_HOST + default n + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + default n + select RT_USING_QSPI + select RT_USING_SPI + if BSP_USING_QSPI + config BSP_USING_QSPI1 + bool "Enable QSPI1" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LEXT + + config BSP_RTC_USING_LEXT + bool "RTC USING LEXT" + + config BSP_RTC_USING_LICK + bool "RTC USING LICK" + endchoice + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default y + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable timer1 output pwm" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1_CH1 + bool "Enable PWM1 channel1" + default n + + config BSP_USING_PWM1_CH4 + bool "Enable PWM1 channel4" + default n + endif + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output pwm" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH1 + bool "Enable PWM2 channel1" + default n + + config BSP_USING_PWM2_CH2 + bool "Enable PWM2 channel2" + default n + endif + endif + + menuconfig BSP_USING_HWTIMER + bool "Enable HWTIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_HWTMR3 + bool "Enable hardware timer3" + default n + config BSP_USING_HWTMR4 + bool "Enable hardware timer4" + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1 BUS" + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 63 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 63 + default 23 + endif + config BSP_USING_I2C2 + bool "Enable I2C2 BUS" + if BSP_USING_I2C2 + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 0 63 + default 26 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 0 63 + default 27 + endif + config BSP_USING_I2C3 + bool "Enable I2C3 BUS" + if BSP_USING_I2C3 + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 0 63 + default 8 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 0 63 + default 41 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using CAN1" + default n + endif +endmenu + +endmenu diff --git a/bsp/at32/at32f402-start/board/SConscript b/bsp/at32/at32f402-start/board/SConscript new file mode 100644 index 00000000000..424f26e6a17 --- /dev/null +++ b/bsp/at32/at32f402-start/board/SConscript @@ -0,0 +1,29 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +src/board.c +src/at32_msp.c +''') + +path = [cwd] +path += [cwd + '/inc'] + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/startup/gcc/startup_at32f402_405.s'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/startup/mdk/startup_at32f402_405.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/startup/iar/startup_at32f402_405.s'] + +CPPDEFINES = ['AT32F402RCT7'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/at32/at32f402-start/board/inc/at32_msp.h b/bsp/at32/at32f402-start/board/inc/at32_msp.h new file mode 100644 index 00000000000..982e1947f51 --- /dev/null +++ b/bsp/at32/at32f402-start/board/inc/at32_msp.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-10-18 shelton first version + */ + +#ifndef __AT32_MSP_H__ +#define __AT32_MSP_H__ + +void at32_msp_usart_init(void *instance); +void at32_msp_spi_init(void *instance); +void at32_msp_tmr_init(void *instance); +void at32_msp_i2c_init(void *instance); +void at32_msp_adc_init(void *instance); +void at32_msp_hwtmr_init(void *instance); +void at32_msp_can_init(void *instance); +void at32_msp_qspi_init(void *instance); +void at32_msp_usb_init(void *instance); + +#endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f402-start/board/inc/at32f402_405_conf.h b/bsp/at32/at32f402-start/board/inc/at32f402_405_conf.h new file mode 100644 index 00000000000..a4c3cbf39b2 --- /dev/null +++ b/bsp/at32/at32f402-start/board/inc/at32f402_405_conf.h @@ -0,0 +1,149 @@ +/** + ************************************************************************** + * @file at32f402_405_conf.h + * @brief at32f402_405 config header file + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F402_405_CONF_H +#define __AT32F402_405_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief in the following line adjust the value of high speed external crystal (hext) + * used in your application + * + * tip: to avoid modifying this file each time you need to use different hext, you + * can define the hext value in your toolchain compiler preprocessor. + * + */ +#if !defined HEXT_VALUE +#define HEXT_VALUE ((uint32_t)12000000) /*!< value of the high speed external crystal in hz */ +#endif + +/** + * @brief in the following line adjust the high speed external crystal (hext) startup + * timeout value + */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */ + +/* module define -------------------------------------------------------------*/ +#define ACC_MODULE_ENABLED +#define ADC_MODULE_ENABLED +#define CAN_MODULE_ENABLED +#define CRC_MODULE_ENABLED +#define CRM_MODULE_ENABLED +#define DEBUG_MODULE_ENABLED +#define DMA_MODULE_ENABLED +#define ERTC_MODULE_ENABLED +#define EXINT_MODULE_ENABLED +#define FLASH_MODULE_ENABLED +#define GPIO_MODULE_ENABLED +#define I2C_MODULE_ENABLED +#define MISC_MODULE_ENABLED +#define PWC_MODULE_ENABLED +#define QSPI_MODULE_ENABLED +#define SCFG_MODULE_ENABLED +#define SPI_MODULE_ENABLED +#define TMR_MODULE_ENABLED +#define USART_MODULE_ENABLED +#define USB_MODULE_ENABLED +#define WDT_MODULE_ENABLED +#define WWDT_MODULE_ENABLED + +/* includes ------------------------------------------------------------------*/ +#ifdef ACC_MODULE_ENABLED +#include "at32f402_405_acc.h" +#endif +#ifdef ADC_MODULE_ENABLED +#include "at32f402_405_adc.h" +#endif +#ifdef CAN_MODULE_ENABLED +#include "at32f402_405_can.h" +#endif +#ifdef CRC_MODULE_ENABLED +#include "at32f402_405_crc.h" +#endif +#ifdef CRM_MODULE_ENABLED +#include "at32f402_405_crm.h" +#endif +#ifdef DEBUG_MODULE_ENABLED +#include "at32f402_405_debug.h" +#endif +#ifdef DMA_MODULE_ENABLED +#include "at32f402_405_dma.h" +#endif +#ifdef ERTC_MODULE_ENABLED +#include "at32f402_405_ertc.h" +#endif +#ifdef EXINT_MODULE_ENABLED +#include "at32f402_405_exint.h" +#endif +#ifdef FLASH_MODULE_ENABLED +#include "at32f402_405_flash.h" +#endif +#ifdef GPIO_MODULE_ENABLED +#include "at32f402_405_gpio.h" +#endif +#ifdef I2C_MODULE_ENABLED +#include "at32f402_405_i2c.h" +#endif +#ifdef MISC_MODULE_ENABLED +#include "at32f402_405_misc.h" +#endif +#ifdef PWC_MODULE_ENABLED +#include "at32f402_405_pwc.h" +#endif +#ifdef QSPI_MODULE_ENABLED +#include "at32f402_405_qspi.h" +#endif +#ifdef SCFG_MODULE_ENABLED +#include "at32f402_405_scfg.h" +#endif +#ifdef SPI_MODULE_ENABLED +#include "at32f402_405_spi.h" +#endif +#ifdef TMR_MODULE_ENABLED +#include "at32f402_405_tmr.h" +#endif +#ifdef USART_MODULE_ENABLED +#include "at32f402_405_usart.h" +#endif +#ifdef USB_MODULE_ENABLED +#include "at32f402_405_usb.h" +#endif +#ifdef WDT_MODULE_ENABLED +#include "at32f402_405_wdt.h" +#endif +#ifdef WWDT_MODULE_ENABLED +#include "at32f402_405_wwdt.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/at32/at32f402-start/board/inc/board.h b/bsp/at32/at32f402-start/board/inc/board.h new file mode 100644 index 00000000000..e428db5151f --- /dev/null +++ b/bsp/at32/at32f402-start/board/inc/board.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-08 shelton first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "at32f402_405.h" +#include "at32_msp.h" +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AT32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define FLASH_PAGE_SIZE (2 * 1024) +#define AT32_FLASH_SIZE (256 * 1024) +#define AT32_FLASH_END_ADDRESS ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE)) + +/* internal sram memory size[kbytes] <96>, default: 96*/ +#define AT32_SRAM_SIZE 96 +#define AT32_SRAM_END (0x20000000 + AT32_SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END AT32_SRAM_END + +void system_clock_config(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/at32/at32f402-start/board/linker_scripts/link.icf b/bsp/at32/at32f402-start/board/linker_scripts/link.icf new file mode 100644 index 00000000000..491b798cd0f --- /dev/null +++ b/bsp/at32/at32f402-start/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/at32/at32f402-start/board/linker_scripts/link.lds b/bsp/at32/at32f402-start/board/linker_scripts/link.lds new file mode 100644 index 00000000000..7caef989e3e --- /dev/null +++ b/bsp/at32/at32f402-start/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for AT32 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/at32/at32f402-start/board/linker_scripts/link.sct b/bsp/at32/at32f402-start/board/linker_scripts/link.sct new file mode 100644 index 00000000000..0529ba2b9c2 --- /dev/null +++ b/bsp/at32/at32f402-start/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00018000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/at32/at32f402-start/board/src/at32_msp.c b/bsp/at32/at32f402-start/board/src/at32_msp.c new file mode 100644 index 00000000000..711a9e8babc --- /dev/null +++ b/bsp/at32/at32f402-start/board/src/at32_msp.c @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-10-18 shelton first version + */ + +#include +#include "at32f402_405.h" +#include "at32_msp.h" + +#ifdef BSP_USING_UART +void at32_msp_usart_init(void *instance) +{ + gpio_init_type gpio_init_struct; + usart_type *usart_x = (usart_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_UART1 + if(USART1 == usart_x) + { + crm_periph_clock_enable(CRM_USART1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_init_struct.gpio_pins = GPIO_PINS_10; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE9, GPIO_MUX_7); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE10, GPIO_MUX_7); + } +#endif +#ifdef BSP_USING_UART2 + if(USART2 == usart_x) + { + crm_periph_clock_enable(CRM_USART2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_2; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_init_struct.gpio_pins = GPIO_PINS_3; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE2, GPIO_MUX_7); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE3, GPIO_MUX_7); + } +#endif +#ifdef BSP_USING_UART3 + if(USART3 == usart_x) + { + crm_periph_clock_enable(CRM_USART3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_init_struct.gpio_pins = GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_7); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_7); + } +#endif + /* add others */ +} +#endif /* BSP_USING_SERIAL */ + +#ifdef BSP_USING_SPI +void at32_msp_spi_init(void *instance) +{ + gpio_init_type gpio_init_struct; + spi_type *spi_x = (spi_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_SPI1 + if(SPI1 == spi_x) + { + crm_periph_clock_enable(CRM_SPI1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = GPIO_PINS_5 | GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE5, GPIO_MUX_5); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE6, GPIO_MUX_5); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE7, GPIO_MUX_5); + } +#endif +#ifdef BSP_USING_SPI2 + if(SPI2 == spi_x) + { + crm_periph_clock_enable(CRM_SPI2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = GPIO_PINS_2 | GPIO_PINS_3 | GPIO_PINS_7; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE2, GPIO_MUX_5); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE3, GPIO_MUX_5); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE7, GPIO_MUX_5); + } +#endif + /* add others */ +} +#endif /* BSP_USING_SPI */ + +#ifdef BSP_USING_PWM +void at32_msp_tmr_init(void *instance) +{ + gpio_init_type gpio_init_struct; + tmr_type *tmr_x = (tmr_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + if(tmr_x == TMR1) + { + /* tmr1 clock enable */ + crm_periph_clock_enable(CRM_TMR1_PERIPH_CLOCK, TRUE); + /* gpioa clock enable */ + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + + /* gpioa configuration: tmr1 channel1 and channel4 as alternate function push-pull */ + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8 | GPIO_PINS_11; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_1); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE11, GPIO_MUX_1); + } + + if(tmr_x == TMR2) + { + /* tmr2 clock enable */ + crm_periph_clock_enable(CRM_TMR2_PERIPH_CLOCK, TRUE); + /* gpioa clock enable */ + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + + /* gpioa configuration: tmr1 channel1 and channel2 as alternate function push-pull */ + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_0 | GPIO_PINS_1; + gpio_init(GPIOA, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE0, GPIO_MUX_1); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE1, GPIO_MUX_1); + } + /* add others */ +} +#endif /* BSP_USING_PWM */ + +#ifdef BSP_USING_ADC +void at32_msp_adc_init(void *instance) +{ + gpio_init_type gpio_init_struct; + adc_type *adc_x = (adc_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_ADC1 + if(adc_x == ADC1) + { + /* adc1 & gpio clock enable */ + crm_periph_clock_enable(CRM_ADC1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + /* configure adc channel as analog input */ + gpio_init_struct.gpio_pins = GPIO_PINS_0 | GPIO_PINS_1 | GPIO_PINS_2 | GPIO_PINS_3 | GPIO_PINS_4 | GPIO_PINS_5; + gpio_init_struct.gpio_mode = GPIO_MODE_ANALOG; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif +} +#endif /* BSP_USING_ADC */ + +#ifdef BSP_USING_HWTIMER +void at32_msp_hwtmr_init(void *instance) +{ + tmr_type *tmr_x = (tmr_type *)instance; + +#ifdef BSP_USING_HWTMR3 + if(tmr_x == TMR3) + { + /* tmr3 clock enable */ + crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE); + } +#endif +} +#endif + +#ifdef BSP_USING_CAN +void at32_msp_can_init(void *instance) +{ + gpio_init_type gpio_init_struct; + can_type *can_x = (can_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_CAN1 + if(can_x == CAN1) + { + crm_periph_clock_enable(CRM_CAN1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8 | GPIO_PINS_9; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE8, GPIO_MUX_9); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE9, GPIO_MUX_9); + } +#endif +} +#endif /* BSP_USING_CAN */ + +#ifdef BSP_USING_QSPI +void at32_msp_qspi_init(void *instance) +{ + gpio_init_type gpio_init_struct; + qspi_type *qspi_x = (qspi_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_QSPI1 + if(qspi_x == QSPI1) + { + crm_periph_clock_enable(CRM_QSPI1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_2 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_init_struct.gpio_pins = GPIO_PINS_5 | GPIO_PINS_8 | GPIO_PINS_9 | GPIO_PINS_11; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE2, GPIO_MUX_11); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_11); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE5, GPIO_MUX_11); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE8, GPIO_MUX_11); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_11); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE11, GPIO_MUX_11); + } +#endif +} +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_USING_USBOTG +void at32_msp_usb_init(void *instance) +{ + /* defalut usb clock from hext */ + usb_clk48_s clk_s = USB_CLK_HEXT; + +#if defined (BSP_USING_HOST_USBOTG1) || defined (BSP_USING_DEVICE_USBOTG1) + crm_periph_clock_enable(CRM_OTGFS1_PERIPH_CLOCK, TRUE); +#endif + + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + /* attention: pllu divider is set at board.c */ + /* enable pllu clock output */ + crm_pllu_output_set(TRUE); + /* wait till pllu is ready */ + while(crm_flag_get(CRM_PLLU_STABLE_FLAG) == RESET) + { + } + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_PLLU); + } +} +#endif /* BSP_USING_USBOTG */ diff --git a/bsp/at32/at32f402-start/board/src/board.c b/bsp/at32/at32f402-start/board/src/board.c new file mode 100644 index 00000000000..be830ff82b4 --- /dev/null +++ b/bsp/at32/at32f402-start/board/src/board.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-10-18 shelton first version + */ + +#include "board.h" + +void system_clock_config(void) +{ + /* reset crm */ + crm_reset(); + + /* config flash psr register */ + flash_psr_set(FLASH_WAIT_CYCLE_6); + + /* enable pwc periph clock */ + crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); + + /* set power ldo output voltage to 1.3v */ + pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); + + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); + + /* wait till hext is ready */ + while(crm_hext_stable_wait() == ERROR) + { + } + + /* if pll parameter has changed, please use the AT32_New_Clock_Configuration tool for new configuration. */ + crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FP_4); + + /* config pllu div */ + crm_pllu_div_set(CRM_PLL_FU_18); + + /* enable pll */ + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + + /* config ahbclk */ + crm_ahb_div_set(CRM_AHB_DIV_1); + + /* config apb2clk, the maximum frequency of APB2 clock is 216 MHz */ + crm_apb2_div_set(CRM_APB2_DIV_1); + + /* config apb1clk, the maximum frequency of APB1 clock is 120 MHz */ + crm_apb1_div_set(CRM_APB1_DIV_2); + + /* enable auto step mode */ + crm_auto_step_mode_enable(TRUE); + + /* select pll as system clock source */ + crm_sysclk_switch(CRM_SCLK_PLL); + + /* wait till pll is used as system clock source */ + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + + /* disable auto step mode */ + crm_auto_step_mode_enable(FALSE); + + /* update system_core_clock global variable */ + system_core_clock_update(); +} diff --git a/bsp/at32/at32f402-start/project.ewp b/bsp/at32/at32f402-start/project.ewp new file mode 100644 index 00000000000..f0153cd5ae4 --- /dev/null +++ b/bsp/at32/at32f402-start/project.ewp @@ -0,0 +1,2358 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK 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+ + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\core\device.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + + Drivers + + $PROJ_DIR$\board\src\at32_msp.c + + + $PROJ_DIR$\board\src\board.c + + + $PROJ_DIR$\..\libraries\AT32F402_405_Firmware_Library\cmsis\cm4\device_support\startup\iar\startup_at32f402_405.s + + + $PROJ_DIR$\..\libraries\rt_drivers\drv_common.c + + + $PROJ_DIR$\..\libraries\rt_drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\rt_drivers\drv_usart.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + 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$PROJ_DIR$\..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_debug.c + + + $PROJ_DIR$\..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_adc.c + + + $PROJ_DIR$\..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_wwdt.c + + + $PROJ_DIR$\..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_misc.c + + + $PROJ_DIR$\..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_gpio.c + + + + POSIX + + + usbotg_library + + diff --git a/bsp/at32/at32f402-start/project.eww b/bsp/at32/at32f402-start/project.eww new file mode 100644 index 00000000000..c2cb02eb1e8 --- /dev/null +++ b/bsp/at32/at32f402-start/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/at32/at32f402-start/project.uvopt b/bsp/at32/at32f402-start/project.uvopt new file mode 100644 index 00000000000..7127c3c6d05 --- /dev/null +++ b/bsp/at32/at32f402-start/project.uvopt @@ -0,0 +1,167 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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__RTTHREAD__ + + ..\..\..\include;..\libraries\rt_drivers\config;..\libraries\AT32F402_405_Firmware_Library\cmsis\cm4\device_support;..\..\..\components\libc\compilers\common\include;..\libraries\AT32F402_405_Firmware_Library\drivers\inc;..\..\..\components\drivers\include;..\libraries\rt_drivers;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;.;board\inc;board;..\..\..\components\libc\posix\ipc;..\libraries\AT32F402_405_Firmware_Library\cmsis\cm4\core_support;..\libraries\usbotg_library\inc;applications;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\epoll + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + 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..\libraries\AT32F402_405_Firmware_Library\cmsis\cm4\device_support\startup\mdk\startup_at32f402_405.s + + + + + drv_common.c + 1 + ..\libraries\rt_drivers\drv_common.c + + + + + drv_gpio.c + 1 + ..\libraries\rt_drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\rt_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + 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..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_scfg.c + + + + + system_at32f402_405.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\cmsis\cm4\device_support\system_at32f402_405.c + + + + + at32f402_405_dma.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_dma.c + + + + + at32f402_405_usb.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_usb.c + + + + + at32f402_405_can.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_can.c + + + + + at32f402_405_flash.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_flash.c + + + + + at32f402_405_qspi.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_qspi.c + + + + + at32f402_405_exint.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_exint.c + + + + + at32f402_405_crc.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_crc.c + + + + + at32f402_405_crm.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_crm.c + + + + + at32f402_405_i2c.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_i2c.c + + + + + at32f402_405_debug.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_debug.c + + + + + at32f402_405_adc.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_adc.c + + + + + at32f402_405_wwdt.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_wwdt.c + + + + + at32f402_405_misc.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_misc.c + + + + + at32f402_405_gpio.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_gpio.c + + + + + + + diff --git a/bsp/at32/at32f402-start/project.uvprojx b/bsp/at32/at32f402-start/project.uvprojx new file mode 100644 index 00000000000..c492da3316a --- /dev/null +++ b/bsp/at32/at32f402-start/project.uvprojx @@ -0,0 +1,910 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + AT32F402RCT7 + ArteryTek + ArteryTek.AT32F402_405_DFP.2.0.1 + IRAM(0x20000000,0x18000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F402_256 -FS08000000 -FL040000 -FP0($$Device:AT32F402RCT7$Flash\AT32F402_256.FLM)) + 0 + $$Device:AT32F402RCT7$Device\Include\at32f402_405.h + + + + + + + + + + $$Device:AT32F402RCT7$SVD\AT32F402xx_v2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, AT32F402RCT7, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ + + 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..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_scfg.c + + + + + system_at32f402_405.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\cmsis\cm4\device_support\system_at32f402_405.c + + + + + at32f402_405_dma.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_dma.c + + + + + at32f402_405_usb.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_usb.c + + + + + at32f402_405_can.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_can.c + + + + + at32f402_405_flash.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_flash.c + + + + + at32f402_405_qspi.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_qspi.c + + + + + at32f402_405_exint.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_exint.c + + + + + at32f402_405_crc.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_crc.c + + + + + at32f402_405_crm.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_crm.c + + + + + at32f402_405_i2c.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_i2c.c + + + + + at32f402_405_debug.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_debug.c + + + + + at32f402_405_adc.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_adc.c + + + + + at32f402_405_wwdt.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_wwdt.c + + + + + at32f402_405_misc.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_misc.c + + + + + at32f402_405_gpio.c + 1 + ..\libraries\AT32F402_405_Firmware_Library\drivers\src\at32f402_405_gpio.c + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + diff --git a/bsp/at32/at32f402-start/rtconfig.h b/bsp/at32/at32f402-start/rtconfig.h new file mode 100644 index 00000000000..fbe8690ac1c --- /dev/null +++ b/bsp/at32/at32f402-start/rtconfig.h @@ -0,0 +1,178 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_AT32 +#define SOC_SERIES_AT32F402 + +/* Hardware Drivers Config */ + +#define SOC_AT32F402RCT7 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_SERIAL + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +#endif diff --git a/bsp/at32/at32f402-start/rtconfig.py b/bsp/at32/at32f402-start/rtconfig.py new file mode 100644 index 00000000000..b542aa27e37 --- /dev/null +++ b/bsp/at32/at32f402-start/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/at32/at32f402-start/template.ewp b/bsp/at32/at32f402-start/template.ewp new file mode 100644 index 00000000000..2dae5e8a87e --- /dev/null +++ b/bsp/at32/at32f402-start/template.ewp @@ -0,0 +1,2040 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 30 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/at32/at32f402-start/template.eww b/bsp/at32/at32f402-start/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/at32/at32f402-start/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/at32/at32f402-start/template.uvopt b/bsp/at32/at32f402-start/template.uvopt new file mode 100644 index 00000000000..7127c3c6d05 --- /dev/null +++ b/bsp/at32/at32f402-start/template.uvopt @@ -0,0 +1,167 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 12 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"AT-Link-EZ CMSIS-DAP" -U0DF531B010C0765905978507 -O78 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -FO7 -FD20000000 -FC800 -FN1 -FF0AT32F402_256 -FS08000000 -FL040000 + + + 0 + JL2CM3 + -U788529815 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0AT32F403A_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC800 -FD20000000 -FF0AT32F402_256 -FL040000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + diff --git a/bsp/at32/at32f402-start/template.uvoptx b/bsp/at32/at32f402-start/template.uvoptx new file mode 100644 index 00000000000..7b2c6f78e83 --- /dev/null +++ b/bsp/at32/at32f402-start/template.uvoptx @@ -0,0 +1,185 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0AT32F402_256 -FL040000 -FS08000000 -FP0($$Device:AT32F402RCT7$Flash\AT32F402_256.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0AT32F402_256.FLM -FS08000000 -FL040000 -FP0($$Device:AT32F402RCT7$Flash\AT32F402_256.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/at32/at32f402-start/template.uvproj b/bsp/at32/at32f402-start/template.uvproj new file mode 100644 index 00000000000..06a709f68ee --- /dev/null +++ b/bsp/at32/at32f402-start/template.uvproj @@ -0,0 +1,407 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + + + AT32F402RCT7 + ArteryTek + IRAM(0x20000000-0x20017FFF) IROM(0x08000000-0x0803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ArteryTek\AT32F402_405\startup_at32f402_405.s" ("AT32F402_405 Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0AT32F402_256 -FS08000000 -FL040000) + 0 + at32f402_405.h + + + + + + + + + + SFD\ArteryTek\AT32F402\AT32F402xx_v2.SFR + 0 + 0 + + + + ArteryTek\AT32F402_405\ + ArteryTek\AT32F402_405\ + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + + 0 + 12 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + diff --git a/bsp/at32/at32f402-start/template.uvprojx b/bsp/at32/at32f402-start/template.uvprojx new file mode 100644 index 00000000000..e5489a2f51b --- /dev/null +++ b/bsp/at32/at32f402-start/template.uvprojx @@ -0,0 +1,405 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + AT32F402RCT7 + ArteryTek + ArteryTek.AT32F402_405_DFP.2.0.1 + IRAM(0x20000000,0x18000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F402_256 -FS08000000 -FL040000 -FP0($$Device:AT32F402RCT7$Flash\AT32F402_256.FLM)) + 0 + $$Device:AT32F402RCT7$Device\Include\at32f402_405.h + + + + + + + + + + $$Device:AT32F402RCT7$SVD\AT32F402xx_v2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/at32/at32f403a-start/project.ewp b/bsp/at32/at32f403a-start/project.ewp index 9f64d91c334..6449ffd6ef8 100644 --- a/bsp/at32/at32f403a-start/project.ewp +++ b/bsp/at32/at32f403a-start/project.ewp @@ -351,28 +351,27 @@