From 549efde1229cbd064bfb074009a9b0ce34d93f97 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 15 Nov 2024 00:03:19 +0500 Subject: [PATCH] add the update mechanism for the support of mip register --- riscv-isac/riscv_isac/InstructionObject.py | 12 +++++++++++- riscv-isac/riscv_isac/coverage.py | 4 ++-- riscv-isac/riscv_isac/plugins/c_sail.py | 21 +++++++++++++++++++-- 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py index f86fe62c6..822ed6c1b 100644 --- a/riscv-isac/riscv_isac/InstructionObject.py +++ b/riscv-isac/riscv_isac/InstructionObject.py @@ -90,7 +90,8 @@ def __init__( mem_val = None, trap_dict = None, inxFlag = None, - is_sgn_extd = None + is_sgn_extd = None, + mip_updated_val = None ): ''' @@ -135,6 +136,7 @@ def __init__( self.matches_for_options = None self.mem_val = mem_val self.trap_dict = trap_dict + self.mip_updated_val = mip_updated_val def is_sig_update(self): return self.instr_name in instrs_sig_update @@ -198,9 +200,17 @@ def evaluate_instr_vars(self, xlen, flen, arch_state, csr_regfile, instr_vars): instr_vars['access_len'] = 1 else: instr_vars['access_len'] = None + #Update the values for the trap registers self.trap_registers_update(instr_vars,self.trap_dict) + #Update the value of MIP as soon as the hart updates it. + if self.mip_updated_val is not None: + if isinstance(csr_regfile['mip'], str): + csr_regfile['mip'] = int(csr_regfile['mip'], 16) | self.mip_updated_val + else: + csr_regfile['mip'] = csr_regfile['mip'] | self.mip_updated_val + # capture the register operand values rs1_val = self.evaluate_instr_var("rs1_val", instr_vars, arch_state) rs2_val = self.evaluate_instr_var("rs2_val", instr_vars, arch_state) diff --git a/riscv-isac/riscv_isac/coverage.py b/riscv-isac/riscv_isac/coverage.py index b906473de..3c049e1d7 100644 --- a/riscv-isac/riscv_isac/coverage.py +++ b/riscv-isac/riscv_isac/coverage.py @@ -973,8 +973,8 @@ def old_fn_csr_comb_covpt(csr_reg): # if instr_vars["mode_change"] is not None: #change the state only on the instruction csr_regfile["mcause"] = instr_vars["mcause"] csr_regfile["scause"] = instr_vars["scause"] - csr_regfile["mtval"] = instr_vars["mtval"] - csr_regfile["stval"] = instr_vars["stval"] + csr_regfile["mtval"] = instr_vars["mtval"] + csr_regfile["stval"] = instr_vars["stval"] if 'rs1' in instr_vars: rs1 = instr_vars['rs1'] diff --git a/riscv-isac/riscv_isac/plugins/c_sail.py b/riscv-isac/riscv_isac/plugins/c_sail.py index 42f42e91e..854a272cb 100644 --- a/riscv-isac/riscv_isac/plugins/c_sail.py +++ b/riscv-isac/riscv_isac/plugins/c_sail.py @@ -22,6 +22,8 @@ def setup(self, trace, arch): instr_pattern_c_sail_trap = re.compile(r'trapping\sfrom\s(?P\w+\sto\s\w+)\sto\shandle\s(?P\w+.*)\shandling\sexc#(?P0x[0-9a-fA-F]+)\sat\spriv\s\w\swith\stval\s(?P0x[0-9a-fA-F]+)') instr_pattern_c_sail_interrupt = re.compile(r'Handling\s(?P\w+):\s(?P0x[0-9a-fA-F]+)\shandling\sint#0x[0-9a-fA-F]+\sat\spriv\s\w\swith\stval\s(?P0x[0-9a-fA-F]+)') instr_pattern_c_sail_ret = re.compile(r'ret-ing\sfrom\s(?P\w+\sto\s\w+)') + instr_pattern_c_sail_mip = re.compile(r'\(mip\.(?P\w+)\s<-\s(?P[0-9a-fA-F]+b[0-9a-fA-F]+)\)') +# (?P)\s<-\s(?P)) def extractInstruction(self, line): instr_pattern = self.instr_pattern_c_sail re_search = instr_pattern.search(line) @@ -124,6 +126,20 @@ def extractMemVal(self, line): else: return mem_val + def extractMIPVal(self, line): + ''' + Function to extract the hart updated value of MIP CSR. + return: int -> value updated in the MIP + ''' + instr_pattern = self.instr_pattern_c_sail_mip.search(line) + mip = {'mei': 0x800, 'sei': 0x200, 'mti': 0x80, 'sti': 0x20,'msi': 0x8,'ssi': 0x2} + + if instr_pattern: + if instr_pattern.group("bit").lower() in mip.keys(): + return mip[instr_pattern.group("bit").lower()] * int(instr_pattern.group("val"), 2) + else: + return None + def extracttrapvals(self, line): instr_trap_pattern = self.instr_pattern_c_sail_trap.search(line) instr_interrupt_pattern = self.instr_pattern_c_sail_interrupt.search(line) @@ -151,7 +167,7 @@ def extracttrapvals(self, line): trap_dict = {"mode_change": None, "call_type": None, "exc_num": None, "tval": None} self.old_trap_dict = trap_dict - #maintain the values if None unit the new trap appears + #maintain the values if None until the new trap appears if instr_trap_pattern is None or instr_ret_pattern is None: trap_dict = self.old_trap_dict return trap_dict @@ -169,5 +185,6 @@ def __iter__(self): vm_addr_dict = self.extractVirtualMemory(line) mem_val = self.extractMemVal(line) trap_dict = self.extracttrapvals(line) - instrObj = instructionObject(instr, 'None', addr, reg_commit = reg_commit, csr_commit = csr_commit, mnemonic = mnemonic, mode = mode, vm_addr_dict = vm_addr_dict, mem_val = mem_val, trap_dict = trap_dict) + mip_updated_val = self.extractMIPVal(line) + instrObj = instructionObject(instr, 'None', addr, reg_commit = reg_commit, csr_commit = csr_commit, mnemonic = mnemonic, mode = mode, vm_addr_dict = vm_addr_dict, mem_val = mem_val, trap_dict = trap_dict, mip_updated_val = mip_updated_val) yield instrObj