From b137ea5596dfb111cf1dbf873102002daf1e7db9 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sun, 28 Jan 2024 18:06:55 -0600 Subject: [PATCH] Add Zawrs extension tests --- CHANGELOG.md | 3 + riscv-test-suite/env/test_macros.h | 9 + riscv-test-suite/rv32i_m/Zawrs/src/zawrs.S | 192 +++++++++++++++++++++ riscv-test-suite/rv64i_m/Zawrs/src/zawrs.S | 192 +++++++++++++++++++++ 4 files changed, 396 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/Zawrs/src/zawrs.S create mode 100644 riscv-test-suite/rv64i_m/Zawrs/src/zawrs.S diff --git a/CHANGELOG.md b/CHANGELOG.md index a5bd6dbfa..21db34b34 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # CHANGELOG +## [3.8.10] -- 2024-01-28 +- add tests for zawrs extension + ## [3.8.9] -- 2024-01-12 - Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated. diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index be19bf88e..5f583a9ed 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -1088,6 +1088,15 @@ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE) sub x1,x1,tempreg ;\ RVTEST_SIGUPD(swreg,x1,offset) +/* RVTEST_SIGUPD_CSR(SIG, TMP, CSR) + This macro reads the provided CSR and stores the + value in the signature referenced by SIG using the + help of the temporary register TMP. + */ +#define RVTEST_SIGUPD_CSR(_SIG, _TMP, _CSR) ;\ + csrr _TMP, _CSR ;\ + RVTEST_SIGUPD(_SIG, _TMP) + //--------------------------------- Migration aliases ------------------------------------------ #ifdef RV_COMPLIANCE_RV32M diff --git a/riscv-test-suite/rv32i_m/Zawrs/src/zawrs.S b/riscv-test-suite/rv32i_m/Zawrs/src/zawrs.S new file mode 100644 index 000000000..cee82c20d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zawrs/src/zawrs.S @@ -0,0 +1,192 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the wrs instruction of the RISC-V Zawrs extension +// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV32IA_Zicsr") +#define WRS_STO .word MATCH_WRS_STO +#define WRS_NTO .word MATCH_WRS_NTO +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE(x15, signature_x15_m) + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*Zawrs.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",zawrs) + + # Locally enable STIP interrupts + li x1, MIP_STIP + csrw CSR_MIE, x1 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIE) + + # Set TW + li x1, MSTATUS_TW + csrr x2, CSR_MSTATUS + or x1, x1, x2 + csrw CSR_MSTATUS, x1 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MSTATUS) + + # no reservation, no interrupts pending; sto completes + WRS_STO + + # reservation valid, no interrupts pending; sto completes + la x1, test_data + lr.w x1, (x1) + WRS_STO + + # reservation valid, interrupt pending; sto completes + li x1, MIP_STIP + csrw mip, x1 + WRS_STO + + # Clear interrupt, cancel reservation + csrw mip, x0 + la x1, test_data + sc.w x0, x0, (x1) + + csrw satp, x0 + + RVTEST_GOTO_LOWER_MODE Smode + + # no reservation, no interrupts pending; sto completes + WRS_STO + + # reservation valid, no interrupts pending; sto completes + la x1, test_data + lr.w x1, (x1) + WRS_STO + + # reservation valid, no interrupts pending; TW is 1 + # nto takes illegal interrupt + la x1, test_data + lr.w x1, (x1) + WRS_NTO + j 1f + # shold resume here if illegal inst happened + RVTEST_SIGUPD(x15, x0) + j 2f +1: + # Should branch here if illegal inst did not happen + li x1, 1 + RVTEST_SIGUPD(x15, x1) +2: + # cancel reservation + la x1, test_data + sc.w x0, x0, (x1) + RVTEST_GOTO_MMODE + + # Pend an interrupt + li x1, MIP_STIP + csrw mip, x1 + csrw mideleg, x1 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIP) + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIDELEG) + RVTEST_GOTO_LOWER_MODE Smode + + # reservation valid, interrupt pending + la x1, test_data + lr.w x1, (x1) + WRS_NTO + # execution comes here if no illegal inst happened + j 2f + # execution comes here if illegal inst happened + j 3f +2: + RVTEST_SIGUPD(x15, x0) + j 4f +3: + li x1, 1 + RVTEST_SIGUPD(x15, x1) +4: + # cancel reservation + la x1, test_data + sc.w x0, x0, (x1) + RVTEST_GOTO_MMODE + + csrw mip, x0 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIP) + + RVTEST_GOTO_LOWER_MODE Umode + # no reservation, no interrupts pending; sto completes + WRS_STO + + # reservation valid, no interrupts pending; sto completes + la x1, test_data + lr.w x1, (x1) + WRS_STO + + # reservation valid, no interrupts pending; TW is 1; + # nto takes illegal interrupt + la x1, test_data + lr.w x1, (x1) + WRS_NTO + j 1f + # shold resume here if illegal inst happened + RVTEST_SIGUPD(x15, x0) + j 2f +1: + # Should branch here if illegal inst did not happen + li x1, 1 + RVTEST_SIGUPD(x15, x1) +2: + # cancel reservation + la x1, test_data + sc.w x0, x0, (x1) + RVTEST_GOTO_MMODE + +#endif + + # --------------------------------------------------------------------------------------------- + # HALT + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# Input data section. + .data + .align 8 +test_data: +RVTEST_DATA_END + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x15_m: + .fill 32*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zawrs/src/zawrs.S b/riscv-test-suite/rv64i_m/Zawrs/src/zawrs.S new file mode 100644 index 000000000..dcaf6fae6 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zawrs/src/zawrs.S @@ -0,0 +1,192 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the wrs instruction of the RISC-V Zawrs extension +// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV64IA_Zicsr") +#define WRS_STO .word MATCH_WRS_STO +#define WRS_NTO .word MATCH_WRS_NTO +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE(x15, signature_x15_m) + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*Zawrs.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",zawrs) + + # Locally enable STIP interrupts + li x1, MIP_STIP + csrw CSR_MIE, x1 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIE) + + # Set TW + li x1, MSTATUS_TW + csrr x2, CSR_MSTATUS + or x1, x1, x2 + csrw CSR_MSTATUS, x1 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MSTATUS) + + # no reservation, no interrupts pending; sto completes + WRS_STO + + # reservation valid, no interrupts pending; sto completes + la x1, test_data + lr.w x1, (x1) + WRS_STO + + # reservation valid, interrupt pending; sto completes + li x1, MIP_STIP + csrw mip, x1 + WRS_STO + + # Clear interrupt, cancel reservation + csrw mip, x0 + la x1, test_data + sc.w x0, x0, (x1) + + csrw satp, x0 + + RVTEST_GOTO_LOWER_MODE Smode + + # no reservation, no interrupts pending; sto completes + WRS_STO + + # reservation valid, no interrupts pending; sto completes + la x1, test_data + lr.w x1, (x1) + WRS_STO + + # reservation valid, no interrupts pending; TW is 1 + # nto takes illegal interrupt + la x1, test_data + lr.w x1, (x1) + WRS_NTO + j 1f + # shold resume here if illegal inst happened + RVTEST_SIGUPD(x15, x0) + j 2f +1: + # Should branch here if illegal inst did not happen + li x1, 1 + RVTEST_SIGUPD(x15, x1) +2: + # cancel reservation + la x1, test_data + sc.w x0, x0, (x1) + RVTEST_GOTO_MMODE + + # Pend an interrupt + li x1, MIP_STIP + csrw mip, x1 + csrw mideleg, x1 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIP) + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIDELEG) + RVTEST_GOTO_LOWER_MODE Smode + + # reservation valid, interrupt pending + la x1, test_data + lr.w x1, (x1) + WRS_NTO + # execution comes here if no illegal inst happened + j 2f + # execution comes here if illegal inst happened + j 3f +2: + RVTEST_SIGUPD(x15, x0) + j 4f +3: + li x1, 1 + RVTEST_SIGUPD(x15, x1) +4: + # cancel reservation + la x1, test_data + sc.w x0, x0, (x1) + RVTEST_GOTO_MMODE + + csrw mip, x0 + RVTEST_SIGUPD_CSR(x15, x1, CSR_MIP) + + RVTEST_GOTO_LOWER_MODE Umode + # no reservation, no interrupts pending; sto completes + WRS_STO + + # reservation valid, no interrupts pending; sto completes + la x1, test_data + lr.w x1, (x1) + WRS_STO + + # reservation valid, no interrupts pending; TW is 1; + # nto takes illegal interrupt + la x1, test_data + lr.w x1, (x1) + WRS_NTO + j 1f + # shold resume here if illegal inst happened + RVTEST_SIGUPD(x15, x0) + j 2f +1: + # Should branch here if illegal inst did not happen + li x1, 1 + RVTEST_SIGUPD(x15, x1) +2: + # cancel reservation + la x1, test_data + sc.w x0, x0, (x1) + RVTEST_GOTO_MMODE + +#endif + + # --------------------------------------------------------------------------------------------- + # HALT + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# Input data section. + .data + .align 8 +test_data: +RVTEST_DATA_END + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x15_m: + .fill 32*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END