diff --git a/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_csr-comb.S b/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_csr-comb.S
new file mode 100644
index 000000000..f9d54572c
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_csr-comb.S
@@ -0,0 +1,1108 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.11.1
+// timestamp : Thu Dec 28 20:55:13 2023 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/srmcfg.cgf \
+ \
+//                  -- xlen 32  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file is used for the test of CSR-combination coverpoint described in srmcfg covergroup.
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I_ZICSR")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//$cond;def TEST_CASE_1=True;",srmcfg)
+
+
+RVTEST_SIGBASE(x28, signature_x28_0)
+
+
+inst_0_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3)
+
+
+inst_0_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 0, x28)
+
+
+inst_0_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_1_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf800000)
+
+
+inst_1_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 4, x28)
+
+
+inst_1_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_2_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7f)
+
+
+inst_2_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 8, x28)
+
+
+inst_2_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_3_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3ff0fff)
+
+
+inst_3_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 12, x28)
+
+
+inst_3_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_4_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffd0fff)
+
+
+inst_4_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 16, x28)
+
+
+inst_4_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_5_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0f80)
+
+
+inst_5_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 20, x28)
+
+
+inst_5_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_6_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xc000000)
+
+
+inst_6_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 24, x28)
+
+
+inst_6_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_7_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff80000)
+
+
+inst_7_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 28, x28)
+
+
+inst_7_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_8_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffc)
+
+
+inst_8_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 32, x28)
+
+
+inst_8_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_9_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfdf0fff)
+
+
+inst_9_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 36, x28)
+
+
+inst_9_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_10_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x8000000)
+
+
+inst_10_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 40, x28)
+
+
+inst_10_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_11_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff07ff)
+
+
+inst_11_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 44, x28)
+
+
+inst_11_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_12_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fc0)
+
+
+inst_12_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 48, x28)
+
+
+inst_12_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_13_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0800)
+
+
+inst_13_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 52, x28)
+
+
+inst_13_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_14_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0c00)
+
+
+inst_14_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 56, x28)
+
+
+inst_14_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_15_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff)
+
+
+inst_15_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 60, x28)
+
+
+inst_15_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_16_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xe000000)
+
+
+inst_16_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 64, x28)
+
+
+inst_16_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_17_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fe0)
+
+
+inst_17_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 68, x28)
+
+
+inst_17_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_18_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ff0)
+
+
+inst_18_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 72, x28)
+
+
+inst_18_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_19_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1)
+
+
+inst_19_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 76, x28)
+
+
+inst_19_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_20_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x0)
+
+
+inst_20_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 80, x28)
+
+
+inst_20_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_21_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3ff)
+
+
+inst_21_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 84, x28)
+
+
+inst_21_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_22_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x10fff)
+
+
+inst_22_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 88, x28)
+
+
+inst_22_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_23_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfef0fff)
+
+
+inst_23_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 92, x28)
+
+
+inst_23_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_24_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7ff0fff)
+
+
+inst_24_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 96, x28)
+
+
+inst_24_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_25_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xdff0fff)
+
+
+inst_25_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 100, x28)
+
+
+inst_25_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_26_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0eff)
+
+
+inst_26_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 104, x28)
+
+
+inst_26_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_27_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x30fff)
+
+
+inst_27_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 108, x28)
+
+
+inst_27_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_28_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf0fff)
+
+
+inst_28_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 112, x28)
+
+
+inst_28_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_29_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffe0000)
+
+
+inst_29_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 116, x28)
+
+
+inst_29_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_30_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfbf0fff)
+
+
+inst_30_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 120, x28)
+
+
+inst_30_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_31_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7f0fff)
+
+
+inst_31_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 124, x28)
+
+
+inst_31_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_32_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0e00)
+
+
+inst_32_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 128, x28)
+
+
+inst_32_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_33_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfe00000)
+
+
+inst_33_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 132, x28)
+
+
+inst_33_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_34_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fdf)
+
+
+inst_34_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 136, x28)
+
+
+inst_34_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_35_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfc00000)
+
+
+inst_35_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 140, x28)
+
+
+inst_35_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_36_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffe0fff)
+
+
+inst_36_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 144, x28)
+
+
+inst_36_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_37_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1f)
+
+
+inst_37_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 148, x28)
+
+
+inst_37_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_38_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7)
+
+
+inst_38_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 152, x28)
+
+
+inst_38_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_39_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffd)
+
+
+inst_39_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 156, x28)
+
+
+inst_39_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_40_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ff8)
+
+
+inst_40_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 160, x28)
+
+
+inst_40_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_41_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffb)
+
+
+inst_41_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 164, x28)
+
+
+inst_41_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_42_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3f)
+
+
+inst_42_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 168, x28)
+
+
+inst_42_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_43_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf000000)
+
+
+inst_43_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 172, x28)
+
+
+inst_43_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_44_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1f0fff)
+
+
+inst_44_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 176, x28)
+
+
+inst_44_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_45_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffb0fff)
+
+
+inst_45_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 180, x28)
+
+
+inst_45_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_46_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0000)
+
+
+inst_46_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 184, x28)
+
+
+inst_46_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_47_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fbf)
+
+
+inst_47_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 188, x28)
+
+
+inst_47_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_48_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3f0fff)
+
+
+inst_48_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 192, x28)
+
+
+inst_48_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_49_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fff)
+
+
+inst_49_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 196, x28)
+
+
+inst_49_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_50_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xbff0fff)
+
+
+inst_50_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 200, x28)
+
+
+inst_50_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_51_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff70fff)
+
+
+inst_51_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 204, x28)
+
+
+inst_51_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_52_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0f00)
+
+
+inst_52_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 208, x28)
+
+
+inst_52_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_53_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff)
+
+
+inst_53_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 212, x28)
+
+
+inst_53_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_54_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1ff)
+
+
+inst_54_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 216, x28)
+
+
+inst_54_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_55_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7ff)
+
+
+inst_55_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 220, x28)
+
+
+inst_55_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_56_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff0fff)
+
+
+inst_56_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 224, x28)
+
+
+inst_56_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_57_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xeff0fff)
+
+
+inst_57_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 228, x28)
+
+
+inst_57_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_58_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffc0000)
+
+
+inst_58_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 232, x28)
+
+
+inst_58_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_59_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0dff)
+
+
+inst_59_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 236, x28)
+
+
+inst_59_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_60_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0f7f)
+
+
+inst_60_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 240, x28)
+
+
+inst_60_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_61_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ff7)
+
+
+inst_61_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 244, x28)
+
+
+inst_61_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_62_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff00000)
+
+
+inst_62_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 248, x28)
+
+
+inst_62_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_63_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fef)
+
+
+inst_63_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 252, x28)
+
+
+inst_63_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_64_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1ff0fff)
+
+
+inst_64_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 256, x28)
+
+
+inst_64_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_65_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0bff)
+
+
+inst_65_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 260, x28)
+
+
+inst_65_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_66_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x70fff)
+
+
+inst_66_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 264, x28)
+
+
+inst_66_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_67_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf)
+
+
+inst_67_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 268, x28)
+
+
+inst_67_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_68_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffe)
+
+
+inst_68_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 272, x28)
+
+
+inst_68_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_69_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf7f0fff)
+
+
+inst_69_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 276, x28)
+
+
+inst_69_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x28_0:
+    .fill 70*(XLEN/32),4,0xdeadbeef
+
+RVMODEL_DATA_END
diff --git a/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_mstateen0.S b/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_mstateen0.S
new file mode 100644
index 000000000..0e62d7583
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_mstateen0.S
@@ -0,0 +1,133 @@
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the Smstaten and Ssqosid interactions
+// 
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV32I_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+  RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Smstateen.*Ssqosid.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True", srmcfg_mstateen)
+
+  RVTEST_SIGBASE(x1,signature_x1)
+
+  # setup PMP to allow execution in U and S mode
+  li x2, PMP_TOR | PMP_X | PMP_W | PMP_R
+  csrw pmpcfg0, x2
+  csrr x2, pmpcfg0
+  beq  x2, x0, no_TOR_try_NAPOT
+  li x2, 0xFFFFFFFF
+  csrw pmpaddr0, x2
+  j Mend_PMP
+no_TOR_try_NAPOT:
+  li x2, PMP_NAPOT | PMP_X | PMP_W | PMP_R
+  csrw pmpcfg0, x2
+  csrr x2, pmpcfg0
+  beq  x2, x0, Mend_PMP
+  li x2, 0x1FFFFFFF
+  csrw pmpaddr0, x2
+Mend_PMP:
+  csrw satp, x0
+
+  li x2, 0x05550AAA
+  csrw CSR_SRMCFG, x2
+
+  # transfer to Umode and access the CSR - access faults
+  RVTEST_GOTO_LOWER_MODE Umode
+  csrw CSR_SRMCFG, x0
+  nop
+  nop
+  nop
+  nop
+  nop
+  RVTEST_GOTO_MMODE
+
+  # transfer to Umode and access the CSR - access faults
+  RVTEST_GOTO_LOWER_MODE Smode
+  csrw CSR_SRMCFG, x0
+  nop
+  nop
+  nop
+  nop
+  nop
+  RVTEST_GOTO_MMODE
+
+  csrr x2, CSR_SRMCFG
+  RVTEST_SIGUPD(x1, x2, 0 * REGWIDTH)
+
+  # Enable Smode access to srmcfg
+  csrr x3, CSR_MSTATEEN0H
+  li x2, MSTATEEN0H_PRIV114
+  or x3, x2, x2
+  csrw CSR_MSTATEEN0H, x3
+
+  csrr x2, CSR_MSTATEEN0H
+  RVTEST_SIGUPD(x1, x2, 1 * REGWIDTH)
+
+  # transfer to Smode and access the CSR - access succeeds
+  RVTEST_GOTO_LOWER_MODE Smode
+  li x2, 0x0AAA0555
+  csrw CSR_SRMCFG, x2
+  RVTEST_GOTO_MMODE
+
+  csrr x2, CSR_SRMCFG
+  RVTEST_SIGUPD(x1, x2, 2 * REGWIDTH)
+
+  # transfer to Umode and access the CSR - access faults
+  RVTEST_GOTO_LOWER_MODE Umode
+  csrw CSR_SRMCFG, x0
+  nop
+  nop
+  nop
+  nop
+  nop
+  RVTEST_GOTO_MMODE
+
+  csrr x2, CSR_SRMCFG
+  RVTEST_SIGUPD(x1, x2, 3 * REGWIDTH)
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+# Input data section.
+  .data
+  .align 4
+RVTEST_DATA_END
+
+# Output data section.
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+signature_x1:
+  .fill 16*((XLEN/8)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+  .fill 64*(XLEN/32),4,0xdeadbeef
+#endif
+
+#ifdef rvtest_gpr_save
+gpr_save:
+  .fill 32*(XLEN/32), 4, 0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END
diff --git a/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_csr-comb.S b/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_csr-comb.S
new file mode 100644
index 000000000..e61a1e3c0
--- /dev/null
+++ b/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_csr-comb.S
@@ -0,0 +1,1108 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.11.1
+// timestamp : Thu Dec 28 21:59:52 2023 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/srmcfg.cgf \
+ \
+//                  -- xlen 64  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file is used for the test of CSR-combination coverpoint described in srmcfg covergroup.
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I_ZICSR")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//$cond;def TEST_CASE_1=True;",srmcfg)
+
+
+RVTEST_SIGBASE(x28, signature_x28_0)
+
+
+inst_0_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0f80)
+
+
+inst_0_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 0, x28)
+
+
+inst_0_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_1_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7ff)
+
+
+inst_1_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 8, x28)
+
+
+inst_1_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_2_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x8000000)
+
+
+inst_2_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 16, x28)
+
+
+inst_2_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_3_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff00000)
+
+
+inst_3_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 24, x28)
+
+
+inst_3_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_4_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0e00)
+
+
+inst_4_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 32, x28)
+
+
+inst_4_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_5_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ff0)
+
+
+inst_5_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 40, x28)
+
+
+inst_5_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_6_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff)
+
+
+inst_6_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 48, x28)
+
+
+inst_6_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_7_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0dff)
+
+
+inst_7_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 56, x28)
+
+
+inst_7_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_8_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xc000000)
+
+
+inst_8_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 64, x28)
+
+
+inst_8_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_9_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff07ff)
+
+
+inst_9_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 72, x28)
+
+
+inst_9_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_10_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0000)
+
+
+inst_10_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 80, x28)
+
+
+inst_10_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_11_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fef)
+
+
+inst_11_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 88, x28)
+
+
+inst_11_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_12_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffe0fff)
+
+
+inst_12_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 96, x28)
+
+
+inst_12_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_13_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xbff0fff)
+
+
+inst_13_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 104, x28)
+
+
+inst_13_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_14_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fdf)
+
+
+inst_14_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 112, x28)
+
+
+inst_14_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_15_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x70fff)
+
+
+inst_15_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 120, x28)
+
+
+inst_15_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_16_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff)
+
+
+inst_16_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 128, x28)
+
+
+inst_16_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_17_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7f)
+
+
+inst_17_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 136, x28)
+
+
+inst_17_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_18_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7ff0fff)
+
+
+inst_18_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 144, x28)
+
+
+inst_18_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_19_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ff8)
+
+
+inst_19_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 152, x28)
+
+
+inst_19_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_20_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffe)
+
+
+inst_20_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 160, x28)
+
+
+inst_20_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_21_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1f)
+
+
+inst_21_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 168, x28)
+
+
+inst_21_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_22_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xeff0fff)
+
+
+inst_22_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 176, x28)
+
+
+inst_22_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_23_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fc0)
+
+
+inst_23_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 184, x28)
+
+
+inst_23_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_24_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x30fff)
+
+
+inst_24_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 192, x28)
+
+
+inst_24_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_25_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfc00000)
+
+
+inst_25_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 200, x28)
+
+
+inst_25_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_26_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff70fff)
+
+
+inst_26_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 208, x28)
+
+
+inst_26_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_27_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffd)
+
+
+inst_27_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 216, x28)
+
+
+inst_27_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_28_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3)
+
+
+inst_28_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 224, x28)
+
+
+inst_28_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_29_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3ff0fff)
+
+
+inst_29_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 232, x28)
+
+
+inst_29_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_30_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0800)
+
+
+inst_30_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 240, x28)
+
+
+inst_30_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_31_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf7f0fff)
+
+
+inst_31_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 248, x28)
+
+
+inst_31_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_32_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3f0fff)
+
+
+inst_32_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 256, x28)
+
+
+inst_32_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_33_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fe0)
+
+
+inst_33_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 264, x28)
+
+
+inst_33_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_34_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fff)
+
+
+inst_34_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 272, x28)
+
+
+inst_34_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_35_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0f7f)
+
+
+inst_35_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 280, x28)
+
+
+inst_35_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_36_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfef0fff)
+
+
+inst_36_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 288, x28)
+
+
+inst_36_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_37_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x0)
+
+
+inst_37_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 296, x28)
+
+
+inst_37_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_38_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3ff)
+
+
+inst_38_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 304, x28)
+
+
+inst_38_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_39_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ff7)
+
+
+inst_39_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 312, x28)
+
+
+inst_39_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_40_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf0fff)
+
+
+inst_40_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 320, x28)
+
+
+inst_40_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_41_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7)
+
+
+inst_41_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 328, x28)
+
+
+inst_41_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_42_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x3f)
+
+
+inst_42_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 336, x28)
+
+
+inst_42_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_43_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xe000000)
+
+
+inst_43_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 344, x28)
+
+
+inst_43_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_44_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffb)
+
+
+inst_44_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 352, x28)
+
+
+inst_44_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_45_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0eff)
+
+
+inst_45_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 360, x28)
+
+
+inst_45_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_46_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfdf0fff)
+
+
+inst_46_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 368, x28)
+
+
+inst_46_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_47_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffe0000)
+
+
+inst_47_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 376, x28)
+
+
+inst_47_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_48_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0fbf)
+
+
+inst_48_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 384, x28)
+
+
+inst_48_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_49_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xdff0fff)
+
+
+inst_49_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 392, x28)
+
+
+inst_49_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_50_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf000000)
+
+
+inst_50_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 400, x28)
+
+
+inst_50_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_51_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1ff)
+
+
+inst_51_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 408, x28)
+
+
+inst_51_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_52_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x7f0fff)
+
+
+inst_52_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 416, x28)
+
+
+inst_52_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_53_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfe00000)
+
+
+inst_53_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 424, x28)
+
+
+inst_53_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_54_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf)
+
+
+inst_54_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 432, x28)
+
+
+inst_54_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_55_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffd0fff)
+
+
+inst_55_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 440, x28)
+
+
+inst_55_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_56_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xf800000)
+
+
+inst_56_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 448, x28)
+
+
+inst_56_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_57_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffc0000)
+
+
+inst_57_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 456, x28)
+
+
+inst_57_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_58_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1ff0fff)
+
+
+inst_58_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 464, x28)
+
+
+inst_58_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_59_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0bff)
+
+
+inst_59_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 472, x28)
+
+
+inst_59_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_60_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xffb0fff)
+
+
+inst_60_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 480, x28)
+
+
+inst_60_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_61_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0ffc)
+
+
+inst_61_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 488, x28)
+
+
+inst_61_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_62_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff0fff)
+
+
+inst_62_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 496, x28)
+
+
+inst_62_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_63_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0c00)
+
+
+inst_63_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 504, x28)
+
+
+inst_63_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_64_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfbf0fff)
+
+
+inst_64_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 512, x28)
+
+
+inst_64_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_65_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1)
+
+
+inst_65_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 520, x28)
+
+
+inst_65_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_66_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x1f0fff)
+
+
+inst_66_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 528, x28)
+
+
+inst_66_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_67_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xfff0f00)
+
+
+inst_67_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 536, x28)
+
+
+inst_67_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_68_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0x10fff)
+
+
+inst_68_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 544, x28)
+
+
+inst_68_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+
+inst_69_csr_write_0:
+
+WRITE_TO_CSR_FIELD_W_MASK(CSR_SRMCFG, x1, x30, x31, 0xfff0fff, 0xff80000)
+
+
+inst_69_csr_read_sig_upd_0:
+
+READ_CSR_REG_AND_UPD_SIG(CSR_SRMCFG, x29, 552, x28)
+
+
+inst_69_csr_restore_0:
+
+RESTORE_CSR_REG(CSR_SRMCFG, x1)
+
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x28_0:
+    .fill 70*(XLEN/32),4,0xdeadbeef
+
+RVMODEL_DATA_END
diff --git a/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_mstateen0.S b/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_mstateen0.S
new file mode 100644
index 000000000..8764503c6
--- /dev/null
+++ b/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_mstateen0.S
@@ -0,0 +1,132 @@
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the Smstaten and Ssqosid interactions
+// 
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV64I_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+  RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Smstateen.*Ssqosid.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True", srmcfg_mstateen)
+
+  RVTEST_SIGBASE(x1,signature_x1)
+
+  # setup PMP to allow execution in U and S mode
+  li x2, PMP_TOR | PMP_X | PMP_W | PMP_R
+  csrw pmpcfg0, x2
+  csrr x2, pmpcfg0
+  beq  x2, x0, no_TOR_try_NAPOT
+  li x2, 0xFFFFFFFF
+  csrw pmpaddr0, x2
+  j Mend_PMP
+no_TOR_try_NAPOT:
+  li x2, PMP_NAPOT | PMP_X | PMP_W | PMP_R
+  csrw pmpcfg0, x2
+  csrr x2, pmpcfg0
+  beq  x2, x0, Mend_PMP
+  li x2, 0x1FFFFFFF
+  csrw pmpaddr0, x2
+Mend_PMP:
+
+  li x2, 0x05550AAA
+  csrw CSR_SRMCFG, x2
+
+  # transfer to Umode and access the CSR - access faults
+  RVTEST_GOTO_LOWER_MODE Umode
+  csrw CSR_SRMCFG, x0
+  nop
+  nop
+  nop
+  nop
+  nop
+  RVTEST_GOTO_MMODE
+
+  # transfer to Umode and access the CSR - access faults
+  RVTEST_GOTO_LOWER_MODE Smode
+  csrw CSR_SRMCFG, x0
+  nop
+  nop
+  nop
+  nop
+  nop
+  RVTEST_GOTO_MMODE
+
+  csrr x2, CSR_SRMCFG
+  RVTEST_SIGUPD(x1, x2, 0 * REGWIDTH)
+
+  # Enable Smode access to srmcfg
+  csrr x3, CSR_MSTATEEN0
+  li x2, MSTATEEN0_PRIV114
+  or x3, x2, x2
+  csrw CSR_MSTATEEN0, x3
+
+  csrr x2, CSR_MSTATEEN0
+  RVTEST_SIGUPD(x1, x2, 1 * REGWIDTH)
+
+  # transfer to Smode and access the CSR - access succeeds
+  RVTEST_GOTO_LOWER_MODE Smode
+  li x2, 0x0AAA0555
+  csrw CSR_SRMCFG, x2
+  RVTEST_GOTO_MMODE
+
+  csrr x2, CSR_SRMCFG
+  RVTEST_SIGUPD(x1, x2, 2 * REGWIDTH)
+
+  # transfer to Umode and access the CSR - access faults
+  RVTEST_GOTO_LOWER_MODE Umode
+  csrw CSR_SRMCFG, x0
+  nop
+  nop
+  nop
+  nop
+  nop
+  RVTEST_GOTO_MMODE
+
+  csrr x2, CSR_SRMCFG
+  RVTEST_SIGUPD(x1, x2, 3 * REGWIDTH)
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+# Input data section.
+  .data
+  .align 4
+RVTEST_DATA_END
+
+# Output data section.
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+signature_x1:
+  .fill 16*((XLEN/8)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+  .fill 64*(XLEN/32),4,0xdeadbeef
+#endif
+
+#ifdef rvtest_gpr_save
+gpr_save:
+  .fill 32*(XLEN/32), 4, 0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END