diff --git a/CHANGELOG.md b/CHANGELOG.md index 76b6cc76b..7be8c3d9e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # CHANGELOG -## [3.8.18] - 2023-07-28 +## [3.8.19] - 2024-05-08 +- Add support for unratified Svadu extension + +## [3.8.18] - 2024-05-08 - Add Zacas ISA extension support. ## [3.8.17] - 2024-05-03 @@ -100,6 +103,9 @@ Add missing check ISA fields in recently modified div and amo tests - Add ACTs for Atomic Extension excluding Lr/Sc Instructions. - Added Test macro for the execution of atomic instructions. +## [3.7.1] - 2023-07-30 +- Add support for unratified Svadu extension + ## [3.7.0] - 2023-05-16 - Updated the LI macro - Make Trap handler compatible for RV32E diff --git a/coverage/rv32_svadu.cgf b/coverage/rv32_svadu.cgf new file mode 100644 index 000000000..eee9cee6f --- /dev/null +++ b/coverage/rv32_svadu.cgf @@ -0,0 +1,8 @@ + +svhad_sv32: + config: + - check ISA:=regex(.*I.*Svhad.*) + opcode: + nop: 0 + + diff --git a/coverage/rv64_svadu.cgf b/coverage/rv64_svadu.cgf new file mode 100644 index 000000000..6514eebfe --- /dev/null +++ b/coverage/rv64_svadu.cgf @@ -0,0 +1,17 @@ +svhad_sv39: + config: + - check ISA:=regex(.*I.*Svhad.*) + opcode: + nop: 0 + +svhad_sv48: + config: + - check ISA:=regex(.*I.*Svhad.*) + opcode: + nop: 0 + +svhad_sv57: + config: + - check ISA:=regex(.*I.*Svhad.*) + opcode: + nop: 0 diff --git a/riscv-test-suite/env/encoding.h b/riscv-test-suite/env/encoding.h index 1ee1285be..1dbe6853a 100755 --- a/riscv-test-suite/env/encoding.h +++ b/riscv-test-suite/env/encoding.h @@ -131,6 +131,18 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_ADUE 0x2000000000000000 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_ADUE 0x20000000 +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 40b60017a..b74d34859 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -30,6 +30,127 @@ #define SIG sig_bgn_off #define VMEM vmem_bgn_off + +#define SATP_SETUP(_TR0, _TR1, MODE);\ + LA(_TR0, rvtest_Sroot_pg_tbl) ;\ + LI(_TR1, MODE) ;\ + srli _TR0, _TR0, 12 ;\ + or _TR0, _TR0, _TR1 ;\ + csrw satp, _TR0 ;\ + +#define SETUP_PMP_SVADU_TEST(swreg, offset, TR0, TR1, TR2) \ + li TR0, -1 ;\ + csrw pmpaddr0, TR0 ;\ + j PMP_exist ;\ + li TR0, 0 ;\ + li TR1, 0 ;\ + j Mend_PMP ;\ +PMP_exist: ;\ + li TR1, PMP_TOR | PMP_X | PMP_W | PMP_R ;\ + csrw pmpcfg0, TR1 ;\ + csrr TR2, pmpcfg0 ;\ + beq TR1, TR2, Mend_PMP ;\ +no_TOR_try_NAPOT: ;\ + li TR1, PMP_NAPOT | PMP_X | PMP_W | PMP_R ;\ + csrw pmpcfg0, TR1 ;\ + csrr TR2, pmpcfg0 ;\ +Mend_PMP: ;\ + RVTEST_SIGUPD(x1,TR0,offset) ;\ + RVTEST_SIGUPD(x1,TR1,offset) ;\ + +#define TEST_SVADU(swreg, PTE_ADDR, VA, offset, menvcfgaddr, adue_bit) \ + sfence.vma ;\ + la t0, VA ;\ + li t2, PTE_X | PTE_W | PTE_R ;\ +1: ;\ + LREG t1, (PTE_ADDR) ;\ + andi t1, t1, ~(PTE_X | PTE_W | PTE_R | PTE_V) ;\ + or t1, t1, t2 ;\ + SREG t1, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + li t1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, t1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + unimp ;\ + ;\ + li t1, MSTATUS_MPRV ;\ + csrc mstatus, t1 ;\ + ;\ + beqz t2, 2f ;\ + addi t2, t2, -1 ;\ + li t1, PTE_W | PTE_R | PTE_V ;\ + bne t2, t1, 1b ;\ + addi t2, t2, -1 ;\ + j 1b ;\ +2: ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\ + ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + unimp ;\ + ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\ + ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + SREG x0, (t0) ;\ + j 3f ;\ + unimp ;\ +3: ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_D) ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + li t0, adue_bit ;\ + csrs menvcfgaddr, t0 ;\ + ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + j 4f ;\ + unimp ;\ +4: ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) + + #define ALL_MEM_PMP ;\ li t2, -1 ;\ csrw pmpaddr0, t2 ;\ @@ -55,23 +176,74 @@ //****NOTE: label `rvtest_Sroot_pg_tbl` must be declared after RVTEST_DATA_END // in the test aligned at 4kiB (use .align 12) - -#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\ - srli _PAR, _PAR, 12 ;\ - slli _PAR, _PAR, 10 ;\ - or _PAR, _PAR, _PR ;\ - .if (level==1) ;\ - LA(_TR1, rvtest_Sroot_pg_tbl) ;\ - .set vpn, ((VA>>22)&0x3FF)<<2 ;\ - .endif ;\ - .if (level==0) ;\ - LA(_TR1, rvtest_slvl1_pg_tbl) ;\ - .set vpn, ((VA>>12)&0x3FF)<<2 ;\ - .endif ;\ - LI(_TR0, vpn) ;\ - add _TR1, _TR1, _TR0 ;\ +#define PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + srli _VAR, _VAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\ + srli _PAR, _PAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\ + slli _PAR, _PAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\ + LI(_TR0, ((1 << RISCV_PGLEVEL_BITS) - 1)) ;\ + and _VAR, _VAR, _TR0 ;\ + slli _VAR, _VAR, ((XLEN >> 5)+1) ;\ + add _TR1, _TR1, _VAR ;\ + srli _PAR, _PAR, 12 ;\ + slli _PAR, _PAR, 10 ;\ + or _PAR, _PAR, _PR ;\ SREG _PAR, 0(_TR1); +#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV48(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==3) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_slvl3_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV57(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==4) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==3) ;\ + LA(_TR1, rvtest_slvl4_pg_tbl) ;\ + .endif ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_slvl3_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + + #define PTE_SETUP_RV64(_PAR, _PR, _TR0, _TR1, VA, level, mode) ;\ srli _PAR, _PAR, 12 ;\ slli _PAR, _PAR, 10 ;\ @@ -151,6 +323,7 @@ or _TR0, _TR0, _PR ;\ SREG _TR0, 0(_TR1) ; + #define SATP_SETUP_SV32 ;\ LA(t6, rvtest_Sroot_pg_tbl) ;\ LI(t5, SATP32_MODE) ;\ @@ -189,7 +362,6 @@ RVTEST_SIGUPD(sigptr, destreg) /* write original AMO val */ - #define NAN_BOXED(__val__,__width__,__max__) ;\ .if __width__ == 16 ;\ .hword __val__ ;\ @@ -1099,6 +1271,7 @@ ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE) sub x1,x1,tempreg ;\ RVTEST_SIGUPD(swreg,x1,offset) + // for updating signatures of Zacas paired destination register (RV32/RV64). #define RVTEST_SIGUPD_PZACAS(_BR,_R1,_R2,...) ;\ .if NARG(__VA_ARGS__) == 1 ;\ diff --git a/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S b/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S new file mode 100644 index 000000000..9c228fd86 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S @@ -0,0 +1,76 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv32) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) + + # Identity map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV32(t1, PTE_V, t0, s2, t2, 1) + + # enable virtual memory in Sv32 mode + SATP_SETUP(t0, t1, SATP32_MODE) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x31a, MENVCFGH_ADUE) + +#endif +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 128*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S new file mode 100644 index 000000000..750cdb72d --- /dev/null +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S @@ -0,0 +1,75 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV64I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv39) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) + + # Idenity map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV39(t1, PTE_V, t0, s2, t2, 2) + + # enable virtual memory in Sv39 mode + SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39)) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_ADUE) +#endif +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 64*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S new file mode 100644 index 000000000..0297707a9 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S @@ -0,0 +1,75 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV64I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv48) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) + + # Identity map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV48(t1, PTE_V, t0, s2, t2, 3) + + # enable virtual memory in Sv48 mode + SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV48)) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_ADUE) +#endif +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 64*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S new file mode 100644 index 000000000..06f9d2405 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S @@ -0,0 +1,75 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV64I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv57) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) + + # Identity map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV57(t1, PTE_V, t0, s2, t2, 4) + + # enable virtual memory in Sv57 mode + SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV57)) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_ADUE) +#endif +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 64*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END