diff --git a/CHANGELOG.md b/CHANGELOG.md
index 2511d0928..a5bd6dbfa 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,16 +1,19 @@
 # CHANGELOG
 
+## [3.8.9] -- 2024-01-12
+- Fixed Check ISA fields to include 32/64 in Zicond tests.  Note that the riscv-ctg CGFs have not been updated.
+
 ## [3.8.8] -- 2024-01-04
 - Fixed macros to allow assembling tests with LLVM.
 
 ## [3.8.7] -- 2024-01-02
 - Update satp initialization macro
 
-## [3.8.6] -- 2013-12-24
+## [3.8.6] -- 2023-12-24
 - Fixed check ISA fields to include 32/64 in Zca and CMO tests.  Note that the riscv-ctg CGFs have not been updated.
 - Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated.
 
-## [3.8.5] -- 2013-12-23
+## [3.8.5] -- 2023-12-23
 - Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023
 - Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E
 
diff --git a/riscv-test-suite/rv32i_m/Zicond/src/czero.eqz-01.S b/riscv-test-suite/rv32i_m/Zicond/src/czero.eqz-01.S
index 978cacd67..1da8a05f5 100644
--- a/riscv-test-suite/rv32i_m/Zicond/src/czero.eqz-01.S
+++ b/riscv-test-suite/rv32i_m/Zicond/src/czero.eqz-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv32i_m/Zicond/src/czero.nez-01.S b/riscv-test-suite/rv32i_m/Zicond/src/czero.nez-01.S
index d3e7649eb..3ffe27707 100644
--- a/riscv-test-suite/rv32i_m/Zicond/src/czero.nez-01.S
+++ b/riscv-test-suite/rv32i_m/Zicond/src/czero.nez-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.nez)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*Zicond.*);def TEST_CASE_1=True;",czero.nez)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/Zicond/src/czero.eqz-01.S b/riscv-test-suite/rv64i_m/Zicond/src/czero.eqz-01.S
index a41fca4f3..5047a7a51 100644
--- a/riscv-test-suite/rv64i_m/Zicond/src/czero.eqz-01.S
+++ b/riscv-test-suite/rv64i_m/Zicond/src/czero.eqz-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*Zicond.*);def TEST_CASE_1=True;",czero.eqz)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 
diff --git a/riscv-test-suite/rv64i_m/Zicond/src/czero.nez-01.S b/riscv-test-suite/rv64i_m/Zicond/src/czero.nez-01.S
index f678a5108..8abc132b8 100644
--- a/riscv-test-suite/rv64i_m/Zicond/src/czero.nez-01.S
+++ b/riscv-test-suite/rv64i_m/Zicond/src/czero.nez-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*Zicond.*);def TEST_CASE_1=True;",czero.nez)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*Zicond.*);def TEST_CASE_1=True;",czero.nez)
 
 RVTEST_SIGBASE(x1,signature_x1_1)