diff --git a/CHANGELOG.md b/CHANGELOG.md index 9dcc07234..919fce822 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,9 @@ # CHANGELOG +## [3.9] - 2024-05-17 +- Cleanup: Fix RVTEST_CASE macros for Zfa tests. +- Fix warning assembler warning message from test_macros.h + ## [3.8.20] - 2024-05-08 - Updated the Zcmop extension - Add Zimop extension. diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 57f95c600..20df01a96 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -385,7 +385,7 @@ Mend_PMP: ;\ .hword 0xffff ;\ .else ;\ .word 0xffffffff ;\ - .endif ;\ + .endif ;\ .endr ; #define ZERO_EXTEND(__val__,__width__,__max__) ;\ diff --git a/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S b/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S index b670ebc23..1d4d28bcb 100644 --- a/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S +++ b/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S @@ -22,7 +22,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fli.d) +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*.Zfa.*);def TEST_CASE_1=True;",fli.d) // Registers with a special purpose #define SIG_BASEREG x1 diff --git a/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S b/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S index 1558be873..4e7a6f83e 100644 --- a/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S +++ b/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S @@ -22,7 +22,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fli.s) +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fli.s) // Registers with a special purpose #define SIG_BASEREG x1 diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S index 005baf5df..73bd4a2bb 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S index 0a21198b3..b2fe8e846 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b22) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b22) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S index 362399806..d44dd6aea 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b23) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b23) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S index 33b80dc62..29ab00cc3 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b24) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b24) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S index 1d8d44bec..03e344e95 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b27) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b27) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S index 6f519ede8..91b9e823d 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b28) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b28) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S index 68ea441c5..3d374b4a4 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b29) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b29) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S index 0529142f2..8b165397c 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S index 6d4cb5ea6..b3d27b678 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S index 330caa1eb..5da487047 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S index ba4356132..4d56f4f77 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S index b670ebc23..72f4a1d9c 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S @@ -22,7 +22,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fli.d) +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fli.d) // Registers with a special purpose #define SIG_BASEREG x1 diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S index 87ecfee67..b9d5e721e 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S index bac788611..a4142474b 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S index b662c8358..b78e8c69f 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S index f84c19f0c..dc0b16b7a 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S index 730cadbed..e4e9fe655 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S index 2070cf33c..c9776e981 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S index 75d60c253..26fc90ff6 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S index 7dda40e3c..57ca470c1 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S index cb8d673a2..9f2456737 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S index ccc892db4..698547dd8 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S index 255106bf1..aed3181e2 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S index d45e52cce..2ec7c86f3 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S index 11da9945b..7f299cfe6 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fround.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fround.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S index 00d16864b..d6b2193b7 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx.d_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx.d_b1-01.S index 0fd521617..16874bb6a 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx.d_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx.d_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",froundnx.d_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",froundnx.d_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx_b1-01.S b/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx_b1-01.S index 2f4de08a7..a275776bd 100644 --- a/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx_b1-01.S +++ b/riscv-test-suite/rv64i_m/D_Zfa/src/froundnx_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S index 5f362c38b..01ace28c2 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S index f98bd570c..aca88bc2d 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S index 1558be873..4e7a6f83e 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S @@ -22,7 +22,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fli.s) +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fli.s) // Registers with a special purpose #define SIG_BASEREG x1 diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S index fb24ade87..c7d43520a 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S index d6f2205a2..b509b0a81 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S index 9ba1d13ca..92abc380d 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S index 95058f95b..fba057fc8 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S index 463da353e..db054657c 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S index 8b516a937..ed92d2891 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S index 046fa9838..caa7e66b5 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0) diff --git a/riscv-test-suite/rv64i_m/F_Zfa/src/froundnx_b1-01.S b/riscv-test-suite/rv64i_m/F_Zfa/src/froundnx_b1-01.S index 2822435b9..046749f85 100644 --- a/riscv-test-suite/rv64i_m/F_Zfa/src/froundnx_b1-01.S +++ b/riscv-test-suite/rv64i_m/F_Zfa/src/froundnx_b1-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",froundnx_b1) RVTEST_FP_ENABLE() RVTEST_VALBASEUPD(x3,test_dataset_0)