From d173d38cc1eea8dde52483d52d1128e88a380090 Mon Sep 17 00:00:00 2001
From: Paul Donahue <pdonahue@ventanamicro.com>
Date: Thu, 1 Aug 2024 16:20:05 -0700
Subject: [PATCH] Fix minor typo

---
 doc/src/CSRs.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/src/CSRs.tex b/doc/src/CSRs.tex
index df56a6d..509ab2f 100644
--- a/doc/src/CSRs.tex
+++ b/doc/src/CSRs.tex
@@ -15,7 +15,7 @@ \section{Machine-level CSRs}
 and existing machine-level CSRs whose size is changed
 by the Advanced Interrupt Architecture.
 Existing CSRs \z{mie}, \z{mip}, and \z{mideleg} are
-widended to 64~bits to support a total of 64 interrupt causes.
+widened to 64~bits to support a total of 64 interrupt causes.
 
 \begin{table*}[h!]
 \begin{center}