diff --git a/constants.py b/constants.py index 3451ade8..cb3e689d 100644 --- a/constants.py +++ b/constants.py @@ -2,6 +2,20 @@ import csv +overlapping_extensions = { + 'rv_zcmt': {'rv_c_d'}, + 'rv_zcmp': {'rv_c_d'}, + 'rv_c': {'rv_zcmop'}, +} + +overlapping_instructions = { + 'c_addi': {'c_nop'}, + 'c_lui': {'c_addi16sp'}, + 'c_mv': {'c_jr'}, + 'c_jalr': {'c_ebreak'}, + 'c_add': {'c_ebreak', 'c_jalr'}, +} + isa_regex = \ re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo|Zca|Zcf|Zcd|Zcb|Zcmp|Zcmt){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}(_Zca){,1}(_Zcf){,1}(_Zcd){,1}(_Zcb){,1}(_Zcmp){,1}(_Zcmt){,1}$") @@ -157,11 +171,8 @@ 'rstsa16', 'rstsa32', 'srli32_u', - 'slli_rv128', 'slli_rv32', - 'srai_rv128', 'srai_rv32', - 'srli_rv128', 'srli_rv32', 'umax32', 'c_mop_1', diff --git a/encoding.h b/encoding.h index 05b51175..ab6f66b6 100644 --- a/encoding.h +++ b/encoding.h @@ -21,6 +21,7 @@ #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 #define MSTATUS_SPELP 0x00800000 +#define MSTATUS_SDT 0x01000000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 @@ -29,12 +30,14 @@ #define MSTATUS_GVA 0x0000004000000000 #define MSTATUS_MPV 0x0000008000000000 #define MSTATUS_MPELP 0x0000020000000000 +#define MSTATUS_MDT 0x0000040000000000 #define MSTATUS64_SD 0x8000000000000000 #define MSTATUSH_SBE 0x00000010 #define MSTATUSH_MBE 0x00000020 #define MSTATUSH_GVA 0x00000040 #define MSTATUSH_MPV 0x00000080 +#define MSTATUSH_MDT 0x00000400 #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 @@ -48,6 +51,7 @@ #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 #define SSTATUS_SPELP 0x00800000 +#define SSTATUS_SDT 0x01000000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 @@ -70,19 +74,22 @@ #define MNSTATUS_MNPP 0x00001800 #define MNSTATUS_MNPV 0x00000080 -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) +#define DCSR_XDEBUGVER (15U<<28) +#define DCSR_EXTCAUSE (7<<24) +#define DCSR_CETRIG (1<<19) #define DCSR_PELP (1<<18) +#define DCSR_EBREAKVS (1<<17) +#define DCSR_EBREAKVU (1<<16) #define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) #define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STEPIE (1<<11) +#define DCSR_STOPCOUNT (1<<10) #define DCSR_STOPTIME (1<<9) #define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) +#define DCSR_V (1<<5) +#define DCSR_MPRVEN (1<<4) +#define DCSR_NMIP (1<<3) #define DCSR_STEP (1<<2) #define DCSR_PRV (3<<0) @@ -141,6 +148,8 @@ #define MIP_MEIP (1 << IRQ_M_EXT) #define MIP_SGEIP (1 << IRQ_S_GEXT) #define MIP_LCOFIP (1 << IRQ_LCOF) +#define MIP_RAS_LOW_PRIO (1ULL << IRQ_RAS_LOW_PRIO) +#define MIP_RAS_HIGH_PRIO (1ULL << IRQ_RAS_HIGH_PRIO) #define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) #define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) @@ -158,11 +167,13 @@ #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 #define MENVCFG_CDE 0x1000000000000000 +#define MENVCFG_DTE 0x0800000000000000 #define MENVCFG_ADUE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 #define MENVCFG_STCE 0x8000000000000000 #define MENVCFGH_CDE 0x10000000 +#define MENVCFGH_DTE 0x08000000 #define MENVCFGH_ADUE 0x20000000 #define MENVCFGH_PBMTE 0x40000000 #define MENVCFGH_STCE 0x80000000 @@ -172,11 +183,15 @@ #define MSTATEEN0_JVT 0x00000004 #define MSTATEEN0_PRIV114 0x0080000000000000 #define MSTATEEN0_HCONTEXT 0x0200000000000000 +#define MSTATEEN0_AIA 0x0800000000000000 +#define MSTATEEN0_CSRIND 0x1000000000000000 #define MSTATEEN0_HENVCFG 0x4000000000000000 #define MSTATEEN_HSTATEEN 0x8000000000000000 #define MSTATEEN0H_PRIV114 0x00800000 #define MSTATEEN0H_HCONTEXT 0x02000000 +#define MSTATEEN0H_AIA 0x08000000 +#define MSTATEEN0H_CSRIND 0x10000000 #define MSTATEEN0H_HENVCFG 0x40000000 #define MSTATEENH_HSTATEEN 0x80000000 @@ -200,10 +215,12 @@ #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 #define HENVCFG_CBZE 0x00000080 +#define HENVCFG_DTE 0x0800000000000000 #define HENVCFG_ADUE 0x2000000000000000 #define HENVCFG_PBMTE 0x4000000000000000 #define HENVCFG_STCE 0x8000000000000000 +#define HENVCFGH_DTE 0x08000000 #define HENVCFGH_ADUE 0x20000000 #define HENVCFGH_PBMTE 0x40000000 #define HENVCFGH_STCE 0x80000000 @@ -224,10 +241,14 @@ #define HSTATEEN0_FCSR 0x00000002 #define HSTATEEN0_JVT 0x00000004 #define HSTATEEN0_SCONTEXT 0x0200000000000000 +#define HSTATEEN0_AIA 0x0800000000000000 +#define HSTATEEN0_CSRIND 0x1000000000000000 #define HSTATEEN0_SENVCFG 0x4000000000000000 #define HSTATEEN_SSTATEEN 0x8000000000000000 #define HSTATEEN0H_SCONTEXT 0x02000000 +#define HSTATEEN0H_AIA 0x08000000 +#define HSTATEEN0H_CSRIND 0x10000000 #define HSTATEEN0H_SENVCFG 0x40000000 #define HSTATEENH_SSTATEEN 0x80000000 @@ -307,21 +328,23 @@ #define PMP_NA4 0x10 #define PMP_NAPOT 0x18 -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_COP 12 -#define IRQ_LCOF 13 +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_COP 12 +#define IRQ_LCOF 13 +#define IRQ_RAS_LOW_PRIO 35 +#define IRQ_RAS_HIGH_PRIO 43 /* page table entry (PTE) fields */ #define PTE_V 0x001 /* Valid */ @@ -348,6 +371,7 @@ /* software check exception xtval codes */ #define LANDING_PAD_FAULT 2 +#define SHADOW_STACK_FAULT 3 #ifdef __riscv diff --git a/parse.py b/parse.py index 1c41d9c0..48507d96 100755 --- a/parse.py +++ b/parse.py @@ -133,7 +133,7 @@ def process_enc_line(line, ext): return (name, single_dict) -def same_base_ext (ext_name, ext_name_list): +def same_base_isa(ext_name, ext_name_list): type1 = ext_name.split("_")[0] for ext_name1 in ext_name_list: type2 = ext_name1.split("_")[0] @@ -144,6 +144,26 @@ def same_base_ext (ext_name, ext_name_list): return True return False +def overlaps(x, y): + x = x.rjust(len(y), '-') + y = y.rjust(len(x), '-') + + for i in range(0, len(x)): + if not (x[i] == '-' or y[i] == '-' or x[i] == y[i]): + return False + + return True + +def overlap_allowed(a, x, y): + return x in a and y in a[x] or \ + y in a and x in a[y] + +def extension_overlap_allowed(x, y): + return overlap_allowed(overlapping_extensions, x, y) + +def instruction_overlap_allowed(x, y): + return overlap_allowed(overlapping_instructions, x, y) + def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]): ''' This function return a dictionary containing all instructions associated @@ -222,29 +242,32 @@ def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]): # instruction is already imported and raise SystemExit if name in instr_dict: var = instr_dict[name]["extension"] - if same_base_ext(ext_name, var): - # disable same names on the same base extensions + if same_base_isa(ext_name, var): + # disable same names on the same base ISA err_msg = f'instruction : {name} from ' err_msg += f'{ext_name} is already ' - err_msg += f'added from {var} in same base extensions' + err_msg += f'added from {var} in same base ISA' logging.error(err_msg) raise SystemExit(1) elif instr_dict[name]['encoding'] != single_dict['encoding']: - # disable same names with different encodings on different base extensions + # disable same names with different encodings on different base ISAs err_msg = f'instruction : {name} from ' err_msg += f'{ext_name} is already ' - err_msg += f'added from {var} but each have different encodings in different base extensions' + err_msg += f'added from {var} but each have different encodings in different base ISAs' logging.error(err_msg) raise SystemExit(1) instr_dict[name]['extension'].extend(single_dict['extension']) else: for key in instr_dict: item = instr_dict[key] - if item["encoding"] == single_dict['encoding'] and same_base_ext(ext_name, item["extension"]): - # disable different names with same encodings on the same base extensions - err_msg = f'instruction : {name} from ' - err_msg += f'{ext_name} has the same encoding with instruction {key} ' - err_msg += f'added from {item["extension"]} in same base extensions' + if overlaps(item['encoding'], single_dict['encoding']) and \ + not extension_overlap_allowed(ext_name, item['extension'][0]) and \ + not instruction_overlap_allowed(name, key) and \ + same_base_isa(ext_name, item['extension']): + # disable different names with overlapping encodings on the same base ISA + err_msg = f'instruction : {name} in extension ' + err_msg += f'{ext_name} overlaps instruction {key} ' + err_msg += f'in extension {item["extension"]}' logging.error(err_msg) raise SystemExit(1) @@ -756,9 +779,7 @@ def make_chisel(instr_dict, spinal_hdl=False): extensions = instr_dict_2_extensions(instr_dict) for e in extensions: e_instrs = filter(lambda i: instr_dict[i]['extension'][0] == e, instr_dict) - if "rv128_" in e: - e_format = e.replace("rv128_", "").upper() + "128" - elif "rv64_" in e: + if "rv64_" in e: e_format = e.replace("rv64_", "").upper() + "64" elif "rv32_" in e: e_format = e.replace("rv32_", "").upper() + "32" diff --git a/unratified/rv32_d_zfa b/rv32_d_zfa similarity index 100% rename from unratified/rv32_d_zfa rename to rv32_d_zfa diff --git a/rv32_zbb b/rv32_zbb index c1947251..bc23350d 100644 --- a/rv32_zbb +++ b/rv32_zbb @@ -1,3 +1,3 @@ -$pseudo_op rv_zbe::pack zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 +$pseudo_op rv_zbkb::pack zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 $pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13 $pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 diff --git a/unratified/rv64_q_zfa b/rv64_q_zfa similarity index 100% rename from unratified/rv64_q_zfa rename to rv64_q_zfa diff --git a/rv64_zbb b/rv64_zbb index 4a8b24af..c7e4e8c1 100644 --- a/rv64_zbb +++ b/rv64_zbb @@ -5,5 +5,5 @@ rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0= rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3 roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3 rori rd rs1 31..26=0x18 shamtd 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 +$pseudo_op rv64_zbkb::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 $pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 diff --git a/rv64_zbkb b/rv64_zbkb index ad2f4a90..b5e06061 100644 --- a/rv64_zbkb +++ b/rv64_zbkb @@ -3,4 +3,4 @@ $import rv64_zbb::rolw $import rv64_zbb::rorw $import rv64_zbb::roriw $import rv64_zbb::rori -$import rv64_zbe::packw +packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 diff --git a/rv64_zk b/rv64_zk index 0ebf71dc..891f48a4 100644 --- a/rv64_zk +++ b/rv64_zk @@ -4,7 +4,7 @@ $import rv64_zbb::rolw $import rv64_zbb::rorw $import rv64_zbb::roriw $import rv64_zbb::rori -$import rv64_zbe::packw +$import rv64_zbkb::packw #import zkne # Scalar AES - RV64 diff --git a/rv64_zkn b/rv64_zkn index 0ebf71dc..891f48a4 100644 --- a/rv64_zkn +++ b/rv64_zkn @@ -4,7 +4,7 @@ $import rv64_zbb::rolw $import rv64_zbb::rorw $import rv64_zbb::roriw $import rv64_zbb::rori -$import rv64_zbe::packw +$import rv64_zbkb::packw #import zkne # Scalar AES - RV64 diff --git a/rv64_zks b/rv64_zks index 6bbad27c..848a283d 100644 --- a/rv64_zks +++ b/rv64_zks @@ -4,4 +4,4 @@ $import rv64_zbb::rolw $import rv64_zbb::rorw $import rv64_zbb::roriw $import rv64_zbb::rori -$import rv64_zbe::packw +$import rv64_zbkb::packw diff --git a/unratified/rv_c_zihintntl b/rv_c_zihintntl similarity index 100% rename from unratified/rv_c_zihintntl rename to rv_c_zihintntl diff --git a/unratified/rv_d_zfa b/rv_d_zfa similarity index 100% rename from unratified/rv_d_zfa rename to rv_d_zfa diff --git a/unratified/rv_f_zfa b/rv_f_zfa similarity index 100% rename from unratified/rv_f_zfa rename to rv_f_zfa diff --git a/unratified/rv_q_zfa b/rv_q_zfa similarity index 100% rename from unratified/rv_q_zfa rename to rv_q_zfa diff --git a/rv_v b/rv_v index 3cc91c5e..03700458 100644 --- a/rv_v +++ b/rv_v @@ -24,18 +24,10 @@ vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 -vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 -vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 -vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 -vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 -vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 -vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 -vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 -vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 # Vector Indexed-Unordered Instructions (including segment part) # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions @@ -43,18 +35,10 @@ vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vluxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vluxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vluxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vluxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 # Vector Strided Instructions (including segment part) # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions @@ -62,18 +46,10 @@ vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 -vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 -vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 -vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 -vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 # Vector Indexed-Ordered Instructions (including segment part) # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions @@ -81,18 +57,10 @@ vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vloxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vloxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vloxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vloxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsoxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsoxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsoxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsoxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 # Unit-stride F31..29=0ault-Only-First Loads # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads @@ -100,10 +68,6 @@ vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 -vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 -vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 -vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 -vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 # Vector Load/Store Whole Registers # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions diff --git a/unratified/rv_zabha b/rv_zabha similarity index 100% rename from unratified/rv_zabha rename to rv_zabha diff --git a/rv_zbkb b/rv_zbkb index 1499d786..d3f2f8da 100644 --- a/rv_zbkb +++ b/rv_zbkb @@ -3,6 +3,6 @@ $import rv_zbb::ror $import rv_zbb::andn $import rv_zbb::orn $import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh +pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 +packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 $pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 diff --git a/rv_zbkx b/rv_zbkx index f6b64d94..12bc0b49 100644 --- a/rv_zbkx +++ b/rv_zbkx @@ -1,2 +1,2 @@ -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 +xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 +xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 diff --git a/unratified/rv_zcmop b/rv_zcmop similarity index 100% rename from unratified/rv_zcmop rename to rv_zcmop diff --git a/unratified/rv_zfh_zfa b/rv_zfh_zfa similarity index 100% rename from unratified/rv_zfh_zfa rename to rv_zfh_zfa diff --git a/unratified/rv_zicond b/rv_zicond similarity index 100% rename from unratified/rv_zicond rename to rv_zicond diff --git a/unratified/rv_zihintntl b/rv_zihintntl similarity index 100% rename from unratified/rv_zihintntl rename to rv_zihintntl diff --git a/unratified/rv_zimop b/rv_zimop similarity index 100% rename from unratified/rv_zimop rename to rv_zimop diff --git a/rv_zk b/rv_zk index c4dc854a..dc60ee5e 100644 --- a/rv_zk +++ b/rv_zk @@ -4,8 +4,8 @@ $import rv_zbb::ror $import rv_zbb::andn $import rv_zbb::orn $import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh +$import rv_zbkb::pack +$import rv_zbkb::packh $pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 #import zbkc @@ -13,8 +13,8 @@ $import rv_zbc::clmul $import rv_zbc::clmulh #import zbkx -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 #import zknh # Scalar SHA256 - RV32/RV64 diff --git a/rv_zkn b/rv_zkn index c4dc854a..dc60ee5e 100644 --- a/rv_zkn +++ b/rv_zkn @@ -4,8 +4,8 @@ $import rv_zbb::ror $import rv_zbb::andn $import rv_zbb::orn $import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh +$import rv_zbkb::pack +$import rv_zbkb::packh $pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 #import zbkc @@ -13,8 +13,8 @@ $import rv_zbc::clmul $import rv_zbc::clmulh #import zbkx -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 #import zknh # Scalar SHA256 - RV32/RV64 diff --git a/rv_zks b/rv_zks index f88a09b9..0a571151 100644 --- a/rv_zks +++ b/rv_zks @@ -4,8 +4,8 @@ $import rv_zbb::ror $import rv_zbb::andn $import rv_zbb::orn $import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh +$import rv_zbkb::pack +$import rv_zbkb::packh $pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 #import zbkc @@ -13,8 +13,8 @@ $import rv_zbc::clmul $import rv_zbc::clmulh #import zbkx -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 # Scalar SM4 - RV32, RV64 $import rv_zksed::sm4ed diff --git a/unratified/rv_zvbb b/rv_zvbb similarity index 100% rename from unratified/rv_zvbb rename to rv_zvbb diff --git a/unratified/rv_zvbc b/rv_zvbc similarity index 100% rename from unratified/rv_zvbc rename to rv_zvbc diff --git a/unratified/rv_zvkg b/rv_zvkg similarity index 100% rename from unratified/rv_zvkg rename to rv_zvkg diff --git a/unratified/rv_zvkn b/rv_zvkn similarity index 100% rename from unratified/rv_zvkn rename to rv_zvkn diff --git a/unratified/rv_zvkned b/rv_zvkned similarity index 100% rename from unratified/rv_zvkned rename to rv_zvkned diff --git a/unratified/rv_zvknha b/rv_zvknha similarity index 100% rename from unratified/rv_zvknha rename to rv_zvknha diff --git a/unratified/rv_zvknhb b/rv_zvknhb similarity index 100% rename from unratified/rv_zvknhb rename to rv_zvknhb diff --git a/unratified/rv_zvks b/rv_zvks similarity index 100% rename from unratified/rv_zvks rename to rv_zvks diff --git a/unratified/rv_zvksed b/rv_zvksed similarity index 100% rename from unratified/rv_zvksed rename to rv_zvksed diff --git a/unratified/rv_zvksh b/rv_zvksh similarity index 100% rename from unratified/rv_zvksh rename to rv_zvksh diff --git a/unratified/rv128_c b/unratified/rv128_c deleted file mode 100644 index 79cd5325..00000000 --- a/unratified/rv128_c +++ /dev/null @@ -1,14 +0,0 @@ -# quadrant 0 -c.lq rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1 -$import rv64_c::c.ld -c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5 -$import rv64_c::c.sd - -#quadrant 1 -$import rv64_c::c.addiw - -#quadrant 2 -c.lqsp rd_n0 c_uimm10sphi c_uimm10splo 1..0=2 15..13=1 -$import rv64_c::c.ldsp -c.sqsp c_rs2 c_uimm10sp_s 1..0=2 15..13=5 -$import rv64_c::c.sdsp diff --git a/unratified/rv128_i b/unratified/rv128_i deleted file mode 100644 index bb2c10b4..00000000 --- a/unratified/rv128_i +++ /dev/null @@ -1,24 +0,0 @@ -# RV128I additions to RV64I - -addid rd rs1 imm12 14..12=0 6..2=0x16 1..0=3 -sllid rd rs1 31..26=0 shamtd 14..12=1 6..2=0x16 1..0=3 -srlid rd rs1 31..26=0 shamtd 14..12=5 6..2=0x16 1..0=3 -sraid rd rs1 31..26=16 shamtd 14..12=5 6..2=0x16 1..0=3 - -addd rd rs1 rs2 31..25=0 14..12=0 6..2=0x1E 1..0=3 -subd rd rs1 rs2 31..25=32 14..12=0 6..2=0x1E 1..0=3 -slld rd rs1 rs2 31..25=0 14..12=1 6..2=0x1E 1..0=3 -srld rd rs1 rs2 31..25=0 14..12=5 6..2=0x1E 1..0=3 -srad rd rs1 rs2 31..25=32 14..12=5 6..2=0x1E 1..0=3 - -lq rd rs1 imm12 14..12=3 6..2=0x03 1..0=3 -ldu rd rs1 imm12 14..12=7 6..2=0x00 1..0=3 - -sq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 - -$pseudo_op rv64_i::slli slli rd rs1 31..27=0 shamtq 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_i::srli srli rd rs1 31..27=0 shamtq 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_i::srai srai rd rs1 31..27=8 shamtq 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_i::slli slli_rv128 rd rs1 31..27=0 shamtq 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_i::srli srli_rv128 rd rs1 31..27=0 shamtq 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_i::srai srai_rv128 rd rs1 31..27=8 shamtq 14..12=5 6..2=0x04 1..0=3 diff --git a/unratified/rv32_zbp b/unratified/rv32_zbp deleted file mode 100644 index ac8a564a..00000000 --- a/unratified/rv32_zbp +++ /dev/null @@ -1,7 +0,0 @@ -$pseudo_op rv64_zbp::grevi grevi rd rs1 31..25=0x34 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::gorci gorci rd rs1 31..25=0x14 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::shfli shfli rd rs1 31..25=4 24=0 shamtw4 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::unshfli unshfli rd rs1 31..25=4 24=0 shamtw4 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 - - diff --git a/unratified/rv32_zbpbo b/unratified/rv32_zbpbo deleted file mode 100644 index bcee3c95..00000000 --- a/unratified/rv32_zbpbo +++ /dev/null @@ -1,4 +0,0 @@ -$import rv_zbb::clz -$import rv_zbt::fsr -$pseudo_op rv64_zbt::fsri fsri rd rs1 rs3 26=1 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x69F 14..12=5 6..0=0x13 diff --git a/unratified/rv32_zbt b/unratified/rv32_zbt deleted file mode 100644 index 4b5a2863..00000000 --- a/unratified/rv32_zbt +++ /dev/null @@ -1,2 +0,0 @@ -$pseudo_op rv64_zbt::fsri fsri rd rs1 rs3 26=1 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 - diff --git a/unratified/rv32_zpn b/unratified/rv32_zpn deleted file mode 100644 index aa1c3336..00000000 --- a/unratified/rv32_zpn +++ /dev/null @@ -1,3 +0,0 @@ -$import rv_m::mulh -$pseudo_op rv64_zpn::srai.u srai.u 31..25=0b1101010 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -$pseudo_op rv64_zpn::insb insb 31..25=0b1010110 24..22=0b000 imm2 rs1 14..12=0b000 rd 6..0=0b1110111 diff --git a/unratified/rv32_zpsf b/unratified/rv32_zpsf deleted file mode 100644 index f1e07b58..00000000 --- a/unratified/rv32_zpsf +++ /dev/null @@ -1,2 +0,0 @@ -add64 31..25=0b1100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sub64 31..25=0b1100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 diff --git a/unratified/rv64_b b/unratified/rv64_b deleted file mode 100644 index 3d01b8c9..00000000 --- a/unratified/rv64_b +++ /dev/null @@ -1,9 +0,0 @@ -# RV64B additions to RV32B - - -slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 -srow rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3 - -sloiw rd rs1 31..26=8 25=0 shamtw 14..12=1 6..2=0x06 1..0=3 -sroiw rd rs1 31..26=8 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 - diff --git a/unratified/rv64_zbe b/unratified/rv64_zbe deleted file mode 100644 index d36b80c2..00000000 --- a/unratified/rv64_zbe +++ /dev/null @@ -1,4 +0,0 @@ -bcompressw rd rs1 rs2 31..25=4 14..12=6 6..2=0x0E 1..0=3 -bdecompressw rd rs1 rs2 31..25=36 14..12=6 6..2=0x0E 1..0=3 -packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 - diff --git a/unratified/rv64_zbf b/unratified/rv64_zbf deleted file mode 100644 index d02b59db..00000000 --- a/unratified/rv64_zbf +++ /dev/null @@ -1,3 +0,0 @@ -bfpw rd rs1 rs2 31..25=36 14..12=7 6..2=0x0E 1..0=3 -$import rv64_zbe::packw - diff --git a/unratified/rv64_zbm b/unratified/rv64_zbm deleted file mode 100644 index 46a5ebf3..00000000 --- a/unratified/rv64_zbm +++ /dev/null @@ -1,7 +0,0 @@ -bmatflip rd rs1 31..20=0x603 14..12=1 6..2=0x04 1..0=3 -bmator rd rs1 rs2 31..25=4 14..12=3 6..2=0x0C 1..0=3 -bmatxor rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip16 rd rs1 31..25=4 24..20=16 14..12=5 6..2=4 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip8 rd rs1 31..25=4 24..20=24 14..12=5 6..2=4 1..0=3 -$import rv_zbe::pack -$import rv_zbp::packu diff --git a/unratified/rv64_zbp b/unratified/rv64_zbp index 6ffc33fc..98d0b2e7 100644 --- a/unratified/rv64_zbp +++ b/unratified/rv64_zbp @@ -2,16 +2,4 @@ grevi rd rs1 31..26=26 shamtd 14..12=5 6..2=0x04 1..0=3 gorci rd rs1 31..26=10 shamtd 14..12=5 6..2=0x04 1..0=3 shfli rd rs1 31..26=2 25=0 shamtw 14..12=1 6..2=0x04 1..0=3 unshfli rd rs1 31..26=2 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 -$import rv64_zbe::packw -packuw rd rs1 rs2 31..25=36 14..12=4 6..2=0x0E 1..0=3 -$import rv64_zbb::rolw -$import rv64_zbb::rorw -$import rv64_zbb::roriw -$import rv64_zbb::rori -gorcw rd rs1 rs2 31..25=20 14..12=5 6..2=0x0E 1..0=3 -grevw rd rs1 rs2 31..25=52 14..12=5 6..2=0x0E 1..0=3 -gorciw rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -greviw rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 -unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 xperm32 rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/unratified/rv64_zbpbo b/unratified/rv64_zbpbo deleted file mode 100644 index f88bd03f..00000000 --- a/unratified/rv64_zbpbo +++ /dev/null @@ -1,2 +0,0 @@ -$import rv64_zbt::fsrw -$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x6BF 14..12=5 6..0=0x13 diff --git a/unratified/rv64_zbr b/unratified/rv64_zbr deleted file mode 100644 index 3b470f12..00000000 --- a/unratified/rv64_zbr +++ /dev/null @@ -1,3 +0,0 @@ -crc32.d rd rs1 31..20=0x613 14..12=1 6..2=0x04 1..0=3 -crc32c.d rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3 - diff --git a/unratified/rv64_zbt b/unratified/rv64_zbt deleted file mode 100644 index d009b733..00000000 --- a/unratified/rv64_zbt +++ /dev/null @@ -1,6 +0,0 @@ -fslw rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3 -fsrw rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3 -fsriw rd rs1 rs3 26..25=2 shamtw 14..12=5 6..2=0x06 1..0=3 -fsri rd rs1 rs3 26=1 shamtd 14..12=5 6..2=0x04 1..0=3 - - diff --git a/unratified/rv64_zpn b/unratified/rv64_zpn deleted file mode 100644 index fa484faf..00000000 --- a/unratified/rv64_zpn +++ /dev/null @@ -1,82 +0,0 @@ -add32 31..25=0b0100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -insb 31..25=0b1010110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -pkbb16 31..25=0b0000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pktt16 31..25=0b0010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -radd32 31..25=0b0000000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uradd32 31..25=0b0010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kadd32 31..25=0b0001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukadd32 31..25=0b0011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sub32 31..25=0b0100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rsub32 31..25=0b0000001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ursub32 31..25=0b0010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksub32 31..25=0b0001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uksub32 31..25=0b0011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -cras32 31..25=0b0100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rcras32 31..25=0b0000010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urcras32 31..25=0b0010010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kcras32 31..25=0b0001010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukcras32 31..25=0b0011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -crsa32 31..25=0b0100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rcrsa32 31..25=0b0000011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urcrsa32 31..25=0b0010011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kcrsa32 31..25=0b0001011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukcrsa32 31..25=0b0011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stas32 31..25=0b1111000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstas32 31..25=0b1011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstas32 31..25=0b1101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstas32 31..25=0b1100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstas32 31..25=0b1110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stsa32 31..25=0b1111001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -$pseudo_op rv_zvkg::vghsh.vv rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstsa32 31..25=0b1101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstsa32 31..25=0b1100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstsa32 31..25=0b1110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smmul 31..25=0b0100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sra32 31..25=0b0101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srai.u 31..26=0b110101 imm6 rs1 14..12=0b001 rd 6..0=0b1110111 -srai32 31..25=0b0111000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -sra32.u 31..25=0b0110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srai32.u 31..25=0b1000000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -srl32 31..25=0b0101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srli32 31..25=0b0111001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -srl32.u 31..25=0b0110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -$pseudo_op rv_zvksh::vsm3me.vv srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -sll32 31..25=0b0101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -slli32 31..25=0b0111010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -ksll32 31..25=0b0110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kslli32 31..25=0b1000010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -kslra32 31..25=0b0101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kslra32.u 31..25=0b0110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smin32 31..25=0b1001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -umin32 31..25=0b1010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smax32 31..25=0b1001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -$pseudo_op rv_zvkned::vaesdf.vv umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -khmbb16 31..25=0b1101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbt16 31..25=0b1110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmtt16 31..25=0b1111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbb16 31..25=0b1101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbt16 31..25=0b1110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmtt16 31..25=0b1111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabb16 31..25=0b1101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabt16 31..25=0b1110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmatt16 31..25=0b1111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smbt32 31..25=0b0001100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smtt32 31..25=0b0010100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmabb32 31..25=0b0101101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmabt32 31..25=0b0110101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmatt32 31..25=0b0111101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmda32 31..25=0b0011100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmxda32 31..25=0b0011101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmaxda32 31..25=0b0100101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmads32 31..25=0b0101110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmadrs32 31..25=0b0110110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmaxds32 31..25=0b0111110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmsda32 31..25=0b0100110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmsxda32 31..25=0b0100111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smds32 31..25=0b0101100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smdrs32 31..25=0b0110100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smxds32 31..25=0b0111100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sraiw.u 31..25=0b0011010 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -pkbt32 31..25=0b0001111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pktb32 31..25=0b0011111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kabs32 31..25=0b1010110 24..20=0b10010 rs1 14..12=0b000 rd 6..0=0b1110111 diff --git a/unratified/rv_b b/unratified/rv_b deleted file mode 100644 index b0b68b0d..00000000 --- a/unratified/rv_b +++ /dev/null @@ -1,12 +0,0 @@ - -slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 -sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 - - -sloi rd rs1 31..26=8 shamtd 14..12=1 6..2=0x04 1..0=3 -sroi rd rs1 31..26=8 shamtd 14..12=5 6..2=0x04 1..0=3 - - - - - diff --git a/unratified/rv_zbe b/unratified/rv_zbe deleted file mode 100644 index 1e8a037d..00000000 --- a/unratified/rv_zbe +++ /dev/null @@ -1,5 +0,0 @@ -bcompress rd rs1 rs2 31..25=4 14..12=6 6..2=0x0C 1..0=3 -bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3 -pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 -packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 - diff --git a/unratified/rv_zbf b/unratified/rv_zbf deleted file mode 100644 index 33dd0a6b..00000000 --- a/unratified/rv_zbf +++ /dev/null @@ -1,4 +0,0 @@ -bfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3 -$import rv_zbe::pack -$import rv_zbe::packh - diff --git a/unratified/rv_zbp b/unratified/rv_zbp index b66d6b40..bd95dd26 100644 --- a/unratified/rv_zbp +++ b/unratified/rv_zbp @@ -1,15 +1 @@ -$import rv_zbb::andn -$import rv_zbb::orn -$import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh -$import rv_zbb::rol -$import rv_zbb::ror -grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 -gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 -shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 -unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 -xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 -xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 xperm16 rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 -packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 diff --git a/unratified/rv_zbpbo b/unratified/rv_zbpbo deleted file mode 100644 index 356fbb20..00000000 --- a/unratified/rv_zbpbo +++ /dev/null @@ -1,6 +0,0 @@ -$import rv_zbe::pack -$import rv_zbp::packu -$import rv_zbb::max -$import rv_zbb::min -$import rv_zbt::cmix -$pseudo_op rv64_zbp::grevi rev8.h rd rs1 31..20=0x688 14..12=5 6..0=0x13 diff --git a/unratified/rv_zbr b/unratified/rv_zbr deleted file mode 100644 index 3cfd5a78..00000000 --- a/unratified/rv_zbr +++ /dev/null @@ -1,7 +0,0 @@ -crc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3 -crc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3 -crc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3 -crc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3 -crc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3 -crc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3 - diff --git a/unratified/rv_zbt b/unratified/rv_zbt deleted file mode 100644 index 9e7b98b7..00000000 --- a/unratified/rv_zbt +++ /dev/null @@ -1,6 +0,0 @@ -cmix rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3 -cmov rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3 - -fsl rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3 -fsr rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3 - diff --git a/unratified/rv_zpn b/unratified/rv_zpn deleted file mode 100644 index 29ab4fd8..00000000 --- a/unratified/rv_zpn +++ /dev/null @@ -1,196 +0,0 @@ -$pseudo_op rv_zicsr::csrrs rdov rd 19..15=0 31..20=0x009 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrci clrov rd 19..15=1 31..20=0x009 14..12=7 6..2=0x1C 1..0=3 -add16 31..25=0b0100000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -add8 31..25=0b0100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ave 31..25=0b1110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs16 31..25=0b1010111 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs32 31..25=0b1010111 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs8 31..25=0b1010111 24..20=0b00000 rs1 14..12=0b000 rd 6..0=0b1110111 -clz16 31..25=0b1010111 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 -clz32 31..25=0b1010111 24..20=0b11001 rs1 14..12=0b000 rd 6..0=0b1110111 -clz8 31..25=0b1010111 24..20=0b00001 rs1 14..12=0b000 rd 6..0=0b1110111 -cmpeq16 31..25=0b0100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -cmpeq8 31..25=0b0100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -cras16 31..25=0b0100010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -crsa16 31..25=0b0100011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kabs16 31..25=0b1010110 24..20=0b10001 rs1 14..12=0b000 rd 6..0=0b1110111 -kabs8 31..25=0b1010110 24..20=0b10000 rs1 14..12=0b000 rd 6..0=0b1110111 -kabsw 31..25=0b1010110 24..20=0b10100 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd16 31..25=0b0001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd8 31..25=0b0001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kaddh 31..25=0b0000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kaddw 31..25=0b0000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kcras16 31..25=0b0001010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kcrsa16 31..25=0b0001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kdmabb 31..25=0b1101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabt 31..25=0b1110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmatt 31..25=0b1111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbb 31..25=0b0000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbt 31..25=0b0001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmtt 31..25=0b0010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khm16 31..25=0b1000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khm8 31..25=0b1000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmbb 31..25=0b0000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbt 31..25=0b0001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmtt 31..25=0b0010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmx16 31..25=0b1001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmx8 31..25=0b1001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kmabb 31..25=0b0101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmabt 31..25=0b0110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmada 31..25=0b0100100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmadrs 31..25=0b0110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmads 31..25=0b0101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmatt 31..25=0b0111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmaxda 31..25=0b0100101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmaxds 31..25=0b0111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmda 31..25=0b0011100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmac 31..25=0b0110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmac.u 31..25=0b0111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb 31..25=0b0100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb.u 31..25=0b0101011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb2 31..25=0b1100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb2.u 31..25=0b1101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt 31..25=0b0110011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt.u 31..25=0b0111011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt2 31..25=0b1110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt2.u 31..25=0b1111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmsb 31..25=0b0100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmsb.u 31..25=0b0101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwb2 31..25=0b1000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwb2.u 31..25=0b1001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwt2 31..25=0b1010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwt2.u 31..25=0b1011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsda 31..25=0b0100110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsxda 31..25=0b0100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmxda 31..25=0b0011101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksll16 31..25=0b0110010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksll8 31..25=0b0110110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslli16 31..25=0b0111010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -kslli8 31..25=0b0111110 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -kslliw 31..25=0b0011011 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -ksllw 31..25=0b0010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kslra16 31..25=0b0101011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra16.u 31..25=0b0110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra8 31..25=0b0101111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra8.u 31..25=0b0110111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslraw 31..25=0b0110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kslraw.u 31..25=0b0111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kstas16 31..25=0b1100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstsa16 31..25=0b1100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksub16 31..25=0b0001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksub8 31..25=0b0001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksubh 31..25=0b0000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksubw 31..25=0b0000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kwmmul 31..25=0b0110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kwmmul.u 31..25=0b0111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -maddr32 31..25=0b1100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -# maxw and minw with 31..24=0b111100 is replaced with MAX and MIN of zbb -msubr32 31..25=0b1100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pbsad 31..25=0b1111110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -pbsada 31..25=0b1111111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -pkbt16 31..25=0b0001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pktb16 31..25=0b0011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -radd16 31..25=0b0000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -radd8 31..25=0b0000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -raddw 31..25=0b0010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -rcras16 31..25=0b0000010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rcrsa16 31..25=0b0000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rstas16 31..25=0b1011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -$pseudo_op rv_zvknha::vsha2ms.vv rstsa16 31..25=0b1011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rsub16 31..25=0b0000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rsub8 31..25=0b0000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rsubw 31..25=0b0010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sclip16 31..25=0b1000010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -sclip32 31..25=0b1110010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -sclip8 31..25=0b1000110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -scmple16 31..25=0b0001110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmple8 31..25=0b0001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmplt16 31..25=0b0000110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmplt8 31..25=0b0000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sll16 31..25=0b0101010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sll8 31..25=0b0101110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -slli16 31..25=0b0111010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -slli8 31..25=0b0111110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -#kslliw holds same opcode as slliw -smaqa 31..25=0b1100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smaqa.su 31..25=0b1100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smax16 31..25=0b1000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smax8 31..25=0b1000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smbb16 31..25=0b0000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smbt16 31..25=0b0001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smdrs 31..25=0b0110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smds 31..25=0b0101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smin16 31..25=0b1000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smin8 31..25=0b1000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smmul.u 31..25=0b0101000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwb 31..25=0b0100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwb.u 31..25=0b0101010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwt 31..25=0b0110010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwt.u 31..25=0b0111010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smtt16 31..25=0b0010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smxds 31..25=0b0111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sra.u 31..25=0b0010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sra16 31..25=0b0101000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra16.u 31..25=0b0110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra8 31..25=0b0101100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra8.u 31..25=0b0110100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srai16 31..25=0b0111000 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srai16.u 31..25=0b0111000 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srai8 31..25=0b0111100 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srai8.u 31..25=0b0111100 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srl16 31..25=0b0101001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl16.u 31..25=0b0110001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl8 31..25=0b0101101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl8.u 31..25=0b0110101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srli16 31..25=0b0111001 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srli16.u 31..25=0b0111001 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srli8 31..25=0b0111101 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srli8.u 31..25=0b0111101 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -stas16 31..25=0b1111010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stsa16 31..25=0b1111011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sub16 31..25=0b0100001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sub8 31..25=0b0100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd810 31..25=0b1010110 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd820 31..25=0b1010110 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd830 31..25=0b1010110 24..20=0b01010 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd831 31..25=0b1010110 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd832 31..25=0b1010110 24..20=0b10011 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip16 31..25=0b1000010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip32 31..25=0b1111010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip8 31..25=0b1000110 24..23=0b10 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmple16 31..25=0b0011110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmple8 31..25=0b0011111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmplt16 31..25=0b0010110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmplt8 31..25=0b0010111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd16 31..25=0b0011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd8 31..25=0b0011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukaddh 31..25=0b0001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukaddw 31..25=0b0001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukcras16 31..25=0b0011010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukcrsa16 31..25=0b0011011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukstas16 31..25=0b1110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstsa16 31..25=0b1110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uksub16 31..25=0b0011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uksub8 31..25=0b0011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uksubh 31..25=0b0001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uksubw 31..25=0b0001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umaqa 31..25=0b1100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umax16 31..25=0b1001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umax8 31..25=0b1001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umin16 31..25=0b1001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umin8 31..25=0b1001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd16 31..25=0b0010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd8 31..25=0b0010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uraddw 31..25=0b0011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -urcras16 31..25=0b0010010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -urcrsa16 31..25=0b0010011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -urstas16 31..25=0b1101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstsa16 31..25=0b1101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ursub16 31..25=0b0010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ursub8 31..25=0b0010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ursubw 31..25=0b0011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -zunpkd810 31..25=0b1010110 24..20=0b01100 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd820 31..25=0b1010110 24..20=0b01101 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd830 31..25=0b1010110 24..20=0b01110 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd831 31..25=0b1010110 24..20=0b01111 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd832 31..25=0b1010110 24..20=0b10111 rs1 14..12=0b000 rd 6..0=0b1110111 diff --git a/unratified/rv_zpsf b/unratified/rv_zpsf deleted file mode 100644 index fb4223ff..00000000 --- a/unratified/rv_zpsf +++ /dev/null @@ -1,37 +0,0 @@ -kadd64 31..25=0b1001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmar64 31..25=0b1001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsr64 31..25=0b1001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksub64 31..25=0b1001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -mulr64 31..25=0b1111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -mulsr64 31..25=0b1110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -radd64 31..25=0b1000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -rsub64 31..25=0b1000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smal 31..25=0b0101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalbb 31..25=0b1000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalbt 31..25=0b1001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalda 31..25=0b1000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaldrs 31..25=0b1001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalds 31..25=0b1000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaltt 31..25=0b1010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalxda 31..25=0b1001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalxds 31..25=0b1010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smar64 31..25=0b1000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smslda 31..25=0b1010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smslxda 31..25=0b1011110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smsr64 31..25=0b1000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smul16 31..25=0b1010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smul8 31..25=0b1010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smulx16 31..25=0b1010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smulx8 31..25=0b1010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd64 31..25=0b1011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukmar64 31..25=0b1011010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukmsr64 31..25=0b1011011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uksub64 31..25=0b1011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umar64 31..25=0b1010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umsr64 31..25=0b1010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umul16 31..25=0b1011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umul8 31..25=0b1011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umulx16 31..25=0b1011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umulx8 31..25=0b1011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd64 31..25=0b1010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ursub64 31..25=0b1010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111