From c7c6877c59ca4b6d914d9d1df8ed42778362694c Mon Sep 17 00:00:00 2001 From: Afonso Oliveira Date: Mon, 7 Oct 2024 10:14:43 +0100 Subject: [PATCH 1/2] Added some V extension Pseudo-instructions Signed-off-by: Afonso Oliveira --- rv_v | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/rv_v b/rv_v index 960336af..3c191dfa 100644 --- a/rv_v +++ b/rv_v @@ -138,6 +138,11 @@ vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +#Pseudo OPFVF +$pseudo_op rv_v::vmflt.vf vmfgt.vv 31..26=0x1b vm rs1 vs2 14..12=0x5 vd 6..0=0x57 +$pseudo_op rv_v::vmfle.vf vmfge.vv 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + + # OPFVV vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 @@ -209,6 +214,10 @@ vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +#Pseudo OPFVV + +$pseudo_op rv_v::vfsgnjn.vv vfneg.v 31..26=0x09 vm vs2=vs1 vs1 14..12=0x1 vd 6..0=0x57 + # OPIVX vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 @@ -302,6 +311,13 @@ vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +#Pseudo OPIVV + +$pseudo_op rv_v::vmslt.vv vmsgt.vv 31..26=0x1b vm vs1 vs2 14..12=0x0 vd 6..0=0x57 +$pseudo_op rv_v::vmsltu.vv vmsgtu.vv 31..26=0x1a vm vs1 vs2 14..12=0x0 vd 6..0=0x57 +$pseudo_op rv_v::vmsle.vv vmsge.vv 31..26=0x1d vm vs1 vs2 14..12=0x0 vd 6..0=0x57 +$pseudo_op rv_v::vmsleu.vv vmsgeu.vv 31..26=0x1c vm vs1 vs2 14..12=0x0 vd 6..0=0x57 + # OPIVI vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 @@ -411,6 +427,13 @@ vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +#Pseudo-Instructions for Vector Integer Extension Instructions + +$pseudo_op rv_v::vmxor.mm vmclr.m 31..26=0x1b 25=1 vs2=vd vs1=vd 14..12=0x2 vd 6..0=0x57 +$pseudo_op rv_v::vmnand.mm vmnot.m 31..26=0x1d 25=1 vs2=vs1 vs1 14..12=0x2 vd 6..0=0x57 +$pseudo_op rv_v::vmand.mm vmmv.m 31..26=0x19 25=1 vs2=vs1 vs1 14..12=0x2 vd 6..0=0x57 +$pseudo_op rv_v::vmxnor.mm vmset.m 31..26=0x1f 25=1 vs2=vd vs1=vd 14..12=0x2 vd 6..0=0x57 + # OPMVX vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 @@ -449,3 +472,5 @@ vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +$pseudo_op rv_v::vfsgnjx.vv vfabs.v 31..26=0x0a vm vs2=vs1 vs1 14..12=0x1 vd 6..0=0x57 From 766c468eb362bc8c2424fd2995a43a004fdad716 Mon Sep 17 00:00:00 2001 From: Afonso Oliveira Date: Fri, 25 Oct 2024 16:26:12 +0100 Subject: [PATCH 2/2] Fixed wrong pseudo instruction definition Signed-off-by: Afonso Oliveira --- rv_v | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/rv_v b/rv_v index 3c191dfa..0f475fcc 100644 --- a/rv_v +++ b/rv_v @@ -138,11 +138,6 @@ vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -#Pseudo OPFVF -$pseudo_op rv_v::vmflt.vf vmfgt.vv 31..26=0x1b vm rs1 vs2 14..12=0x5 vd 6..0=0x57 -$pseudo_op rv_v::vmfle.vf vmfge.vv 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - - # OPFVV vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 @@ -217,6 +212,8 @@ vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 #Pseudo OPFVV $pseudo_op rv_v::vfsgnjn.vv vfneg.v 31..26=0x09 vm vs2=vs1 vs1 14..12=0x1 vd 6..0=0x57 +$pseudo_op rv_v::vmflt.vv vmfgt.vv 31..26=0x1b vm vs1 vs2 14..12=0x5 vd 6..0=0x57 +$pseudo_op rv_v::vmfle.vv vmfge.vv 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # OPIVX vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57