From 5eb62ade3e3f21da9e652239da68e18ae6bc8000 Mon Sep 17 00:00:00 2001 From: "Eric.Cheng" Date: Wed, 16 Feb 2022 19:00:44 -0800 Subject: [PATCH] add macro for vector test to not switch to U-mode after initialization --- p/riscv_test.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/p/riscv_test.h b/p/riscv_test.h index fe14f08..bb7b3f5 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -23,6 +23,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV64MV \ + .macro init; \ + RVTEST_MVECTOR_ENABLE; \ + .endm + #define RVTEST_RV32U \ .macro init; \ .endm @@ -37,6 +42,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV32MV \ + .macro init; \ + RVTEST_MVECTOR_ENABLE; \ + .endm + #define RVTEST_RV64M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ @@ -145,6 +155,14 @@ csrwi fcsr, 0; \ csrwi vcsr, 0; +#define RVTEST_MVECTOR_ENABLE \ + li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \ + (MSTATUS_FS & (MSTATUS_FS >> 1)) | \ + (MSTATUS_MPP); \ + csrs mstatus, a0; \ + csrwi fcsr, 0; \ + csrwi vcsr, 0; + #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ 1: bnez a0, 1b