diff --git a/zilsd.adoc b/zilsd.adoc
index c7bd4a5..b85d8e4 100644
--- a/zilsd.adoc
+++ b/zilsd.adoc
@@ -87,42 +87,27 @@ LD instructions with destination `x0` are processed as any other load, but the r
 
 When using `x0` as `src` of SD or C.SDSP, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.
 
-=== Fault Handling
-
-In implementations that crack Zilsd instructions for sequential execution, correct execution requires addressing idempotent memory, because the hart must be able to handle traps detected during the sequence. The entire sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.
-
-[NOTE]
-====
-It is implementation defined whether interrupts can also be taken during the sequence execution.
-====
-
-=== Software view of the load/store pair sequence
-
-From a software perspective load/store pair instructions appear as:
-
-* load instructions:
-** A sequence of one or more loads reading the bytes of the doubleword without updating rd or rd+1
-*** If the effective address is 4B aligned:
-**** The bytes are grouped into word accesses.
-**** The words may be loaded in any order.
-**** The words may be grouped into doublewords accesses.
-**** Any of the words may be loaded multiple times.
-*** Else:
-**** The bytes may be loaded in any order.
-**** The bytes may be grouped into larger accesses.
-**** Any of the bytes may be loaded multiple times.
-** An atomic write of the load result into rd and rd+1
-* store instructions:
-** A sequence of one or more stores writing the bytes of the doubleword
-*** If the effective address is 4B aligned:
-**** The bytes are grouped into word accesses.
-**** The words may be stored in any order.
-**** The words may be grouped into doublewords accesses.
-**** Any of the words may be stored multiple times.
-*** Else:
-**** The bytes may be stored in any order.
-**** The bytes may be grouped into larger accesses.
-**** Any of the bytes may be stored multiple times.
+=== Exception Handling
+
+For the purposes of RVWMO and exception handling, LD and SD instructions are
+considered to be misaligned loads and stores, with one additional constraint:
+an LD or SD instruction whose effective address is a multiple of 4 gives rise
+to two 4-byte memory operations.
+
+NOTE: This definition permits LD and SD instructions giving rise to exactly one
+memory access, regardless of alignment.
+If instructions with 4-byte-aligned effective address are decomposed
+into two 32b operations, there is no constraint on the order in which the
+operations are performed and each operation is guaranteed to be atomic.
+These decomposed sequences are interruptible.
+Exceptions might occur on subsequent operations, making the effects of previous
+operations within the same instruction visible.
+
+NOTE: Software should make no assumptions about the number or order of
+accessses these instructions might give rise to, beyond the 4-byte constraint
+mentioned above.
+For example, an interrupted store might overwrite the same bytes upon return
+from the interrupt handler.
 
 <<<
 
@@ -300,4 +285,4 @@ Stores a 64-bit value from registers `rs2'` and `rs2'+1`.
 It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.
 It expands to `sd rs2', offset(rs1')`.
 
-Included in: <<zclsd>>
\ No newline at end of file
+Included in: <<zclsd>>