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riscvarchive/riscv-state-enable
Integration into riscv-isa-manual has began.

Note that the work to integrate this specification as a chapter into the Privileged Specification in the riscv-isa-manual tree has began. Please note the PR
  • wmat
  • 1
  • Opened 
    on Feb 7, 2024
  • #15

riscvarchive/riscv-state-enable
*stateen0[0] read-only zeros?

Bits in any stateen CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that hart Does this statement mentioned in the specification apply to *stateen0[0], i.e. ...
  • vernonpang
  • Opened 
    on Feb 1, 2024
  • #14

riscvarchive/riscv-state-enable
Stateen bits designated for custom use?

Current spec has following description: Initially, the following bits are defined in mstateen0, hstateen0, and sstateen0: bit 0 - Custom state bit 1 - fcsr for Zfinx and related extensions (Zdinx, etc.) ...
  • henry-hsieh
  • Opened 
    on Feb 1, 2023
  • #13

riscvarchive/riscv-state-enable
Advice about enabling all state is potentially harmful

Currently the spec has the following: If software at any privilege level does not support multiple contexts for less-privilege levels, then it may choose to maximize less-privileged access to all state ...
  • jrtc27
  • Opened 
    on Sep 7, 2022
  • #12

riscvarchive/riscv-state-enable
Controlling access to floating point and vector state from machine mode

As mentioned in the issue I ve posted about the privileged manual: https://github.com/riscv/riscv-isa-manual/issues/832 , mstatus.FS and mstatus.VS cannot actually be used to disable supervisor-mode access ...
  • dramforever
  • Opened 
    on Aug 2, 2022
  • #11

riscvarchive/riscv-state-enable
Stateen controlling access to state

when a stateen CSR prevents access to state by less-privileged levels, an attempt in one of those privilege modes to execute an instruction that would read or write the protected state raises an illegal ...
  • vernonpang
  • Opened 
    on Aug 1, 2022
  • #10

riscvarchive/riscv-state-enable
How h/stateen become read-only zero for zero bits in mstateen?

When I tried to add support for smstateen extension in spike(https://github.com/riscv-software-src/riscv-isa-sim/pull/1035), I find there are two ways to make that bits read-only zero: 1) not change ...
  • liweiwei90
  • 22
  • Opened 
    on Jul 2, 2022
  • #9

riscvarchive/riscv-state-enable
Why is this extension called Smstateen?

The spec proposes adding several machine level CSRs, so according to chapter 27 ISA Extension Naming Conventions of riscv-spec-20191213.pdf, 27.9 Machine-level Instruction-Set Extensions Standard machine-level ...
  • lbmeng
  • 1
  • Opened 
    on Jun 21, 2022
  • #8

riscvarchive/riscv-state-enable
Clarify traps when Zfinx implemented

When Hypervisor, Zfinx and Smstateen are all implemented, can you please clarify which trap occurs when attempting to execute a floating point instruction in VS mode when mstateen0[1]=1 and hstateen0[1]=0? ...
  • JamesKenneyImperas
  • Opened 
    on Jan 5, 2022
  • #6

riscvarchive/riscv-state-enable
Proposed AIA bit allocations should not be in normative text for stateen spec

Suggest moving to non-normative appendix or to the AIA spec. Also, not clear why they don t follow the stated policy of allocating from least-significant bits.
  • kasanovic
  • Opened 
    on Nov 14, 2021
  • #5
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