Zero-extend variants of vmv.x.s and vmv.s.x

[gsauthof]

It looks a bit asymmetric that there are instruction for loading and zero-extending values from memory (for vector and non-vector loads) but when moving the first vector element it's always sign-extended.

For example, to move the first vector element into a scalar register without sign-extending it one has to mask the superfluous sign-bits again, e.g.:

vmv.x.s a5, v24
andi    a5, a5, 0xff

There was issue #254 - but from reading the discussion there I'm not sure if adding zero-extending variants of vmv.x.s/vmv.s.x is already off the table.

Adding those zero-extending variants would make some programs a bit shorter and arguably the instruction set more symmetric/less surprising.

[solomatnikov]

FYI: there is a discussion to remove sign and zero extending vector loads from the spec:

#362

People generally agree that they should be removed and fractional LMUL should be added to mitigate:

#382