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This repository has been archived by the owner on Mar 20, 2024. It is now read-only.
what will be the result of vwop.wv type of instruction when SEW =8 and EDIV = 2?
will the operation be like vd[7:0] = vs1[7:0] + vs2[3:0] for element 0?
There are some request about operation between 4bit weight and 8 bit feature map, just wondering if EDIV would be the right solution or how can I use RVV for this case.
Thanks
The text was updated successfully, but these errors were encountered:
My understanding is that the base "V" extension currently does not provide support for 4-bit elements; this functionality is meant to be exposed via the Zvediv (sub-) extension. Unfortunately it's hard to be more concrete at present:
The EDIV extension is currently not planned to be part of the base "V" extension, and will change substantially from the current sketch.
Although the Zvediv spec doesn't explicitly address vwop.wv-type instructions, I believe your interpretation matches its intent, after reversing the labels vs1 and vs2 in your pseudocode:
# Double-width result, first source double-width, second source single-width: 2*SEW = 2*SEW op SEW
vwop.wv vd, vs2, vs1, vm # integer vector-vector vd[i] = vs2[i] op vs1[i]
Hi
what will be the result of vwop.wv type of instruction when SEW =8 and EDIV = 2?
will the operation be like vd[7:0] = vs1[7:0] + vs2[3:0] for element 0?
There are some request about operation between 4bit weight and 8 bit feature map, just wondering if EDIV would be the right solution or how can I use RVV for this case.
Thanks
The text was updated successfully, but these errors were encountered: