provide section on HINTs

[David-Horner]

What also needs to be added is a section like RVI and RVC on hints.

They defined the canonical NOP for each.

RV32I reserves a large encoding space for HINT instructions, which are usually used to communicate
performance hints to the microarchitecture. HINTs are encoded as integer computational instruc-
tions with rd= x0 . Hence, like the NOP instruction, HINTs do not change any architecturally visible
state, except for advancing the pc and any applicable performance counters. Implementations are
always allowed to ignore the encoded hints.

RVC HINTs are encoded as computational instructions that do not modify the architectural state,
either because rd= x0 (e.g. C.ADD x0, t0), or because rd is overwritten with a copy of itself (e.g.
C.ADDI t0, 0)

I believe the #503 hint is a sufficient example for the general case of the same register overwritten by a copy of itself.

from #373
When rs1=0 each of the following op.vx and op.vi are equivalent to vmv.v.v

vadd, vsaddu, vsadd, vor, vxor
vsll, vsrl, vsra, vssrl, vssra
vslideup, vslidedown

so, when destination=source these are also "nops".

Are there other general cases that the opcode itself defines a nop?

Should masked instructions with all false mask, and vstart> vl also be discussed in this section?

Do we exclude some cases and why?

Do we address canonical form for equivalences? even if we don't go as far as reserving - #373 ?

Is it sufficient to add these aspects to the documentation for v1.0 even if we do not fully populate hint and equivalence tables?