diff --git a/HardwareRegister.py b/HardwareRegister.py
index 498a7241..12d2acec 100644
--- a/HardwareRegister.py
+++ b/HardwareRegister.py
@@ -72,7 +72,6 @@ def set_well_defined_asm_names(self, llvm_asm: str, llvm_alt: list):
                 )
             )
 
-    # RIZIN SPECIFIC
     @staticmethod
     def get_parse_code_reg_bits(reg_class: str, var: str) -> str:
         """Sub register bits are encoded in a space saving way in the instruction encoding.
@@ -107,7 +106,6 @@ def get_parse_code_reg_bits(reg_class: str, var: str) -> str:
             code += "{} |= 6;\n".format(var)
         return code
 
-    # RIZIN SPECIFIC
     def get_reg_profile(self, offset: int, is_tmp: bool) -> str:
         """Returns a one line register profile description.
 
@@ -126,7 +124,6 @@ def get_reg_profile(self, offset: int, is_tmp: bool) -> str:
             i=indent,
         )
 
-    # RIZIN SPECIFIC
     def get_rz_reg_type(self) -> str:
         if self.is_control and self.is_hvx:
             return "vcc"
diff --git a/Immediate.py b/Immediate.py
index 5f5df3af..a40d1243 100644
--- a/Immediate.py
+++ b/Immediate.py
@@ -129,7 +129,6 @@ def parse_imm_type(self, llvm_imm_type: str) -> None:
                 "Extendable immediate is not 32 or 64bits long!\n" + "imm: {}".format(self.llvm_syntax)
             )
 
-    # RIZIN SPECIFIC
     def c_template(self, force_extendable=False) -> str:
         if self.is_constant:
             return ".info = HEX_OP_TEMPLATE_TYPE_IMM_CONST"
diff --git a/InstructionTemplate.py b/InstructionTemplate.py
index 264a0b3b..614223b8 100644
--- a/InstructionTemplate.py
+++ b/InstructionTemplate.py
@@ -320,7 +320,6 @@ def get_template_in_c(self) -> str:
         code += "}"
         return code
 
-    # RIZIN SPECIFIC
     def get_predicate(self) -> str:
         if not self.is_predicated:
             pred = ["HEX_NOPRED"]
@@ -334,7 +333,6 @@ def get_predicate(self) -> str:
                 pred.append("HEX_PRED_NEW")
         return " | ".join(pred)
 
-    # RIZIN SPECIFIC
     def get_rz_cond_type(self):
         """Returns the rizin conditional type."""
 
@@ -352,7 +350,6 @@ def get_rz_cond_type(self):
             else:
                 return "RZ_TYPE_COND_HEX_SCL_FALSE"
 
-    # RIZIN SPECIFIC
     @property
     def c_rz_op_type(self) -> str:
         if self.is_trap:
@@ -391,7 +388,6 @@ def c_rz_op_type(self) -> str:
         )
         return "RZ_ANALYSIS_OP_TYPE_NULL"
 
-    # RIZIN SPECIFIC
     @staticmethod
     def register_names_to_upper(mnemonic: str) -> str:
         """The syntax can contain lower case register names. Here we convert them to upper case to enable syntax
@@ -402,7 +398,6 @@ def register_names_to_upper(mnemonic: str) -> str:
                 mnemonic = re.sub(reg_name.lower(), reg_name.upper(), mnemonic)
         return mnemonic
 
-    # RIZIN SPECIFIC
     def get_pkt_info_code(self) -> str:
         # Duplexes are always last instr. in packet.
         pass
diff --git a/LLVMImporter.py b/LLVMImporter.py
index a7bd8575..9e561f37 100755
--- a/LLVMImporter.py
+++ b/LLVMImporter.py
@@ -77,7 +77,6 @@ def __init__(self, build_json: bool, test_mode=False):
 
         self.unchanged_files = []  # Src files which had no changes after generation.
 
-        # RIZIN SPECIFIC
         # Name of the function which parses the encoded register index bits.
         self.reg_resolve_decl = list()
 
@@ -352,7 +351,6 @@ def get_cc_regs(self) -> dict:
 
         return cc_regs
 
-    # RIZIN SPECIFIC
     def generate_rizin_code(self) -> None:
         log("Generate and write source code.")
         self.build_hexagon_insn_enum_h()
@@ -370,12 +368,10 @@ def generate_rizin_code(self) -> None:
         # TODO hexagon.h: Gen - HexOpType, IClasses, Regs and its aliases (system = guest),
         #  + corresponding functions in hexagon.c: hex_get_sub_regpair etc.
 
-    # RIZIN SPECIFIC
     # TODO Wouldn't it be a wonderful world...
     def generate_decompiler_code(self) -> None:
         pass
 
-    # RIZIN SPECIFIC
     def add_license_info_header(self) -> None:
         log("Add license headers")
         for subdir, dirs, files in os.walk(PathHandler().complete_path("{RIZIN_DIR}")):
@@ -390,7 +386,6 @@ def add_license_info_header(self) -> None:
                     f.seek(0, 0)
                     f.write(get_license() + "\n" + get_generation_timestamp(self.config) + "\n" + content)
 
-    # RIZIN SPECIFIC
     def build_hexagon_insn_enum_h(self, path: Path = PathHandler().get_output_file("hexagon_insn.h")) -> None:
         code = get_generation_warning_c_code()
         code += "\n"
@@ -408,7 +403,6 @@ def build_hexagon_insn_enum_h(self, path: Path = PathHandler().get_output_file("
 
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     def build_hexagon_disas_c(self, path: Path = PathHandler().get_output_file("hexagon_disas.c")) -> None:
         code = get_generation_warning_c_code()
 
@@ -444,7 +438,6 @@ def build_hexagon_disas_c(self, path: Path = PathHandler().get_output_file("hexa
 
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     def build_hexagon_h(self, path: Path = PathHandler().get_output_file("hexagon.h")) -> None:
         indent = PluginInfo.LINE_INDENT
         general_prefix = PluginInfo.GENERAL_ENUM_PREFIX
@@ -505,7 +498,6 @@ def build_hexagon_h(self, path: Path = PathHandler().get_output_file("hexagon.h"
 
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     def build_hexagon_c(self, path: Path = PathHandler().get_output_file("hexagon.c")) -> None:
         general_prefix = PluginInfo.GENERAL_ENUM_PREFIX
         code = get_generation_warning_c_code()
@@ -581,7 +573,6 @@ def build_dwarf_reg_num_table(self, path: Path = PathHandler().get_output_file("
         code += "}}"
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     def build_asm_hexagon_c(self, path: Path = PathHandler().get_output_file("asm_hexagon.c")) -> None:
         code = get_generation_warning_c_code()
 
@@ -590,7 +581,6 @@ def build_asm_hexagon_c(self, path: Path = PathHandler().get_output_file("asm_he
 
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     def build_hexagon_arch_c(self, path: Path = PathHandler().get_output_file("hexagon_arch.c")):
         code = get_generation_warning_c_code()
 
@@ -600,7 +590,6 @@ def build_hexagon_arch_c(self, path: Path = PathHandler().get_output_file("hexag
 
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     def build_hexagon_arch_h(self, path: Path = PathHandler().get_output_file("hexagon_arch.h")):
         code = get_generation_warning_c_code()
         code += get_include_guard("hexagon_arch.h")
@@ -612,7 +601,6 @@ def build_hexagon_arch_h(self, path: Path = PathHandler().get_output_file("hexag
 
         self.write_src(code, path)
 
-    # RIZIN SPECIFIC
     @staticmethod
     def copy_tests() -> None:
         with open(PathHandler().get_input_dir("analysis-tests").joinpath("hexagon")) as f:
@@ -626,7 +614,6 @@ def copy_tests() -> None:
                 g.writelines(f.readlines())
         log("Copied test files to ./rizin/test/db/", LogLevel.DEBUG)
 
-    # RIZIN SPECIFIC
     def build_analysis_hexagon_c(self, path: Path = PathHandler().get_output_file("analysis_hexagon.c")) -> None:
         """Generates and writes the register profile.
         Note that some registers share the same offsets. R0 and R1:0 are both based at offset 0.
@@ -754,7 +741,6 @@ def get_alias_profile(self) -> str:
 
         return p
 
-    # RIZIN SPECIFIC
     @staticmethod
     def build_cc_hexagon_32_sdb_txt(
         path: Path = PathHandler().get_output_file("cc-hexagon-32.sdb.txt"),
@@ -824,7 +810,6 @@ def build_cc_hexagon_32_sdb_txt(
             for k, v in cc_dict.items():
                 f.write(k + "=" + v + "\n")
 
-    # RIZIN SPECIFIC
     @staticmethod
     def apply_clang_format() -> None:
         log("Apply clang-format.")
diff --git a/README.md b/README.md
index 8424f21c..cfc5fdcc 100644
--- a/README.md
+++ b/README.md
@@ -78,16 +78,6 @@ cd Tests
 python3 -m unittest discover -s . -t .
 ```
 
-# Porting
-
-Apart from some methods, which produce the C code for `rizin`, this code is `rizin` independent.
-In theory, it shouldn't be that hard to use it for disassembler plugins of other reverse engineering frameworks.
-
-So here are some good to know points for porting:
-- All `rizin` specific methods have the leading comment: `# RIZIN SPECIFIC`.
-- Please open an issue if you start working on this code for another reverse engineering framework.
-  We could remove all `rizin` code from this repo and fork our framework specific plugins from it.
-
 # Development info
 
 **Before you open a PR please run and fix the warnings.:
diff --git a/Register.py b/Register.py
index 32b162a2..9e989bc4 100644
--- a/Register.py
+++ b/Register.py
@@ -154,7 +154,6 @@ def parse_reg_type(self) -> None:
         else:
             raise ImplementationException("Unhandled register type: {}".format(self.llvm_reg_class))
 
-    # RIZIN SPECIFIC
     def c_template(self, force_extendable=False) -> str:
         info = ["HEX_OP_TEMPLATE_TYPE_REG"]
         if self.is_out_operand:
@@ -181,7 +180,6 @@ def register_class_name_to_upper(s: str) -> str:
             s = s[:-1]
         return s
 
-    # RIZIN SPECIFIC
     @staticmethod
     def get_func_name_of_class(reg_class: str, is_n_reg: bool) -> str:
         """
@@ -198,7 +196,6 @@ def get_func_name_of_class(reg_class: str, is_n_reg: bool) -> str:
         code = PluginInfo.GENERAL_ENUM_PREFIX.lower() + "get_" + reg_func
         return code
 
-    # RIZIN SPECIFIC
     @staticmethod
     def get_enum_item_of_class(reg_class: str) -> str:
         """
diff --git a/Tests/testEncoding.py b/Tests/testEncoding.py
index 4f317e70..f7625135 100644
--- a/Tests/testEncoding.py
+++ b/Tests/testEncoding.py
@@ -79,7 +79,6 @@ def test_correct_operand_names(self) -> None:
         # TODO
         pass
 
-    # RIZIN SPECIFIC
     def test_shifting_c_code(self) -> None:
         self.assertEqual(
             "{ 0x8, 5 }",