From 70afe2a70b79f3f04ce386b8aca1d9ed0f7f9429 Mon Sep 17 00:00:00 2001
From: Rot127 <unisono@quyllur.org>
Date: Thu, 23 Nov 2023 13:35:33 -0500
Subject: [PATCH] Update CC generation with upper case reg names

---
 LLVMImporter.py | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/LLVMImporter.py b/LLVMImporter.py
index 8d932641..fa352841 100755
--- a/LLVMImporter.py
+++ b/LLVMImporter.py
@@ -1198,26 +1198,28 @@ def build_cc_hexagon_32_sdb_txt(path: Path = Conf.get_path(OutputFile.CC_HEXAGON
             for reg in HexagonArchInfo.CC_REGS["GPR_args"]:
                 n = int(re.search(r"\d{1,2}", reg).group(0))
                 if reg[0] == "R":
-                    cc_dict["cc.hexagon.arg{}".format(n)] = "r{}".format(n)
+                    cc_dict[f"cc.hexagon.arg{n}"] = f"R{n}"
                 elif reg[0] == "D":
+                    # Rizin has currently no way to define a different CC for
+                    # different sized parameters.
                     continue
                 else:
                     raise ImplementationException(
-                        "Could not assign register {} to a specific argument" " value.".format(reg)
+                        f"Could not assign register {reg} to a specific return value."
                     )
             cc_dict["cc.hexagon.argn"] = "stack_rev"
             for reg in HexagonArchInfo.CC_REGS["GPR_ret"]:
                 n = int(re.search(r"\d{1,2}", reg).group(0))
                 if reg[0] == "R":
                     if HexagonArchInfo.CC_REGS["GPR_ret"].index(reg) == 0:
-                        cc_dict["cc.hexagon.ret".format(n)] = "r{}".format(n)
+                        cc_dict["cc.hexagon.ret"] = f"R{n}"
                     else:
                         continue
                 elif reg[0] == "D":
                     continue
                 else:
                     raise ImplementationException(
-                        "Could not assign register {} to a specific return" " value.".format(reg)
+                        f"Could not assign register {reg} to a specific return value."
                     )
 
             f.write("default.cc=hexagon\n\nhexagon=cc\n")
@@ -1229,25 +1231,25 @@ def build_cc_hexagon_32_sdb_txt(path: Path = Conf.get_path(OutputFile.CC_HEXAGON
             for reg in HexagonArchInfo.CC_REGS["HVX_args"]:
                 n = int(re.search(r"\d{1,2}", reg).group(0))
                 if reg[0] == "V":
-                    cc_dict["cc.hvx.arg{}".format(n)] = "v{}".format(n)
+                    cc_dict[f"cc.hvx.arg{n}"] = f"V{n}"
                 elif reg[0] == "W":
                     continue
                 else:
                     raise ImplementationException(
-                        "Could not assign register {} to a specific argument" " value.".format(reg)
+                        f"Could not assign register {reg} to a specific return value."
                     )
             for reg in HexagonArchInfo.CC_REGS["HVX_ret"]:
                 n = int(re.search(r"\d{1,2}", reg).group(0))
                 if reg[0] == "V":
                     if HexagonArchInfo.CC_REGS["HVX_ret"].index(reg) == 0:
-                        cc_dict["cc.hvx.ret".format(n)] = "v{}".format(n)
+                        cc_dict["cc.hvx.ret"] = f"V{n}"
                     else:
                         continue
                 elif reg[0] == "W":
                     continue
                 else:
                     raise ImplementationException(
-                        "Could not assign register {} to a specific return" " value.".format(reg)
+                        f"Could not assign register {reg} to a specific return value."
                     )
             for k, v in cc_dict.items():
                 f.write(k + "=" + v + "\n")