From a0aee5996f7876704e846f65f62f7c4d2af90a76 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Wed, 15 Nov 2023 11:22:30 -0500 Subject: [PATCH] Update to LLVM b6f51787f6c8 (new system instructions.) --- .../instructions/IMPORTED_Pd_l2locka_Rs.json | 411 --------- .../IMPORTED_Rd_ctlbw_Rss_Rt.json | 443 --------- .../instructions/IMPORTED_Rd_dctagr_Rs.json | 420 --------- .../instructions/IMPORTED_Rd_getimask_Rs.json | 420 --------- .../instructions/IMPORTED_Rd_iassignr_Rs.json | 420 --------- .../instructions/IMPORTED_Rd_icdatar_Rs.json | 420 --------- .../instructions/IMPORTED_Rd_ictagr_Rs.json | 420 --------- .../instructions/IMPORTED_Rd_l2tagr_Rs.json | 420 --------- .../IMPORTED_Rd_memw_locked_Rs.json | 420 --------- .../instructions/IMPORTED_Rd_tlboc_Rss.json | 420 --------- import/instructions/IMPORTED_Rd_tlbp_Rs.json | 420 --------- .../IMPORTED_Rdd_memd_locked_Rs.json | 420 --------- import/instructions/IMPORTED_Rdd_tlbr_Rs.json | 420 --------- import/instructions/IMPORTED_barrier.json | 372 -------- import/instructions/IMPORTED_brkpt.json | 372 -------- import/instructions/IMPORTED_ciad_Rs.json | 396 -------- import/instructions/IMPORTED_cswi_Rs.json | 396 -------- import/instructions/IMPORTED_dccleana_Rs.json | 396 -------- .../instructions/IMPORTED_dccleanidx_Rs.json | 396 -------- .../instructions/IMPORTED_dccleaninva_Rs.json | 396 -------- .../IMPORTED_dccleaninvidx_Rs.json | 396 -------- .../IMPORTED_dcfetch_Rs__u11_3.json | 437 --------- import/instructions/IMPORTED_dcinva_Rs.json | 396 -------- import/instructions/IMPORTED_dcinvidx_Rs.json | 396 -------- import/instructions/IMPORTED_dckill.json | 372 -------- .../instructions/IMPORTED_dctagw_Rs_Rt.json | 419 --------- import/instructions/IMPORTED_dczeroa_Rs.json | 396 -------- .../instructions/IMPORTED_diag0_Rss_Rtt.json | 419 --------- .../instructions/IMPORTED_diag1_Rss_Rtt.json | 419 --------- import/instructions/IMPORTED_diag_Rs.json | 396 -------- import/instructions/IMPORTED_iassignw_Rs.json | 396 -------- .../instructions/IMPORTED_icdataw_Rs_Rt.json | 419 --------- import/instructions/IMPORTED_icinva_Rs.json | 396 -------- import/instructions/IMPORTED_icinvidx_Rs.json | 396 -------- import/instructions/IMPORTED_ickill.json | 372 -------- .../instructions/IMPORTED_ictagw_Rs_Rt.json | 419 --------- import/instructions/IMPORTED_isync.json | 372 -------- import/instructions/IMPORTED_k0lock.json | 372 -------- import/instructions/IMPORTED_k0unlock.json | 372 -------- .../instructions/IMPORTED_l2cleanidx_Rs.json | 396 -------- .../IMPORTED_l2cleaninvidx_Rs.json | 396 -------- .../instructions/IMPORTED_l2fetch_Rs_Rt.json | 419 --------- .../instructions/IMPORTED_l2fetch_Rs_Rtt.json | 419 --------- import/instructions/IMPORTED_l2gclean.json | 372 -------- import/instructions/IMPORTED_l2gcleaninv.json | 372 -------- import/instructions/IMPORTED_l2gunlock.json | 372 -------- import/instructions/IMPORTED_l2invidx_Rs.json | 396 -------- import/instructions/IMPORTED_l2kill.json | 372 -------- .../instructions/IMPORTED_l2tagw_Rs_Rt.json | 419 --------- .../instructions/IMPORTED_l2unlocka_Rs.json | 396 -------- .../IMPORTED_memd_locked_Rs_Pd__Rtt.json | 434 --------- .../IMPORTED_memw_locked_Rs_Pd__Rt.json | 434 --------- import/instructions/IMPORTED_nmi_Rs.json | 396 -------- import/instructions/IMPORTED_pause__u8.json | 405 --------- import/instructions/IMPORTED_resume_Rs.json | 396 -------- import/instructions/IMPORTED_rte.json | 372 -------- .../instructions/IMPORTED_setimask_Pt_Rs.json | 410 --------- .../instructions/IMPORTED_setprio_Pt_Rs.json | 410 --------- import/instructions/IMPORTED_siad_Rs.json | 396 -------- import/instructions/IMPORTED_start_Rs.json | 396 -------- import/instructions/IMPORTED_stop_Rs.json | 396 -------- import/instructions/IMPORTED_swi_Rs.json | 396 -------- import/instructions/IMPORTED_syncht.json | 372 -------- .../instructions/IMPORTED_tlbinvasid_Rs.json | 396 -------- import/instructions/IMPORTED_tlblock.json | 372 -------- import/instructions/IMPORTED_tlbunlock.json | 372 -------- import/instructions/IMPORTED_tlbw_Rss_Rt.json | 419 --------- import/instructions/IMPORTED_trace_Rs.json | 396 -------- import/instructions/IMPORTED_trap0__u8.json | 405 --------- .../instructions/IMPORTED_trap1_Rx__u8.json | 437 --------- import/instructions/IMPORTED_wait_Rs.json | 396 -------- rizin/librz/asm/arch/hexagon/hexagon.h | 2 +- rizin/librz/asm/arch/hexagon/hexagon_disas.c | 843 +++++++++--------- rizin/librz/asm/arch/hexagon/hexagon_insn.h | 100 +-- 74 files changed, 473 insertions(+), 28965 deletions(-) delete mode 100644 import/instructions/IMPORTED_Pd_l2locka_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_ctlbw_Rss_Rt.json delete mode 100644 import/instructions/IMPORTED_Rd_dctagr_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_getimask_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_iassignr_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_icdatar_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_ictagr_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_l2tagr_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_memw_locked_Rs.json delete mode 100644 import/instructions/IMPORTED_Rd_tlboc_Rss.json delete mode 100644 import/instructions/IMPORTED_Rd_tlbp_Rs.json delete mode 100644 import/instructions/IMPORTED_Rdd_memd_locked_Rs.json delete mode 100644 import/instructions/IMPORTED_Rdd_tlbr_Rs.json delete mode 100644 import/instructions/IMPORTED_barrier.json delete mode 100644 import/instructions/IMPORTED_brkpt.json delete mode 100644 import/instructions/IMPORTED_ciad_Rs.json delete mode 100644 import/instructions/IMPORTED_cswi_Rs.json delete mode 100644 import/instructions/IMPORTED_dccleana_Rs.json delete mode 100644 import/instructions/IMPORTED_dccleanidx_Rs.json delete mode 100644 import/instructions/IMPORTED_dccleaninva_Rs.json delete mode 100644 import/instructions/IMPORTED_dccleaninvidx_Rs.json delete mode 100644 import/instructions/IMPORTED_dcfetch_Rs__u11_3.json delete mode 100644 import/instructions/IMPORTED_dcinva_Rs.json delete mode 100644 import/instructions/IMPORTED_dcinvidx_Rs.json delete mode 100644 import/instructions/IMPORTED_dckill.json delete mode 100644 import/instructions/IMPORTED_dctagw_Rs_Rt.json delete mode 100644 import/instructions/IMPORTED_dczeroa_Rs.json delete mode 100644 import/instructions/IMPORTED_diag0_Rss_Rtt.json delete mode 100644 import/instructions/IMPORTED_diag1_Rss_Rtt.json delete mode 100644 import/instructions/IMPORTED_diag_Rs.json delete mode 100644 import/instructions/IMPORTED_iassignw_Rs.json delete mode 100644 import/instructions/IMPORTED_icdataw_Rs_Rt.json delete mode 100644 import/instructions/IMPORTED_icinva_Rs.json delete mode 100644 import/instructions/IMPORTED_icinvidx_Rs.json delete mode 100644 import/instructions/IMPORTED_ickill.json delete mode 100644 import/instructions/IMPORTED_ictagw_Rs_Rt.json delete mode 100644 import/instructions/IMPORTED_isync.json delete mode 100644 import/instructions/IMPORTED_k0lock.json delete mode 100644 import/instructions/IMPORTED_k0unlock.json delete mode 100644 import/instructions/IMPORTED_l2cleanidx_Rs.json delete mode 100644 import/instructions/IMPORTED_l2cleaninvidx_Rs.json delete mode 100644 import/instructions/IMPORTED_l2fetch_Rs_Rt.json delete mode 100644 import/instructions/IMPORTED_l2fetch_Rs_Rtt.json delete mode 100644 import/instructions/IMPORTED_l2gclean.json delete mode 100644 import/instructions/IMPORTED_l2gcleaninv.json delete mode 100644 import/instructions/IMPORTED_l2gunlock.json delete mode 100644 import/instructions/IMPORTED_l2invidx_Rs.json delete mode 100644 import/instructions/IMPORTED_l2kill.json delete mode 100644 import/instructions/IMPORTED_l2tagw_Rs_Rt.json delete mode 100644 import/instructions/IMPORTED_l2unlocka_Rs.json delete mode 100644 import/instructions/IMPORTED_memd_locked_Rs_Pd__Rtt.json delete mode 100644 import/instructions/IMPORTED_memw_locked_Rs_Pd__Rt.json delete mode 100644 import/instructions/IMPORTED_nmi_Rs.json delete mode 100644 import/instructions/IMPORTED_pause__u8.json delete mode 100644 import/instructions/IMPORTED_resume_Rs.json delete mode 100644 import/instructions/IMPORTED_rte.json delete mode 100644 import/instructions/IMPORTED_setimask_Pt_Rs.json delete mode 100644 import/instructions/IMPORTED_setprio_Pt_Rs.json delete mode 100644 import/instructions/IMPORTED_siad_Rs.json delete mode 100644 import/instructions/IMPORTED_start_Rs.json delete mode 100644 import/instructions/IMPORTED_stop_Rs.json delete mode 100644 import/instructions/IMPORTED_swi_Rs.json delete mode 100644 import/instructions/IMPORTED_syncht.json delete mode 100644 import/instructions/IMPORTED_tlbinvasid_Rs.json delete mode 100644 import/instructions/IMPORTED_tlblock.json delete mode 100644 import/instructions/IMPORTED_tlbunlock.json delete mode 100644 import/instructions/IMPORTED_tlbw_Rss_Rt.json delete mode 100644 import/instructions/IMPORTED_trace_Rs.json delete mode 100644 import/instructions/IMPORTED_trap0__u8.json delete mode 100644 import/instructions/IMPORTED_trap1_Rx__u8.json delete mode 100644 import/instructions/IMPORTED_wait_Rs.json diff --git a/import/instructions/IMPORTED_Pd_l2locka_Rs.json b/import/instructions/IMPORTED_Pd_l2locka_Rs.json deleted file mode 100644 index f8dbc074..00000000 --- a/import/instructions/IMPORTED_Pd_l2locka_Rs.json +++ /dev/null @@ -1,411 +0,0 @@ -{ - "IMPORTED_Pd_l2locka_Rs": { - "!anonymous": false, - "!fields": [ - "SoftFail", - "Inst" - ], - "!name": "IMPORTED_Pd_l2locka_Rs", - "!superclasses": [ - "InstructionEncoding", - "Instruction", - "InstHexagon", - "HInst", - "OpcodeHexagon", - "Enc_a51a9a" - ], - "AddedComplexity": 0, - "AsmMatchConverter": "", - "AsmString": "$Pd4 = l2locka($Rs32)", - "AsmVariantName": "", - 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0, - "isCVI": 0, - "isCVLoad": [ - 0 - ], - "isCVLoadable": [ - 0 - ], - "isCall": 0, - "isCodeGenOnly": 0, - "isCommutable": 0, - "isCompare": 0, - "isConvergent": 0, - "isConvertibleToThreeAddress": 0, - "isEHScopeReturn": 0, - "isExtendable": [ - 0 - ], - "isExtended": [ - 0 - ], - "isExtentSigned": [ - 0 - ], - "isExtractSubreg": 0, - "isFP": [ - 0 - ], - "isFloat": "false", - "isIndirectBranch": 0, - "isInsertSubreg": 0, - "isMoveImm": 0, - "isMoveReg": 0, - "isNT": "false", - "isNVStorable": [ - 0 - ], - "isNVStore": [ - 0 - ], - "isNewValue": [ - 0 - ], - "isNonTemporal": 0, - "isNotDuplicable": 0, - "isPreISelOpcode": 0, - "isPredicable": 0, - "isPredicateLate": [ - 0 - ], - "isPredicated": [ - 0 - ], - "isPredicatedFalse": [ - 0 - ], - "isPredicatedNew": [ - 0 - ], - "isPseudo": 0, - "isReMaterializable": 0, - "isRegSequence": 0, - "isRestrictNoSlot1Store": 0, - "isRestrictSlot1AOK": [ - 0 - ], - "isReturn": 0, - "isSelect": 0, - "isSolo": [ - 0 - ], - "isSoloAX": [ - 0 - ], - "isSomeOK": [ - 0 - ], - "isTaken": [ - 0 - ], - "isTerminator": 0, - "isTrap": 0, - "isUnpredicable": 0, - "mayLoad": null, - "mayRaiseFPException": 0, - "mayStore": null, - "opExtendable": [ - 0, - 0, - 0 - ], - "opExtentAlign": [ - 0, - 0 - ], - "opExtentBits": [ - 0, - 0, - 0, - 0, - 0 - ], - "opNewValue": [ - 0, - 0, - 0 - ], - "opNewValue2": [ - 0, - 0, - 0 - ], - "prefersSlot3": [ - 0 - ], - "usesCustomInserter": 0, - "variadicOpsAreDefs": 0, - "zero": [ - 0 - ] - } -} \ No newline at end of file diff --git a/rizin/librz/asm/arch/hexagon/hexagon.h b/rizin/librz/asm/arch/hexagon/hexagon.h index c8f6e7e5..d3a86376 100644 --- a/rizin/librz/asm/arch/hexagon/hexagon.h +++ b/rizin/librz/asm/arch/hexagon/hexagon.h @@ -575,7 +575,7 @@ typedef enum { #define BIT_MASK(len) (BIT(len) - 1) #define BF_MASK(start, len) (BIT_MASK(len) << (start)) -#define BF_PREP(x, start, len) (((x)&BIT_MASK(len)) << (start)) +#define BF_PREP(x, start, len) (((x) & BIT_MASK(len)) << (start)) #define BF_GET(y, start, len) (((y) >> (start)) & BIT_MASK(len)) #define BF_GETB(y, start, end) (BF_GET((y), (start), (end) - (start) + 1) diff --git a/rizin/librz/asm/arch/hexagon/hexagon_disas.c b/rizin/librz/asm/arch/hexagon/hexagon_disas.c index d72062f7..d21568a1 100644 --- a/rizin/librz/asm/arch/hexagon/hexagon_disas.c +++ b/rizin/librz/asm/arch/hexagon/hexagon_disas.c @@ -1,9 +1,9 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only -// LLVM commit: ec11388b3342a2b22eae22fd13ff4997b103d155 -// LLVM commit date: 2022-12-21 19:19:58 +0100 (ISO 8601 format) -// Date of code generation: 2022-12-21 14:35:08-05:00 +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-15 11:30:41-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -15049,6 +15049,16 @@ static const HexInsnTemplate templates_normal_0x5[] = { .type = RZ_ANALYSIS_OP_TYPE_NULL, .syntax = "pause()", }, + { + // 0101011111100000PP00000000000000 | rte + .encoding = { .mask = 0xffff3fff, .op = 0x57e00000 }, + .id = HEX_INS_J2_RTE, + .pred = HEX_NOPRED, + .cond = RZ_TYPE_COND_AL, + .type = RZ_ANALYSIS_OP_TYPE_NULL, + .syntax = "rte", + .flags = HEX_INSN_TEMPLATE_FLAG_HAS_JMP_TGT, + }, { // 0101010000000000PP0iiiii000iii00 | trap0(Ii) .encoding = { .mask = 0xffff20e3, .op = 0x54000000 }, @@ -15109,31 +15119,10 @@ static const HexInsnTemplate templates_normal_0x5[] = { .type = RZ_ANALYSIS_OP_TYPE_TRAP, .syntax = "trap1()", }, - { - // 01010110110sssssPP00000000000000 | icinva(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x56c00000 }, - .id = HEX_INS_Y2_ICINVA, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, - }, - .pred = HEX_NOPRED, - .cond = RZ_TYPE_COND_AL, - .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "icinva()", - }, - { - // 0101011111000000PP00000000000010 | isync - .encoding = { .mask = 0xffff3fff, .op = 0x57c00002 }, - .id = HEX_INS_Y2_ISYNC, - .pred = HEX_NOPRED, - .cond = RZ_TYPE_COND_AL, - .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "isync", - }, { // 01010101101sssssPP000000000ddddd | Rd = icdatar(Rs) .encoding = { .mask = 0xffe03fe0, .op = 0x55a00000 }, - .id = HEX_INS_IMPORTED_RD_ICDATAR_RS, + .id = HEX_INS_Y2_ICDATAR, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, @@ -15144,35 +15133,34 @@ static const HexInsnTemplate templates_normal_0x5[] = { .syntax = " = icdatar()", }, { - // 01010101111sssssPP000000000ddddd | Rd = ictagr(Rs) - .encoding = { .mask = 0xffe03fe0, .op = 0x55e00000 }, - .id = HEX_INS_IMPORTED_RD_ICTAGR_RS, + // 01010101110sssssPP1ttttt00000000 | icdataw(Rs,Rt) + .encoding = { .mask = 0xffe020ff, .op = 0x55c02000 }, + .id = HEX_INS_Y2_ICDATAW, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ictagr()", + .syntax = "icdataw(,)", }, { - // 01010101110sssssPP1ttttt00000000 | icdataw(Rs,Rt) - .encoding = { .mask = 0xffe020ff, .op = 0x55c02000 }, - .id = HEX_INS_IMPORTED_ICDATAW_RS_RT, + // 01010110110sssssPP00000000000000 | icinva(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x56c00000 }, + .id = HEX_INS_Y2_ICINVA, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "icdataw(,)", + .syntax = "icinva()", }, { // 01010110110sssssPP00100000000000 | icinvidx(Rs) .encoding = { .mask = 0xffe03fff, .op = 0x56c00800 }, - .id = HEX_INS_IMPORTED_ICINVIDX_RS, + .id = HEX_INS_Y2_ICINVIDX, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, @@ -15184,16 +15172,29 @@ static const HexInsnTemplate templates_normal_0x5[] = { { // 0101011011000000PP01000000000000 | ickill .encoding = { .mask = 0xffff3fff, .op = 0x56c01000 }, - .id = HEX_INS_IMPORTED_ICKILL, + .id = HEX_INS_Y2_ICKILL, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, .syntax = "ickill", }, + { + // 01010101111sssssPP000000000ddddd | Rd = ictagr(Rs) + .encoding = { .mask = 0xffe03fe0, .op = 0x55e00000 }, + .id = HEX_INS_Y2_ICTAGR, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + }, + .pred = HEX_NOPRED, + .cond = RZ_TYPE_COND_AL, + .type = RZ_ANALYSIS_OP_TYPE_NULL, + .syntax = " = ictagr()", + }, { // 01010101110sssssPP0ttttt00000000 | ictagw(Rs,Rt) .encoding = { .mask = 0xffe020ff, .op = 0x55c00000 }, - .id = HEX_INS_IMPORTED_ICTAGW_RS_RT, + .id = HEX_INS_Y2_ICTAGW, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, @@ -15204,13 +15205,13 @@ static const HexInsnTemplate templates_normal_0x5[] = { .syntax = "ictagw(,)", }, { - // 0101011111100000PP00000000000000 | rte - .encoding = { .mask = 0xffff3fff, .op = 0x57e00000 }, - .id = HEX_INS_IMPORTED_RTE, + // 0101011111000000PP00000000000010 | isync + .encoding = { .mask = 0xffff3fff, .op = 0x57c00002 }, + .id = HEX_INS_Y2_ISYNC, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "rte", + .syntax = "isync", }, { { 0 } }, }; @@ -15852,225 +15853,210 @@ static const HexInsnTemplate templates_normal_0x6[] = { .syntax = "brkpt", }, { - // 01100101000xxxxxPP00000000000000 | crswap(Rx,sgp0) - .encoding = { .mask = 0xffe03fff, .op = 0x65000000 }, - .id = HEX_INS_Y2_CRSWAP0, + // 01100100000sssssPP00000001100000 | ciad(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64000060 }, + .id = HEX_INS_Y2_CIAD, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "crswap(,SGP0)", + .syntax = "ciad()", }, { - // 011011101sssssssPP000000000ddddd | Rd = Ss - .encoding = { .mask = 0xff803fe0, .op = 0x6e800000 }, - .id = HEX_INS_Y2_TFRSCRR, + // 01100101000xxxxxPP00000000000000 | crswap(Rx,sgp0) + .encoding = { .mask = 0xffe03fff, .op = 0x65000000 }, + .id = HEX_INS_Y2_CRSWAP0, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 3 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "crswap(,SGP0)", }, { - // 01100111000sssssPP0000000ddddddd | Sd = Rs - .encoding = { .mask = 0xffe03f80, .op = 0x67000000 }, - .id = HEX_INS_Y2_TFRSRCR, + // 01100100000sssssPP00000000100000 | cswi(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64000020 }, + .id = HEX_INS_Y2_CSWI, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 3 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "CSwi()", }, { - // 01100100010sssssPP00000000000000 | wait(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64400000 }, - .id = HEX_INS_Y2_WAIT, + // 01100110000sssssPP000000000ddddd | Rd = getimask(Rs) + .encoding = { .mask = 0xffe03fe0, .op = 0x66000000 }, + .id = HEX_INS_Y2_GETIMASK, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 12 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "wait()", + .syntax = " = getimask()", }, { - // 01100101001xxxxxPP00000000000000 | crswap(Rx,sgp1) - .encoding = { .mask = 0xffe03fff, .op = 0x65200000 }, - .id = HEX_INS_Y4_CRSWAP1, + // 01100110011sssssPP000000000ddddd | Rd = iassignr(Rs) + .encoding = { .mask = 0xffe03fe0, .op = 0x66600000 }, + .id = HEX_INS_Y2_IASSIGNR, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 12 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "crswap(,SGP1)", + .syntax = " = iassignr()", }, { - // 01101101100xxxxxPP00000000000000 | crswap(Rxx,sgp1:0) - .encoding = { .mask = 0xffe03fff, .op = 0x6d800000 }, - .id = HEX_INS_Y4_CRSWAP10, + // 01100100000sssssPP00000001000000 | iassignw(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64000040 }, + .id = HEX_INS_Y2_IASSIGNW, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "crswap(,SGP1:0)", + .syntax = "iassignw()", }, { - // 011011110sssssssPP000000000ddddd | Rdd = Sss - .encoding = { .mask = 0xff803fe0, .op = 0x6f000000 }, - .id = HEX_INS_Y4_TFRSCPP, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 3 }, - }, + // 0110110000100000PP00000001100000 | k0lock + .encoding = { .mask = 0xffff3fff, .op = 0x6c200060 }, + .id = HEX_INS_Y2_K0LOCK, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "k0lock", }, { - // 01101101000sssssPP0000000ddddddd | Sdd = Rss - .encoding = { .mask = 0xffe03f80, .op = 0x6d000000 }, - .id = HEX_INS_Y4_TFRSPCP, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 3 }, - }, + // 0110110000100000PP00000010000000 | k0unlock + .encoding = { .mask = 0xffff3fff, .op = 0x6c200080 }, + .id = HEX_INS_Y2_K0UNLOCK, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "k0unlock", }, { - // 01100010010sssssPP00000000000000 | trace(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x62400000 }, - .id = HEX_INS_Y4_TRACE, + // 01100100010sssssPP00000000100000 | resume(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64400020 }, + .id = HEX_INS_Y2_RESUME, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 6 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "trace()", + .syntax = "resume()", }, { - // 01100010010sssssPP00000000100000 | diag(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x62400020 }, - .id = HEX_INS_Y6_DIAG, + // 01100100100sssssPP0000tt00000000 | setimask(Pt,Rs) + .encoding = { .mask = 0xffe03cff, .op = 0x64800000 }, + .id = HEX_INS_Y2_SETIMASK, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x2, 8 } }, .reg_cls = HEX_REG_CLASS_PRED_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "DIAG()", + .syntax = "setimask(,)", }, { - // 01100010010sssssPP0ttttt01000000 | diag0(Rss,Rtt) - .encoding = { .mask = 0xffe020ff, .op = 0x62400040 }, - .id = HEX_INS_Y6_DIAG0, + // 01100100100sssssPP0000tt00100000 | setprio(Pt,Rs) + .encoding = { .mask = 0xffe03cff, .op = 0x64800020 }, + .id = HEX_INS_Y2_SETPRIO, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 6 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x2, 8 } }, .reg_cls = HEX_REG_CLASS_PRED_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "DIAG0(,)", + .syntax = "setprio(,)", }, { - // 01100010010sssssPP0ttttt01100000 | diag1(Rss,Rtt) - .encoding = { .mask = 0xffe020ff, .op = 0x62400060 }, - .id = HEX_INS_Y6_DIAG1, + // 01100100011sssssPP00000000100000 | start(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64600020 }, + .id = HEX_INS_Y2_START, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 6 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 6 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "DIAG1(,)", + .syntax = "start()", }, { - // 011011101sssssssPP000000000ddddd | Rd = Ss - .encoding = { .mask = 0xff803fe0, .op = 0x6e800000 }, - .id = HEX_INS_IMPORTED_RD_SS, + // 01100100011sssssPP00000000000000 | stop(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64600000 }, + .id = HEX_INS_Y2_STOP, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 3 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "stop()", }, { - // 01101100110sssssPP0ttttt000ddddd | Rd = ctlbw(Rss,Rt) - .encoding = { .mask = 0xffe020e0, .op = 0x6cc00000 }, - .id = HEX_INS_IMPORTED_RD_CTLBW_RSS_RT, + // 01100100000sssssPP00000000000000 | swi(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64000000 }, + .id = HEX_INS_Y2_SWI, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 4 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ctlbw(,)", + .syntax = "swi()", }, { - // 01100110000sssssPP000000000ddddd | Rd = getimask(Rs) - .encoding = { .mask = 0xffe03fe0, .op = 0x66000000 }, - .id = HEX_INS_IMPORTED_RD_GETIMASK_RS, + // 011011101sssssssPP000000000ddddd | Rd = Ss + .encoding = { .mask = 0xff803fe0, .op = 0x6e800000 }, + .id = HEX_INS_Y2_TFRSCRR, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 12 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 3 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = getimask()", + .syntax = " = ", }, { - // 01100110011sssssPP000000000ddddd | Rd = iassignr(Rs) - .encoding = { .mask = 0xffe03fe0, .op = 0x66600000 }, - .id = HEX_INS_IMPORTED_RD_IASSIGNR_RS, + // 01100111000sssssPP0000000ddddddd | Sd = Rs + .encoding = { .mask = 0xffe03f80, .op = 0x67000000 }, + .id = HEX_INS_Y2_TFRSRCR, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 12 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 3 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = iassignr()", + .syntax = " = ", }, { - // 01101100111sssssPP000000000ddddd | Rd = tlboc(Rss) - .encoding = { .mask = 0xffe03fe0, .op = 0x6ce00000 }, - .id = HEX_INS_IMPORTED_RD_TLBOC_RSS, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, - }, + // 0110110000100000PP00000000100000 | tlblock + .encoding = { .mask = 0xffff3fff, .op = 0x6c200020 }, + .id = HEX_INS_Y2_TLBLOCK, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = tlboc()", + .syntax = "tlblock", }, { // 01101100100sssssPP000000000ddddd | Rd = tlbp(Rs) .encoding = { .mask = 0xffe03fe0, .op = 0x6c800000 }, - .id = HEX_INS_IMPORTED_RD_TLBP_RS, + .id = HEX_INS_Y2_TLBP, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, @@ -16080,23 +16066,10 @@ static const HexInsnTemplate templates_normal_0x6[] = { .type = RZ_ANALYSIS_OP_TYPE_NULL, .syntax = " = tlbp()", }, - { - // 011011110sssssssPP000000000ddddd | Rdd = Sss - .encoding = { .mask = 0xff803fe0, .op = 0x6f000000 }, - .id = HEX_INS_IMPORTED_RDD_SSS, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 3 }, - }, - .pred = HEX_NOPRED, - .cond = RZ_TYPE_COND_AL, - .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", - }, { // 01101100010sssssPP000000000ddddd | Rdd = tlbr(Rs) .encoding = { .mask = 0xffe03fe0, .op = 0x6c400000 }, - .id = HEX_INS_IMPORTED_RDD_TLBR_RS, + .id = HEX_INS_Y2_TLBR, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 0 }, { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, @@ -16107,225 +16080,253 @@ static const HexInsnTemplate templates_normal_0x6[] = { .syntax = " = tlbr()", }, { - // 01100111000sssssPP0000000ddddddd | Sd = Rs - .encoding = { .mask = 0xffe03f80, .op = 0x67000000 }, - .id = HEX_INS_IMPORTED_SD_RS, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 3 }, - }, + // 0110110000100000PP00000001000000 | tlbunlock + .encoding = { .mask = 0xffff3fff, .op = 0x6c200040 }, + .id = HEX_INS_Y2_TLBUNLOCK, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "tlbunlock", }, { - // 0110110100-sssssPP-------ddddddd | Sdd = Rss - .encoding = { .mask = 0xffc00000, .op = 0x6d000000 }, - .id = HEX_INS_IMPORTED_SDD_RSS, + // 01101100000sssssPP0ttttt00000000 | tlbw(Rss,Rt) + .encoding = { .mask = 0xffe020ff, .op = 0x6c000000 }, + .id = HEX_INS_Y2_TLBW, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 3 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 5 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 6 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = ", + .syntax = "tlbw(,)", }, { - // 01100100000sssssPP00000001100000 | ciad(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64000060 }, - .id = HEX_INS_IMPORTED_CIAD_RS, + // 01100100010sssssPP00000000000000 | wait(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64400000 }, + .id = HEX_INS_Y2_WAIT, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "ciad()", + .syntax = "wait()", }, { - // 01100100000sssssPP00000000100000 | cswi(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64000020 }, - .id = HEX_INS_IMPORTED_CSWI_RS, + // 01100101001xxxxxPP00000000000000 | crswap(Rx,sgp1) + .encoding = { .mask = 0xffe03fff, .op = 0x65200000 }, + .id = HEX_INS_Y4_CRSWAP1, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "CSwi()", + .syntax = "crswap(,SGP1)", }, { - // 01100100000sssssPP00000001000000 | iassignw(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64000040 }, - .id = HEX_INS_IMPORTED_IASSIGNW_RS, + // 01101101100xxxxxPP00000000000000 | crswap(Rxx,sgp1:0) + .encoding = { .mask = 0xffe03fff, .op = 0x6d800000 }, + .id = HEX_INS_Y4_CRSWAP10, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "iassignw()", + .syntax = "crswap(,SGP1:0)", }, { - // 0110110000100000PP00000001100000 | k0lock - .encoding = { .mask = 0xffff3fff, .op = 0x6c200060 }, - .id = HEX_INS_IMPORTED_K0LOCK, + // 01100100011sssssPP00000001000000 | nmi(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64600040 }, + .id = HEX_INS_Y4_NMI, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 4 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "k0lock", + .syntax = "nmi()", }, { - // 0110110000100000PP00000010000000 | k0unlock - .encoding = { .mask = 0xffff3fff, .op = 0x6c200080 }, - .id = HEX_INS_IMPORTED_K0UNLOCK, + // 01100100100sssssPP00000001100000 | siad(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x64800060 }, + .id = HEX_INS_Y4_SIAD, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "k0unlock", + .syntax = "siad()", }, { - // 01100100011sssssPP00000001000000 | nmi(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64600040 }, - .id = HEX_INS_IMPORTED_NMI_RS, + // 011011110sssssssPP000000000ddddd | Rdd = Sss + .encoding = { .mask = 0xff803fe0, .op = 0x6f000000 }, + .id = HEX_INS_Y4_TFRSCPP, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 4 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 3 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "nmi()", + .syntax = " = ", }, { - // 01100100010sssssPP00000000100000 | resume(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64400020 }, - .id = HEX_INS_IMPORTED_RESUME_RS, + // 01101101000sssssPP0000000ddddddd | Sdd = Rss + .encoding = { .mask = 0xffe03f80, .op = 0x6d000000 }, + .id = HEX_INS_Y4_TFRSPCP, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 3 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "resume()", + .syntax = " = ", }, { - // 01100100100sssssPP0000tt00000000 | setimask(Pt,Rs) - .encoding = { .mask = 0xffe03cff, .op = 0x64800000 }, - .id = HEX_INS_IMPORTED_SETIMASK_PT_RS, + // 01100010010sssssPP00000000000000 | trace(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x62400000 }, + .id = HEX_INS_Y4_TRACE, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x2, 8 } }, .reg_cls = HEX_REG_CLASS_PRED_REGS, .syntax = 9 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 6 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "setimask(,)", + .syntax = "trace()", }, { - // 01100100100sssssPP0000tt00100000 | setprio(Pt,Rs) - .encoding = { .mask = 0xffe03cff, .op = 0x64800020 }, - .id = HEX_INS_IMPORTED_SETPRIO_PT_RS, + // 01101100110sssssPP0ttttt000ddddd | Rd = ctlbw(Rss,Rt) + .encoding = { .mask = 0xffe020e0, .op = 0x6cc00000 }, + .id = HEX_INS_Y5_CTLBW, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x2, 8 } }, .reg_cls = HEX_REG_CLASS_PRED_REGS, .syntax = 8 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "setprio(,)", + .syntax = " = ctlbw(,)", }, { - // 01100100100sssssPP00000001100000 | siad(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64800060 }, - .id = HEX_INS_IMPORTED_SIAD_RS, + // 01101100101sssssPP00000000000000 | tlbinvasid(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x6ca00000 }, + .id = HEX_INS_Y5_TLBASIDI, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "siad()", + .syntax = "tlbinvasid()", }, { - // 01100100011sssssPP00000000100000 | start(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64600020 }, - .id = HEX_INS_IMPORTED_START_RS, + // 01101100111sssssPP000000000ddddd | Rd = tlboc(Rss) + .encoding = { .mask = 0xffe03fe0, .op = 0x6ce00000 }, + .id = HEX_INS_Y5_TLBOC, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 6 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "start()", + .syntax = " = tlboc()", }, { - // 01100100011sssssPP00000000000000 | stop(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64600000 }, - .id = HEX_INS_IMPORTED_STOP_RS, + // 01100010010sssssPP00000000100000 | diag(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0x62400020 }, + .id = HEX_INS_Y6_DIAG, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 5 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "stop()", + .syntax = "DIAG()", }, { - // 01100100000sssssPP00000000000000 | swi(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x64000000 }, - .id = HEX_INS_IMPORTED_SWI_RS, + // 01100010010sssssPP0ttttt01000000 | diag0(Rss,Rtt) + .encoding = { .mask = 0xffe020ff, .op = 0x62400040 }, + .id = HEX_INS_Y6_DIAG0, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 4 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 6 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "swi()", + .syntax = "DIAG0(,)", }, { - // 01101100101sssssPP00000000000000 | tlbinvasid(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0x6ca00000 }, - .id = HEX_INS_IMPORTED_TLBINVASID_RS, + // 01100010010sssssPP0ttttt01100000 | diag1(Rss,Rtt) + .encoding = { .mask = 0xffe020ff, .op = 0x62400060 }, + .id = HEX_INS_Y6_DIAG1, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 6 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "tlbinvasid()", + .syntax = "DIAG1(,)", }, { - // 0110110000100000PP00000000100000 | tlblock - .encoding = { .mask = 0xffff3fff, .op = 0x6c200020 }, - .id = HEX_INS_IMPORTED_TLBLOCK, + // 011011101sssssssPP000000000ddddd | Rd = Ss + .encoding = { .mask = 0xff803fe0, .op = 0x6e800000 }, + .id = HEX_INS_IMPORTED_RD_SS, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 3 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "tlblock", + .syntax = " = ", }, { - // 0110110000100000PP00000001000000 | tlbunlock - .encoding = { .mask = 0xffff3fff, .op = 0x6c200040 }, - .id = HEX_INS_IMPORTED_TLBUNLOCK, + // 011011110sssssssPP000000000ddddd | Rdd = Sss + .encoding = { .mask = 0xff803fe0, .op = 0x6f000000 }, + .id = HEX_INS_IMPORTED_RDD_SSS, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 16 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 3 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "tlbunlock", + .syntax = " = ", }, { - // 01101100000sssssPP0ttttt00000000 | tlbw(Rss,Rt) - .encoding = { .mask = 0xffe020ff, .op = 0x6c000000 }, - .id = HEX_INS_IMPORTED_TLBW_RSS_RT, + // 01100111000sssssPP0000000ddddddd | Sd = Rs + .encoding = { .mask = 0xffe03f80, .op = 0x67000000 }, + .id = HEX_INS_IMPORTED_SD_RS, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 5 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 6 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 3 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "tlbw(,)", + .syntax = " = ", + }, + { + // 0110110100-sssssPP-------ddddddd | Sdd = Rss + .encoding = { .mask = 0xffc00000, .op = 0x6d000000 }, + .id = HEX_INS_IMPORTED_SDD_RSS, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x7, 0 } }, .reg_cls = HEX_REG_CLASS_SYS_REGS64, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 3 }, + }, + .pred = HEX_NOPRED, + .cond = RZ_TYPE_COND_AL, + .type = RZ_ANALYSIS_OP_TYPE_NULL, + .syntax = " = ", }, { { 0 } }, }; @@ -23973,179 +23974,159 @@ static const HexInsnTemplate templates_normal_0xa[] = { .syntax = "dccleana()", }, { - // 10100000010sssssPP00000000000000 | dccleaninva(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa0400000 }, - .id = HEX_INS_Y2_DCCLEANINVA, + // 10100010001sssssPP00000000000000 | dccleanidx(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa2200000 }, + .id = HEX_INS_Y2_DCCLEANIDX, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 12 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dccleaninva()", + .syntax = "dccleanidx()", }, { - // 10100000001sssssPP00000000000000 | dcinva(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa0200000 }, - .id = HEX_INS_Y2_DCINVA, + // 10100000010sssssPP00000000000000 | dccleaninva(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa0400000 }, + .id = HEX_INS_Y2_DCCLEANINVA, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 12 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dcinva()", + .syntax = "dccleaninva()", }, { - // 10100000110sssssPP00000000000000 | dczeroa(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa0c00000 }, - .id = HEX_INS_Y2_DCZEROA, + // 10100010011sssssPP00000000000000 | dccleaninvidx(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa2600000 }, + .id = HEX_INS_Y2_DCCLEANINVIDX, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 14 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dczeroa()", - }, - { - // 1010100001000000PP00000000000000 | syncht - .encoding = { .mask = 0xffff3fff, .op = 0xa8400000 }, - .id = HEX_INS_Y2_SYNCHT, - .pred = HEX_NOPRED, - .cond = RZ_TYPE_COND_AL, - .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "syncht", + .syntax = "dccleaninvidx()", }, { - // 10100110000sssssPP0ttttt00000000 | l2fetch(Rs,Rt) - .encoding = { .mask = 0xffe020ff, .op = 0xa6000000 }, - .id = HEX_INS_Y4_L2FETCH, + // 10100000001sssssPP00000000000000 | dcinva(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa0200000 }, + .id = HEX_INS_Y2_DCINVA, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2fetch(,)", + .syntax = "dcinva()", }, { - // 10100110100sssssPP0ttttt00000000 | l2fetch(Rs,Rtt) - .encoding = { .mask = 0xffe020ff, .op = 0xa6800000 }, - .id = HEX_INS_Y5_L2FETCH, + // 10100010010sssssPP00000000000000 | dcinvidx(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa2400000 }, + .id = HEX_INS_Y2_DCINVIDX, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2fetch(,)", + .syntax = "dcinvidx()", }, { - // 10100110000sssssPP0ttttt01000000 | dmlink(Rs,Rt) - .encoding = { .mask = 0xffe020ff, .op = 0xa6000040 }, - .id = HEX_INS_Y6_DMLINK, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, - }, + // 1010001000000000PP00000000000000 | dckill + .encoding = { .mask = 0xffff3fff, .op = 0xa2000000 }, + .id = HEX_INS_Y2_DCKILL, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dmlink(,)", + .syntax = "dckill", }, { - // 1010100000000000PP000000011ddddd | Rd = dmpause - .encoding = { .mask = 0xffff3fe0, .op = 0xa8000060 }, - .id = HEX_INS_Y6_DMPAUSE, + // 10100100001sssssPP000000000ddddd | Rd = dctagr(Rs) + .encoding = { .mask = 0xffe03fe0, .op = 0xa4200000 }, + .id = HEX_INS_Y2_DCTAGR, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = dmpause", + .syntax = " = dctagr()", }, { - // 1010100000000000PP000000010ddddd | Rd = dmpoll - .encoding = { .mask = 0xffff3fe0, .op = 0xa8000040 }, - .id = HEX_INS_Y6_DMPOLL, + // 10100100000sssssPP0ttttt00000000 | dctagw(Rs,Rt) + .encoding = { .mask = 0xffe020ff, .op = 0xa4000000 }, + .id = HEX_INS_Y2_DCTAGW, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = dmpoll", + .syntax = "dctagw(,)", }, { - // 10100110000sssssPP00000010000000 | dmresume(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa6000080 }, - .id = HEX_INS_Y6_DMRESUME, + // 10100000110sssssPP00000000000000 | dczeroa(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa0c00000 }, + .id = HEX_INS_Y2_DCZEROA, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dmresume()", + .syntax = "dczeroa()", }, { - // 10100110000sssssPP00000000100000 | dmstart(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa6000020 }, - .id = HEX_INS_Y6_DMSTART, + // 10101000011sssssPP00000000000000 | l2cleaninvidx(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa8600000 }, + .id = HEX_INS_Y2_L2CLEANINVIDX, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 14 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dmstart()", + .syntax = "l2cleaninvidx()", }, { - // 1010100000000000PP000000001ddddd | Rd = dmwait - .encoding = { .mask = 0xffff3fe0, .op = 0xa8000020 }, - .id = HEX_INS_Y6_DMWAIT, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - }, + // 1010100000100000PP00000000000000 | l2kill + .encoding = { .mask = 0xffff3fff, .op = 0xa8200000 }, + .id = HEX_INS_Y2_L2KILL, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = dmwait", + .syntax = "l2kill", }, { - // 10100000111sssssPP100000000000dd | Pd = l2locka(Rs) - .encoding = { .mask = 0xffe03ffc, .op = 0xa0e02000 }, - .id = HEX_INS_IMPORTED_PD_L2LOCKA_RS, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x2, 0 } }, .reg_cls = HEX_REG_CLASS_PRED_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, - }, + // 1010100001000000PP00000000000000 | syncht + .encoding = { .mask = 0xffff3fff, .op = 0xa8400000 }, + .id = HEX_INS_Y2_SYNCHT, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = l2locka()", + .syntax = "syncht", }, { - // 10100100001sssssPP000000000ddddd | Rd = dctagr(Rs) - .encoding = { .mask = 0xffe03fe0, .op = 0xa4200000 }, - .id = HEX_INS_IMPORTED_RD_DCTAGR_RS, + // 10100110000sssssPP0ttttt00000000 | l2fetch(Rs,Rt) + .encoding = { .mask = 0xffe020ff, .op = 0xa6000000 }, + .id = HEX_INS_Y4_L2FETCH, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = " = dctagr()", + .syntax = "l2fetch(,)", }, { // 10100100011sssssPP000000000ddddd | Rd = l2tagr(Rs) .encoding = { .mask = 0xffe03fe0, .op = 0xa4600000 }, - .id = HEX_INS_IMPORTED_RD_L2TAGR_RS, + .id = HEX_INS_Y4_L2TAGR, .ops = { { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, @@ -24156,183 +24137,203 @@ static const HexInsnTemplate templates_normal_0xa[] = { .syntax = " = l2tagr()", }, { - // 10100010001sssssPP00000000000000 | dccleanidx(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa2200000 }, - .id = HEX_INS_IMPORTED_DCCLEANIDX_RS, + // 10100100010sssssPP0ttttt00000000 | l2tagw(Rs,Rt) + .encoding = { .mask = 0xffe020ff, .op = 0xa4400000 }, + .id = HEX_INS_Y4_L2TAGW, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dccleanidx()", + .syntax = "l2tagw(,)", }, { - // 10100010011sssssPP00000000000000 | dccleaninvidx(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa2600000 }, - .id = HEX_INS_IMPORTED_DCCLEANINVIDX_RS, + // 10100110001sssssPP00000000000000 | l2cleanidx(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa6200000 }, + .id = HEX_INS_Y5_L2CLEANIDX, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 14 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dccleaninvidx()", + .syntax = "l2cleanidx()", }, { - // 10100010010sssssPP00000000000000 | dcinvidx(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa2400000 }, - .id = HEX_INS_IMPORTED_DCINVIDX_RS, + // 10100110100sssssPP0ttttt00000000 | l2fetch(Rs,Rtt) + .encoding = { .mask = 0xffe020ff, .op = 0xa6800000 }, + .id = HEX_INS_Y5_L2FETCH, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dcinvidx()", + .syntax = "l2fetch(,)", }, { - // 1010001000000000PP00000000000000 | dckill - .encoding = { .mask = 0xffff3fff, .op = 0xa2000000 }, - .id = HEX_INS_IMPORTED_DCKILL, + // 1010100000100000PP01000000000000 | l2gclean + .encoding = { .mask = 0xffff3fff, .op = 0xa8201000 }, + .id = HEX_INS_Y5_L2GCLEAN, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dckill", + .syntax = "l2gclean", }, { - // 10100100000sssssPP0ttttt00000000 | dctagw(Rs,Rt) - .encoding = { .mask = 0xffe020ff, .op = 0xa4000000 }, - .id = HEX_INS_IMPORTED_DCTAGW_RS_RT, - .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, - }, + // 1010100000100000PP01100000000000 | l2gcleaninv + .encoding = { .mask = 0xffff3fff, .op = 0xa8201800 }, + .id = HEX_INS_Y5_L2GCLEANINV, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "dctagw(,)", + .syntax = "l2gcleaninv", }, { - // 10100110001sssssPP00000000000000 | l2cleanidx(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa6200000 }, - .id = HEX_INS_IMPORTED_L2CLEANIDX_RS, + // 1010100000100000PP00100000000000 | l2gunlock + .encoding = { .mask = 0xffff3fff, .op = 0xa8200800 }, + .id = HEX_INS_Y5_L2GUNLOCK, + .pred = HEX_NOPRED, + .cond = RZ_TYPE_COND_AL, + .type = RZ_ANALYSIS_OP_TYPE_NULL, + .syntax = "l2gunlock", + }, + { + // 10100110010sssssPP00000000000000 | l2invidx(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa6400000 }, + .id = HEX_INS_Y5_L2INVIDX, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2cleanidx()", + .syntax = "l2invidx()", }, { - // 10101000011sssssPP00000000000000 | l2cleaninvidx(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa8600000 }, - .id = HEX_INS_IMPORTED_L2CLEANINVIDX_RS, + // 10100000111sssssPP100000000000dd | Pd = l2locka(Rs) + .encoding = { .mask = 0xffe03ffc, .op = 0xa0e02000 }, + .id = HEX_INS_Y5_L2LOCKA, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 14 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x2, 0 } }, .reg_cls = HEX_REG_CLASS_PRED_REGS, .syntax = 0 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 11 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2cleaninvidx()", + .syntax = " = l2locka()", }, { - // 1010100000100000PP01000000000000 | l2gclean - .encoding = { .mask = 0xffff3fff, .op = 0xa8201000 }, - .id = HEX_INS_IMPORTED_L2GCLEAN, + // 10100110011sssssPP00000000000000 | l2unlocka(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa6600000 }, + .id = HEX_INS_Y5_L2UNLOCKA, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2gclean", + .syntax = "l2unlocka()", }, { - // 1010011010100000PP0ttttt00000000 | l2gclean(Rtt) - .encoding = { .mask = 0xffff20ff, .op = 0xa6a00000 }, - .id = HEX_INS_IMPORTED_L2GCLEAN_RTT, + // 10100110000sssssPP0ttttt01000000 | dmlink(Rs,Rt) + .encoding = { .mask = 0xffe020ff, .op = 0xa6000040 }, + .id = HEX_INS_Y6_DMLINK, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2gclean()", + .syntax = "dmlink(,)", }, { - // 1010100000100000PP01100000000000 | l2gcleaninv - .encoding = { .mask = 0xffff3fff, .op = 0xa8201800 }, - .id = HEX_INS_IMPORTED_L2GCLEANINV, + // 1010100000000000PP000000011ddddd | Rd = dmpause + .encoding = { .mask = 0xffff3fe0, .op = 0xa8000060 }, + .id = HEX_INS_Y6_DMPAUSE, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2gcleaninv", + .syntax = " = dmpause", }, { - // 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt) - .encoding = { .mask = 0xffff20ff, .op = 0xa6c00000 }, - .id = HEX_INS_IMPORTED_L2GCLEANINV_RTT, + // 1010100000000000PP000000010ddddd | Rd = dmpoll + .encoding = { .mask = 0xffff3fe0, .op = 0xa8000040 }, + .id = HEX_INS_Y6_DMPOLL, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 12 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2gcleaninv()", + .syntax = " = dmpoll", }, { - // 1010100000100000PP00100000000000 | l2gunlock - .encoding = { .mask = 0xffff3fff, .op = 0xa8200800 }, - .id = HEX_INS_IMPORTED_L2GUNLOCK, + // 10100110000sssssPP00000010000000 | dmresume(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa6000080 }, + .id = HEX_INS_Y6_DMRESUME, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2gunlock", + .syntax = "dmresume()", }, { - // 10100110010sssssPP00000000000000 | l2invidx(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa6400000 }, - .id = HEX_INS_IMPORTED_L2INVIDX_RS, + // 10100110000sssssPP00000000100000 | dmstart(Rs) + .encoding = { .mask = 0xffe03fff, .op = 0xa6000020 }, + .id = HEX_INS_Y6_DMSTART, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 9 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2invidx()", + .syntax = "dmstart()", }, { - // 1010100000100000PP00000000000000 | l2kill - .encoding = { .mask = 0xffff3fff, .op = 0xa8200000 }, - .id = HEX_INS_IMPORTED_L2KILL, + // 1010100000000000PP000000001ddddd | Rd = dmwait + .encoding = { .mask = 0xffff3fe0, .op = 0xa8000020 }, + .id = HEX_INS_Y6_DMWAIT, + .ops = { + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_OUT, .masks = { { 0x5, 0 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 0 }, + }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2kill", + .syntax = " = dmwait", }, { - // 10100100010sssssPP0ttttt00000000 | l2tagw(Rs,Rt) - .encoding = { .mask = 0xffe020ff, .op = 0xa4400000 }, - .id = HEX_INS_IMPORTED_L2TAGW_RS_RT, + // 1010011010100000PP0ttttt00000000 | l2gclean(Rtt) + .encoding = { .mask = 0xffff20ff, .op = 0xa6a00000 }, + .id = HEX_INS_IMPORTED_L2GCLEAN_RTT, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 7 }, - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 8 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 9 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2tagw(,)", + .syntax = "l2gclean()", }, { - // 10100110011sssssPP00000000000000 | l2unlocka(Rs) - .encoding = { .mask = 0xffe03fff, .op = 0xa6600000 }, - .id = HEX_INS_IMPORTED_L2UNLOCKA_RS, + // 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt) + .encoding = { .mask = 0xffff20ff, .op = 0xa6c00000 }, + .id = HEX_INS_IMPORTED_L2GCLEANINV_RTT, .ops = { - { .info = HEX_OP_TEMPLATE_TYPE_REG, .masks = { { 0x5, 16 } }, .reg_cls = HEX_REG_CLASS_INT_REGS, .syntax = 10 }, + { .info = HEX_OP_TEMPLATE_TYPE_REG | HEX_OP_TEMPLATE_FLAG_REG_PAIR, .masks = { { 0x5, 8 } }, .reg_cls = HEX_REG_CLASS_DOUBLE_REGS, .syntax = 12 }, }, .pred = HEX_NOPRED, .cond = RZ_TYPE_COND_AL, .type = RZ_ANALYSIS_OP_TYPE_NULL, - .syntax = "l2unlocka()", + .syntax = "l2gcleaninv()", }, { { 0 } }, }; diff --git a/rizin/librz/asm/arch/hexagon/hexagon_insn.h b/rizin/librz/asm/arch/hexagon/hexagon_insn.h index e797527e..eb8e49bf 100644 --- a/rizin/librz/asm/arch/hexagon/hexagon_insn.h +++ b/rizin/librz/asm/arch/hexagon/hexagon_insn.h @@ -1,9 +1,9 @@ // SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only -// LLVM commit: ec11388b3342a2b22eae22fd13ff4997b103d155 -// LLVM commit date: 2022-12-21 19:19:58 +0100 (ISO 8601 format) -// Date of code generation: 2022-12-21 14:19:00-05:00 +// LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c +// LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format) +// Date of code generation: 2023-11-15 11:30:41-05:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -451,6 +451,7 @@ typedef enum { HEX_INS_J2_PLOOP2SR, HEX_INS_J2_PLOOP3SI, HEX_INS_J2_PLOOP3SR, + HEX_INS_J2_RTE, HEX_INS_J2_TRAP0, HEX_INS_J2_TRAP1, HEX_INS_J2_UNPAUSE, @@ -2266,25 +2267,71 @@ typedef enum { HEX_INS_V6_ZEXTRACT, HEX_INS_Y2_BARRIER, HEX_INS_Y2_BREAK, + HEX_INS_Y2_CIAD, HEX_INS_Y2_CRSWAP0, + HEX_INS_Y2_CSWI, HEX_INS_Y2_DCCLEANA, + HEX_INS_Y2_DCCLEANIDX, HEX_INS_Y2_DCCLEANINVA, + HEX_INS_Y2_DCCLEANINVIDX, HEX_INS_Y2_DCFETCHBO, HEX_INS_Y2_DCINVA, + HEX_INS_Y2_DCINVIDX, + HEX_INS_Y2_DCKILL, + HEX_INS_Y2_DCTAGR, + HEX_INS_Y2_DCTAGW, HEX_INS_Y2_DCZEROA, + HEX_INS_Y2_GETIMASK, + HEX_INS_Y2_IASSIGNR, + HEX_INS_Y2_IASSIGNW, + HEX_INS_Y2_ICDATAR, + HEX_INS_Y2_ICDATAW, HEX_INS_Y2_ICINVA, + HEX_INS_Y2_ICINVIDX, + HEX_INS_Y2_ICKILL, + HEX_INS_Y2_ICTAGR, + HEX_INS_Y2_ICTAGW, HEX_INS_Y2_ISYNC, + HEX_INS_Y2_K0LOCK, + HEX_INS_Y2_K0UNLOCK, + HEX_INS_Y2_L2CLEANINVIDX, + HEX_INS_Y2_L2KILL, + HEX_INS_Y2_RESUME, + HEX_INS_Y2_SETIMASK, + HEX_INS_Y2_SETPRIO, + HEX_INS_Y2_START, + HEX_INS_Y2_STOP, + HEX_INS_Y2_SWI, HEX_INS_Y2_SYNCHT, HEX_INS_Y2_TFRSCRR, HEX_INS_Y2_TFRSRCR, + HEX_INS_Y2_TLBLOCK, + HEX_INS_Y2_TLBP, + HEX_INS_Y2_TLBR, + HEX_INS_Y2_TLBUNLOCK, + HEX_INS_Y2_TLBW, HEX_INS_Y2_WAIT, HEX_INS_Y4_CRSWAP1, HEX_INS_Y4_CRSWAP10, HEX_INS_Y4_L2FETCH, + HEX_INS_Y4_L2TAGR, + HEX_INS_Y4_L2TAGW, + HEX_INS_Y4_NMI, + HEX_INS_Y4_SIAD, HEX_INS_Y4_TFRSCPP, HEX_INS_Y4_TFRSPCP, HEX_INS_Y4_TRACE, + HEX_INS_Y5_CTLBW, + HEX_INS_Y5_L2CLEANIDX, HEX_INS_Y5_L2FETCH, + HEX_INS_Y5_L2GCLEAN, + HEX_INS_Y5_L2GCLEANINV, + HEX_INS_Y5_L2GUNLOCK, + HEX_INS_Y5_L2INVIDX, + HEX_INS_Y5_L2LOCKA, + HEX_INS_Y5_L2UNLOCKA, + HEX_INS_Y5_TLBASIDI, + HEX_INS_Y5_TLBOC, HEX_INS_Y6_DIAG, HEX_INS_Y6_DIAG0, HEX_INS_Y6_DIAG1, @@ -2297,60 +2344,13 @@ typedef enum { HEX_INS_DEP_A2_ADDSAT, HEX_INS_DEP_A2_SUBSAT, HEX_INS_DEP_S2_PACKHL, - HEX_INS_IMPORTED_PD_L2LOCKA_RS, HEX_INS_IMPORTED_RD_SS, - HEX_INS_IMPORTED_RD_CTLBW_RSS_RT, - HEX_INS_IMPORTED_RD_DCTAGR_RS, - HEX_INS_IMPORTED_RD_GETIMASK_RS, - HEX_INS_IMPORTED_RD_IASSIGNR_RS, - HEX_INS_IMPORTED_RD_ICDATAR_RS, - HEX_INS_IMPORTED_RD_ICTAGR_RS, - HEX_INS_IMPORTED_RD_L2TAGR_RS, HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT, - HEX_INS_IMPORTED_RD_TLBOC_RSS, - HEX_INS_IMPORTED_RD_TLBP_RS, HEX_INS_IMPORTED_RDD_SSS, - HEX_INS_IMPORTED_RDD_TLBR_RS, HEX_INS_IMPORTED_SD_RS, HEX_INS_IMPORTED_SDD_RSS, - HEX_INS_IMPORTED_CIAD_RS, - HEX_INS_IMPORTED_CSWI_RS, - HEX_INS_IMPORTED_DCCLEANIDX_RS, - HEX_INS_IMPORTED_DCCLEANINVIDX_RS, - HEX_INS_IMPORTED_DCINVIDX_RS, - HEX_INS_IMPORTED_DCKILL, - HEX_INS_IMPORTED_DCTAGW_RS_RT, - HEX_INS_IMPORTED_IASSIGNW_RS, - HEX_INS_IMPORTED_ICDATAW_RS_RT, - HEX_INS_IMPORTED_ICINVIDX_RS, - HEX_INS_IMPORTED_ICKILL, - HEX_INS_IMPORTED_ICTAGW_RS_RT, - HEX_INS_IMPORTED_K0LOCK, - HEX_INS_IMPORTED_K0UNLOCK, - HEX_INS_IMPORTED_L2CLEANIDX_RS, - HEX_INS_IMPORTED_L2CLEANINVIDX_RS, - HEX_INS_IMPORTED_L2GCLEAN, HEX_INS_IMPORTED_L2GCLEAN_RTT, - HEX_INS_IMPORTED_L2GCLEANINV, HEX_INS_IMPORTED_L2GCLEANINV_RTT, - HEX_INS_IMPORTED_L2GUNLOCK, - HEX_INS_IMPORTED_L2INVIDX_RS, - HEX_INS_IMPORTED_L2KILL, - HEX_INS_IMPORTED_L2TAGW_RS_RT, - HEX_INS_IMPORTED_L2UNLOCKA_RS, - HEX_INS_IMPORTED_NMI_RS, - HEX_INS_IMPORTED_RESUME_RS, - HEX_INS_IMPORTED_RTE, - HEX_INS_IMPORTED_SETIMASK_PT_RS, - HEX_INS_IMPORTED_SETPRIO_PT_RS, - HEX_INS_IMPORTED_SIAD_RS, - HEX_INS_IMPORTED_START_RS, - HEX_INS_IMPORTED_STOP_RS, - HEX_INS_IMPORTED_SWI_RS, - HEX_INS_IMPORTED_TLBINVASID_RS, - HEX_INS_IMPORTED_TLBLOCK, - HEX_INS_IMPORTED_TLBUNLOCK, - HEX_INS_IMPORTED_TLBW_RSS_RT, HEX_INS_SA1_ADDI, HEX_INS_SA1_ADDRX, HEX_INS_SA1_ADDSP,