From e323d195b92c8dcc6b73e3148891a64850da27d7 Mon Sep 17 00:00:00 2001
From: Rot127 <unisono@quyllur.org>
Date: Tue, 14 Nov 2023 12:27:50 -0500
Subject: [PATCH] Several tiny syntactical and style fixes

---
 handwritten/hexagon_il_c/functions.c | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/handwritten/hexagon_il_c/functions.c b/handwritten/hexagon_il_c/functions.c
index 689cc92a..57f99cff 100644
--- a/handwritten/hexagon_il_c/functions.c
+++ b/handwritten/hexagon_il_c/functions.c
@@ -5,7 +5,7 @@
  * \brief Sends the IL op at \p start to the position \p newloc.
  *
  * Note: THis is a copy of the same function implemented by Qualcomm in QEMU.
- * See: https://github.com/quic/qemu/blob/d48125de38f48a61d6423ef6a01156d6dff9ee2c/target/hexagon/decode.c#L224-L244
+ * See: https://gitlab.com/qemu-project/qemu/-/blob/master/target/hexagon/decode.c :: decode_send_insn_to
  *
  * \param ops The IL ops list.
  * \param start Index of the op to move.
@@ -39,7 +39,7 @@ static void hex_send_insn_to_i(RzVector /* HexILOp* */ *ops, ut8 start, ut8 newl
  * and stores the result in \p p->il_ops
  *
  * The shuffle algorithm implemented here is a copy of Qualcomm's implementation in QEMU:
- * https://github.com/quic/qemu/blob/d48125de38f48a61d6423ef6a01156d6dff9ee2c/target/hexagon/decode.c#L423-L543
+ * https://gitlab.com/qemu-project/qemu/-/blob/master/target/hexagon/decode.c :: decode_shuffle_for_execution
  *
  * Though some changes were made:
  * * Endloops are not handled here (they are pushed to the ops list afterwards).
@@ -61,9 +61,7 @@ RZ_IPI bool hex_shuffle_insns(RZ_INOUT HexPkt *p) {
 	}
 	RzVector *ops = p->il_ops;
 
-	//
 	// Do the shuffle
-	//
 	bool changed = false;
 	int i;
 	bool flag; /* flag means we've seen a non-memory instruction */
@@ -108,16 +106,16 @@ RZ_IPI bool hex_shuffle_insns(RZ_INOUT HexPkt *p) {
 				flag = true;
 			}
 		}
-
 		if (changed) {
 			continue;
 		}
-		/* Compares go first, may be reordered with regard to each other */
+
+		/* Comparisons go first, may be reordered with regard to each other */
 		for (flag = false, i = 0; i < last_insn + 1; i++) {
 			op = rz_vector_index_ptr(ops, i);
 			if ((op->attr & HEX_IL_INSN_ATTR_WPRED) &&
 				(op->attr & HEX_IL_INSN_ATTR_MEM_WRITE)) {
-				/* This should be a compare (not a store conditional) */
+				/* This should be a comparison (not a store conditional) */
 				if (flag) {
 					hex_send_insn_to_i(ops, i, 0);
 					changed = true;
@@ -251,7 +249,7 @@ static bool set_pkt_il_ops(RZ_INOUT HexPkt *p) {
 	}
 	return true;
 not_impl:
-	RZ_LOG_INFO("Hexagon instruction %" PFMT32d " not implemented.\n", pos->bin.insn->identifier);
+	RZ_LOG_WARN("Hexagon instruction %" PFMT32d " not implemented.\n", pos->bin.insn->identifier);
 	return false;
 }
 
@@ -300,7 +298,7 @@ RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op) {
 	static bool might_has_jumped = false;
 	HexState *state = hexagon_get_state();
 	if (!state) {
-		RZ_LOG_WARN("Could not get hexagon state!\n");
+		RZ_LOG_WARN("Failed to get hexagon plugin state data!\n");
 		return NULL;
 	}
 	HexPkt *p = hex_get_pkt(state, addr);
@@ -739,8 +737,6 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_cancel_slot(RZ_BORROW HexPkt *pkt, ut8 slot) {
 		RZ_LOG_WARN("Slot %d does not exist!", slot);
 	}
 	pkt->il_op_stats.slot_cancelled |= (1 << slot);
-	// TODO Does this really need to be tracked in the VM?
-	// return SETG("slot_cancelled", LOGOR(VARG("slot_cancelled"), SHIFTL0(U8(1), U8(slot))));
 	return EMPTY();
 }