From bef6e36fe77e1cbaecab9ff77203f298e5bb5a1c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 18 Mar 2022 20:53:24 +0100 Subject: [PATCH] ipq807x: UBI related clock fixes Add the missing PPE Crypto clock and fix the UBI clock enablement. This is a prerequisite for the NSS work. Signed-off-by: Robert Marko --- ...lk-qcom-ipq8074-add-PPE-crypto-clock.patch | 68 ++++++++++++ ...-set-BRANCH_HALT_DELAY-flag-for-UBI-.patch | 105 ++++++++++++++++++ 2 files changed, 173 insertions(+) create mode 100644 target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch create mode 100644 target/linux/ipq807x/patches-5.15/0146-clk-qcom-ipq8074-set-BRANCH_HALT_DELAY-flag-for-UBI-.patch diff --git a/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch b/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch new file mode 100644 index 00000000000000..f3a2f200f06864 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch @@ -0,0 +1,68 @@ +From f05295ef5e58a042f3a66490f6e75c6af83a329f Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Mar 2022 12:46:28 +0100 +Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock + +The built-in PPE engine has a dedicated clock for the EIP-197 crypto +engine. + +So, since the required clock currently missing add support for it. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + + 2 files changed, 20 insertions(+) + +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index c24e33321f72..6ece246f54a9 100644 +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { + }, + }; + ++static struct clk_branch gcc_crypto_ppe_clk = { ++ .halt_reg = 0x68310, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x68310, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_crypto_ppe_clk", ++ .parent_names = (const char *[]){ ++ "nss_ppe_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_branch gcc_nssnoc_ce_apb_clk = { + .halt_reg = 0x6830c, + .clkr = { +@@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { + [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, ++ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, + }; + + static const struct qcom_reset_map gcc_ipq8074_resets[] = { +diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +index 07402d970959..3ed155969c5d 100644 +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -233,6 +233,7 @@ + #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 + #define GCC_PCIE0_RCHNG_CLK_SRC 225 + #define GCC_PCIE0_RCHNG_CLK 226 ++#define GCC_CRYPTO_PPE_CLK 227 + + #define GCC_BLSP1_BCR 0 + #define GCC_BLSP1_QUP1_BCR 1 +-- +2.35.1 + diff --git a/target/linux/ipq807x/patches-5.15/0146-clk-qcom-ipq8074-set-BRANCH_HALT_DELAY-flag-for-UBI-.patch b/target/linux/ipq807x/patches-5.15/0146-clk-qcom-ipq8074-set-BRANCH_HALT_DELAY-flag-for-UBI-.patch new file mode 100644 index 00000000000000..833ef7c8b11ba2 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0146-clk-qcom-ipq8074-set-BRANCH_HALT_DELAY-flag-for-UBI-.patch @@ -0,0 +1,105 @@ +From 28a3cea6641607c7fd717516c38351d891d3e5cb Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Mar 2022 13:01:55 +0100 +Subject: [PATCH] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks + +Currently, attempting to enable the UBI clocks will cause the stuck at +off warning to be printed and clk_enable will fail. + +[ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' + +Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY +flag on UBI clocks, so lets do the same. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c +index 6ece246f54a9..25859c4cdeea 100644 +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { + + static struct clk_branch gcc_ubi0_ahb_clk = { + .halt_reg = 0x6820c, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6820c, + .enable_mask = BIT(0), +@@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { + + static struct clk_branch gcc_ubi0_axi_clk = { + .halt_reg = 0x68200, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68200, + .enable_mask = BIT(0), +@@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { + + static struct clk_branch gcc_ubi0_nc_axi_clk = { + .halt_reg = 0x68204, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68204, + .enable_mask = BIT(0), +@@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { + + static struct clk_branch gcc_ubi0_core_clk = { + .halt_reg = 0x68210, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68210, + .enable_mask = BIT(0), +@@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { + + static struct clk_branch gcc_ubi0_mpt_clk = { + .halt_reg = 0x68208, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68208, + .enable_mask = BIT(0), +@@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { + + static struct clk_branch gcc_ubi1_ahb_clk = { + .halt_reg = 0x6822c, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6822c, + .enable_mask = BIT(0), +@@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { + + static struct clk_branch gcc_ubi1_axi_clk = { + .halt_reg = 0x68220, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68220, + .enable_mask = BIT(0), +@@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { + + static struct clk_branch gcc_ubi1_nc_axi_clk = { + .halt_reg = 0x68224, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68224, + .enable_mask = BIT(0), +@@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { + + static struct clk_branch gcc_ubi1_core_clk = { + .halt_reg = 0x68230, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68230, + .enable_mask = BIT(0), +@@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { + + static struct clk_branch gcc_ubi1_mpt_clk = { + .halt_reg = 0x68228, ++ .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x68228, + .enable_mask = BIT(0), +-- +2.35.1 +