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Evaluate "OH! Open Hardware for Chip Designers" to be included #11

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rodrigomelo9 opened this issue Apr 7, 2020 · 0 comments
Open

Evaluate "OH! Open Hardware for Chip Designers" to be included #11

rodrigomelo9 opened this issue Apr 7, 2020 · 0 comments

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@rodrigomelo9
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The repo is here. The last commit was in 2017, but it seems that there are a lot of cores which can be used to detect (or not :P) problems with Yosys (because is Verilog 2005).
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