From 37129a2f1c3be04324e7af306c2f0b0123dfd2a0 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Mon, 16 Oct 2023 01:45:58 +0100 Subject: [PATCH] Add new cortex-m-interrupt-number crate --- Cargo.toml | 1 + cortex-m-interrupt-number/Cargo.toml | 12 ++++++++++++ cortex-m-interrupt-number/README.md | 10 ++++++++++ cortex-m-interrupt-number/src/lib.rs | 20 ++++++++++++++++++++ cortex-m/CHANGELOG.md | 1 + cortex-m/Cargo.toml | 1 + cortex-m/src/interrupt.rs | 21 --------------------- cortex-m/src/peripheral/nvic.rs | 2 +- 8 files changed, 46 insertions(+), 22 deletions(-) create mode 100644 cortex-m-interrupt-number/Cargo.toml create mode 100644 cortex-m-interrupt-number/README.md create mode 100644 cortex-m-interrupt-number/src/lib.rs diff --git a/Cargo.toml b/Cargo.toml index 059853a0..4d32d3c2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -4,6 +4,7 @@ members = [ "cortex-m", "cortex-m-rt", "cortex-m-semihosting", + "cortex-m-interrupt-number", "panic-itm", "panic-semihosting", "testsuite", diff --git a/cortex-m-interrupt-number/Cargo.toml b/cortex-m-interrupt-number/Cargo.toml new file mode 100644 index 00000000..bcc16e52 --- /dev/null +++ b/cortex-m-interrupt-number/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "cortex-m-interrupt-number" +version = "1.0.0" +edition = "2021" +categories = ["embedded", "hardware-support", "no-std"] +description = "Shared trait for Cortex-M interrupt numbers" +keywords = ["arm", "cortex-m", "register", "peripheral"] +license = "MIT OR Apache-2.0" +readme = "README.md" +repository = "https://github.com/rust-embedded/cortex-m" + +[dependencies] diff --git a/cortex-m-interrupt-number/README.md b/cortex-m-interrupt-number/README.md new file mode 100644 index 00000000..fa5c89bf --- /dev/null +++ b/cortex-m-interrupt-number/README.md @@ -0,0 +1,10 @@ +# cortex-m-interrupt-number + +This crate provides the definition of a trait that is shared between +the `cortex-m` crate and all peripheral access crates (PACs) for +Cortex-M microcontrollers. + +The PACs must implement the `InterruptNumber` trait on an enum of possible +interrupts; refer to the `InterruptNumber` [documentation] for more details. + +[documentation]: https://docs.rs/cortex-m-interrupt-number diff --git a/cortex-m-interrupt-number/src/lib.rs b/cortex-m-interrupt-number/src/lib.rs new file mode 100644 index 00000000..fadb39ef --- /dev/null +++ b/cortex-m-interrupt-number/src/lib.rs @@ -0,0 +1,20 @@ +/// Trait for enums of external interrupt numbers. +/// +/// This trait should be implemented by a peripheral access crate (PAC) +/// on its enum of available external interrupts for a specific device. +/// Each variant must convert to a u16 of its interrupt number, +/// which is its exception number - 16. +/// +/// # Safety +/// +/// This trait must only be implemented on enums of device interrupts. Each +/// enum variant must represent a distinct value (no duplicates are permitted), +/// and must always return the same value (do not change at runtime). +/// +/// These requirements ensure safe nesting of critical sections. +pub unsafe trait InterruptNumber: Copy { + /// Return the interrupt number associated with this variant. + /// + /// See trait documentation for safety requirements. + fn number(self) -> u16; +} diff --git a/cortex-m/CHANGELOG.md b/cortex-m/CHANGELOG.md index db2827f0..74e05cd9 100644 --- a/cortex-m/CHANGELOG.md +++ b/cortex-m/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Breaking changes - `NVIC::request()` no longer requires `&mut self`. +- `InterruptNumber` is now provided by the `cortex-m-interrupt-number` trait ### Added - Updated `SCB.ICSR.VECTACTIVE`/`SCB::vect_active()` to be 9 bits instead of 8. diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml index cdd63bd9..e4da2015 100644 --- a/cortex-m/Cargo.toml +++ b/cortex-m/Cargo.toml @@ -17,6 +17,7 @@ rust-version = "1.59" links = "cortex-m" # prevent multiple versions of this crate to be linked together [dependencies] +cortex-m-interrupt-number = "1.0.0" critical-section = "1.0.0" volatile-register = "0.2.0" bitfield = "0.13.2" diff --git a/cortex-m/src/interrupt.rs b/cortex-m/src/interrupt.rs index f6ce9908..2610bf62 100644 --- a/cortex-m/src/interrupt.rs +++ b/cortex-m/src/interrupt.rs @@ -5,27 +5,6 @@ use core::arch::asm; #[cfg(cortex_m)] use core::sync::atomic::{compiler_fence, Ordering}; -/// Trait for enums of external interrupt numbers. -/// -/// This trait should be implemented by a peripheral access crate (PAC) -/// on its enum of available external interrupts for a specific device. -/// Each variant must convert to a u16 of its interrupt number, -/// which is its exception number - 16. -/// -/// # Safety -/// -/// This trait must only be implemented on enums of device interrupts. Each -/// enum variant must represent a distinct value (no duplicates are permitted), -/// and must always return the same value (do not change at runtime). -/// -/// These requirements ensure safe nesting of critical sections. -pub unsafe trait InterruptNumber: Copy { - /// Return the interrupt number associated with this variant. - /// - /// See trait documentation for safety requirements. - fn number(self) -> u16; -} - /// Disables all interrupts in the current core. #[cfg(cortex_m)] #[inline] diff --git a/cortex-m/src/peripheral/nvic.rs b/cortex-m/src/peripheral/nvic.rs index fccd6a2c..f876da04 100644 --- a/cortex-m/src/peripheral/nvic.rs +++ b/cortex-m/src/peripheral/nvic.rs @@ -4,7 +4,7 @@ use volatile_register::RW; #[cfg(not(armv6m))] use volatile_register::{RO, WO}; -use crate::interrupt::InterruptNumber; +use cortex_m_interrupt_number::InterruptNumber; use crate::peripheral::NVIC; /// Register block